mirror of
https://github.com/NanjingForestryUniversity/valveboard.git
synced 2025-11-09 23:04:01 +00:00
First commit on tobacco-sorting branch
add epc9600 example Co-Authored-By: Suhandong <80463329+Suhandong@users.noreply.github.com> Co-Authored-By: FGR-cmd <80112392+FGR-cmd@users.noreply.github.com>
This commit is contained in:
Miaow
parent
b5d6295638
commit
a8e54608b3
@ -1,6 +1,6 @@
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# 阀板
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# 阀板
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阀板接收上位机给的数据，按其要求控制高速喷阀的开启和关闭，用在棉花、烟叶、茶叶等分选机上，喷阀多用来吹走其中的杂质。因此阀板是分选步骤上控制最终执行机构的驱动板，要求高速、稳定
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阀板接收上位机给的数据，按其要求控制高速喷阀的开启和关闭，用在棉花、烟叶、茶叶等分选机上，喷阀多用来吹走其中的杂质。因此阀板是分选步骤上控制最终执行机构的驱动板，要求高速、稳定。**这个文件夹下为烟梗分选机阀板相关内容。**
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## 目录结构
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## 目录结构
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@ -2,7 +2,7 @@
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## 概述
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## 概述
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按照阀板程序，这里为基于两个平台的发送端实现
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按照阀板程序，这里为基于三个平台的发送端实现
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- stm32f103
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- stm32f103
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@ -11,6 +11,10 @@
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- zynq7100
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- zynq7100
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实现了发送模块，可直接例化
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实现了发送模块，可直接例化
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- epc9600
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基于嵌入式linux的程序，线程安全，具体板子为EPC-9600I-L，是广州致远电子有限公司开发的基于AM335x系列处理器的工控主板，处理器内核为800MHz的Arm Cortex-A8。
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## 作者
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## 作者
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65
examples/epc9600/.gitignore
vendored
Normal file
65
examples/epc9600/.gitignore
vendored
Normal file
@ -0,0 +1,65 @@
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# Prerequisites
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*.d
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.vscode/*
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!.vscode/settings.json
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!.vscode/tasks.json
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!.vscode/launch.json
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!.vscode/extensions.json
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!.vscode/*.code-snippets
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build/*
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# Local History for Visual Studio Code
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.history/
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# Built Visual Studio Code Extensions
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*.vsix
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# Object files
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*.o
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*.ko
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*.obj
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*.elf
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# Linker output
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*.ilk
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*.map
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*.exp
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# Precompiled Headers
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*.gch
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*.pch
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# Libraries
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*.lib
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*.a
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*.la
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*.lo
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# Shared objects (inc. Windows DLLs)
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*.dll
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*.so
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*.so.*
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*.dylib
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# Executables
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*.exe
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*.out
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*.app
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*.i*86
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*.x86_64
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*.hex
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# Debug files
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*.dSYM/
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*.su
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*.idb
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*.pdb
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# Kernel Module Compile Results
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*.mod*
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*.cmd
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.tmp_versions/
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modules.order
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Module.symvers
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Mkfile.old
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dkms.conf
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24
examples/epc9600/.vscode/settings.json
vendored
Normal file
24
examples/epc9600/.vscode/settings.json
vendored
Normal file
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{
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"files.associations": {
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"stdlib.h": "c",
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"assert.h": "c",
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"valve_init.h": "c",
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"gpio.h": "c",
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"type_traits": "c",
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"gpio_common.h": "c",
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"unistd.h": "c",
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"stdint.h": "c",
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"stat.h": "c",
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"types.h": "c",
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"pthread.h": "c",
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"pthreadtypes.h": "c",
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"valve.h": "c"
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},
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"makefile.launchConfigurations": [
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{
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"cwd": "/home/miaow/zlg/two_tobacco",
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"binaryPath": "/home/miaow/zlg/two_tobacco/gpio_test",
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"binaryArgs": []
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}
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]
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}
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86
examples/epc9600/Makefile
Normal file
86
examples/epc9600/Makefile
Normal file
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#makefile for file_ioctl
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CROSS_COMPILE ?= /home/miaow/software/arm-2011.03/bin/arm-none-linux-gnueabi-
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TARGET := main
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BUILD_DIR := build
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ifeq ("$(origin V)", "command line")
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KBUILD_VERBOSE = $(V)
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endif
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ifndef KBUILD_VERBOSE
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KBUILD_VERBOSE = 0
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endif
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ifeq ($(KBUILD_VERBOSE),1)
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quiet =
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Q =
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else
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quiet=quiet_
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Q = @
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endif
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ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4
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ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
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quiet=silent_
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endif
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else # make-3.8x
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ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
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quiet=silent_
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endif
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endif
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SRC := $(wildcard *.c)
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ASM_SRC := $(wildcard *.s)
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OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.o)))
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ASM_OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.o)))
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DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.dis)))
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ASM_DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.dis)))
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_TARGET := $(BUILD_DIR)/$(TARGET)
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TARGET_DIS := $(BUILD_DIR)/target.dis
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LD = $(CROSS_COMPILE)ld
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CC = $(CROSS_COMPILE)gcc
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CPP = $(CC) -E
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AR = $(CROSS_COMPILE)ar
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LDR = $(CROSS_COMPILE)ldr
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STRIP = $(CROSS_COMPILE)strip
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OBJCOPY = $(CROSS_COMPILE)objcopy
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OBJDUMP = $(CROSS_COMPILE)objdump
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CFLAGS = -g -std=gnu99 -Wall -I.
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LDFLAGS = -lpthread -lc -lm -marmelf_linux_eabi
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.SECONDARY:
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.PHONY:all
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all: $(_TARGET) $(DIS) $(ASM_DIS) $(TARGET_DIS)
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$(BUILD_DIR)/%.i:%.c Makefile | $(BUILD_DIR)
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$(Q)$(CC) -E $(CFLAGS) $< -o $@
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$(BUILD_DIR)/%.s:$(BUILD_DIR)/%.i Makefile | $(BUILD_DIR)
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$(Q)$(CC) -S $(CFLAGS) $< -o $@
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$(BUILD_DIR)/%.o:$(BUILD_DIR)/%.s Makefile | $(BUILD_DIR)
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$(Q)$(CC) -c $(CFLAGS) $< -o $@
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$(BUILD_DIR)/%.o:%.s Makefile | $(BUILD_DIR)
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$(Q)$(CC) -c $(CFLAGS) $< -o $@
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$(BUILD_DIR)/%.dis:$(BUILD_DIR)/%.o Makefile | $(BUILD_DIR)
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$(Q)$(OBJDUMP) -s -d $< > $@
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$(TARGET_DIS):$(_TARGET) Makefile | $(BUILD_DIR)
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$(Q)$(OBJDUMP) -s -d $< > $@
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$(_TARGET):$(OBJ) $(ASM_OBJ) Makefile | $(BUILD_DIR)
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$(Q)$(CC) $(OBJ) $(ASM_OBJ) $(LDFLAGS) -o $@
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.PHONY:clean
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clean:
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$(Q)$(RM) $(BUILD_DIR)/* -f
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.PHONY:install
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install:$(TARGET)
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$(Q)chmod 777 $(TARGET)
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.PHONY:$(BUILD_DIR)
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$(BUILD_DIR):
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$(Q)if [ ! -d $(BUILD_DIR) ]; then mkdir -p $@; fi
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18
examples/epc9600/delay.s
Normal file
18
examples/epc9600/delay.s
Normal file
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.global delay_us
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.func delay_us
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delay_us:
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cmp r0, #0
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moveq pc, lr
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stmfd sp!, {r1, r2, fp, lr}
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mov r1, r0
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big_loop:
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ldr r2, =266
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loop:
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sub r2, r2, #1
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cmp r2, #0
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bne loop
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sub r1, r1, #1
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cmp r1, #0
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bne big_loop
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ldmfd sp!, {r1, r2, fp, pc}
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.endfunc
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60
examples/epc9600/gpio_common.c
Normal file
60
examples/epc9600/gpio_common.c
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/**
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* @file gpio_common.c
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* @brief Operate the GPIO port of Zhou Ligong linux industrial control board
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* @details is_file_exist(const char *file_path) determine whether the specified file exists
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* print_array(int *array, int count) used to print out the value of the queue buffer, easy to debug and use
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* @mainpage github.com/NanjingForestryUniversity
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* @author miaow
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* @email 3703781@qq.com
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* @version v0.9.0
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* @date 2021/12/25 merry christmas
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*/
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#include <gpio_common.h>
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char perror_buffer[1024] = {0};
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char *gpio_value_file_gpo_list[8] = {GPIO_GET_VALUE_FILE(52), GPIO_GET_VALUE_FILE(53),
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GPIO_GET_VALUE_FILE(54), GPIO_GET_VALUE_FILE(55),
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GPIO_GET_VALUE_FILE(56), GPIO_GET_VALUE_FILE(57),
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GPIO_GET_VALUE_FILE(58), GPIO_GET_VALUE_FILE(59)};
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char *gpio_pin_str[8] = {"52", "53", "54", "55", "56", "57", "58", "59"};
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int gpio_pin_str_len[8] = {2, 2, 2, 2, 2, 2, 2, 2};
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char *gpio_pin_value_str[2] = {"0", "1"};
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int gpio_pin_value_str_len[2] = {1, 1};
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int gpo_value_fd[8] = {0};
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/**
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* @brief determine whether the specified file exists
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* @param file_path file path
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* @return 1 - success, -1 - error
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*/
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int is_file_exist(const char *file_path)
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{
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if (file_path == NULL)
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return -1;
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if (access(file_path, F_OK) == 0)
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return 1;
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return -1;
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}
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/**
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* @brief Put the processed host computer data into the queue
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* @param array Buffer pointer in the queue
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* @param count The number of data in the buffer
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*/
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void print_array(int *array, int count)
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{
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if (count == 0)
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{
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printf("[]\r\n");
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return;
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}
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printf("[");
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int i;
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for (i = 0; i < count - 1; i++)
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{
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printf("%d,", array[i]);
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}
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printf("%d]\r\n", array[i]);
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}
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79
examples/epc9600/gpio_common.h
Normal file
79
examples/epc9600/gpio_common.h
Normal file
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#ifndef __GPIO_H
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#define __GPIO_H
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <stdint.h>
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#include <fcntl.h>
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#include <termios.h>
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#include <errno.h>
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#include <string.h>
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#include <assert.h>
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#include <sys/types.h>
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#define GPIO_EXPORT_PATH "/sys/class/gpio/export"
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#define GPIO_GET_PIN_STR(pin) #pin
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#define GPIO_GET_VALUE_FILE(pin) "/sys/class/gpio/gpio" #pin "/value"
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#define GPIO_PINDEF_TO_INDEX(pin_t) ((int)pin_t)
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#define GPIO_VALUEDEF_TO_INDEX(value_t) ((int)value_t)
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#define ON_ERROR(res, message1, message2) \
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if (res < 0) \
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{ \
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sprintf(perror_buffer, "error %d at %s:%d, %s, %s", res, __FILE__, __LINE__, message1, message2); \
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perror(perror_buffer); \
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}
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#define ON_ERROR_RET_VOID(res, message1, message2) \
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ON_ERROR(res, message1, message2); \
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if (res < 0) \
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return;
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#define ON_ERROR_RET(res, message1, message2, retval) \
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ON_ERROR(res, message1, message2); \
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if (res < 0) \
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return retval;
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typedef enum
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{
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GPO0 = 0,
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GPO1 = 1,
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GPO2 = 2,
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GPO3 = 3,
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GPO4 = 4,
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GPO5 = 5,
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GPO6 = 6,
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GPO7 = 7
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} gpo_pin_enum_t;
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typedef enum
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{
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GPI0 = 8,
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GPI1 = 9,
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GPI2 = 10,
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GPI3 = 11,
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GPI4 = 12,
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GPI5 = 13,
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GPI6 = 14,
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GPI7 = 15
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} gpi_pin_enum_t;
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typedef enum
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{
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GPIO_VALUE_LOW = 0,
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GPIO_VALUE_HIGH = 1
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}gpio_value_enum_t;
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int is_file_exist(const char *file_path);
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extern char perror_buffer[];
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extern char *gpio_value_file_gpo_list[];
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extern char *gpio_pin_str[];
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extern int gpio_pin_str_len[];
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extern char *gpio_pin_value_str[];
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extern int gpo_value_fd[];
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extern int gpio_pin_value_str_len[];
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void print_array(int *array, int count);
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#endif
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||||||
29
examples/epc9600/main.c
Normal file
29
examples/epc9600/main.c
Normal file
@ -0,0 +1,29 @@
|
|||||||
|
#include <valve.h>
|
||||||
|
#include <sys/socket.h>
|
||||||
|
#include <arpa/inet.h>
|
||||||
|
#include <math.h>
|
||||||
|
|
||||||
|
queue_msg_t queue_msg = {NULL, 1024, 0, 0, 0, 0, 0};
|
||||||
|
valvedata_t valvedata = {0};
|
||||||
|
queue_msg_t queue = {0};
|
||||||
|
|
||||||
|
#define ROTATE_UINT64_RIGHT(x, n) ((x) >> (n)) | ((x) << ((64) - (n)))
|
||||||
|
#define ROTATE_UINT64_LEFT(x, n) ((x) << (n)) | ((x) >> ((64) - (n)))
|
||||||
|
|
||||||
|
int main(int argc, char *argv[])
|
||||||
|
{
|
||||||
|
uint64_t aaa = (uint64_t)pow(2.0, 48.0);
|
||||||
|
printf(motd);
|
||||||
|
queue_init(&queue, 1024);
|
||||||
|
valve_init();
|
||||||
|
valvedata.valvedata_1 = 1;
|
||||||
|
for (uint64_t i = 0; i < aaa; i++)
|
||||||
|
{
|
||||||
|
valvedata.valvedata_1 = i; // ROTATE_UINT64_RIGHT(valvedata.valvedata_1, 1);
|
||||||
|
valve_sendmsg(&valvedata);
|
||||||
|
}
|
||||||
|
queue_deinit(&queue);
|
||||||
|
valve_deinit();
|
||||||
|
printf(motd2);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
220
examples/epc9600/valve.c
Normal file
220
examples/epc9600/valve.c
Normal file
@ -0,0 +1,220 @@
|
|||||||
|
/**
|
||||||
|
* @file valve.c
|
||||||
|
* @brief Operate the valveboard with Linux application
|
||||||
|
* @details Call valve_init() paired with valve_deinit() as their names imply, valve_send() can be executed several times to operate up to 6 valveboards between valve_init() and valve_deinit()
|
||||||
|
* @mainpage github.com/NanjingForestryUniversity
|
||||||
|
* @author miaow
|
||||||
|
* @email 3703781@qq.com
|
||||||
|
* @version v0.9.0
|
||||||
|
* @date 2021/12/25 merry christmas
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <valve.h>
|
||||||
|
#include <gpio_common.h>
|
||||||
|
#include <pthread.h>
|
||||||
|
#include <unistd.h>
|
||||||
|
|
||||||
|
|
||||||
|
// Write to the file desc (global variable `gpo_value_fd` in gpio_common.c) to operate a gpio.
|
||||||
|
// So gpo_value_fd should be initialized in valve_init with great care.
|
||||||
|
// Also, gpo_value_fd/gpi_value_fd is used in other .c files (read pluse of encoder, etc).
|
||||||
|
#define __GPO_SET_BIT(pin_t) __GPO_SET(pin_t, GPIO_VALUE_HIGH)
|
||||||
|
#define __GPO_CLR_BIT(pin_t) __GPO_SET(pin_t, GPIO_VALUE_LOW)
|
||||||
|
#define __GPO_SET(pin_t, value_t) write(gpo_value_fd[GPIO_PINDEF_TO_INDEX(pin_t)], gpio_pin_value_str[GPIO_VALUEDEF_TO_INDEX(value_t)], gpio_pin_value_str_len[GPIO_VALUEDEF_TO_INDEX(value_t)])
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
int need_send; // Set this variable to 1 will cause a packet of sending
|
||||||
|
pthread_mutex_t need_send_mutex;
|
||||||
|
uint64_t data[6]; // Encoded data for sending
|
||||||
|
pthread_mutex_t data_mutex; // don't use, use need_send_mutex instead
|
||||||
|
int need_exit; // loop_thread joins to parent-thread at need_exit==1
|
||||||
|
pthread_mutex_t need_exit_mutex; // don't use, use need_send_mutex instead
|
||||||
|
pthread_t loop_thread; // The sending thread
|
||||||
|
pthread_cond_t is_sending;
|
||||||
|
} valve_global_t;
|
||||||
|
|
||||||
|
static valve_global_t _global_structure;
|
||||||
|
valve_pin_enum_t valveboard_x_sdata[] = {VALVE_SDATA_1, VALVE_SDATA_2, VALVE_SDATA_3, VALVE_SDATA_4, VALVE_SDATA_5, VALVE_SDATA_6};
|
||||||
|
|
||||||
|
static const int _delay = 1000 / SCLK_FREQUENCE_KHZ + 1;
|
||||||
|
static const int _delay_on_2 = 500 / SCLK_FREQUENCE_KHZ + 1;
|
||||||
|
|
||||||
|
extern int delay_us(int us);
|
||||||
|
void *loop_thread_func(void *param);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize valve-related gpos and start loop_thread which keeps communicating with valveboards, SEN/SCLK/SDATA1/SDATA2/SDATA3/SDATA4/SDATA5/SDATA6
|
||||||
|
* @return 0 - success, -1 - error
|
||||||
|
*/
|
||||||
|
int valve_init()
|
||||||
|
{
|
||||||
|
//打开GPIO
|
||||||
|
int fd_export = open(GPIO_EXPORT_PATH, O_WRONLY);
|
||||||
|
ON_ERROR_RET(fd_export, GPIO_EXPORT_PATH, "export in valve_init()", -1);
|
||||||
|
for (int i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
if (is_file_exist(gpio_value_file_gpo_list[i]))
|
||||||
|
continue;
|
||||||
|
int ret = write(fd_export, gpio_pin_str[i], gpio_pin_str_len[i]);
|
||||||
|
ON_ERROR_RET(ret, gpio_pin_str[i], "open value file in valve_init()", -1);
|
||||||
|
}
|
||||||
|
for (int i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
gpo_value_fd[i] = open(gpio_value_file_gpo_list[i], O_RDWR);
|
||||||
|
ON_ERROR_RET(gpo_value_fd[i], gpio_value_file_gpo_list[i], "open value file in valve_init()", -1);
|
||||||
|
}
|
||||||
|
|
||||||
|
close(fd_export);
|
||||||
|
pthread_mutex_init(&_global_structure.need_send_mutex, NULL);
|
||||||
|
pthread_mutex_init(&_global_structure.data_mutex, NULL);
|
||||||
|
pthread_mutex_init(&_global_structure.need_exit_mutex, NULL);
|
||||||
|
pthread_cond_init(&_global_structure.is_sending, NULL);
|
||||||
|
|
||||||
|
int ret = pthread_create(&_global_structure.loop_thread, NULL, loop_thread_func, NULL);
|
||||||
|
ON_ERROR_RET(ret, "thread create error in valve_init()", "", -1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function runs in child thread and handles communication with valveboard
|
||||||
|
*/
|
||||||
|
void *loop_thread_func(void *param)
|
||||||
|
{
|
||||||
|
printf("loop_thread in %s start\r\n", __FILE__);
|
||||||
|
int need_exit = 0;
|
||||||
|
while (!need_exit)
|
||||||
|
{
|
||||||
|
pthread_mutex_lock(&_global_structure.need_send_mutex);
|
||||||
|
|
||||||
|
|
||||||
|
if (_global_structure.need_send == 0)
|
||||||
|
{
|
||||||
|
__GPO_CLR_BIT(VALVE_SCLK);
|
||||||
|
|
||||||
|
delay_us(_delay);
|
||||||
|
__GPO_SET_BIT(VALVE_SCLK);
|
||||||
|
delay_us(_delay);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
delay_us(_delay);
|
||||||
|
int i = 48;
|
||||||
|
|
||||||
|
__GPO_SET_BIT(VALVE_SEN);
|
||||||
|
|
||||||
|
while (i--)
|
||||||
|
{
|
||||||
|
|
||||||
|
__GPO_CLR_BIT(VALVE_SCLK);
|
||||||
|
delay_us(_delay_on_2);
|
||||||
|
__GPO_SET(VALVE_SDATA_1, (_global_structure.data[0] & 1UL));
|
||||||
|
__GPO_SET(VALVE_SDATA_2, (_global_structure.data[1] & 1UL));
|
||||||
|
__GPO_SET(VALVE_SDATA_3, (_global_structure.data[2] & 1UL));
|
||||||
|
__GPO_SET(VALVE_SDATA_4, (_global_structure.data[3] & 1UL));
|
||||||
|
__GPO_SET(VALVE_SDATA_5, (_global_structure.data[4] & 1UL));
|
||||||
|
__GPO_SET(VALVE_SDATA_6, (_global_structure.data[5] & 1UL));
|
||||||
|
_global_structure.data[0] >>= 1;
|
||||||
|
_global_structure.data[1] >>= 1;
|
||||||
|
_global_structure.data[2] >>= 1;
|
||||||
|
_global_structure.data[3] >>= 1;
|
||||||
|
_global_structure.data[4] >>= 1;
|
||||||
|
_global_structure.data[5] >>= 1;
|
||||||
|
delay_us(_delay_on_2);
|
||||||
|
__GPO_SET_BIT(VALVE_SCLK);
|
||||||
|
delay_us(_delay);
|
||||||
|
}
|
||||||
|
__GPO_CLR_BIT(VALVE_SEN);
|
||||||
|
_global_structure.need_send = 0;
|
||||||
|
pthread_cond_signal(&_global_structure.is_sending);
|
||||||
|
}
|
||||||
|
|
||||||
|
// pthread_mutex_lock(&_global_structure.need_exit_mutex);
|
||||||
|
need_exit = _global_structure.need_exit;
|
||||||
|
// pthread_mutex_unlock(&_global_structure.need_exit_mutex);
|
||||||
|
|
||||||
|
pthread_mutex_unlock(&_global_structure.need_send_mutex);
|
||||||
|
}
|
||||||
|
printf("loop_thread in %s exit\r\n", __FILE__);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set valve valve in forms of array.
|
||||||
|
* @param valve_data An array with size of 6,
|
||||||
|
* for example, valve_data[0]=64'h0000_FFFF_FFFF_FFFF represents the first valveboard all on
|
||||||
|
* valve_data[5]=64'h0000_0000_0000_0001 represents the last valveboard turn on its first valve
|
||||||
|
* @return 0 - success, -1 - error
|
||||||
|
*/
|
||||||
|
int valve_send(uint64_t *valve_data)
|
||||||
|
{
|
||||||
|
pthread_mutex_lock(&_global_structure.need_send_mutex);
|
||||||
|
while (_global_structure.need_send == 1)
|
||||||
|
pthread_cond_wait(&_global_structure.is_sending, &_global_structure.need_send_mutex);
|
||||||
|
|
||||||
|
for (int i = 0; i < 6; i++)
|
||||||
|
{
|
||||||
|
_global_structure.data[i] = ~valve_data[i]; // 1 represents on in parameter of this function while off when putting data on the bus
|
||||||
|
}
|
||||||
|
_global_structure.need_send = 1; // Set this variable to 1 will cause a sending packet
|
||||||
|
pthread_mutex_unlock(&_global_structure.need_send_mutex);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set valve valve in forms of struct.
|
||||||
|
* @param valve_data the valve_data struct
|
||||||
|
* @return 0 - success, -1 - error
|
||||||
|
*/
|
||||||
|
int valve_sendmsg(valvedata_t *valve_data)
|
||||||
|
{
|
||||||
|
pthread_mutex_lock(&_global_structure.need_send_mutex);
|
||||||
|
while (_global_structure.need_send == 1)
|
||||||
|
pthread_cond_wait(&_global_structure.is_sending, &_global_structure.need_send_mutex);
|
||||||
|
|
||||||
|
_global_structure.data[0] = ~valve_data->valvedata_1; // 1 represents on in parameter of this function while off when putting data on the bus
|
||||||
|
_global_structure.data[1] = ~valve_data->valvedata_2;
|
||||||
|
_global_structure.data[2] = ~valve_data->valvedata_3;
|
||||||
|
_global_structure.data[3] = ~valve_data->valvedata_4;
|
||||||
|
_global_structure.data[4] = ~valve_data->valvedata_5;
|
||||||
|
_global_structure.data[5] = ~valve_data->valvedata_6;
|
||||||
|
|
||||||
|
_global_structure.need_send = 1; // Set this variable to 1 will cause a sending packet
|
||||||
|
pthread_mutex_unlock(&_global_structure.need_send_mutex);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitialize and turn off all the valve.
|
||||||
|
* @param valve_data An array with size of 6,
|
||||||
|
* for example, valve_data[0]=64'h0000_FFFF_FFFF_FFFF represents the first valveboard all on
|
||||||
|
* valve_data[5]=64'h0000_0000_0000_0001 represents the last valveboard turn on its first valve
|
||||||
|
* @note This function DOES BLOCKS 100000 us at least and DOES NOT UNEXPORT gpos
|
||||||
|
* @return 0 - success, -1 - error
|
||||||
|
*/
|
||||||
|
int valve_deinit()
|
||||||
|
{
|
||||||
|
uint64_t tmp[6] = {0};
|
||||||
|
valve_send(tmp);
|
||||||
|
usleep(100000);
|
||||||
|
pthread_mutex_lock(&_global_structure.need_send_mutex);
|
||||||
|
_global_structure.need_exit = 1;
|
||||||
|
pthread_mutex_unlock(&_global_structure.need_send_mutex);
|
||||||
|
pthread_join(_global_structure.loop_thread, NULL);
|
||||||
|
pthread_mutex_destroy(&_global_structure.need_exit_mutex);
|
||||||
|
pthread_mutex_destroy(&_global_structure.need_send_mutex);
|
||||||
|
pthread_mutex_destroy(&_global_structure.data_mutex);
|
||||||
|
pthread_cond_destroy(&_global_structure.is_sending);
|
||||||
|
memset((void *)_global_structure.data, 0, sizeof(_global_structure.data));
|
||||||
|
_global_structure.need_exit = 0;
|
||||||
|
_global_structure.need_send = 0;
|
||||||
|
|
||||||
|
int ret;
|
||||||
|
for (int i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
ret = close(gpo_value_fd[i]);
|
||||||
|
ON_ERROR_RET(ret, "close value file in valve_init()", "", -1);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
35
examples/epc9600/valve.h
Normal file
35
examples/epc9600/valve.h
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
#ifndef __VALVE_INIT_H
|
||||||
|
#define __VALVE_INIT_H
|
||||||
|
#include <gpio_common.h>
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
VALVE_SEN=GPIO_PINDEF_TO_INDEX(GPO1),
|
||||||
|
VALVE_SCLK=GPIO_PINDEF_TO_INDEX(GPO2),
|
||||||
|
VALVE_SDATA_1=GPIO_PINDEF_TO_INDEX(GPO0),
|
||||||
|
VALVE_SDATA_2=GPIO_PINDEF_TO_INDEX(GPO3),
|
||||||
|
VALVE_SDATA_3=GPIO_PINDEF_TO_INDEX(GPO4),
|
||||||
|
VALVE_SDATA_4=GPIO_PINDEF_TO_INDEX(GPO5),
|
||||||
|
VALVE_SDATA_5=GPIO_PINDEF_TO_INDEX(GPO6),
|
||||||
|
VALVE_SDATA_6=GPIO_PINDEF_TO_INDEX(GPO7)
|
||||||
|
}valve_pin_enum_t;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint64_t valvedata_1;
|
||||||
|
uint64_t valvedata_2;
|
||||||
|
uint64_t valvedata_3;
|
||||||
|
uint64_t valvedata_4;
|
||||||
|
uint64_t valvedata_5;
|
||||||
|
uint64_t valvedata_6;
|
||||||
|
} valvedata_t;
|
||||||
|
|
||||||
|
|
||||||
|
#define SCLK_FREQUENCE_KHZ 10000
|
||||||
|
|
||||||
|
int valve_init(void);
|
||||||
|
int valve_send(uint64_t* valve_data);
|
||||||
|
int valve_deinit(void);
|
||||||
|
int valve_sendmsg(valvedata_t* valve_data);
|
||||||
|
|
||||||
|
#endif
|
||||||
@ -1,2 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<filters version="20.1" />
|
|
||||||
@ -1,12 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<preferences>
|
|
||||||
<debug showDebugMenu="0" />
|
|
||||||
<systemtable filter="All Interfaces">
|
|
||||||
<columns>
|
|
||||||
<connections preferredWidth="47" />
|
|
||||||
<irq preferredWidth="34" />
|
|
||||||
</columns>
|
|
||||||
</systemtable>
|
|
||||||
<library expandedCategories="Library,Project" />
|
|
||||||
<window width="1293" height="1041" x="0" y="0" />
|
|
||||||
</preferences>
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1 +0,0 @@
|
|||||||
Thu Nov 11 17:04:12 2021
|
|
||||||
@ -1,111 +0,0 @@
|
|||||||
Design Assistant report for PF1
|
|
||||||
Thu Nov 04 10:40:09 2021
|
|
||||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
|
||||||
; Table of Contents ;
|
|
||||||
---------------------
|
|
||||||
1. Legal Notice
|
|
||||||
2. Design Assistant Summary
|
|
||||||
3. Design Assistant Settings
|
|
||||||
4. Design Assistant Messages
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
----------------
|
|
||||||
; Legal Notice ;
|
|
||||||
----------------
|
|
||||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
|
||||||
Your use of Intel Corporation's design tools, logic functions
|
|
||||||
and other software and tools, and any partner logic
|
|
||||||
functions, and any output files from any of the foregoing
|
|
||||||
(including device programming or simulation files), and any
|
|
||||||
associated documentation or information are expressly subject
|
|
||||||
to the terms and conditions of the Intel Program License
|
|
||||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
||||||
the Intel FPGA IP License Agreement, or other applicable license
|
|
||||||
agreement, including, without limitation, that your use is for
|
|
||||||
the sole purpose of programming logic devices manufactured by
|
|
||||||
Intel and sold by Intel or its authorized distributors. Please
|
|
||||||
refer to the applicable agreement for further details, at
|
|
||||||
https://fpgasoftware.intel.com/eula.
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------+
|
|
||||||
; Design Assistant Summary ;
|
|
||||||
+-----------------------------------+-------------------------------------+
|
|
||||||
; Design Assistant Status ; Analyzed - Thu Nov 04 10:40:09 2021 ;
|
|
||||||
; Revision Name ; PF1 ;
|
|
||||||
; Top-level Entity Name ; PF1 ;
|
|
||||||
; Family ; MAX II ;
|
|
||||||
; Total Critical Violations ; 0 ;
|
|
||||||
; Total High Violations ; 0 ;
|
|
||||||
; Total Medium Violations ; 0 ;
|
|
||||||
; Total Information only Violations ; 0 ;
|
|
||||||
+-----------------------------------+-------------------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
||||||
; Design Assistant Settings ;
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
|
|
||||||
; Option ; Setting ; To ;
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
|
|
||||||
; Design Assistant mode ; Post-Fitting ; ;
|
|
||||||
; Threshold value for clock net not mapped to clock spines rule ; 25 ; ;
|
|
||||||
; Minimum number of clock port feed by gated clocks ; 30 ; ;
|
|
||||||
; Minimum number of node fan-out ; 30 ; ;
|
|
||||||
; Maximum number of nodes to report ; 50 ; ;
|
|
||||||
; Rule C101: Gated clock should be implemented according to the Intel FPGA standard scheme ; On ; ;
|
|
||||||
; Rule C102: Logic cell should not be used to generate an inverted clock signal ; On ; ;
|
|
||||||
; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; On ; ;
|
|
||||||
; Rule C104: Clock signal source should drive only clock input ports ; On ; ;
|
|
||||||
; Rule C105: Clock signal should be a global signal ; On ; ;
|
|
||||||
; Rule C106: Clock signal source should not drive registers triggered by different clock edges ; On ; ;
|
|
||||||
; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ;
|
|
||||||
; Rule R102: External reset signals should be synchronized using two cascaded registers ; On ; ;
|
|
||||||
; Rule R103: External reset signal should be correctly synchronized ; On ; ;
|
|
||||||
; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized ; On ; ;
|
|
||||||
; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized ; On ; ;
|
|
||||||
; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ;
|
|
||||||
; Rule T102: Top nodes with the highest number of fan-outs ; On ; ;
|
|
||||||
; Rule A101: Design should not contain combinational loops ; On ; ;
|
|
||||||
; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ;
|
|
||||||
; Rule A103: Design should not contain delay chains ; On ; ;
|
|
||||||
; Rule A104: Design should not contain ripple clock structures ; On ; ;
|
|
||||||
; Rule A105: Pulses should not be implemented asynchronously ; On ; ;
|
|
||||||
; Rule A106: Multiple pulses should not be generated in design ; On ; ;
|
|
||||||
; Rule A107: Design should not contain SR latches ; On ; ;
|
|
||||||
; Rule A108: Design should not contain latches ; On ; ;
|
|
||||||
; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ;
|
|
||||||
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ;
|
|
||||||
; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source ; On ; ;
|
|
||||||
; Rule S104: Clock port and any other port of a register should not be driven by the same signal source ; On ; ;
|
|
||||||
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ;
|
|
||||||
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ;
|
|
||||||
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ;
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
|
|
||||||
|
|
||||||
|
|
||||||
+---------------------------+
|
|
||||||
; Design Assistant Messages ;
|
|
||||||
+---------------------------+
|
|
||||||
Info: *******************************************************************
|
|
||||||
Info: Running Quartus Prime Design Assistant
|
|
||||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
|
||||||
Info: Processing started: Thu Nov 04 10:40:08 2021
|
|
||||||
Info: Command: quartus_drc PF1 -c PF1
|
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
|
||||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
|
||||||
Info (332144): No user constrained base clocks found in the design
|
|
||||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
|
||||||
Warning (332068): No clocks defined in design.
|
|
||||||
Info (308007): Design Assistant information: finished post-fitting analysis of current design -- generated 0 information messages and 0 warning messages
|
|
||||||
Info: Quartus Prime Design Assistant was successful. 0 errors, 3 warnings
|
|
||||||
Info: Peak virtual memory: 4625 megabytes
|
|
||||||
Info: Processing ended: Thu Nov 04 10:40:09 2021
|
|
||||||
Info: Elapsed time: 00:00:01
|
|
||||||
Info: Total CPU time (on all processors): 00:00:00
|
|
||||||
|
|
||||||
|
|
||||||
@ -1,96 +0,0 @@
|
|||||||
EDA Netlist Writer report for PF1
|
|
||||||
Thu Nov 11 17:04:11 2021
|
|
||||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
|
||||||
; Table of Contents ;
|
|
||||||
---------------------
|
|
||||||
1. Legal Notice
|
|
||||||
2. EDA Netlist Writer Summary
|
|
||||||
3. Simulation Settings
|
|
||||||
4. Simulation Generated Files
|
|
||||||
5. EDA Netlist Writer Messages
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
----------------
|
|
||||||
; Legal Notice ;
|
|
||||||
----------------
|
|
||||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
|
||||||
Your use of Intel Corporation's design tools, logic functions
|
|
||||||
and other software and tools, and any partner logic
|
|
||||||
functions, and any output files from any of the foregoing
|
|
||||||
(including device programming or simulation files), and any
|
|
||||||
associated documentation or information are expressly subject
|
|
||||||
to the terms and conditions of the Intel Program License
|
|
||||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
||||||
the Intel FPGA IP License Agreement, or other applicable license
|
|
||||||
agreement, including, without limitation, that your use is for
|
|
||||||
the sole purpose of programming logic devices manufactured by
|
|
||||||
Intel and sold by Intel or its authorized distributors. Please
|
|
||||||
refer to the applicable agreement for further details, at
|
|
||||||
https://fpgasoftware.intel.com/eula.
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------+
|
|
||||||
; EDA Netlist Writer Summary ;
|
|
||||||
+---------------------------+---------------------------------------+
|
|
||||||
; EDA Netlist Writer Status ; Successful - Thu Nov 11 17:04:11 2021 ;
|
|
||||||
; Revision Name ; PF1 ;
|
|
||||||
; Top-level Entity Name ; PF1 ;
|
|
||||||
; Family ; MAX II ;
|
|
||||||
; Simulation Files Creation ; Successful ;
|
|
||||||
+---------------------------+---------------------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
|
||||||
; Simulation Settings ;
|
|
||||||
+---------------------------------------------------------------------------------------------------+---------------------------+
|
|
||||||
; Option ; Setting ;
|
|
||||||
+---------------------------------------------------------------------------------------------------+---------------------------+
|
|
||||||
; Tool Name ; ModelSim-Altera (Verilog) ;
|
|
||||||
; Generate functional simulation netlist ; Off ;
|
|
||||||
; Time scale ; 1 ps ;
|
|
||||||
; Truncate long hierarchy paths ; Off ;
|
|
||||||
; Map illegal HDL characters ; Off ;
|
|
||||||
; Flatten buses into individual nodes ; Off ;
|
|
||||||
; Maintain hierarchy ; Off ;
|
|
||||||
; Bring out device-wide set/reset signals as ports ; Off ;
|
|
||||||
; Enable glitch filtering ; Off ;
|
|
||||||
; Do not write top level VHDL entity ; Off ;
|
|
||||||
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
|
|
||||||
; Architecture name in VHDL output netlist ; structure ;
|
|
||||||
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
|
|
||||||
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
|
|
||||||
+---------------------------------------------------------------------------------------------------+---------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------+
|
|
||||||
; Simulation Generated Files ;
|
|
||||||
+----------------------------------------------------------------------+
|
|
||||||
; Generated Files ;
|
|
||||||
+----------------------------------------------------------------------+
|
|
||||||
; C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/PF1.vo ;
|
|
||||||
; C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/PF1_v.sdo ;
|
|
||||||
+----------------------------------------------------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------+
|
|
||||||
; EDA Netlist Writer Messages ;
|
|
||||||
+-----------------------------+
|
|
||||||
Info: *******************************************************************
|
|
||||||
Info: Running Quartus Prime EDA Netlist Writer
|
|
||||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
|
||||||
Info: Processing started: Thu Nov 11 17:04:11 2021
|
|
||||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1
|
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
|
||||||
Info (204018): Generated files "PF1.vo" and "PF1_v.sdo" in directory "C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/" for EDA simulation tool
|
|
||||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
|
||||||
Info: Peak virtual memory: 4628 megabytes
|
|
||||||
Info: Processing ended: Thu Nov 11 17:04:11 2021
|
|
||||||
Info: Elapsed time: 00:00:00
|
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
|
||||||
|
|
||||||
|
|
||||||
@ -1,8 +0,0 @@
|
|||||||
<sld_project_info>
|
|
||||||
<project>
|
|
||||||
<hash md5_digest_80b="81513109a5d40b1ef46d"/>
|
|
||||||
</project>
|
|
||||||
<file_info>
|
|
||||||
<file device="EPM1270T144C5" path="PF1.sof" usercode="0xFFFFFFFF"/>
|
|
||||||
</file_info>
|
|
||||||
</sld_project_info>
|
|
||||||
@ -1,4 +0,0 @@
|
|||||||
Warning (10268): Verilog HDL information at PF1.v(161): always construct contains both blocking and non-blocking assignments
|
|
||||||
Warning (10268): Verilog HDL information at PF1.v(206): always construct contains both blocking and non-blocking assignments
|
|
||||||
Warning (10268): Verilog HDL information at PF1.v(250): always construct contains both blocking and non-blocking assignments
|
|
||||||
Warning (10268): Verilog HDL information at PF1.v(294): always construct contains both blocking and non-blocking assignments
|
|
||||||
BIN
firmware/PF1.pof
BIN
firmware/PF1.pof
Binary file not shown.
@ -1,30 +0,0 @@
|
|||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Copyright (C) 1991-2010 Altera Corporation
|
|
||||||
# Your use of Altera Corporation's design tools, logic functions
|
|
||||||
# and other software and tools, and its AMPP partner logic
|
|
||||||
# functions, and any output files from any of the foregoing
|
|
||||||
# (including device programming or simulation files), and any
|
|
||||||
# associated documentation or information are expressly subject
|
|
||||||
# to the terms and conditions of the Altera Program License
|
|
||||||
# Subscription Agreement, Altera MegaCore Function License
|
|
||||||
# Agreement, or other applicable license agreement, including,
|
|
||||||
# without limitation, that your use is for the sole purpose of
|
|
||||||
# programming logic devices manufactured by Altera and sold by
|
|
||||||
# Altera or its authorized distributors. Please refer to the
|
|
||||||
# applicable agreement for further details.
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Quartus II
|
|
||||||
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version
|
|
||||||
# Date created = 13:42:56 December 10, 2011
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
|
|
||||||
QUARTUS_VERSION = "9.1"
|
|
||||||
DATE = "13:42:56 December 10, 2011"
|
|
||||||
|
|
||||||
# Revisions
|
|
||||||
|
|
||||||
PROJECT_REVISION = "PF1"
|
|
||||||
@ -1,910 +0,0 @@
|
|||||||
Classic Timing Analyzer report for PF1
|
|
||||||
Tue Jan 03 15:28:03 2012
|
|
||||||
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
|
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
|
||||||
; Table of Contents ;
|
|
||||||
---------------------
|
|
||||||
1. Legal Notice
|
|
||||||
2. Timing Analyzer Summary
|
|
||||||
3. Timing Analyzer Settings
|
|
||||||
4. Clock Settings Summary
|
|
||||||
5. Parallel Compilation
|
|
||||||
6. Clock Setup: 'clk'
|
|
||||||
7. Clock Setup: 'SCLK'
|
|
||||||
8. tsu
|
|
||||||
9. tco
|
|
||||||
10. th
|
|
||||||
11. Timing Analyzer Messages
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
----------------
|
|
||||||
; Legal Notice ;
|
|
||||||
----------------
|
|
||||||
Copyright (C) 1991-2009 Altera Corporation
|
|
||||||
Your use of Altera Corporation's design tools, logic functions
|
|
||||||
and other software and tools, and its AMPP partner logic
|
|
||||||
functions, and any output files from any of the foregoing
|
|
||||||
(including device programming or simulation files), and any
|
|
||||||
associated documentation or information are expressly subject
|
|
||||||
to the terms and conditions of the Altera Program License
|
|
||||||
Subscription Agreement, Altera MegaCore Function License
|
|
||||||
Agreement, or other applicable license agreement, including,
|
|
||||||
without limitation, that your use is for the sole purpose of
|
|
||||||
programming logic devices manufactured by Altera and sold by
|
|
||||||
Altera or its authorized distributors. Please refer to the
|
|
||||||
applicable agreement for further details.
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
||||||
; Timing Analyzer Summary ;
|
|
||||||
+------------------------------+-------+---------------+----------------------------------+-----------+------------+------------+----------+--------------+
|
|
||||||
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
|
|
||||||
+------------------------------+-------+---------------+----------------------------------+-----------+------------+------------+----------+--------------+
|
|
||||||
; Worst-case tsu ; N/A ; None ; 3.893 ns ; SEN ; S_PFr[44] ; -- ; SCLK ; 0 ;
|
|
||||||
; Worst-case tco ; N/A ; None ; 8.833 ns ; S_PFr2[5] ; S_PF[5] ; clk ; -- ; 0 ;
|
|
||||||
; Worst-case th ; N/A ; None ; 0.072 ns ; SEN ; i[4] ; -- ; SCLK ; 0 ;
|
|
||||||
; Clock Setup: 'clk' ; N/A ; None ; 95.93 MHz ( period = 10.424 ns ) ; cnt[17] ; S_PFr2[41] ; clk ; clk ; 0 ;
|
|
||||||
; Clock Setup: 'SCLK' ; N/A ; None ; 126.07 MHz ( period = 7.932 ns ) ; i[4] ; S_PFr[44] ; SCLK ; SCLK ; 0 ;
|
|
||||||
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
|
|
||||||
+------------------------------+-------+---------------+----------------------------------+-----------+------------+------------+----------+--------------+
|
|
||||||
|
|
||||||
|
|
||||||
+--------------------------------------------------------------------------------------------------------------------+
|
|
||||||
; Timing Analyzer Settings ;
|
|
||||||
+---------------------------------------------------------------------+--------------------+------+----+-------------+
|
|
||||||
; Option ; Setting ; From ; To ; Entity Name ;
|
|
||||||
+---------------------------------------------------------------------+--------------------+------+----+-------------+
|
|
||||||
; Device Name ; EPM240T100C5 ; ; ; ;
|
|
||||||
; Timing Models ; Final ; ; ; ;
|
|
||||||
; Default hold multicycle ; Same as Multicycle ; ; ; ;
|
|
||||||
; Cut paths between unrelated clock domains ; On ; ; ; ;
|
|
||||||
; Cut off read during write signal paths ; On ; ; ; ;
|
|
||||||
; Cut off feedback from I/O pins ; On ; ; ; ;
|
|
||||||
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
|
|
||||||
; Ignore Clock Settings ; Off ; ; ; ;
|
|
||||||
; Analyze latches as synchronous elements ; On ; ; ; ;
|
|
||||||
; Enable Recovery/Removal analysis ; Off ; ; ; ;
|
|
||||||
; Enable Clock Latency ; Off ; ; ; ;
|
|
||||||
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
|
|
||||||
; Minimum Core Junction Temperature ; 0 ; ; ; ;
|
|
||||||
; Maximum Core Junction Temperature ; 85 ; ; ; ;
|
|
||||||
; Number of source nodes to report per destination node ; 10 ; ; ; ;
|
|
||||||
; Number of destination nodes to report ; 10 ; ; ; ;
|
|
||||||
; Number of paths to report ; 200 ; ; ; ;
|
|
||||||
; Report Minimum Timing Checks ; Off ; ; ; ;
|
|
||||||
; Use Fast Timing Models ; Off ; ; ; ;
|
|
||||||
; Report IO Paths Separately ; Off ; ; ; ;
|
|
||||||
; Perform Multicorner Analysis ; Off ; ; ; ;
|
|
||||||
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
|
|
||||||
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
|
|
||||||
; Output I/O Timing Endpoint ; Near End ; ; ; ;
|
|
||||||
+---------------------------------------------------------------------+--------------------+------+----+-------------+
|
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
||||||
; Clock Settings Summary ;
|
|
||||||
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
|
|
||||||
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
|
|
||||||
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
|
|
||||||
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
|
|
||||||
; SCLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
|
|
||||||
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
|
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------+
|
|
||||||
; Parallel Compilation ;
|
|
||||||
+----------------------------+-------------+
|
|
||||||
; Processors ; Number ;
|
|
||||||
+----------------------------+-------------+
|
|
||||||
; Number detected on machine ; 2 ;
|
|
||||||
; Maximum allowed ; 2 ;
|
|
||||||
; ; ;
|
|
||||||
; Average used ; 1.00 ;
|
|
||||||
; Maximum used ; 1 ;
|
|
||||||
; ; ;
|
|
||||||
; Usage by Processor ; % Time Used ;
|
|
||||||
; 1 processor ; 100.0% ;
|
|
||||||
; 2 processors ; 0.0% ;
|
|
||||||
+----------------------------+-------------+
|
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
||||||
; Clock Setup: 'clk' ;
|
|
||||||
+-----------------------------------------+-----------------------------------------------------+---------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
|
|
||||||
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
|
|
||||||
+-----------------------------------------+-----------------------------------------------------+---------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
|
|
||||||
; N/A ; 95.93 MHz ( period = 10.424 ns ) ; cnt[17] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.715 ns ;
|
|
||||||
; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[2] ; clk ; clk ; None ; None ; 9.250 ns ;
|
|
||||||
; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[5] ; clk ; clk ; None ; None ; 9.250 ns ;
|
|
||||||
; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[3] ; clk ; clk ; None ; None ; 9.250 ns ;
|
|
||||||
; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[4] ; clk ; clk ; None ; None ; 9.250 ns ;
|
|
||||||
; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[1] ; clk ; clk ; None ; None ; 9.250 ns ;
|
|
||||||
; N/A ; 100.67 MHz ( period = 9.933 ns ) ; cnt[11] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.224 ns ;
|
|
||||||
; N/A ; 101.11 MHz ( period = 9.890 ns ) ; cnt[3] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.181 ns ;
|
|
||||||
; N/A ; 101.15 MHz ( period = 9.886 ns ) ; cnt[17] ; S_PFr2[13] ; clk ; clk ; None ; None ; 9.177 ns ;
|
|
||||||
; N/A ; 101.16 MHz ( period = 9.885 ns ) ; cnt[17] ; S_PFr2[36] ; clk ; clk ; None ; None ; 9.176 ns ;
|
|
||||||
; N/A ; 101.19 MHz ( period = 9.882 ns ) ; cnt[17] ; S_PFr2[44] ; clk ; clk ; None ; None ; 9.173 ns ;
|
|
||||||
; N/A ; 101.26 MHz ( period = 9.876 ns ) ; cnt[17] ; S_PFr2[37] ; clk ; clk ; None ; None ; 9.167 ns ;
|
|
||||||
; N/A ; 101.90 MHz ( period = 9.814 ns ) ; cnt[17] ; cnt[3] ; clk ; clk ; None ; None ; 9.105 ns ;
|
|
||||||
; N/A ; 101.92 MHz ( period = 9.812 ns ) ; cnt[2] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.103 ns ;
|
|
||||||
; N/A ; 102.26 MHz ( period = 9.779 ns ) ; cnt[7] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.070 ns ;
|
|
||||||
; N/A ; 102.43 MHz ( period = 9.763 ns ) ; cnt[17] ; cnt[14] ; clk ; clk ; None ; None ; 9.054 ns ;
|
|
||||||
; N/A ; 102.43 MHz ( period = 9.763 ns ) ; cnt[17] ; cnt[2] ; clk ; clk ; None ; None ; 9.054 ns ;
|
|
||||||
; N/A ; 103.52 MHz ( period = 9.660 ns ) ; cnt[6] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.951 ns ;
|
|
||||||
; N/A ; 103.70 MHz ( period = 9.643 ns ) ; cnt[17] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.934 ns ;
|
|
||||||
; N/A ; 103.71 MHz ( period = 9.642 ns ) ; cnt[17] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.933 ns ;
|
|
||||||
; N/A ; 103.78 MHz ( period = 9.636 ns ) ; cnt[17] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.927 ns ;
|
|
||||||
; N/A ; 103.79 MHz ( period = 9.635 ns ) ; cnt[17] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.926 ns ;
|
|
||||||
; N/A ; 103.95 MHz ( period = 9.620 ns ) ; cnt[1] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.911 ns ;
|
|
||||||
; N/A ; 104.07 MHz ( period = 9.609 ns ) ; cnt[17] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.900 ns ;
|
|
||||||
; N/A ; 104.08 MHz ( period = 9.608 ns ) ; cnt[17] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.899 ns ;
|
|
||||||
; N/A ; 104.09 MHz ( period = 9.607 ns ) ; cnt[17] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.898 ns ;
|
|
||||||
; N/A ; 104.16 MHz ( period = 9.601 ns ) ; cnt[17] ; cnt[12] ; clk ; clk ; None ; None ; 8.892 ns ;
|
|
||||||
; N/A ; 104.18 MHz ( period = 9.599 ns ) ; cnt[17] ; cnt[7] ; clk ; clk ; None ; None ; 8.890 ns ;
|
|
||||||
; N/A ; 104.78 MHz ( period = 9.544 ns ) ; cnt[17] ; cnt[13] ; clk ; clk ; None ; None ; 8.835 ns ;
|
|
||||||
; N/A ; 105.03 MHz ( period = 9.521 ns ) ; cnt[16] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.812 ns ;
|
|
||||||
; N/A ; 105.45 MHz ( period = 9.483 ns ) ; cnt[5] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.774 ns ;
|
|
||||||
; N/A ; 105.50 MHz ( period = 9.479 ns ) ; cnt[17] ; S_PFr2[46] ; clk ; clk ; None ; None ; 8.770 ns ;
|
|
||||||
; N/A ; 105.53 MHz ( period = 9.476 ns ) ; cnt[17] ; S_PFr2[10] ; clk ; clk ; None ; None ; 8.767 ns ;
|
|
||||||
; N/A ; 105.53 MHz ( period = 9.476 ns ) ; cnt[0] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.767 ns ;
|
|
||||||
; N/A ; 105.59 MHz ( period = 9.471 ns ) ; cnt[17] ; S_PFr2[12] ; clk ; clk ; None ; None ; 8.762 ns ;
|
|
||||||
; N/A ; 105.59 MHz ( period = 9.471 ns ) ; cnt[17] ; S_PFr2[15] ; clk ; clk ; None ; None ; 8.762 ns ;
|
|
||||||
; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[2] ; clk ; clk ; None ; None ; 8.759 ns ;
|
|
||||||
; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[5] ; clk ; clk ; None ; None ; 8.759 ns ;
|
|
||||||
; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[3] ; clk ; clk ; None ; None ; 8.759 ns ;
|
|
||||||
; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[4] ; clk ; clk ; None ; None ; 8.759 ns ;
|
|
||||||
; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[1] ; clk ; clk ; None ; None ; 8.759 ns ;
|
|
||||||
; N/A ; 105.86 MHz ( period = 9.446 ns ) ; cnt[4] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.737 ns ;
|
|
||||||
; N/A ; 106.02 MHz ( period = 9.432 ns ) ; cnt[17] ; cnt[11] ; clk ; clk ; None ; None ; 8.723 ns ;
|
|
||||||
; N/A ; 106.03 MHz ( period = 9.431 ns ) ; cnt[17] ; cnt[15] ; clk ; clk ; None ; None ; 8.722 ns ;
|
|
||||||
; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[2] ; clk ; clk ; None ; None ; 8.716 ns ;
|
|
||||||
; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[5] ; clk ; clk ; None ; None ; 8.716 ns ;
|
|
||||||
; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[3] ; clk ; clk ; None ; None ; 8.716 ns ;
|
|
||||||
; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[4] ; clk ; clk ; None ; None ; 8.716 ns ;
|
|
||||||
; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[1] ; clk ; clk ; None ; None ; 8.716 ns ;
|
|
||||||
; N/A ; 106.15 MHz ( period = 9.421 ns ) ; cnt[17] ; S_PFr2[27] ; clk ; clk ; None ; None ; 8.712 ns ;
|
|
||||||
; N/A ; 106.16 MHz ( period = 9.420 ns ) ; cnt[17] ; cnt[6] ; clk ; clk ; None ; None ; 8.711 ns ;
|
|
||||||
; N/A ; 106.44 MHz ( period = 9.395 ns ) ; cnt[11] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.686 ns ;
|
|
||||||
; N/A ; 106.45 MHz ( period = 9.394 ns ) ; cnt[11] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.685 ns ;
|
|
||||||
; N/A ; 106.48 MHz ( period = 9.391 ns ) ; cnt[11] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.682 ns ;
|
|
||||||
; N/A ; 106.55 MHz ( period = 9.385 ns ) ; cnt[11] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.676 ns ;
|
|
||||||
; N/A ; 106.68 MHz ( period = 9.374 ns ) ; cnt[17] ; S_PFr2[28] ; clk ; clk ; None ; None ; 8.665 ns ;
|
|
||||||
; N/A ; 106.69 MHz ( period = 9.373 ns ) ; cnt[17] ; cnt[1] ; clk ; clk ; None ; None ; 8.664 ns ;
|
|
||||||
; N/A ; 106.76 MHz ( period = 9.367 ns ) ; cnt[17] ; S_PFr2[25] ; clk ; clk ; None ; None ; 8.658 ns ;
|
|
||||||
; N/A ; 106.78 MHz ( period = 9.365 ns ) ; cnt[17] ; S_PFr2[21] ; clk ; clk ; None ; None ; 8.656 ns ;
|
|
||||||
; N/A ; 106.79 MHz ( period = 9.364 ns ) ; cnt[17] ; S_PFr2[3] ; clk ; clk ; None ; None ; 8.655 ns ;
|
|
||||||
; N/A ; 106.88 MHz ( period = 9.356 ns ) ; cnt[17] ; S_PFr2[18] ; clk ; clk ; None ; None ; 8.647 ns ;
|
|
||||||
; N/A ; 106.93 MHz ( period = 9.352 ns ) ; cnt[3] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.643 ns ;
|
|
||||||
; N/A ; 106.94 MHz ( period = 9.351 ns ) ; cnt[3] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.642 ns ;
|
|
||||||
; N/A ; 106.97 MHz ( period = 9.348 ns ) ; cnt[3] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.639 ns ;
|
|
||||||
; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[2] ; clk ; clk ; None ; None ; 8.638 ns ;
|
|
||||||
; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[5] ; clk ; clk ; None ; None ; 8.638 ns ;
|
|
||||||
; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[3] ; clk ; clk ; None ; None ; 8.638 ns ;
|
|
||||||
; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[4] ; clk ; clk ; None ; None ; 8.638 ns ;
|
|
||||||
; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[1] ; clk ; clk ; None ; None ; 8.638 ns ;
|
|
||||||
; N/A ; 107.01 MHz ( period = 9.345 ns ) ; cnt[17] ; cnt[4] ; clk ; clk ; None ; None ; 8.636 ns ;
|
|
||||||
; N/A ; 107.01 MHz ( period = 9.345 ns ) ; cnt[17] ; cnt[0] ; clk ; clk ; None ; None ; 8.636 ns ;
|
|
||||||
; N/A ; 107.04 MHz ( period = 9.342 ns ) ; cnt[3] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.633 ns ;
|
|
||||||
; N/A ; 107.04 MHz ( period = 9.342 ns ) ; cnt[17] ; cnt[5] ; clk ; clk ; None ; None ; 8.633 ns ;
|
|
||||||
; N/A ; 107.07 MHz ( period = 9.340 ns ) ; cnt[17] ; S_PFr2[26] ; clk ; clk ; None ; None ; 8.631 ns ;
|
|
||||||
; N/A ; 107.26 MHz ( period = 9.323 ns ) ; cnt[11] ; cnt[3] ; clk ; clk ; None ; None ; 8.614 ns ;
|
|
||||||
; N/A ; 107.30 MHz ( period = 9.320 ns ) ; cnt[17] ; S_PFr2[43] ; clk ; clk ; None ; None ; 8.611 ns ;
|
|
||||||
; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[2] ; clk ; clk ; None ; None ; 8.605 ns ;
|
|
||||||
; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[5] ; clk ; clk ; None ; None ; 8.605 ns ;
|
|
||||||
; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[3] ; clk ; clk ; None ; None ; 8.605 ns ;
|
|
||||||
; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[4] ; clk ; clk ; None ; None ; 8.605 ns ;
|
|
||||||
; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[1] ; clk ; clk ; None ; None ; 8.605 ns ;
|
|
||||||
; N/A ; 107.76 MHz ( period = 9.280 ns ) ; cnt[3] ; cnt[3] ; clk ; clk ; None ; None ; 8.571 ns ;
|
|
||||||
; N/A ; 107.83 MHz ( period = 9.274 ns ) ; cnt[2] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.565 ns ;
|
|
||||||
; N/A ; 107.84 MHz ( period = 9.273 ns ) ; cnt[2] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.564 ns ;
|
|
||||||
; N/A ; 107.84 MHz ( period = 9.273 ns ) ; cnt[9] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.564 ns ;
|
|
||||||
; N/A ; 107.85 MHz ( period = 9.272 ns ) ; cnt[11] ; cnt[14] ; clk ; clk ; None ; None ; 8.563 ns ;
|
|
||||||
; N/A ; 107.85 MHz ( period = 9.272 ns ) ; cnt[11] ; cnt[2] ; clk ; clk ; None ; None ; 8.563 ns ;
|
|
||||||
; N/A ; 107.87 MHz ( period = 9.270 ns ) ; cnt[2] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.561 ns ;
|
|
||||||
; N/A ; 107.94 MHz ( period = 9.264 ns ) ; cnt[2] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.555 ns ;
|
|
||||||
; N/A ; 108.21 MHz ( period = 9.241 ns ) ; cnt[7] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.532 ns ;
|
|
||||||
; N/A ; 108.23 MHz ( period = 9.240 ns ) ; cnt[7] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.531 ns ;
|
|
||||||
; N/A ; 108.26 MHz ( period = 9.237 ns ) ; cnt[7] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.528 ns ;
|
|
||||||
; N/A ; 108.31 MHz ( period = 9.233 ns ) ; cnt[17] ; S_PFr2[16] ; clk ; clk ; None ; None ; 8.524 ns ;
|
|
||||||
; N/A ; 108.33 MHz ( period = 9.231 ns ) ; cnt[7] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.522 ns ;
|
|
||||||
; N/A ; 108.35 MHz ( period = 9.229 ns ) ; cnt[3] ; cnt[14] ; clk ; clk ; None ; None ; 8.520 ns ;
|
|
||||||
; N/A ; 108.35 MHz ( period = 9.229 ns ) ; cnt[3] ; cnt[2] ; clk ; clk ; None ; None ; 8.520 ns ;
|
|
||||||
; N/A ; 108.39 MHz ( period = 9.226 ns ) ; cnt[17] ; S_PFr2[17] ; clk ; clk ; None ; None ; 8.517 ns ;
|
|
||||||
; N/A ; 108.42 MHz ( period = 9.223 ns ) ; cnt[17] ; cnt[17] ; clk ; clk ; None ; None ; 8.514 ns ;
|
|
||||||
; N/A ; 108.67 MHz ( period = 9.202 ns ) ; cnt[2] ; cnt[3] ; clk ; clk ; None ; None ; 8.493 ns ;
|
|
||||||
; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[2] ; clk ; clk ; None ; None ; 8.486 ns ;
|
|
||||||
; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[5] ; clk ; clk ; None ; None ; 8.486 ns ;
|
|
||||||
; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[3] ; clk ; clk ; None ; None ; 8.486 ns ;
|
|
||||||
; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[4] ; clk ; clk ; None ; None ; 8.486 ns ;
|
|
||||||
; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[1] ; clk ; clk ; None ; None ; 8.486 ns ;
|
|
||||||
; N/A ; 109.06 MHz ( period = 9.169 ns ) ; cnt[7] ; cnt[3] ; clk ; clk ; None ; None ; 8.460 ns ;
|
|
||||||
; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[2] ; clk ; clk ; None ; None ; 8.446 ns ;
|
|
||||||
; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[5] ; clk ; clk ; None ; None ; 8.446 ns ;
|
|
||||||
; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[3] ; clk ; clk ; None ; None ; 8.446 ns ;
|
|
||||||
; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[4] ; clk ; clk ; None ; None ; 8.446 ns ;
|
|
||||||
; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[17] ; cnt[16] ; clk ; clk ; None ; None ; 8.446 ns ;
|
|
||||||
; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[1] ; clk ; clk ; None ; None ; 8.446 ns ;
|
|
||||||
; N/A ; 109.27 MHz ( period = 9.152 ns ) ; cnt[11] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.443 ns ;
|
|
||||||
; N/A ; 109.28 MHz ( period = 9.151 ns ) ; cnt[11] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.442 ns ;
|
|
||||||
; N/A ; 109.28 MHz ( period = 9.151 ns ) ; cnt[2] ; cnt[14] ; clk ; clk ; None ; None ; 8.442 ns ;
|
|
||||||
; N/A ; 109.28 MHz ( period = 9.151 ns ) ; cnt[2] ; cnt[2] ; clk ; clk ; None ; None ; 8.442 ns ;
|
|
||||||
; N/A ; 109.35 MHz ( period = 9.145 ns ) ; cnt[11] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.436 ns ;
|
|
||||||
; N/A ; 109.36 MHz ( period = 9.144 ns ) ; cnt[11] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.435 ns ;
|
|
||||||
; N/A ; 109.43 MHz ( period = 9.138 ns ) ; cnt[17] ; cnt[19] ; clk ; clk ; None ; None ; 8.429 ns ;
|
|
||||||
; N/A ; 109.63 MHz ( period = 9.122 ns ) ; cnt[6] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.413 ns ;
|
|
||||||
; N/A ; 109.64 MHz ( period = 9.121 ns ) ; cnt[6] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.412 ns ;
|
|
||||||
; N/A ; 109.67 MHz ( period = 9.118 ns ) ; cnt[11] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.409 ns ;
|
|
||||||
; N/A ; 109.67 MHz ( period = 9.118 ns ) ; cnt[6] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.409 ns ;
|
|
||||||
; N/A ; 109.67 MHz ( period = 9.118 ns ) ; cnt[7] ; cnt[14] ; clk ; clk ; None ; None ; 8.409 ns ;
|
|
||||||
; N/A ; 109.67 MHz ( period = 9.118 ns ) ; cnt[7] ; cnt[2] ; clk ; clk ; None ; None ; 8.409 ns ;
|
|
||||||
; N/A ; 109.69 MHz ( period = 9.117 ns ) ; cnt[11] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.408 ns ;
|
|
||||||
; N/A ; 109.69 MHz ( period = 9.117 ns ) ; cnt[16] ; cnt[16] ; clk ; clk ; None ; None ; 8.408 ns ;
|
|
||||||
; N/A ; 109.70 MHz ( period = 9.116 ns ) ; cnt[11] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.407 ns ;
|
|
||||||
; N/A ; 109.75 MHz ( period = 9.112 ns ) ; cnt[6] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.403 ns ;
|
|
||||||
; N/A ; 109.77 MHz ( period = 9.110 ns ) ; cnt[11] ; cnt[12] ; clk ; clk ; None ; None ; 8.401 ns ;
|
|
||||||
; N/A ; 109.78 MHz ( period = 9.109 ns ) ; cnt[3] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.400 ns ;
|
|
||||||
; N/A ; 109.79 MHz ( period = 9.108 ns ) ; cnt[3] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.399 ns ;
|
|
||||||
; N/A ; 109.79 MHz ( period = 9.108 ns ) ; cnt[11] ; cnt[7] ; clk ; clk ; None ; None ; 8.399 ns ;
|
|
||||||
; N/A ; 109.87 MHz ( period = 9.102 ns ) ; cnt[3] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.393 ns ;
|
|
||||||
; N/A ; 109.88 MHz ( period = 9.101 ns ) ; cnt[3] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.392 ns ;
|
|
||||||
; N/A ; 109.99 MHz ( period = 9.092 ns ) ; cnt[7] ; cnt[19] ; clk ; clk ; None ; None ; 8.383 ns ;
|
|
||||||
; N/A ; 110.11 MHz ( period = 9.082 ns ) ; cnt[1] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.373 ns ;
|
|
||||||
; N/A ; 110.12 MHz ( period = 9.081 ns ) ; cnt[1] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.372 ns ;
|
|
||||||
; N/A ; 110.16 MHz ( period = 9.078 ns ) ; cnt[1] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.369 ns ;
|
|
||||||
; N/A ; 110.19 MHz ( period = 9.075 ns ) ; cnt[3] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.366 ns ;
|
|
||||||
; N/A ; 110.20 MHz ( period = 9.074 ns ) ; cnt[3] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.365 ns ;
|
|
||||||
; N/A ; 110.22 MHz ( period = 9.073 ns ) ; cnt[3] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.364 ns ;
|
|
||||||
; N/A ; 110.23 MHz ( period = 9.072 ns ) ; cnt[1] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.363 ns ;
|
|
||||||
; N/A ; 110.29 MHz ( period = 9.067 ns ) ; cnt[3] ; cnt[12] ; clk ; clk ; None ; None ; 8.358 ns ;
|
|
||||||
; N/A ; 110.31 MHz ( period = 9.065 ns ) ; cnt[3] ; cnt[7] ; clk ; clk ; None ; None ; 8.356 ns ;
|
|
||||||
; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[2] ; clk ; clk ; None ; None ; 8.347 ns ;
|
|
||||||
; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[5] ; clk ; clk ; None ; None ; 8.347 ns ;
|
|
||||||
; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[3] ; clk ; clk ; None ; None ; 8.347 ns ;
|
|
||||||
; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[4] ; clk ; clk ; None ; None ; 8.347 ns ;
|
|
||||||
; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[1] ; clk ; clk ; None ; None ; 8.347 ns ;
|
|
||||||
; N/A ; 110.46 MHz ( period = 9.053 ns ) ; cnt[11] ; cnt[13] ; clk ; clk ; None ; None ; 8.344 ns ;
|
|
||||||
; N/A ; 110.50 MHz ( period = 9.050 ns ) ; cnt[6] ; cnt[3] ; clk ; clk ; None ; None ; 8.341 ns ;
|
|
||||||
; N/A ; 110.58 MHz ( period = 9.043 ns ) ; cnt[17] ; timer[0] ; clk ; clk ; None ; None ; 8.334 ns ;
|
|
||||||
; N/A ; 110.73 MHz ( period = 9.031 ns ) ; cnt[2] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.322 ns ;
|
|
||||||
; N/A ; 110.74 MHz ( period = 9.030 ns ) ; cnt[2] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.321 ns ;
|
|
||||||
; N/A ; 110.82 MHz ( period = 9.024 ns ) ; cnt[10] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.315 ns ;
|
|
||||||
; N/A ; 110.82 MHz ( period = 9.024 ns ) ; cnt[2] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.315 ns ;
|
|
||||||
; N/A ; 110.83 MHz ( period = 9.023 ns ) ; cnt[2] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.314 ns ;
|
|
||||||
; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[2] ; clk ; clk ; None ; None ; 8.309 ns ;
|
|
||||||
; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[5] ; clk ; clk ; None ; None ; 8.309 ns ;
|
|
||||||
; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[3] ; clk ; clk ; None ; None ; 8.309 ns ;
|
|
||||||
; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[4] ; clk ; clk ; None ; None ; 8.309 ns ;
|
|
||||||
; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[1] ; clk ; clk ; None ; None ; 8.309 ns ;
|
|
||||||
; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[2] ; clk ; clk ; None ; None ; 8.302 ns ;
|
|
||||||
; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[5] ; clk ; clk ; None ; None ; 8.302 ns ;
|
|
||||||
; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[3] ; clk ; clk ; None ; None ; 8.302 ns ;
|
|
||||||
; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[4] ; clk ; clk ; None ; None ; 8.302 ns ;
|
|
||||||
; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[1] ; clk ; clk ; None ; None ; 8.302 ns ;
|
|
||||||
; N/A ; 110.99 MHz ( period = 9.010 ns ) ; cnt[3] ; cnt[13] ; clk ; clk ; None ; None ; 8.301 ns ;
|
|
||||||
; N/A ; 110.99 MHz ( period = 9.010 ns ) ; cnt[1] ; cnt[3] ; clk ; clk ; None ; None ; 8.301 ns ;
|
|
||||||
; N/A ; 111.12 MHz ( period = 8.999 ns ) ; cnt[6] ; cnt[14] ; clk ; clk ; None ; None ; 8.290 ns ;
|
|
||||||
; N/A ; 111.12 MHz ( period = 8.999 ns ) ; cnt[6] ; cnt[2] ; clk ; clk ; None ; None ; 8.290 ns ;
|
|
||||||
; N/A ; 111.14 MHz ( period = 8.998 ns ) ; cnt[7] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.289 ns ;
|
|
||||||
; N/A ; 111.15 MHz ( period = 8.997 ns ) ; cnt[2] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.288 ns ;
|
|
||||||
; N/A ; 111.15 MHz ( period = 8.997 ns ) ; cnt[7] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.288 ns ;
|
|
||||||
; N/A ; 111.16 MHz ( period = 8.996 ns ) ; cnt[2] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.287 ns ;
|
|
||||||
; N/A ; 111.17 MHz ( period = 8.995 ns ) ; cnt[2] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.286 ns ;
|
|
||||||
; N/A ; 111.22 MHz ( period = 8.991 ns ) ; cnt[7] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.282 ns ;
|
|
||||||
; N/A ; 111.23 MHz ( period = 8.990 ns ) ; cnt[7] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.281 ns ;
|
|
||||||
; N/A ; 111.25 MHz ( period = 8.989 ns ) ; cnt[2] ; cnt[12] ; clk ; clk ; None ; None ; 8.280 ns ;
|
|
||||||
; N/A ; 111.26 MHz ( period = 8.988 ns ) ; cnt[11] ; S_PFr2[46] ; clk ; clk ; None ; None ; 8.279 ns ;
|
|
||||||
; N/A ; 111.27 MHz ( period = 8.987 ns ) ; cnt[2] ; cnt[7] ; clk ; clk ; None ; None ; 8.278 ns ;
|
|
||||||
; N/A ; 111.30 MHz ( period = 8.985 ns ) ; cnt[11] ; S_PFr2[10] ; clk ; clk ; None ; None ; 8.276 ns ;
|
|
||||||
; N/A ; 111.32 MHz ( period = 8.983 ns ) ; cnt[16] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.274 ns ;
|
|
||||||
; N/A ; 111.33 MHz ( period = 8.982 ns ) ; cnt[16] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.273 ns ;
|
|
||||||
; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[2] ; clk ; clk ; None ; None ; 8.272 ns ;
|
|
||||||
; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[5] ; clk ; clk ; None ; None ; 8.272 ns ;
|
|
||||||
; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[3] ; clk ; clk ; None ; None ; 8.272 ns ;
|
|
||||||
; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[4] ; clk ; clk ; None ; None ; 8.272 ns ;
|
|
||||||
; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[1] ; clk ; clk ; None ; None ; 8.272 ns ;
|
|
||||||
; N/A ; 111.36 MHz ( period = 8.980 ns ) ; cnt[11] ; S_PFr2[12] ; clk ; clk ; None ; None ; 8.271 ns ;
|
|
||||||
; N/A ; 111.36 MHz ( period = 8.980 ns ) ; cnt[11] ; S_PFr2[15] ; clk ; clk ; None ; None ; 8.271 ns ;
|
|
||||||
; N/A ; 111.37 MHz ( period = 8.979 ns ) ; cnt[16] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.270 ns ;
|
|
||||||
; N/A ; 111.45 MHz ( period = 8.973 ns ) ; cnt[16] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.264 ns ;
|
|
||||||
; N/A ; 111.56 MHz ( period = 8.964 ns ) ; cnt[7] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.255 ns ;
|
|
||||||
; N/A ; 111.57 MHz ( period = 8.963 ns ) ; cnt[7] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.254 ns ;
|
|
||||||
; N/A ; 111.58 MHz ( period = 8.962 ns ) ; cnt[7] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.253 ns ;
|
|
||||||
; N/A ; 111.62 MHz ( period = 8.959 ns ) ; cnt[1] ; cnt[14] ; clk ; clk ; None ; None ; 8.250 ns ;
|
|
||||||
; N/A ; 111.62 MHz ( period = 8.959 ns ) ; cnt[1] ; cnt[2] ; clk ; clk ; None ; None ; 8.250 ns ;
|
|
||||||
; N/A ; 111.66 MHz ( period = 8.956 ns ) ; cnt[7] ; cnt[12] ; clk ; clk ; None ; None ; 8.247 ns ;
|
|
||||||
; N/A ; 111.68 MHz ( period = 8.954 ns ) ; cnt[7] ; cnt[7] ; clk ; clk ; None ; None ; 8.245 ns ;
|
|
||||||
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
|
|
||||||
+-----------------------------------------+-----------------------------------------------------+---------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
||||||
; Clock Setup: 'SCLK' ;
|
|
||||||
+-----------------------------------------+-----------------------------------------------------+------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
|
|
||||||
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
|
|
||||||
+-----------------------------------------+-----------------------------------------------------+------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
|
|
||||||
; N/A ; 126.07 MHz ( period = 7.932 ns ) ; i[4] ; S_PFr[44] ; SCLK ; SCLK ; None ; None ; 7.223 ns ;
|
|
||||||
; N/A ; 130.94 MHz ( period = 7.637 ns ) ; i[4] ; S_PFr[14] ; SCLK ; SCLK ; None ; None ; 6.928 ns ;
|
|
||||||
; N/A ; 131.03 MHz ( period = 7.632 ns ) ; i[4] ; S_PFr[12] ; SCLK ; SCLK ; None ; None ; 6.923 ns ;
|
|
||||||
; N/A ; 131.06 MHz ( period = 7.630 ns ) ; i[4] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 6.921 ns ;
|
|
||||||
; N/A ; 131.48 MHz ( period = 7.606 ns ) ; i[4] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 6.897 ns ;
|
|
||||||
; N/A ; 131.58 MHz ( period = 7.600 ns ) ; i[4] ; S_PFr[36] ; SCLK ; SCLK ; None ; None ; 6.891 ns ;
|
|
||||||
; N/A ; 132.17 MHz ( period = 7.566 ns ) ; i[4] ; S_PFr[34] ; SCLK ; SCLK ; None ; None ; 6.857 ns ;
|
|
||||||
; N/A ; 132.36 MHz ( period = 7.555 ns ) ; i[4] ; S_PFr[32] ; SCLK ; SCLK ; None ; None ; 6.846 ns ;
|
|
||||||
; N/A ; 134.16 MHz ( period = 7.454 ns ) ; i[4] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 6.745 ns ;
|
|
||||||
; N/A ; 135.41 MHz ( period = 7.385 ns ) ; i[5] ; S_PFr[14] ; SCLK ; SCLK ; None ; None ; 6.676 ns ;
|
|
||||||
; N/A ; 135.48 MHz ( period = 7.381 ns ) ; i[0] ; S_PFr[44] ; SCLK ; SCLK ; None ; None ; 6.672 ns ;
|
|
||||||
; N/A ; 135.50 MHz ( period = 7.380 ns ) ; i[5] ; S_PFr[12] ; SCLK ; SCLK ; None ; None ; 6.671 ns ;
|
|
||||||
; N/A ; 135.54 MHz ( period = 7.378 ns ) ; i[5] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 6.669 ns ;
|
|
||||||
; N/A ; 135.63 MHz ( period = 7.373 ns ) ; i[4] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 6.664 ns ;
|
|
||||||
; N/A ; 136.04 MHz ( period = 7.351 ns ) ; i[0] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 6.642 ns ;
|
|
||||||
; N/A ; 136.05 MHz ( period = 7.350 ns ) ; i[2] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 6.641 ns ;
|
|
||||||
; N/A ; 136.84 MHz ( period = 7.308 ns ) ; i[4] ; S_PFr[5] ; SCLK ; SCLK ; None ; None ; 6.599 ns ;
|
|
||||||
; N/A ; 137.38 MHz ( period = 7.279 ns ) ; i[0] ; S_PFr[14] ; SCLK ; SCLK ; None ; None ; 6.570 ns ;
|
|
||||||
; N/A ; 137.48 MHz ( period = 7.274 ns ) ; i[0] ; S_PFr[12] ; SCLK ; SCLK ; None ; None ; 6.565 ns ;
|
|
||||||
; N/A ; 137.51 MHz ( period = 7.272 ns ) ; i[0] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 6.563 ns ;
|
|
||||||
; N/A ; 137.82 MHz ( period = 7.256 ns ) ; i[4] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 6.547 ns ;
|
|
||||||
; N/A ; 138.06 MHz ( period = 7.243 ns ) ; i[4] ; S_PFr[39] ; SCLK ; SCLK ; None ; None ; 6.534 ns ;
|
|
||||||
; N/A ; 139.06 MHz ( period = 7.191 ns ) ; i[4] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 6.482 ns ;
|
|
||||||
; N/A ; 139.88 MHz ( period = 7.149 ns ) ; i[4] ; S_PFr[21] ; SCLK ; SCLK ; None ; None ; 6.440 ns ;
|
|
||||||
; N/A ; 139.88 MHz ( period = 7.149 ns ) ; i[4] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 6.440 ns ;
|
|
||||||
; N/A ; 139.90 MHz ( period = 7.148 ns ) ; i[2] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 6.439 ns ;
|
|
||||||
; N/A ; 139.94 MHz ( period = 7.146 ns ) ; i[5] ; S_PFr[5] ; SCLK ; SCLK ; None ; None ; 6.437 ns ;
|
|
||||||
; N/A ; 139.98 MHz ( period = 7.144 ns ) ; i[2] ; S_PFr[23] ; SCLK ; SCLK ; None ; None ; 6.435 ns ;
|
|
||||||
; N/A ; 140.10 MHz ( period = 7.138 ns ) ; i[2] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 6.429 ns ;
|
|
||||||
; N/A ; 140.23 MHz ( period = 7.131 ns ) ; i[2] ; S_PFr[0] ; SCLK ; SCLK ; None ; None ; 6.422 ns ;
|
|
||||||
; N/A ; 141.88 MHz ( period = 7.048 ns ) ; i[5] ; S_PFr[44] ; SCLK ; SCLK ; None ; None ; 6.339 ns ;
|
|
||||||
; N/A ; 141.92 MHz ( period = 7.046 ns ) ; i[0] ; S_PFr[21] ; SCLK ; SCLK ; None ; None ; 6.337 ns ;
|
|
||||||
; N/A ; 141.92 MHz ( period = 7.046 ns ) ; i[0] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 6.337 ns ;
|
|
||||||
; N/A ; 142.69 MHz ( period = 7.008 ns ) ; i[5] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 6.299 ns ;
|
|
||||||
; N/A ; 143.86 MHz ( period = 6.951 ns ) ; i[3] ; S_PFr[5] ; SCLK ; SCLK ; None ; None ; 6.242 ns ;
|
|
||||||
; N/A ; 144.22 MHz ( period = 6.934 ns ) ; i[5] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 6.225 ns ;
|
|
||||||
; N/A ; 144.89 MHz ( period = 6.902 ns ) ; i[3] ; S_PFr[44] ; SCLK ; SCLK ; None ; None ; 6.193 ns ;
|
|
||||||
; N/A ; 145.07 MHz ( period = 6.893 ns ) ; i[4] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 6.184 ns ;
|
|
||||||
; N/A ; 145.12 MHz ( period = 6.891 ns ) ; i[4] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 6.182 ns ;
|
|
||||||
; N/A ; 145.22 MHz ( period = 6.886 ns ) ; i[3] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 6.177 ns ;
|
|
||||||
; N/A ; 145.29 MHz ( period = 6.883 ns ) ; i[3] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 6.174 ns ;
|
|
||||||
; N/A ; 145.35 MHz ( period = 6.880 ns ) ; i[4] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 6.171 ns ;
|
|
||||||
; N/A ; 145.35 MHz ( period = 6.880 ns ) ; i[4] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 6.171 ns ;
|
|
||||||
; N/A ; 145.41 MHz ( period = 6.877 ns ) ; i[4] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 6.168 ns ;
|
|
||||||
; N/A ; 145.52 MHz ( period = 6.872 ns ) ; i[3] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 6.163 ns ;
|
|
||||||
; N/A ; 145.58 MHz ( period = 6.869 ns ) ; i[3] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 6.160 ns ;
|
|
||||||
; N/A ; 145.62 MHz ( period = 6.867 ns ) ; i[1] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 6.158 ns ;
|
|
||||||
; N/A ; 146.71 MHz ( period = 6.816 ns ) ; i[2] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 6.107 ns ;
|
|
||||||
; N/A ; 146.78 MHz ( period = 6.813 ns ) ; i[2] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 6.104 ns ;
|
|
||||||
; N/A ; 146.97 MHz ( period = 6.804 ns ) ; i[2] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 6.095 ns ;
|
|
||||||
; N/A ; 147.04 MHz ( period = 6.801 ns ) ; i[2] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 6.092 ns ;
|
|
||||||
; N/A ; 147.86 MHz ( period = 6.763 ns ) ; i[0] ; S_PFr[5] ; SCLK ; SCLK ; None ; None ; 6.054 ns ;
|
|
||||||
; N/A ; 148.04 MHz ( period = 6.755 ns ) ; i[4] ; S_PFr[13] ; SCLK ; SCLK ; None ; None ; 6.046 ns ;
|
|
||||||
; N/A ; 148.37 MHz ( period = 6.740 ns ) ; i[4] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 6.031 ns ;
|
|
||||||
; N/A ; 148.43 MHz ( period = 6.737 ns ) ; i[4] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 6.028 ns ;
|
|
||||||
; N/A ; 148.85 MHz ( period = 6.718 ns ) ; i[5] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 6.009 ns ;
|
|
||||||
; N/A ; 148.85 MHz ( period = 6.718 ns ) ; i[5] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 6.009 ns ;
|
|
||||||
; N/A ; 149.12 MHz ( period = 6.706 ns ) ; i[3] ; S_PFr[36] ; SCLK ; SCLK ; None ; None ; 5.997 ns ;
|
|
||||||
; N/A ; 149.14 MHz ( period = 6.705 ns ) ; i[0] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 5.996 ns ;
|
|
||||||
; N/A ; 149.77 MHz ( period = 6.677 ns ) ; i[1] ; S_PFr[26] ; SCLK ; SCLK ; None ; None ; 5.968 ns ;
|
|
||||||
; N/A ; 149.81 MHz ( period = 6.675 ns ) ; i[1] ; S_PFr[27] ; SCLK ; SCLK ; None ; None ; 5.966 ns ;
|
|
||||||
; N/A ; 149.88 MHz ( period = 6.672 ns ) ; i[3] ; S_PFr[34] ; SCLK ; SCLK ; None ; None ; 5.963 ns ;
|
|
||||||
; N/A ; 149.88 MHz ( period = 6.672 ns ) ; i[4] ; S_PFr[38] ; SCLK ; SCLK ; None ; None ; 5.963 ns ;
|
|
||||||
; N/A ; 149.97 MHz ( period = 6.668 ns ) ; i[3] ; S_PFr[26] ; SCLK ; SCLK ; None ; None ; 5.959 ns ;
|
|
||||||
; N/A ; 150.02 MHz ( period = 6.666 ns ) ; i[3] ; S_PFr[27] ; SCLK ; SCLK ; None ; None ; 5.957 ns ;
|
|
||||||
; N/A ; 150.13 MHz ( period = 6.661 ns ) ; i[3] ; S_PFr[32] ; SCLK ; SCLK ; None ; None ; 5.952 ns ;
|
|
||||||
; N/A ; 150.20 MHz ( period = 6.658 ns ) ; i[5] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 5.949 ns ;
|
|
||||||
; N/A ; 150.26 MHz ( period = 6.655 ns ) ; i[1] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 5.946 ns ;
|
|
||||||
; N/A ; 150.35 MHz ( period = 6.651 ns ) ; i[3] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 5.942 ns ;
|
|
||||||
; N/A ; 150.42 MHz ( period = 6.648 ns ) ; i[1] ; S_PFr[0] ; SCLK ; SCLK ; None ; None ; 5.939 ns ;
|
|
||||||
; N/A ; 150.58 MHz ( period = 6.641 ns ) ; i[5] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 5.932 ns ;
|
|
||||||
; N/A ; 150.63 MHz ( period = 6.639 ns ) ; i[5] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.930 ns ;
|
|
||||||
; N/A ; 150.65 MHz ( period = 6.638 ns ) ; i[3] ; S_PFr[39] ; SCLK ; SCLK ; None ; None ; 5.929 ns ;
|
|
||||||
; N/A ; 150.94 MHz ( period = 6.625 ns ) ; i[5] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 5.916 ns ;
|
|
||||||
; N/A ; 151.24 MHz ( period = 6.612 ns ) ; i[1] ; S_PFr[30] ; SCLK ; SCLK ; None ; None ; 5.903 ns ;
|
|
||||||
; N/A ; 151.26 MHz ( period = 6.611 ns ) ; i[4] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 5.902 ns ;
|
|
||||||
; N/A ; 151.42 MHz ( period = 6.604 ns ) ; i[3] ; S_PFr[30] ; SCLK ; SCLK ; None ; None ; 5.895 ns ;
|
|
||||||
; N/A ; 151.49 MHz ( period = 6.601 ns ) ; i[1] ; S_PFr[31] ; SCLK ; SCLK ; None ; None ; 5.892 ns ;
|
|
||||||
; N/A ; 151.61 MHz ( period = 6.596 ns ) ; i[2] ; S_PFr[41] ; SCLK ; SCLK ; None ; None ; 5.887 ns ;
|
|
||||||
; N/A ; 151.68 MHz ( period = 6.593 ns ) ; i[3] ; S_PFr[31] ; SCLK ; SCLK ; None ; None ; 5.884 ns ;
|
|
||||||
; N/A ; 151.70 MHz ( period = 6.592 ns ) ; i[5] ; S_PFr[13] ; SCLK ; SCLK ; None ; None ; 5.883 ns ;
|
|
||||||
; N/A ; 151.77 MHz ( period = 6.589 ns ) ; i[3] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.880 ns ;
|
|
||||||
; N/A ; 151.84 MHz ( period = 6.586 ns ) ; i[5] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 5.877 ns ;
|
|
||||||
; N/A ; 152.07 MHz ( period = 6.576 ns ) ; i[2] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 5.867 ns ;
|
|
||||||
; N/A ; 152.44 MHz ( period = 6.560 ns ) ; i[0] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 5.851 ns ;
|
|
||||||
; N/A ; 152.70 MHz ( period = 6.549 ns ) ; i[2] ; S_PFr[26] ; SCLK ; SCLK ; None ; None ; 5.840 ns ;
|
|
||||||
; N/A ; 152.70 MHz ( period = 6.549 ns ) ; i[4] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 5.840 ns ;
|
|
||||||
; N/A ; 152.74 MHz ( period = 6.547 ns ) ; i[2] ; S_PFr[27] ; SCLK ; SCLK ; None ; None ; 5.838 ns ;
|
|
||||||
; N/A ; 153.02 MHz ( period = 6.535 ns ) ; i[0] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 5.826 ns ;
|
|
||||||
; N/A ; 153.07 MHz ( period = 6.533 ns ) ; i[0] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.824 ns ;
|
|
||||||
; N/A ; 153.30 MHz ( period = 6.523 ns ) ; i[3] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 5.814 ns ;
|
|
||||||
; N/A ; 153.30 MHz ( period = 6.523 ns ) ; i[3] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 5.814 ns ;
|
|
||||||
; N/A ; 153.40 MHz ( period = 6.519 ns ) ; i[0] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 5.810 ns ;
|
|
||||||
; N/A ; 153.54 MHz ( period = 6.513 ns ) ; i[2] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.804 ns ;
|
|
||||||
; N/A ; 153.54 MHz ( period = 6.513 ns ) ; i[1] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 5.804 ns ;
|
|
||||||
; N/A ; 153.70 MHz ( period = 6.506 ns ) ; i[0] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 5.797 ns ;
|
|
||||||
; N/A ; 153.75 MHz ( period = 6.504 ns ) ; i[3] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 5.795 ns ;
|
|
||||||
; N/A ; 153.87 MHz ( period = 6.499 ns ) ; i[0] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 5.790 ns ;
|
|
||||||
; N/A ; 154.08 MHz ( period = 6.490 ns ) ; i[5] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 5.781 ns ;
|
|
||||||
; N/A ; 154.23 MHz ( period = 6.484 ns ) ; i[2] ; S_PFr[30] ; SCLK ; SCLK ; None ; None ; 5.775 ns ;
|
|
||||||
; N/A ; 154.25 MHz ( period = 6.483 ns ) ; i[5] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 5.774 ns ;
|
|
||||||
; N/A ; 154.32 MHz ( period = 6.480 ns ) ; i[5] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 5.771 ns ;
|
|
||||||
; N/A ; 154.49 MHz ( period = 6.473 ns ) ; i[2] ; S_PFr[31] ; SCLK ; SCLK ; None ; None ; 5.764 ns ;
|
|
||||||
; N/A ; 154.94 MHz ( period = 6.454 ns ) ; i[1] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 5.745 ns ;
|
|
||||||
; N/A ; 154.99 MHz ( period = 6.452 ns ) ; i[0] ; S_PFr[39] ; SCLK ; SCLK ; None ; None ; 5.743 ns ;
|
|
||||||
; N/A ; 155.01 MHz ( period = 6.451 ns ) ; i[1] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 5.742 ns ;
|
|
||||||
; N/A ; 155.09 MHz ( period = 6.448 ns ) ; i[5] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 5.739 ns ;
|
|
||||||
; N/A ; 155.23 MHz ( period = 6.442 ns ) ; i[1] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 5.733 ns ;
|
|
||||||
; N/A ; 155.30 MHz ( period = 6.439 ns ) ; i[1] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 5.730 ns ;
|
|
||||||
; N/A ; 155.81 MHz ( period = 6.418 ns ) ; i[3] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 5.709 ns ;
|
|
||||||
; N/A ; 155.88 MHz ( period = 6.415 ns ) ; i[2] ; S_PFr[35] ; SCLK ; SCLK ; None ; None ; 5.706 ns ;
|
|
||||||
; N/A ; 155.96 MHz ( period = 6.412 ns ) ; i[2] ; S_PFr[11] ; SCLK ; SCLK ; None ; None ; 5.703 ns ;
|
|
||||||
; N/A ; 155.98 MHz ( period = 6.411 ns ) ; i[2] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 5.702 ns ;
|
|
||||||
; N/A ; 156.40 MHz ( period = 6.394 ns ) ; i[2] ; S_PFr[9] ; SCLK ; SCLK ; None ; None ; 5.685 ns ;
|
|
||||||
; N/A ; 156.62 MHz ( period = 6.385 ns ) ; i[2] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 5.676 ns ;
|
|
||||||
; N/A ; 156.62 MHz ( period = 6.385 ns ) ; i[3] ; S_PFr[13] ; SCLK ; SCLK ; None ; None ; 5.676 ns ;
|
|
||||||
; N/A ; 156.67 MHz ( period = 6.383 ns ) ; i[2] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 5.674 ns ;
|
|
||||||
; N/A ; 156.94 MHz ( period = 6.372 ns ) ; i[5] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 5.663 ns ;
|
|
||||||
; N/A ; 157.41 MHz ( period = 6.353 ns ) ; i[5] ; S_PFr[21] ; SCLK ; SCLK ; None ; None ; 5.644 ns ;
|
|
||||||
; N/A ; 157.41 MHz ( period = 6.353 ns ) ; i[5] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 5.644 ns ;
|
|
||||||
; N/A ; 157.70 MHz ( period = 6.341 ns ) ; i[1] ; S_PFr[29] ; SCLK ; SCLK ; None ; None ; 5.632 ns ;
|
|
||||||
; N/A ; 157.73 MHz ( period = 6.340 ns ) ; i[0] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 5.631 ns ;
|
|
||||||
; N/A ; 157.75 MHz ( period = 6.339 ns ) ; i[3] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 5.630 ns ;
|
|
||||||
; N/A ; 157.80 MHz ( period = 6.337 ns ) ; i[1] ; S_PFr[28] ; SCLK ; SCLK ; None ; None ; 5.628 ns ;
|
|
||||||
; N/A ; 157.85 MHz ( period = 6.335 ns ) ; i[0] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 5.626 ns ;
|
|
||||||
; N/A ; 157.85 MHz ( period = 6.335 ns ) ; i[0] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 5.626 ns ;
|
|
||||||
; N/A ; 157.93 MHz ( period = 6.332 ns ) ; i[3] ; S_PFr[29] ; SCLK ; SCLK ; None ; None ; 5.623 ns ;
|
|
||||||
; N/A ; 158.03 MHz ( period = 6.328 ns ) ; i[3] ; S_PFr[28] ; SCLK ; SCLK ; None ; None ; 5.619 ns ;
|
|
||||||
; N/A ; 158.81 MHz ( period = 6.297 ns ) ; i[4] ; S_PFr[35] ; SCLK ; SCLK ; None ; None ; 5.588 ns ;
|
|
||||||
; N/A ; 159.11 MHz ( period = 6.285 ns ) ; i[5] ; S_PFr[39] ; SCLK ; SCLK ; None ; None ; 5.576 ns ;
|
|
||||||
; N/A ; 159.82 MHz ( period = 6.257 ns ) ; i[5] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 5.548 ns ;
|
|
||||||
; N/A ; 160.23 MHz ( period = 6.241 ns ) ; i[3] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 5.532 ns ;
|
|
||||||
; N/A ; 160.41 MHz ( period = 6.234 ns ) ; i[5] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 5.525 ns ;
|
|
||||||
; N/A ; 160.62 MHz ( period = 6.226 ns ) ; i[3] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 5.517 ns ;
|
|
||||||
; N/A ; 160.95 MHz ( period = 6.213 ns ) ; i[2] ; S_PFr[29] ; SCLK ; SCLK ; None ; None ; 5.504 ns ;
|
|
||||||
; N/A ; 161.06 MHz ( period = 6.209 ns ) ; i[2] ; S_PFr[28] ; SCLK ; SCLK ; None ; None ; 5.500 ns ;
|
|
||||||
; N/A ; 161.45 MHz ( period = 6.194 ns ) ; i[1] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 5.485 ns ;
|
|
||||||
; N/A ; 161.50 MHz ( period = 6.192 ns ) ; i[0] ; S_PFr[13] ; SCLK ; SCLK ; None ; None ; 5.483 ns ;
|
|
||||||
; N/A ; 161.55 MHz ( period = 6.190 ns ) ; i[1] ; S_PFr[23] ; SCLK ; SCLK ; None ; None ; 5.481 ns ;
|
|
||||||
; N/A ; 161.58 MHz ( period = 6.189 ns ) ; i[4] ; S_PFr[37] ; SCLK ; SCLK ; None ; None ; 5.480 ns ;
|
|
||||||
; N/A ; 162.55 MHz ( period = 6.152 ns ) ; i[1] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.443 ns ;
|
|
||||||
; N/A ; 163.59 MHz ( period = 6.113 ns ) ; i[1] ; S_PFr[41] ; SCLK ; SCLK ; None ; None ; 5.404 ns ;
|
|
||||||
; N/A ; 163.69 MHz ( period = 6.109 ns ) ; i[0] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 5.400 ns ;
|
|
||||||
; N/A ; 163.75 MHz ( period = 6.107 ns ) ; i[0] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 5.398 ns ;
|
|
||||||
; N/A ; 163.77 MHz ( period = 6.106 ns ) ; i[0] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 5.397 ns ;
|
|
||||||
; N/A ; 164.18 MHz ( period = 6.091 ns ) ; i[4] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 5.382 ns ;
|
|
||||||
; N/A ; 164.20 MHz ( period = 6.090 ns ) ; i[4] ; S_PFr[6] ; SCLK ; SCLK ; None ; None ; 5.381 ns ;
|
|
||||||
; N/A ; 164.28 MHz ( period = 6.087 ns ) ; i[4] ; S_PFr[41] ; SCLK ; SCLK ; None ; None ; 5.378 ns ;
|
|
||||||
; N/A ; 164.28 MHz ( period = 6.087 ns ) ; i[4] ; S_PFr[42] ; SCLK ; SCLK ; None ; None ; 5.378 ns ;
|
|
||||||
; N/A ; 164.34 MHz ( period = 6.085 ns ) ; i[4] ; S_PFr[45] ; SCLK ; SCLK ; None ; None ; 5.376 ns ;
|
|
||||||
; N/A ; 164.42 MHz ( period = 6.082 ns ) ; i[0] ; S_PFr[23] ; SCLK ; SCLK ; None ; None ; 5.373 ns ;
|
|
||||||
; N/A ; 164.55 MHz ( period = 6.077 ns ) ; i[0] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 5.368 ns ;
|
|
||||||
; N/A ; 165.21 MHz ( period = 6.053 ns ) ; i[4] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 5.344 ns ;
|
|
||||||
; N/A ; 165.34 MHz ( period = 6.048 ns ) ; i[0] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 5.339 ns ;
|
|
||||||
; N/A ; 167.34 MHz ( period = 5.976 ns ) ; i[3] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 5.267 ns ;
|
|
||||||
; N/A ; 167.48 MHz ( period = 5.971 ns ) ; i[3] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 5.262 ns ;
|
|
||||||
; N/A ; 168.24 MHz ( period = 5.944 ns ) ; i[3] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 5.235 ns ;
|
|
||||||
; N/A ; 168.27 MHz ( period = 5.943 ns ) ; i[0] ; S_PFr[36] ; SCLK ; SCLK ; None ; None ; 5.234 ns ;
|
|
||||||
; N/A ; 168.58 MHz ( period = 5.932 ns ) ; i[1] ; S_PFr[35] ; SCLK ; SCLK ; None ; None ; 5.223 ns ;
|
|
||||||
; N/A ; 168.66 MHz ( period = 5.929 ns ) ; i[5] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 5.220 ns ;
|
|
||||||
; N/A ; 168.66 MHz ( period = 5.929 ns ) ; i[1] ; S_PFr[11] ; SCLK ; SCLK ; None ; None ; 5.220 ns ;
|
|
||||||
; N/A ; 168.69 MHz ( period = 5.928 ns ) ; i[1] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 5.219 ns ;
|
|
||||||
; N/A ; 169.00 MHz ( period = 5.917 ns ) ; i[3] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 5.208 ns ;
|
|
||||||
; N/A ; 169.18 MHz ( period = 5.911 ns ) ; i[1] ; S_PFr[9] ; SCLK ; SCLK ; None ; None ; 5.202 ns ;
|
|
||||||
; N/A ; 169.23 MHz ( period = 5.909 ns ) ; i[0] ; S_PFr[34] ; SCLK ; SCLK ; None ; None ; 5.200 ns ;
|
|
||||||
; N/A ; 169.49 MHz ( period = 5.900 ns ) ; i[1] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 5.191 ns ;
|
|
||||||
; N/A ; 169.49 MHz ( period = 5.900 ns ) ; i[2] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 5.191 ns ;
|
|
||||||
; N/A ; 169.55 MHz ( period = 5.898 ns ) ; i[0] ; S_PFr[32] ; SCLK ; SCLK ; None ; None ; 5.189 ns ;
|
|
||||||
; N/A ; 169.64 MHz ( period = 5.895 ns ) ; i[2] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 5.186 ns ;
|
|
||||||
; N/A ; 171.32 MHz ( period = 5.837 ns ) ; i[3] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 5.128 ns ;
|
|
||||||
; N/A ; 172.09 MHz ( period = 5.811 ns ) ; i[4] ; S_PFr[11] ; SCLK ; SCLK ; None ; None ; 5.102 ns ;
|
|
||||||
; N/A ; 172.12 MHz ( period = 5.810 ns ) ; i[5] ; S_PFr[23] ; SCLK ; SCLK ; None ; None ; 5.101 ns ;
|
|
||||||
; N/A ; 172.27 MHz ( period = 5.805 ns ) ; i[2] ; S_PFr[6] ; SCLK ; SCLK ; None ; None ; 5.096 ns ;
|
|
||||||
; N/A ; 172.44 MHz ( period = 5.799 ns ) ; i[4] ; S_PFr[9] ; SCLK ; SCLK ; None ; None ; 5.090 ns ;
|
|
||||||
; N/A ; 172.53 MHz ( period = 5.796 ns ) ; i[2] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 5.087 ns ;
|
|
||||||
; N/A ; 173.07 MHz ( period = 5.778 ns ) ; i[3] ; S_PFr[38] ; SCLK ; SCLK ; None ; None ; 5.069 ns ;
|
|
||||||
; N/A ; 173.34 MHz ( period = 5.769 ns ) ; i[2] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 5.060 ns ;
|
|
||||||
; N/A ; 173.67 MHz ( period = 5.758 ns ) ; i[3] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 5.049 ns ;
|
|
||||||
; N/A ; 173.67 MHz ( period = 5.758 ns ) ; i[0] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 5.049 ns ;
|
|
||||||
; N/A ; 174.40 MHz ( period = 5.734 ns ) ; i[3] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 5.025 ns ;
|
|
||||||
; N/A ; 175.69 MHz ( period = 5.692 ns ) ; i[3] ; S_PFr[35] ; SCLK ; SCLK ; None ; None ; 4.983 ns ;
|
|
||||||
; N/A ; 176.15 MHz ( period = 5.677 ns ) ; i[2] ; S_PFr[40] ; SCLK ; SCLK ; None ; None ; 4.968 ns ;
|
|
||||||
; N/A ; 176.30 MHz ( period = 5.672 ns ) ; i[2] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 4.963 ns ;
|
|
||||||
; N/A ; 176.40 MHz ( period = 5.669 ns ) ; i[2] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 4.960 ns ;
|
|
||||||
; N/A ; 176.43 MHz ( period = 5.668 ns ) ; i[4] ; S_PFr[40] ; SCLK ; SCLK ; None ; None ; 4.959 ns ;
|
|
||||||
; N/A ; 176.49 MHz ( period = 5.666 ns ) ; i[2] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 4.957 ns ;
|
|
||||||
; N/A ; 176.55 MHz ( period = 5.664 ns ) ; i[2] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 4.955 ns ;
|
|
||||||
; N/A ; 177.05 MHz ( period = 5.648 ns ) ; i[5] ; S_PFr[11] ; SCLK ; SCLK ; None ; None ; 4.939 ns ;
|
|
||||||
; N/A ; 177.43 MHz ( period = 5.636 ns ) ; i[5] ; S_PFr[9] ; SCLK ; SCLK ; None ; None ; 4.927 ns ;
|
|
||||||
; N/A ; 177.59 MHz ( period = 5.631 ns ) ; i[4] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 4.922 ns ;
|
|
||||||
; N/A ; 177.87 MHz ( period = 5.622 ns ) ; i[1] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 4.913 ns ;
|
|
||||||
; N/A ; 178.41 MHz ( period = 5.605 ns ) ; i[4] ; S_PFr[31] ; SCLK ; SCLK ; None ; None ; 4.896 ns ;
|
|
||||||
; N/A ; 178.44 MHz ( period = 5.604 ns ) ; i[4] ; S_PFr[30] ; SCLK ; SCLK ; None ; None ; 4.895 ns ;
|
|
||||||
; N/A ; 178.51 MHz ( period = 5.602 ns ) ; i[4] ; S_PFr[28] ; SCLK ; SCLK ; None ; None ; 4.893 ns ;
|
|
||||||
; N/A ; 178.57 MHz ( period = 5.600 ns ) ; i[4] ; S_PFr[27] ; SCLK ; SCLK ; None ; None ; 4.891 ns ;
|
|
||||||
; N/A ; 178.57 MHz ( period = 5.600 ns ) ; i[4] ; S_PFr[29] ; SCLK ; SCLK ; None ; None ; 4.891 ns ;
|
|
||||||
; N/A ; 178.73 MHz ( period = 5.595 ns ) ; i[4] ; S_PFr[26] ; SCLK ; SCLK ; None ; None ; 4.886 ns ;
|
|
||||||
; N/A ; 178.86 MHz ( period = 5.591 ns ) ; i[5] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 4.882 ns ;
|
|
||||||
; N/A ; 179.08 MHz ( period = 5.584 ns ) ; i[3] ; S_PFr[37] ; SCLK ; SCLK ; None ; None ; 4.875 ns ;
|
|
||||||
; N/A ; 180.31 MHz ( period = 5.546 ns ) ; i[0] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 4.837 ns ;
|
|
||||||
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
|
|
||||||
+-----------------------------------------+-----------------------------------------------------+------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
|
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------+
|
|
||||||
; tsu ;
|
|
||||||
+-------+--------------+------------+-------+-----------+----------+
|
|
||||||
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
|
|
||||||
+-------+--------------+------------+-------+-----------+----------+
|
|
||||||
; N/A ; None ; 3.893 ns ; SEN ; S_PFr[44] ; SCLK ;
|
|
||||||
; N/A ; None ; 3.567 ns ; SEN ; S_PFr[47] ; SCLK ;
|
|
||||||
; N/A ; None ; 3.561 ns ; SEN ; S_PFr[36] ; SCLK ;
|
|
||||||
; N/A ; None ; 3.527 ns ; SEN ; S_PFr[34] ; SCLK ;
|
|
||||||
; N/A ; None ; 3.516 ns ; SEN ; S_PFr[32] ; SCLK ;
|
|
||||||
; N/A ; None ; 3.334 ns ; SEN ; S_PFr[43] ; SCLK ;
|
|
||||||
; N/A ; None ; 3.269 ns ; SEN ; S_PFr[5] ; SCLK ;
|
|
||||||
; N/A ; None ; 3.217 ns ; SEN ; S_PFr[46] ; SCLK ;
|
|
||||||
; N/A ; None ; 3.204 ns ; SEN ; S_PFr[39] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.841 ns ; SEN ; S_PFr[1] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.841 ns ; SEN ; S_PFr[3] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.716 ns ; SEN ; S_PFr[13] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.655 ns ; SEN ; S_PFr[19] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.633 ns ; SEN ; S_PFr[38] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.572 ns ; SEN ; S_PFr[15] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.510 ns ; SEN ; S_PFr[33] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.390 ns ; SEN ; S_PFr[18] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.350 ns ; SEN ; S_PFr[21] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.350 ns ; SEN ; S_PFr[25] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.258 ns ; SEN ; S_PFr[35] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.150 ns ; SEN ; S_PFr[37] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.138 ns ; SEN ; S_PFr[16] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.134 ns ; SEN ; S_PFr[17] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.052 ns ; SEN ; S_PFr[7] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.051 ns ; SEN ; S_PFr[6] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.048 ns ; SEN ; S_PFr[14] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.048 ns ; SEN ; S_PFr[41] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.048 ns ; SEN ; S_PFr[42] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.046 ns ; SEN ; S_PFr[45] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.043 ns ; SEN ; S_PFr[12] ; SCLK ;
|
|
||||||
; N/A ; None ; 2.041 ns ; SEN ; S_PFr[10] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.939 ns ; SEN ; S_PFr[24] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.936 ns ; SEN ; S_PFr[20] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.772 ns ; SEN ; S_PFr[11] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.760 ns ; SEN ; S_PFr[9] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.716 ns ; SEN ; S_PFr[22] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.710 ns ; SEN ; S_PFr[23] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.629 ns ; SEN ; S_PFr[40] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.617 ns ; SDATA ; S_PFr[31] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.616 ns ; SDATA ; S_PFr[26] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.612 ns ; SDATA ; S_PFr[29] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.608 ns ; SDATA ; S_PFr[28] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.606 ns ; SDATA ; S_PFr[30] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.605 ns ; SDATA ; S_PFr[27] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.597 ns ; SDATA ; S_PFr[1] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.597 ns ; SDATA ; S_PFr[3] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.596 ns ; SDATA ; S_PFr[11] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.592 ns ; SDATA ; S_PFr[35] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.581 ns ; SDATA ; S_PFr[9] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.553 ns ; SDATA ; S_PFr[23] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.547 ns ; SDATA ; S_PFr[16] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.498 ns ; SDATA ; S_PFr[17] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.491 ns ; SDATA ; S_PFr[22] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.452 ns ; SEN ; S_PFr[0] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.438 ns ; SDATA ; S_PFr[41] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.304 ns ; SEN ; S_PFr[8] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.302 ns ; SEN ; S_PFr[2] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.299 ns ; SDATA ; S_PFr[21] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.299 ns ; SDATA ; S_PFr[25] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.288 ns ; SEN ; S_PFr[4] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.197 ns ; SDATA ; S_PFr[45] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.115 ns ; SDATA ; S_PFr[7] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.076 ns ; SDATA ; S_PFr[36] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.041 ns ; SDATA ; S_PFr[38] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.013 ns ; SDATA ; S_PFr[10] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.012 ns ; SDATA ; S_PFr[12] ; SCLK ;
|
|
||||||
; N/A ; None ; 1.003 ns ; SDATA ; S_PFr[14] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.969 ns ; SDATA ; S_PFr[6] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.910 ns ; SDATA ; S_PFr[0] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.841 ns ; SDATA ; S_PFr[4] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.839 ns ; SDATA ; S_PFr[20] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.835 ns ; SDATA ; S_PFr[24] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.833 ns ; SDATA ; S_PFr[2] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.826 ns ; SDATA ; S_PFr[8] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.824 ns ; SDATA ; S_PFr[19] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.813 ns ; SDATA ; S_PFr[18] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.810 ns ; SDATA ; S_PFr[42] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.809 ns ; SDATA ; S_PFr[34] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.806 ns ; SEN ; S_PFr[31] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.803 ns ; SEN ; S_PFr[30] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.801 ns ; SEN ; S_PFr[27] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.801 ns ; SEN ; S_PFr[28] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.801 ns ; SEN ; S_PFr[29] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.798 ns ; SDATA ; S_PFr[43] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.794 ns ; SEN ; S_PFr[26] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.776 ns ; SDATA ; S_PFr[37] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.775 ns ; SDATA ; S_PFr[44] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.774 ns ; SDATA ; S_PFr[13] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.765 ns ; SDATA ; S_PFr[5] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.743 ns ; SDATA ; S_PFr[47] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.741 ns ; SDATA ; S_PFr[39] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.740 ns ; SDATA ; S_PFr[46] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.730 ns ; SDATA ; S_PFr[15] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.598 ns ; SDATA ; S_PFr[33] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.590 ns ; SDATA ; S_PFr[40] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.527 ns ; SDATA ; S_PFr[32] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.482 ns ; SEN ; i[2] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.482 ns ; SEN ; i[1] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.482 ns ; SEN ; i[0] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.482 ns ; SEN ; i[5] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.482 ns ; SEN ; i[3] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.482 ns ; SEN ; i[4] ; SCLK ;
|
|
||||||
+-------+--------------+------------+-------+-----------+----------+
|
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------+
|
|
||||||
; tco ;
|
|
||||||
+-------+--------------+------------+------------+----------+------------+
|
|
||||||
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
|
|
||||||
+-------+--------------+------------+------------+----------+------------+
|
|
||||||
; N/A ; None ; 8.833 ns ; S_PFr2[5] ; S_PF[5] ; clk ;
|
|
||||||
; N/A ; None ; 8.819 ns ; S_PFr2[14] ; S_PF[14] ; clk ;
|
|
||||||
; N/A ; None ; 8.802 ns ; S_PFr2[26] ; S_PF[26] ; clk ;
|
|
||||||
; N/A ; None ; 8.785 ns ; S_PFr2[9] ; S_PF[9] ; clk ;
|
|
||||||
; N/A ; None ; 8.773 ns ; S_PFr2[6] ; S_PF[6] ; clk ;
|
|
||||||
; N/A ; None ; 8.755 ns ; S_PFr2[36] ; S_PF[36] ; clk ;
|
|
||||||
; N/A ; None ; 8.750 ns ; S_PFr2[11] ; S_PF[11] ; clk ;
|
|
||||||
; N/A ; None ; 8.738 ns ; S_PFr2[35] ; S_PF[35] ; clk ;
|
|
||||||
; N/A ; None ; 8.729 ns ; S_PFr2[28] ; S_PF[28] ; clk ;
|
|
||||||
; N/A ; None ; 8.703 ns ; S_PFr2[30] ; S_PF[30] ; clk ;
|
|
||||||
; N/A ; None ; 8.696 ns ; S_PFr2[4] ; S_PF[4] ; clk ;
|
|
||||||
; N/A ; None ; 8.685 ns ; S_PFr2[31] ; S_PF[31] ; clk ;
|
|
||||||
; N/A ; None ; 8.674 ns ; S_PFr2[23] ; S_PF[23] ; clk ;
|
|
||||||
; N/A ; None ; 8.662 ns ; S_PFr2[2] ; S_PF[2] ; clk ;
|
|
||||||
; N/A ; None ; 8.650 ns ; S_PFr2[27] ; S_PF[27] ; clk ;
|
|
||||||
; N/A ; None ; 8.578 ns ; S_PFr2[13] ; S_PF[13] ; clk ;
|
|
||||||
; N/A ; None ; 8.569 ns ; S_PFr2[33] ; S_PF[33] ; clk ;
|
|
||||||
; N/A ; None ; 8.564 ns ; S_PFr2[22] ; S_PF[22] ; clk ;
|
|
||||||
; N/A ; None ; 8.556 ns ; S_PFr2[29] ; S_PF[29] ; clk ;
|
|
||||||
; N/A ; None ; 8.540 ns ; S_PFr2[20] ; S_PF[20] ; clk ;
|
|
||||||
; N/A ; None ; 8.465 ns ; S_PFr2[7] ; S_PF[7] ; clk ;
|
|
||||||
; N/A ; None ; 8.460 ns ; S_PFr2[0] ; S_PF[0] ; clk ;
|
|
||||||
; N/A ; None ; 8.392 ns ; S_PFr2[34] ; S_PF[34] ; clk ;
|
|
||||||
; N/A ; None ; 8.349 ns ; S_PFr2[17] ; S_PF[17] ; clk ;
|
|
||||||
; N/A ; None ; 8.334 ns ; S_PFr2[39] ; S_PF[39] ; clk ;
|
|
||||||
; N/A ; None ; 8.311 ns ; S_PFr2[45] ; S_PF[45] ; clk ;
|
|
||||||
; N/A ; None ; 8.231 ns ; S_PFr2[38] ; S_PF[38] ; clk ;
|
|
||||||
; N/A ; None ; 8.211 ns ; S_PFr2[16] ; S_PF[16] ; clk ;
|
|
||||||
; N/A ; None ; 8.204 ns ; S_PFr2[41] ; S_PF[41] ; clk ;
|
|
||||||
; N/A ; None ; 8.204 ns ; S_PFr2[1] ; S_PF[1] ; clk ;
|
|
||||||
; N/A ; None ; 8.202 ns ; S_PFr2[47] ; S_PF[47] ; clk ;
|
|
||||||
; N/A ; None ; 8.129 ns ; S_PFr2[46] ; S_PF[46] ; clk ;
|
|
||||||
; N/A ; None ; 8.103 ns ; S_PFr2[32] ; S_PF[32] ; clk ;
|
|
||||||
; N/A ; None ; 8.101 ns ; S_PFr2[12] ; S_PF[12] ; clk ;
|
|
||||||
; N/A ; None ; 8.095 ns ; S_PFr2[3] ; S_PF[3] ; clk ;
|
|
||||||
; N/A ; None ; 8.094 ns ; S_PFr2[15] ; S_PF[15] ; clk ;
|
|
||||||
; N/A ; None ; 8.090 ns ; S_PFr2[40] ; S_PF[40] ; clk ;
|
|
||||||
; N/A ; None ; 8.078 ns ; S_PFr2[37] ; S_PF[37] ; clk ;
|
|
||||||
; N/A ; None ; 8.072 ns ; S_PFr2[25] ; S_PF[25] ; clk ;
|
|
||||||
; N/A ; None ; 8.070 ns ; S_PFr2[44] ; S_PF[44] ; clk ;
|
|
||||||
; N/A ; None ; 8.066 ns ; S_PFr2[8] ; S_PF[8] ; clk ;
|
|
||||||
; N/A ; None ; 8.024 ns ; S_PFr2[18] ; S_PF[18] ; clk ;
|
|
||||||
; N/A ; None ; 7.910 ns ; S_PFr2[19] ; S_PF[19] ; clk ;
|
|
||||||
; N/A ; None ; 7.886 ns ; S_PFr2[24] ; S_PF[24] ; clk ;
|
|
||||||
; N/A ; None ; 6.854 ns ; S_PFr2[10] ; S_PF[10] ; clk ;
|
|
||||||
; N/A ; None ; 6.848 ns ; S_PFr2[21] ; S_PF[21] ; clk ;
|
|
||||||
; N/A ; None ; 6.820 ns ; S_PFr2[43] ; S_PF[43] ; clk ;
|
|
||||||
; N/A ; None ; 6.814 ns ; S_PFr2[42] ; S_PF[42] ; clk ;
|
|
||||||
+-------+--------------+------------+------------+----------+------------+
|
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------+
|
|
||||||
; th ;
|
|
||||||
+---------------+-------------+-----------+-------+-----------+----------+
|
|
||||||
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
|
|
||||||
+---------------+-------------+-----------+-------+-----------+----------+
|
|
||||||
; N/A ; None ; 0.072 ns ; SEN ; i[2] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.072 ns ; SEN ; i[1] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.072 ns ; SEN ; i[0] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.072 ns ; SEN ; i[5] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.072 ns ; SEN ; i[3] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.072 ns ; SEN ; i[4] ; SCLK ;
|
|
||||||
; N/A ; None ; 0.027 ns ; SDATA ; S_PFr[32] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.036 ns ; SDATA ; S_PFr[40] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.044 ns ; SDATA ; S_PFr[33] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.176 ns ; SDATA ; S_PFr[15] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.186 ns ; SDATA ; S_PFr[46] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.187 ns ; SDATA ; S_PFr[39] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.189 ns ; SDATA ; S_PFr[47] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.211 ns ; SDATA ; S_PFr[5] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.220 ns ; SDATA ; S_PFr[13] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.221 ns ; SDATA ; S_PFr[44] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.222 ns ; SDATA ; S_PFr[37] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.240 ns ; SEN ; S_PFr[26] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.244 ns ; SDATA ; S_PFr[43] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.247 ns ; SEN ; S_PFr[27] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.247 ns ; SEN ; S_PFr[28] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.247 ns ; SEN ; S_PFr[29] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.249 ns ; SEN ; S_PFr[30] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.252 ns ; SEN ; S_PFr[31] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.255 ns ; SDATA ; S_PFr[34] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.256 ns ; SDATA ; S_PFr[42] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.259 ns ; SDATA ; S_PFr[18] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.270 ns ; SDATA ; S_PFr[19] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.272 ns ; SDATA ; S_PFr[8] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.279 ns ; SDATA ; S_PFr[2] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.281 ns ; SDATA ; S_PFr[24] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.285 ns ; SDATA ; S_PFr[20] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.287 ns ; SDATA ; S_PFr[4] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.356 ns ; SDATA ; S_PFr[0] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.415 ns ; SDATA ; S_PFr[6] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.449 ns ; SDATA ; S_PFr[14] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.458 ns ; SDATA ; S_PFr[12] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.459 ns ; SDATA ; S_PFr[10] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.487 ns ; SDATA ; S_PFr[38] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.522 ns ; SDATA ; S_PFr[36] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.561 ns ; SDATA ; S_PFr[7] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.643 ns ; SDATA ; S_PFr[45] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.734 ns ; SEN ; S_PFr[4] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.745 ns ; SDATA ; S_PFr[21] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.745 ns ; SDATA ; S_PFr[25] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.748 ns ; SEN ; S_PFr[2] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.750 ns ; SEN ; S_PFr[8] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.884 ns ; SDATA ; S_PFr[41] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.898 ns ; SEN ; S_PFr[0] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.937 ns ; SDATA ; S_PFr[22] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.944 ns ; SDATA ; S_PFr[17] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.993 ns ; SDATA ; S_PFr[16] ; SCLK ;
|
|
||||||
; N/A ; None ; -0.999 ns ; SDATA ; S_PFr[23] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.027 ns ; SDATA ; S_PFr[9] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.038 ns ; SDATA ; S_PFr[35] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.042 ns ; SDATA ; S_PFr[11] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.043 ns ; SDATA ; S_PFr[1] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.043 ns ; SDATA ; S_PFr[3] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.051 ns ; SDATA ; S_PFr[27] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.052 ns ; SDATA ; S_PFr[30] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.054 ns ; SDATA ; S_PFr[28] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.058 ns ; SDATA ; S_PFr[29] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.062 ns ; SDATA ; S_PFr[26] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.063 ns ; SDATA ; S_PFr[31] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.075 ns ; SEN ; S_PFr[40] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.156 ns ; SEN ; S_PFr[23] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.162 ns ; SEN ; S_PFr[22] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.206 ns ; SEN ; S_PFr[9] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.218 ns ; SEN ; S_PFr[11] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.382 ns ; SEN ; S_PFr[20] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.385 ns ; SEN ; S_PFr[24] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.487 ns ; SEN ; S_PFr[10] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.489 ns ; SEN ; S_PFr[12] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.492 ns ; SEN ; S_PFr[45] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.494 ns ; SEN ; S_PFr[14] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.494 ns ; SEN ; S_PFr[41] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.494 ns ; SEN ; S_PFr[42] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.497 ns ; SEN ; S_PFr[6] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.498 ns ; SEN ; S_PFr[7] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.580 ns ; SEN ; S_PFr[17] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.584 ns ; SEN ; S_PFr[16] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.596 ns ; SEN ; S_PFr[37] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.704 ns ; SEN ; S_PFr[35] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.796 ns ; SEN ; S_PFr[21] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.796 ns ; SEN ; S_PFr[25] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.836 ns ; SEN ; S_PFr[18] ; SCLK ;
|
|
||||||
; N/A ; None ; -1.956 ns ; SEN ; S_PFr[33] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.018 ns ; SEN ; S_PFr[15] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.079 ns ; SEN ; S_PFr[38] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.101 ns ; SEN ; S_PFr[19] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.162 ns ; SEN ; S_PFr[13] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.287 ns ; SEN ; S_PFr[1] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.287 ns ; SEN ; S_PFr[3] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.650 ns ; SEN ; S_PFr[39] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.663 ns ; SEN ; S_PFr[46] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.715 ns ; SEN ; S_PFr[5] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.780 ns ; SEN ; S_PFr[43] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.962 ns ; SEN ; S_PFr[32] ; SCLK ;
|
|
||||||
; N/A ; None ; -2.973 ns ; SEN ; S_PFr[34] ; SCLK ;
|
|
||||||
; N/A ; None ; -3.007 ns ; SEN ; S_PFr[36] ; SCLK ;
|
|
||||||
; N/A ; None ; -3.013 ns ; SEN ; S_PFr[47] ; SCLK ;
|
|
||||||
; N/A ; None ; -3.339 ns ; SEN ; S_PFr[44] ; SCLK ;
|
|
||||||
+---------------+-------------+-----------+-------+-----------+----------+
|
|
||||||
|
|
||||||
|
|
||||||
+--------------------------+
|
|
||||||
; Timing Analyzer Messages ;
|
|
||||||
+--------------------------+
|
|
||||||
Info: *******************************************************************
|
|
||||||
Info: Running Quartus II Classic Timing Analyzer
|
|
||||||
Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
|
|
||||||
Info: Processing started: Tue Jan 03 15:28:01 2012
|
|
||||||
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PF1 -c PF1
|
|
||||||
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
|
|
||||||
Info: Started post-fitting delay annotation
|
|
||||||
Info: Delay annotation completed successfully
|
|
||||||
Warning: Found pins functioning as undefined clocks and/or memory enables
|
|
||||||
Info: Assuming node "clk" is an undefined clock
|
|
||||||
Info: Assuming node "SCLK" is an undefined clock
|
|
||||||
Info: Clock "clk" has Internal fmax of 95.93 MHz between source register "cnt[17]" and destination register "S_PFr2[41]" (period= 10.424 ns)
|
|
||||||
Info: + Longest register to register delay is 9.715 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N9; Fanout = 5; REG Node = 'cnt[17]'
|
|
||||||
Info: 2: + IC(3.167 ns) + CELL(0.200 ns) = 3.367 ns; Loc. = LC_X5_Y4_N2; Fanout = 1; COMB Node = 'LessThan0~0'
|
|
||||||
Info: 3: + IC(0.741 ns) + CELL(0.740 ns) = 4.848 ns; Loc. = LC_X5_Y4_N6; Fanout = 1; COMB Node = 'LessThan0~4'
|
|
||||||
Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.353 ns; Loc. = LC_X5_Y4_N7; Fanout = 72; COMB Node = 'cnt[20]~44'
|
|
||||||
Info: 5: + IC(3.771 ns) + CELL(0.591 ns) = 9.715 ns; Loc. = LC_X3_Y1_N5; Fanout = 2; REG Node = 'S_PFr2[41]'
|
|
||||||
Info: Total cell delay = 1.731 ns ( 17.82 % )
|
|
||||||
Info: Total interconnect delay = 7.984 ns ( 82.18 % )
|
|
||||||
Info: - Smallest clock skew is 0.000 ns
|
|
||||||
Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk'
|
|
||||||
Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y1_N5; Fanout = 2; REG Node = 'S_PFr2[41]'
|
|
||||||
Info: Total cell delay = 2.081 ns ( 62.16 % )
|
|
||||||
Info: Total interconnect delay = 1.267 ns ( 37.84 % )
|
|
||||||
Info: - Longest clock path from clock "clk" to source register is 3.348 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk'
|
|
||||||
Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N9; Fanout = 5; REG Node = 'cnt[17]'
|
|
||||||
Info: Total cell delay = 2.081 ns ( 62.16 % )
|
|
||||||
Info: Total interconnect delay = 1.267 ns ( 37.84 % )
|
|
||||||
Info: + Micro clock to output delay of source is 0.376 ns
|
|
||||||
Info: + Micro setup delay of destination is 0.333 ns
|
|
||||||
Info: Clock "SCLK" has Internal fmax of 126.07 MHz between source register "i[4]" and destination register "S_PFr[44]" (period= 7.932 ns)
|
|
||||||
Info: + Longest register to register delay is 7.223 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'i[4]'
|
|
||||||
Info: 2: + IC(1.018 ns) + CELL(0.511 ns) = 1.529 ns; Loc. = LC_X3_Y2_N9; Fanout = 7; COMB Node = 'Decoder0~1'
|
|
||||||
Info: 3: + IC(2.334 ns) + CELL(0.200 ns) = 4.063 ns; Loc. = LC_X6_Y1_N2; Fanout = 4; COMB Node = 'Decoder0~23'
|
|
||||||
Info: 4: + IC(2.569 ns) + CELL(0.591 ns) = 7.223 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr[44]'
|
|
||||||
Info: Total cell delay = 1.302 ns ( 18.03 % )
|
|
||||||
Info: Total interconnect delay = 5.921 ns ( 81.97 % )
|
|
||||||
Info: - Smallest clock skew is 0.000 ns
|
|
||||||
Info: + Shortest clock path from clock "SCLK" to destination register is 6.206 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'
|
|
||||||
Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr[44]'
|
|
||||||
Info: Total cell delay = 2.050 ns ( 33.03 % )
|
|
||||||
Info: Total interconnect delay = 4.156 ns ( 66.97 % )
|
|
||||||
Info: - Longest clock path from clock "SCLK" to source register is 6.206 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'
|
|
||||||
Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'i[4]'
|
|
||||||
Info: Total cell delay = 2.050 ns ( 33.03 % )
|
|
||||||
Info: Total interconnect delay = 4.156 ns ( 66.97 % )
|
|
||||||
Info: + Micro clock to output delay of source is 0.376 ns
|
|
||||||
Info: + Micro setup delay of destination is 0.333 ns
|
|
||||||
Info: tsu for register "S_PFr[44]" (data pin = "SEN", clock pin = "SCLK") is 3.893 ns
|
|
||||||
Info: + Longest pin to register delay is 9.766 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 8; PIN Node = 'SEN'
|
|
||||||
Info: 2: + IC(2.740 ns) + CELL(0.200 ns) = 4.072 ns; Loc. = LC_X3_Y2_N9; Fanout = 7; COMB Node = 'Decoder0~1'
|
|
||||||
Info: 3: + IC(2.334 ns) + CELL(0.200 ns) = 6.606 ns; Loc. = LC_X6_Y1_N2; Fanout = 4; COMB Node = 'Decoder0~23'
|
|
||||||
Info: 4: + IC(2.569 ns) + CELL(0.591 ns) = 9.766 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr[44]'
|
|
||||||
Info: Total cell delay = 2.123 ns ( 21.74 % )
|
|
||||||
Info: Total interconnect delay = 7.643 ns ( 78.26 % )
|
|
||||||
Info: + Micro setup delay of destination is 0.333 ns
|
|
||||||
Info: - Shortest clock path from clock "SCLK" to destination register is 6.206 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'
|
|
||||||
Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr[44]'
|
|
||||||
Info: Total cell delay = 2.050 ns ( 33.03 % )
|
|
||||||
Info: Total interconnect delay = 4.156 ns ( 66.97 % )
|
|
||||||
Info: tco from clock "clk" to destination pin "S_PF[5]" through register "S_PFr2[5]" is 8.833 ns
|
|
||||||
Info: + Longest clock path from clock "clk" to source register is 3.348 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk'
|
|
||||||
Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; REG Node = 'S_PFr2[5]'
|
|
||||||
Info: Total cell delay = 2.081 ns ( 62.16 % )
|
|
||||||
Info: Total interconnect delay = 1.267 ns ( 37.84 % )
|
|
||||||
Info: + Micro clock to output delay of source is 0.376 ns
|
|
||||||
Info: + Longest register to pin delay is 5.109 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; REG Node = 'S_PFr2[5]'
|
|
||||||
Info: 2: + IC(2.787 ns) + CELL(2.322 ns) = 5.109 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'S_PF[5]'
|
|
||||||
Info: Total cell delay = 2.322 ns ( 45.45 % )
|
|
||||||
Info: Total interconnect delay = 2.787 ns ( 54.55 % )
|
|
||||||
Info: th for register "i[2]" (data pin = "SEN", clock pin = "SCLK") is 0.072 ns
|
|
||||||
Info: + Longest clock path from clock "SCLK" to destination register is 6.206 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'
|
|
||||||
Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X3_Y2_N3; Fanout = 13; REG Node = 'i[2]'
|
|
||||||
Info: Total cell delay = 2.050 ns ( 33.03 % )
|
|
||||||
Info: Total interconnect delay = 4.156 ns ( 66.97 % )
|
|
||||||
Info: + Micro hold delay of destination is 0.221 ns
|
|
||||||
Info: - Shortest pin to register delay is 6.355 ns
|
|
||||||
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 8; PIN Node = 'SEN'
|
|
||||||
Info: 2: + IC(3.463 ns) + CELL(1.760 ns) = 6.355 ns; Loc. = LC_X3_Y2_N3; Fanout = 13; REG Node = 'i[2]'
|
|
||||||
Info: Total cell delay = 2.892 ns ( 45.51 % )
|
|
||||||
Info: Total interconnect delay = 3.463 ns ( 54.49 % )
|
|
||||||
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
|
|
||||||
Info: Peak virtual memory: 130 megabytes
|
|
||||||
Info: Processing ended: Tue Jan 03 15:28:03 2012
|
|
||||||
Info: Elapsed time: 00:00:02
|
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
|
||||||
|
|
||||||
|
|
||||||
@ -1,66 +0,0 @@
|
|||||||
--------------------------------------------------------------------------------------
|
|
||||||
Timing Analyzer Summary
|
|
||||||
--------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Type : Worst-case tsu
|
|
||||||
Slack : N/A
|
|
||||||
Required Time : None
|
|
||||||
Actual Time : 3.893 ns
|
|
||||||
From : SEN
|
|
||||||
To : S_PFr[44]
|
|
||||||
From Clock : --
|
|
||||||
To Clock : SCLK
|
|
||||||
Failed Paths : 0
|
|
||||||
|
|
||||||
Type : Worst-case tco
|
|
||||||
Slack : N/A
|
|
||||||
Required Time : None
|
|
||||||
Actual Time : 8.833 ns
|
|
||||||
From : S_PFr2[5]
|
|
||||||
To : S_PF[5]
|
|
||||||
From Clock : clk
|
|
||||||
To Clock : --
|
|
||||||
Failed Paths : 0
|
|
||||||
|
|
||||||
Type : Worst-case th
|
|
||||||
Slack : N/A
|
|
||||||
Required Time : None
|
|
||||||
Actual Time : 0.072 ns
|
|
||||||
From : SEN
|
|
||||||
To : i[4]
|
|
||||||
From Clock : --
|
|
||||||
To Clock : SCLK
|
|
||||||
Failed Paths : 0
|
|
||||||
|
|
||||||
Type : Clock Setup: 'clk'
|
|
||||||
Slack : N/A
|
|
||||||
Required Time : None
|
|
||||||
Actual Time : 95.93 MHz ( period = 10.424 ns )
|
|
||||||
From : cnt[17]
|
|
||||||
To : S_PFr2[41]
|
|
||||||
From Clock : clk
|
|
||||||
To Clock : clk
|
|
||||||
Failed Paths : 0
|
|
||||||
|
|
||||||
Type : Clock Setup: 'SCLK'
|
|
||||||
Slack : N/A
|
|
||||||
Required Time : None
|
|
||||||
Actual Time : 126.07 MHz ( period = 7.932 ns )
|
|
||||||
From : i[4]
|
|
||||||
To : S_PFr[44]
|
|
||||||
From Clock : SCLK
|
|
||||||
To Clock : SCLK
|
|
||||||
Failed Paths : 0
|
|
||||||
|
|
||||||
Type : Total number of failed paths
|
|
||||||
Slack :
|
|
||||||
Required Time :
|
|
||||||
Actual Time :
|
|
||||||
From :
|
|
||||||
To :
|
|
||||||
From Clock :
|
|
||||||
To Clock :
|
|
||||||
Failed Paths : 0
|
|
||||||
|
|
||||||
--------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
@ -1,153 +0,0 @@
|
|||||||
module PF1(
|
|
||||||
clk,rst_n,
|
|
||||||
S_PF,
|
|
||||||
SCLK,
|
|
||||||
SEN,
|
|
||||||
SDATA,
|
|
||||||
);
|
|
||||||
|
|
||||||
input clk; //50MHz
|
|
||||||
input rst_n; //µÍµçƽ¸´Î»ÐźÅ
|
|
||||||
input SCLK;
|
|
||||||
input SEN;
|
|
||||||
input SDATA;
|
|
||||||
|
|
||||||
output[47:0] S_PF;
|
|
||||||
|
|
||||||
reg[21:0] cnt;
|
|
||||||
reg[5:0] timer;
|
|
||||||
reg[47:0] S_PFr;
|
|
||||||
reg[6:0] i;
|
|
||||||
reg[47:0] S_PFr2;
|
|
||||||
|
|
||||||
//always @ (posedge clk or negedge rst_n)
|
|
||||||
// if(!rst_n) cnt <= 18'd0;
|
|
||||||
// else
|
|
||||||
// begin
|
|
||||||
// cnt <= cnt+1'b1;
|
|
||||||
// if(cnt == 5001) cnt <= 0;
|
|
||||||
// end
|
|
||||||
|
|
||||||
reg r_data_in0;
|
|
||||||
reg o_rising_edge;
|
|
||||||
|
|
||||||
always@(posedge clk or negedge rst_n)
|
|
||||||
begin
|
|
||||||
if (!rst_n)
|
|
||||||
r_data_in0 <= 0;
|
|
||||||
else begin
|
|
||||||
r_data_in0 <= SCLK;
|
|
||||||
if ({r_data_in0, SCLK} == 2'b01)
|
|
||||||
o_rising_edge <= 1;
|
|
||||||
else
|
|
||||||
o_rising_edge <= 0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
always @ (posedge clk)
|
|
||||||
if(cnt<20'hfffff)
|
|
||||||
begin
|
|
||||||
cnt <= cnt + 1'b1;
|
|
||||||
end
|
|
||||||
else if (timer<60)
|
|
||||||
begin
|
|
||||||
cnt <= 0;
|
|
||||||
timer <= timer + 1'b1;
|
|
||||||
S_PFr2 <= 48'hffffffffffff;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
S_PFr2 <= S_PFr;
|
|
||||||
end
|
|
||||||
|
|
||||||
always @ (posedge SCLK)
|
|
||||||
if (!SEN)
|
|
||||||
begin
|
|
||||||
i <= 0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
if(timer==60)
|
|
||||||
begin
|
|
||||||
i <= i+1'b1;
|
|
||||||
S_PFr[i] <= SDATA;
|
|
||||||
/* case(i)
|
|
||||||
6'd0: S_PFr[0] <= SDATA;
|
|
||||||
6'd1: S_PFr[1] <= SDATA;
|
|
||||||
6'd2: S_PFr[2] <= SDATA;
|
|
||||||
6'd3: S_PFr[3] <= SDATA;
|
|
||||||
6'd4: S_PFr[4] <= SDATA;
|
|
||||||
6'd5: S_PFr[5] <= SDATA;
|
|
||||||
6'd6: S_PFr[6] <= SDATA;
|
|
||||||
6'd7: S_PFr[7] <= SDATA;
|
|
||||||
6'd8: S_PFr[8] <= SDATA;
|
|
||||||
6'd9: S_PFr[9] <= SDATA;
|
|
||||||
6'd10: S_PFr[10] <= SDATA;
|
|
||||||
6'd11: S_PFr[11] <= SDATA;
|
|
||||||
6'd12: S_PFr[12] <= SDATA;
|
|
||||||
6'd13: S_PFr[13] <= SDATA;
|
|
||||||
6'd14: S_PFr[14] <= SDATA;
|
|
||||||
6'd15: S_PFr[15] <= SDATA;
|
|
||||||
6'd16: S_PFr[16] <= SDATA;
|
|
||||||
6'd17: S_PFr[17] <= SDATA;
|
|
||||||
6'd18: S_PFr[18] <= SDATA;
|
|
||||||
6'd19: S_PFr[19] <= SDATA;
|
|
||||||
6'd20: S_PFr[20] <= SDATA;
|
|
||||||
6'd21: S_PFr[21] <= SDATA;
|
|
||||||
6'd22: S_PFr[22] <= SDATA;
|
|
||||||
6'd23: S_PFr[23] <= SDATA;
|
|
||||||
6'd24: S_PFr[24] <= SDATA;
|
|
||||||
6'd25: S_PFr[25] <= SDATA;
|
|
||||||
6'd26: S_PFr[26] <= SDATA;
|
|
||||||
6'd27: S_PFr[27] <= SDATA;
|
|
||||||
6'd28: S_PFr[28] <= SDATA;
|
|
||||||
6'd29: S_PFr[29] <= SDATA;
|
|
||||||
6'd30: S_PFr[30] <= SDATA;
|
|
||||||
6'd31: S_PFr[31] <= SDATA;
|
|
||||||
6'd32: S_PFr[32] <= SDATA;
|
|
||||||
6'd33: S_PFr[33] <= SDATA;
|
|
||||||
6'd34: S_PFr[34] <= SDATA;
|
|
||||||
6'd35: S_PFr[35] <= SDATA;
|
|
||||||
6'd36: S_PFr[36] <= SDATA;
|
|
||||||
6'd37: S_PFr[37] <= SDATA;
|
|
||||||
6'd38: S_PFr[38] <= SDATA;
|
|
||||||
6'd39: S_PFr[39] <= SDATA;
|
|
||||||
6'd40: S_PFr[40] <= SDATA;
|
|
||||||
6'd41: S_PFr[41] <= SDATA;
|
|
||||||
6'd42: S_PFr[42] <= SDATA;
|
|
||||||
6'd43: S_PFr[43] <= SDATA;
|
|
||||||
6'd44: S_PFr[44] <= SDATA;
|
|
||||||
6'd45: S_PFr[45] <= SDATA;
|
|
||||||
6'd46: S_PFr[46] <= SDATA;
|
|
||||||
6'd47: S_PFr[47] <= SDATA;
|
|
||||||
default: ;
|
|
||||||
endcase*/
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*always @ (negedge SEN or negedge rst_n)
|
|
||||||
if(!rst_n) S_PFr2 <= 48'hffffffffffff;
|
|
||||||
else if(!SEN)
|
|
||||||
begin
|
|
||||||
S_PFr2 <= S_PFr;
|
|
||||||
end
|
|
||||||
*/
|
|
||||||
// else if(cnt == 5000)
|
|
||||||
// begin
|
|
||||||
// timer <= timer+1'b1; //ÿ0.1msÔöÒ»
|
|
||||||
// if(!SEN)
|
|
||||||
// begin
|
|
||||||
// case(timer)
|
|
||||||
// 1: S_PFr2 <= S_PFr;
|
|
||||||
// 17: timer <= 1'b0;
|
|
||||||
// default: ;
|
|
||||||
// endcase
|
|
||||||
// end
|
|
||||||
// end
|
|
||||||
|
|
||||||
assign S_PF = S_PFr2;
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
@ -1,692 +0,0 @@
|
|||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Copyright (C) 1991-2011 Altera Corporation
|
|
||||||
# Your use of Altera Corporation's design tools, logic functions
|
|
||||||
# and other software and tools, and its AMPP partner logic
|
|
||||||
# functions, and any output files from any of the foregoing
|
|
||||||
# (including device programming or simulation files), and any
|
|
||||||
# associated documentation or information are expressly subject
|
|
||||||
# to the terms and conditions of the Altera Program License
|
|
||||||
# Subscription Agreement, Altera MegaCore Function License
|
|
||||||
# Agreement, or other applicable license agreement, including,
|
|
||||||
# without limitation, that your use is for the sole purpose of
|
|
||||||
# programming logic devices manufactured by Altera and sold by
|
|
||||||
# Altera or its authorized distributors. Please refer to the
|
|
||||||
# applicable agreement for further details.
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Quartus II
|
|
||||||
# Version 11.0 Build 157 04/27/2011 SJ Full Version
|
|
||||||
# Date created = 21:56:36 February 04, 2012
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
#
|
|
||||||
# Note:
|
|
||||||
#
|
|
||||||
# 1) Do not modify this file. This file was generated
|
|
||||||
# automatically by the Quartus II software and is used
|
|
||||||
# to preserve global assignments across Quartus II versions.
|
|
||||||
#
|
|
||||||
# -------------------------------------------------------------------------- #
|
|
||||||
|
|
||||||
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
|
|
||||||
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
|
|
||||||
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
|
|
||||||
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
|
|
||||||
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
|
|
||||||
set_global_assignment -name SMART_RECOMPILE Off
|
|
||||||
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
|
|
||||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
|
|
||||||
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
|
|
||||||
set_global_assignment -name HC_OUTPUT_DIR hc_output
|
|
||||||
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
|
|
||||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
|
|
||||||
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
|
|
||||||
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
|
|
||||||
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
|
|
||||||
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
|
|
||||||
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
|
|
||||||
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
|
|
||||||
set_global_assignment -name REVISION_TYPE Base
|
|
||||||
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
|
|
||||||
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
|
|
||||||
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
|
|
||||||
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
|
|
||||||
set_global_assignment -name DO_COMBINED_ANALYSIS Off
|
|
||||||
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
|
|
||||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
|
|
||||||
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
|
|
||||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
|
|
||||||
set_global_assignment -name MUX_RESTRUCTURE Auto
|
|
||||||
set_global_assignment -name ENABLE_IP_DEBUG Off
|
|
||||||
set_global_assignment -name SAVE_DISK_SPACE On
|
|
||||||
set_global_assignment -name DISABLE_OCP_HW_EVAL Off
|
|
||||||
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
|
|
||||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
|
|
||||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
|
|
||||||
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
|
|
||||||
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
|
|
||||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
|
|
||||||
set_global_assignment -name FAMILY -value "Cyclone IV GX"
|
|
||||||
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
|
|
||||||
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
|
|
||||||
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
|
|
||||||
set_global_assignment -name SAFE_STATE_MACHINE Off
|
|
||||||
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
|
|
||||||
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
|
|
||||||
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
|
|
||||||
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
|
|
||||||
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
|
|
||||||
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
|
|
||||||
set_global_assignment -name PARALLEL_SYNTHESIS -value OFF
|
|
||||||
set_global_assignment -name DSP_BLOCK_BALANCING Auto
|
|
||||||
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name NOT_GATE_PUSH_BACK On
|
|
||||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
|
|
||||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
|
|
||||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
|
|
||||||
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
|
|
||||||
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
|
|
||||||
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
|
|
||||||
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
|
|
||||||
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
|
|
||||||
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
|
|
||||||
set_global_assignment -name IGNORE_SOFT_BUFFERS On
|
|
||||||
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
|
|
||||||
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
|
|
||||||
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
|
|
||||||
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
|
|
||||||
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
|
|
||||||
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
|
|
||||||
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
|
|
||||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
|
|
||||||
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
|
|
||||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
|
|
||||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
|
|
||||||
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
|
|
||||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
|
|
||||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
|
|
||||||
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
|
|
||||||
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
|
|
||||||
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
|
|
||||||
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
|
|
||||||
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
|
|
||||||
set_global_assignment -name AUTO_LCELL_INSERTION On
|
|
||||||
set_global_assignment -name CARRY_CHAIN_LENGTH 48
|
|
||||||
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
|
|
||||||
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
|
|
||||||
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
|
|
||||||
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
|
|
||||||
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
|
|
||||||
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
|
|
||||||
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
|
|
||||||
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
|
|
||||||
set_global_assignment -name AUTO_CARRY_CHAINS On
|
|
||||||
set_global_assignment -name AUTO_CASCADE_CHAINS On
|
|
||||||
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
|
|
||||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
|
|
||||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
|
|
||||||
set_global_assignment -name AUTO_ROM_RECOGNITION On
|
|
||||||
set_global_assignment -name AUTO_RAM_RECOGNITION On
|
|
||||||
set_global_assignment -name AUTO_DSP_RECOGNITION On
|
|
||||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
|
|
||||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
|
||||||
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
|
|
||||||
set_global_assignment -name STRICT_RAM_RECOGNITION Off
|
|
||||||
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
|
|
||||||
set_global_assignment -name FORCE_SYNCH_CLEAR Off
|
|
||||||
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
|
|
||||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
|
|
||||||
set_global_assignment -name AUTO_RESOURCE_SHARING Off
|
|
||||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
|
|
||||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
|
|
||||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
|
|
||||||
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
|
|
||||||
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
|
|
||||||
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
|
|
||||||
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Arria II GZ"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy III"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone IV GX"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix IV"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone IV E"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy IV"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III LS"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix III"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
|
|
||||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Arria II GX"
|
|
||||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
|
|
||||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
|
|
||||||
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
|
|
||||||
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
|
|
||||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
|
|
||||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
|
|
||||||
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
|
|
||||||
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
|
|
||||||
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
|
|
||||||
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
|
|
||||||
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
|
|
||||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
|
|
||||||
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
|
|
||||||
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
|
|
||||||
set_global_assignment -name SYNTHESIS_EFFORT Auto
|
|
||||||
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
|
|
||||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
|
|
||||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
|
|
||||||
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
|
|
||||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
|
|
||||||
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
|
|
||||||
set_global_assignment -name SYNTHESIS_SEED 1
|
|
||||||
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
|
|
||||||
set_global_assignment -name AUTO_MERGE_PLLS On
|
|
||||||
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
|
|
||||||
set_global_assignment -name TXPMA_SLEW_RATE Low
|
|
||||||
set_global_assignment -name ADCE_ENABLED Auto
|
|
||||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
|
|
||||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
|
|
||||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
|
|
||||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
|
|
||||||
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
|
|
||||||
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
|
|
||||||
set_global_assignment -name DEVICE AUTO
|
|
||||||
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
|
|
||||||
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
|
|
||||||
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
|
|
||||||
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
|
|
||||||
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
|
|
||||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
|
|
||||||
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
|
|
||||||
set_global_assignment -name STRATIX_UPDATE_MODE Standard
|
|
||||||
set_global_assignment -name CVP_MODE Off
|
|
||||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name ARRIAV_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
|
|
||||||
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
|
|
||||||
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
|
|
||||||
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
|
|
||||||
set_global_assignment -name USER_START_UP_CLOCK Off
|
|
||||||
set_global_assignment -name ENABLE_VREFA_PIN Off
|
|
||||||
set_global_assignment -name ENABLE_VREFB_PIN Off
|
|
||||||
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
|
|
||||||
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
|
|
||||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
|
|
||||||
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
|
|
||||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
|
|
||||||
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
|
|
||||||
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
|
|
||||||
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
|
|
||||||
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
|
|
||||||
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
|
||||||
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
|
|
||||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
|
|
||||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
|
|
||||||
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
|
|
||||||
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
|
|
||||||
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
|
|
||||||
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
|
|
||||||
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
|
|
||||||
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
|
|
||||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
|
|
||||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
|
|
||||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
|
|
||||||
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
|
|
||||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
|
|
||||||
set_global_assignment -name CRC_ERROR_CHECKING Off
|
|
||||||
set_global_assignment -name INTERNAL_SCRUBBING Off
|
|
||||||
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
|
|
||||||
set_global_assignment -name PR_READY_OPEN_DRAIN On
|
|
||||||
set_global_assignment -name ENABLE_CVP_CONFDONE Off
|
|
||||||
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
|
|
||||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
|
|
||||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
|
|
||||||
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
|
|
||||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
|
|
||||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
|
|
||||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
|
|
||||||
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
|
|
||||||
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
|
|
||||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
|
|
||||||
set_global_assignment -name OPTIMIZE_SSN Off
|
|
||||||
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
|
|
||||||
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
|
|
||||||
set_global_assignment -name ECO_REGENERATE_REPORT Off
|
|
||||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING -value ON
|
|
||||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
|
|
||||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
|
|
||||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
|
|
||||||
set_global_assignment -name SEED 1
|
|
||||||
set_global_assignment -name SLOW_SLEW_RATE Off
|
|
||||||
set_global_assignment -name PCI_IO Off
|
|
||||||
set_global_assignment -name TURBO_BIT On
|
|
||||||
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
|
|
||||||
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
|
|
||||||
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
|
|
||||||
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
|
|
||||||
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
|
|
||||||
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
|
|
||||||
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
|
|
||||||
set_global_assignment -name AUTO_PACKED_REGISTERS Off
|
|
||||||
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
|
|
||||||
set_global_assignment -name NORMAL_LCELL_INSERT On
|
|
||||||
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
|
|
||||||
set_global_assignment -name AUTO_DELAY_CHAINS On
|
|
||||||
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
|
|
||||||
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
|
|
||||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
|
||||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
|
|
||||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
|
|
||||||
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
|
|
||||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
|
|
||||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
|
|
||||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
|
|
||||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
|
|
||||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
|
|
||||||
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
|
|
||||||
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
|
|
||||||
set_global_assignment -name FITTER_EFFORT "Auto Fit"
|
|
||||||
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
|
|
||||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
|
|
||||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
|
|
||||||
set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
|
|
||||||
set_global_assignment -name AUTO_GLOBAL_CLOCK On
|
|
||||||
set_global_assignment -name AUTO_GLOBAL_OE On
|
|
||||||
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
|
|
||||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
|
|
||||||
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
|
|
||||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
|
|
||||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
|
|
||||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
|
|
||||||
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
|
|
||||||
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
|
|
||||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
|
|
||||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
|
|
||||||
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value ON
|
|
||||||
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
|
|
||||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
|
|
||||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
|
|
||||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
|
|
||||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III"
|
|
||||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
|
|
||||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
|
|
||||||
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
|
|
||||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
|
|
||||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
|
|
||||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
|
|
||||||
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
|
|
||||||
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
|
|
||||||
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
|
|
||||||
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
|
|
||||||
set_global_assignment -name PR_DONE_OPEN_DRAIN On
|
|
||||||
set_global_assignment -name NCEO_OPEN_DRAIN On
|
|
||||||
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
|
|
||||||
set_global_assignment -name ENABLE_PR_PINS Off
|
|
||||||
set_global_assignment -name CLAMPING_DIODE Off
|
|
||||||
set_global_assignment -name TRI_STATE_SPI_PINS Off
|
|
||||||
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
|
|
||||||
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
|
|
||||||
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
|
|
||||||
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
|
|
||||||
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
|
|
||||||
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
|
|
||||||
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
|
|
||||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
|
|
||||||
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
|
|
||||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
|
|
||||||
set_global_assignment -name COMPRESSION_MODE Off
|
|
||||||
set_global_assignment -name CLOCK_SOURCE Internal
|
|
||||||
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
|
|
||||||
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
|
|
||||||
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
|
||||||
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
|
|
||||||
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
|
||||||
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
|
|
||||||
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
|
|
||||||
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
|
|
||||||
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
|
|
||||||
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
|
|
||||||
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
|
|
||||||
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
|
|
||||||
set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
|
|
||||||
set_global_assignment -name SECURITY_BIT Off
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
|
|
||||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
|
|
||||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
|
|
||||||
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
|
|
||||||
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
|
|
||||||
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
|
|
||||||
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
|
|
||||||
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
|
|
||||||
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
|
|
||||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
|
|
||||||
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
|
||||||
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
|
||||||
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
|
||||||
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
|
||||||
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
|
|
||||||
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
|
|
||||||
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
|
|
||||||
set_global_assignment -name GENERATE_TTF_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_RBF_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_HEX_FILE Off
|
|
||||||
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
|
|
||||||
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
|
|
||||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
|
|
||||||
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
|
|
||||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
|
|
||||||
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
|
|
||||||
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
|
|
||||||
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
|
|
||||||
set_global_assignment -name ENABLE_OCT_DONE Off
|
|
||||||
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
|
|
||||||
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
|
|
||||||
set_global_assignment -name START_TIME 0ns
|
|
||||||
set_global_assignment -name SIMULATION_MODE TIMING
|
|
||||||
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
|
|
||||||
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
|
|
||||||
set_global_assignment -name SETUP_HOLD_DETECTION Off
|
|
||||||
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
|
|
||||||
set_global_assignment -name CHECK_OUTPUTS Off
|
|
||||||
set_global_assignment -name SIMULATION_COVERAGE On
|
|
||||||
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
|
|
||||||
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
|
|
||||||
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
|
|
||||||
set_global_assignment -name GLITCH_DETECTION Off
|
|
||||||
set_global_assignment -name GLITCH_INTERVAL 1ns
|
|
||||||
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
|
|
||||||
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
|
|
||||||
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
|
|
||||||
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
|
|
||||||
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
|
|
||||||
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
|
|
||||||
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
|
|
||||||
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
|
|
||||||
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
|
|
||||||
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
|
|
||||||
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
|
|
||||||
set_global_assignment -name DRC_TOP_FANOUT 50
|
|
||||||
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
|
|
||||||
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
|
|
||||||
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
|
|
||||||
set_global_assignment -name ENABLE_DRC_SETTINGS Off
|
|
||||||
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
|
|
||||||
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
|
|
||||||
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
|
|
||||||
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
|
|
||||||
set_global_assignment -name MERGE_HEX_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_SVF_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_ISC_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_JAM_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_JBC_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
|
|
||||||
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
|
|
||||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
|
|
||||||
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
|
|
||||||
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
|
|
||||||
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
|
|
||||||
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
|
|
||||||
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
|
||||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
|
|
||||||
set_global_assignment -name POWER_USE_PVA On
|
|
||||||
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
|
|
||||||
set_global_assignment -name POWER_USE_INPUT_FILES Off
|
|
||||||
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
|
|
||||||
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
|
|
||||||
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
|
|
||||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
|
|
||||||
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
|
|
||||||
set_global_assignment -name POWER_TJ_VALUE 25
|
|
||||||
set_global_assignment -name POWER_USE_TA_VALUE 25
|
|
||||||
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
|
|
||||||
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
|
|
||||||
set_global_assignment -name IGNORE_PARTITIONS Off
|
|
||||||
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
|
|
||||||
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
|
|
||||||
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
|
|
||||||
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
|
|
||||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
|
|
||||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
|
|
||||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
|
|
||||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
|
|
||||||
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
|
|
||||||
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
|
|
||||||
set_global_assignment -name EQC_BBOX_MERGE On
|
|
||||||
set_global_assignment -name EQC_LVDS_MERGE On
|
|
||||||
set_global_assignment -name EQC_RAM_UNMERGING On
|
|
||||||
set_global_assignment -name EQC_DFF_SS_EMULATION On
|
|
||||||
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
|
|
||||||
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
|
|
||||||
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
|
|
||||||
set_global_assignment -name EQC_STRUCTURE_MATCHING On
|
|
||||||
set_global_assignment -name EQC_AUTO_BREAK_CONE On
|
|
||||||
set_global_assignment -name EQC_POWER_UP_COMPARE Off
|
|
||||||
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
|
|
||||||
set_global_assignment -name EQC_AUTO_INVERSION On
|
|
||||||
set_global_assignment -name EQC_AUTO_TERMINATE On
|
|
||||||
set_global_assignment -name EQC_SUB_CONE_REPORT Off
|
|
||||||
set_global_assignment -name EQC_RENAMING_RULES On
|
|
||||||
set_global_assignment -name EQC_PARAMETER_CHECK On
|
|
||||||
set_global_assignment -name EQC_AUTO_PORTSWAP On
|
|
||||||
set_global_assignment -name EQC_DETECT_DONT_CARES On
|
|
||||||
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
|
|
||||||
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
|
|
||||||
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
|
|
||||||
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
|
|
||||||
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
|
|
||||||
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
|
|
||||||
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
|
|
||||||
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
|
|
||||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
|
|
||||||
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
|
|
||||||
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
|
|
||||||
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
|
|
||||||
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
|
|
||||||
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
|
|
||||||
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
|
|
||||||
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
|
|
||||||
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
|
|
||||||
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
|
||||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
|
|
||||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
|
|
||||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
|
|
||||||
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
|
||||||
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
|
||||||
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
|
|
||||||
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
|
||||||
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
|
||||||
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
|
|
||||||
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
|
|
||||||
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
|
|
||||||
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
|
|
||||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
|
|
||||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
|
|
||||||
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
|
|
||||||
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
|
|
||||||
@ -1,23 +0,0 @@
|
|||||||
Info: Start Nativelink Simulation process
|
|
||||||
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
|
|
||||||
|
|
||||||
========= EDA Simulation Settings =====================
|
|
||||||
|
|
||||||
Sim Mode : RTL
|
|
||||||
Family : maxii
|
|
||||||
Quartus root : c:/programdata/intelfpga_lite/20.1/quartus/bin64/
|
|
||||||
Quartus sim root : c:/programdata/intelfpga_lite/20.1/quartus/eda/sim_lib
|
|
||||||
Simulation Tool : modelsim-altera
|
|
||||||
Simulation Language : verilog
|
|
||||||
Simulation Mode : GUI
|
|
||||||
Sim Output File :
|
|
||||||
Sim SDF file :
|
|
||||||
Sim dir : simulation\modelsim
|
|
||||||
|
|
||||||
=======================================================
|
|
||||||
|
|
||||||
Info: Starting NativeLink simulation with ModelSim-Altera software
|
|
||||||
Sourced NativeLink script c:/programdata/intelfpga_lite/20.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
|
|
||||||
Warning: File PF1_run_msim_rtl_verilog.do already exists - backing up current file as PF1_run_msim_rtl_verilog.do.bak11
|
|
||||||
Info: Spawning ModelSim-Altera Simulation software
|
|
||||||
Info: NativeLink simulation flow was successful
|
|
||||||
@ -1,6 +1,6 @@
|
|||||||
# 阀板固件
|
# 阀板固件
|
||||||
|
|
||||||
这是阀板上CPLD的固件，严格意义上也属于硬件，因为是描述的硬件结构。这个固件是按照通信协议写的，但比通信协议能适应更广的传输速度，`SCLK`从5MHz到2Hz都可以
|
这是阀板上CPLD的固件，严格意义上也属于硬件，因为是描述的硬件结构。这个固件是按照通信协议写的，但比通信协议能适应更广的传输速度，**烟梗分选机上`SCLK`为1MHz，高电平时间为0.37ms**
|
||||||
|
|
||||||
## 如何烧录
|
## 如何烧录
|
||||||
|
|
||||||
|
|||||||
22
firmware/cr_ie_info.json
Normal file
22
firmware/cr_ie_info.json
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
{
|
||||||
|
"system" : {
|
||||||
|
"platform" : "windows64",
|
||||||
|
"os_name" : "Windows 10",
|
||||||
|
"os_version" : "10.0"
|
||||||
|
},
|
||||||
|
"error" : {
|
||||||
|
"executable" : "quartus_map",
|
||||||
|
"comment" : "not_applicable",
|
||||||
|
"error_message" : "Key not defined in data file: INT_PAD_COUNT",
|
||||||
|
"source_file" : "/quartus/ddb/dev/dev_pad_info_body.cpp",
|
||||||
|
"line" : "358",
|
||||||
|
"stack_trace" : "\t0x7ff8680a4263: DDB_DEV + 0x44263 (DEV_PAD_INFO::get_number_of_pads + 0x17cd3)\n\t0x7ff86637350d: db_cut + 0x29350d (?get_user_pins_available@CUT_RPT_UTILITY@@SAHXZ + 0x7d)\n\t0x7ff866396f2e: db_cut + 0x2b6f2e (?update_summary@CUT_RPT_UTILITY@@QEAAXW4CUT_SUMMARY_TYPE@@W4CUT_PROCESSING_STATUS@@_N222HH@Z + 0x3cde)\n\t0x7ff77e623f84: quartus_map + 0x23f84 (?write_reports@QSYN_FRAMEWORK@@UEAA_N_NPEBD@Z + 0x644)\n\t0x7ff885541587: comp_qexe + 0x11587 (qexe_do_normal + 0x267)\n\t0x7ff885546622: comp_qexe + 0x16622 (qexe_run + 0x432)\n\t0x7ff885547371: comp_qexe + 0x17371 (?qexe_standard_main@@YAHPEAVQEXE_FRAMEWORK@@PEAPEBUQEXE_OPTION_DEFINITION@@HPEAPEBD@Z + 0xc1)\n\t0x7ff77e61b42b: quartus_map + 0x1b42b (?qsyn_main@@YAHHPEAPEBD@Z + 0x53b)\n\t0x7ff890783258: CCL_MSG + 0x13258 (?msg_main_thread@@YAPEAXPEAX@Z + 0x18)\n\t0x7ff890784a5e: CCL_MSG + 0x14a5e (?msg_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x6e)\n\t0x7ff890896af0: ccl_mem + 0x16af0 (?mem_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x70)\n\t0x7ff890782af1: CCL_MSG + 0x12af1 (?msg_exe_main@@YAHHPEAPEBDP6AHH0@Z@Z + 0xa1)\n\t0x7ff77e62a236: quartus_map + 0x2a236 (__tmainCRTStartup + 0x10e)\n\t0x7ff8b24f7033: KERNEL32 + 0x17033 (BaseThreadInitThunk + 0x13)\n\t0x7ff8b3162650: ntdll + 0x52650 (RtlUserThreadStart + 0x20)\n",
|
||||||
|
"subsystem" : "DEV"
|
||||||
|
},
|
||||||
|
"quartus" : {
|
||||||
|
"quartus_bits" : "64",
|
||||||
|
"version" : "20.1.0",
|
||||||
|
"build" : "711",
|
||||||
|
"edition" : "Lite Edition"
|
||||||
|
}
|
||||||
|
}
|
||||||
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@ -1,10 +0,0 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1635993608838 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Design Assistant Quartus Prime " "Running Quartus Prime Design Assistant" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1635993608838 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 04 10:40:08 2021 " "Processing started: Thu Nov 04 10:40:08 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1635993608838 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Assistant" 0 -1 1635993608838 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_drc PF1 -c PF1 " "Command: quartus_drc PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Design Assistant" 0 -1 1635993608838 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Assistant" 0 -1 1635993609081 ""}
|
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PF1.sdc " "Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Design Assistant" 0 -1 1635993609137 ""}
|
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Design Assistant" 0 -1 1635993609137 ""}
|
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Design Assistant" 0 -1 1635993609137 ""}
|
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Design Assistant" 0 -1 1635993609139 ""}
|
|
||||||
{ "Info" "IDRC_REPORT_HEALTH_POST_FITTER" "0 0 " "Design Assistant information: finished post-fitting analysis of current design -- generated 0 information messages and 0 warning messages" { } { } 2 308007 "Design Assistant information: finished post-fitting analysis of current design -- generated %1!d! information messages and %2!d! warning messages" 0 0 "Design Assistant" 0 -1 1635993609144 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Design Assistant 0 s 3 s Quartus Prime " "Quartus Prime Design Assistant was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4625 " "Peak virtual memory: 4625 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1635993609162 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 04 10:40:09 2021 " "Processing ended: Thu Nov 04 10:40:09 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1635993609162 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1635993609162 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1635993609162 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Assistant" 0 -1 1635993609162 ""}
|
|
||||||
Binary file not shown.
@ -1,6 +0,0 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1636621451390 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636621451390 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 11 17:04:11 2021 " "Processing started: Thu Nov 11 17:04:11 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636621451390 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1636621451390 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1636621451390 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1636621451686 ""}
|
|
||||||
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "PF1.vo PF1_v.sdo C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/ simulation " "Generated files \"PF1.vo\" and \"PF1_v.sdo\" in directory \"C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204018 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1636621451832 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4628 " "Peak virtual memory: 4628 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636621451851 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 17:04:11 2021 " "Processing ended: Thu Nov 11 17:04:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636621451851 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636621451851 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636621451851 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1636621451851 ""}
|
|
||||||
Binary file not shown.
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@ -1,12 +0,0 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1636621433177 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636621433179 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 11 17:03:53 2021 " "Processing started: Thu Nov 11 17:03:53 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636621433179 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621433179 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621433179 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1636621433564 ""}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1636621433564 ""}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_pf1.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_pf1.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_PF1 " "Found entity 1: tb_PF1" { } { { "tb_PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1636621440103 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621440103 ""}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pf1.v 1 1 " "Found 1 design units, including 1 entities, in source file pf1.v" { { "Info" "ISGN_ENTITY_NAME" "1 PF1 " "Found entity 1: PF1" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1636621440106 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621440106 ""}
|
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "PF1 " "Elaborating entity \"PF1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1636621440151 ""}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 PF1.v(88) " "Verilog HDL assignment warning at PF1.v(88): truncated value with size 32 to match size of target (5)" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1636621440167 "|PF1"}
|
|
||||||
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 288 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 264 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 143 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 91 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1636621440797 ""}
|
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1636621440977 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1636621440977 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1636621440977 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1636621440977 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4712 " "Peak virtual memory: 4712 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636621441175 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 17:04:01 2021 " "Processing ended: Thu Nov 11 17:04:01 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636621441175 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636621441175 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636621441175 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621441175 ""}
|
|
||||||
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|
|||||||
start_full_compilation:s:00:00:20
|
|
||||||
start_analysis_synthesis:s:00:00:09-start_full_compilation
|
|
||||||
start_analysis_elaboration:s-start_full_compilation
|
|
||||||
start_fitter:s:00:00:06-start_full_compilation
|
|
||||||
start_assembler:s:00:00:01-start_full_compilation
|
|
||||||
start_timing_analyzer:s:00:00:02-start_full_compilation
|
|
||||||
start_eda_netlist_writer:s:00:00:02-start_full_compilation
|
|
||||||
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Load Diff
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@ -1,6 +0,0 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:50:56 2011 " "Info: Processing started: Mon Dec 26 14:50:56 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Peak virtual memory: 144 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:50:59 2011 " "Info: Processing ended: Mon Dec 26 14:50:59 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
|
||||||
@ -1,6 +0,0 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:51:03 2011 " "Info: Processing started: Mon Dec 26 14:51:03 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Warning" "WVLGO_INVALID_TIMESCALE_SELECTED_FOR_PLL_DESIGN" "" "Warning: An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." { } { } 0 0 "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "PF1.vo PF1_v.sdo D:/proj/quartus/TEA/PF_DS/simulation/modelsim/ simulation " "Info: Generated files \"PF1.vo\" and \"PF1_v.sdo\" in directory \"D:/proj/quartus/TEA/PF_DS/simulation/modelsim/\" for EDA simulation tool" { } { } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Peak virtual memory: 124 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:51:04 2011 " "Info: Processing ended: Mon Dec 26 14:51:04 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
|
||||||
File diff suppressed because one or more lines are too long
@ -1,11 +0,0 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:50:47 2011 " "Info: Processing started: Mon Dec 26 14:50:47 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "PF1 PF1.v(7) " "Warning (10238): Verilog Module Declaration warning at PF1.v(7): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"PF1\"" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 7 0 0 } } } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PF1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file PF1.v" { { "Info" "ISGN_ENTITY_NAME" "1 PF1 " "Info: Found entity 1: PF1" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "PF1 " "Info: Elaborating entity \"PF1\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
|
|
||||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "o_rising_edge PF1.v(32) " "Warning (10036): Verilog HDL or VHDL warning at PF1.v(32): object \"o_rising_edge\" assigned a value but never read" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 32 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "i\[6\] " "Info: Register \"i\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
|
|
||||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_n " "Warning (15610): No output dependent on input pin \"rst_n\"" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 10 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Info: Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "48 " "Info: Implemented 48 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "188 " "Info: Implemented 188 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Peak virtual memory: 171 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:50:50 2011 " "Info: Processing ended: Mon Dec 26 14:50:50 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
|
|
||||||
@ -1,98 +0,0 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1636374815481 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374815481 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:35 2021 " "Processing started: Mon Nov 08 20:33:35 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374815481 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374815481 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374815481 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1636374815734 ""}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1636374815734 ""}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_pf1.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_pf1.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_PF1 " "Found entity 1: tb_PF1" { } { { "tb_PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1636374822193 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374822193 ""}
|
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pf1.v 1 1 " "Found 1 design units, including 1 entities, in source file pf1.v" { { "Info" "ISGN_ENTITY_NAME" "1 PF1 " "Found entity 1: PF1" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1636374822195 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374822195 ""}
|
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "PF1 " "Elaborating entity \"PF1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1636374822215 ""}
|
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 PF1.v(88) " "Verilog HDL assignment warning at PF1.v(88): truncated value with size 32 to match size of target (5)" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1636374822219 "|PF1"}
|
|
||||||
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 288 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 264 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 143 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 91 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1636374822704 ""}
|
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1636374822800 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1636374822800 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1636374822800 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1636374822800 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4712 " "Peak virtual memory: 4712 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374822852 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:42 2021 " "Processing ended: Mon Nov 08 20:33:42 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374822852 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374822852 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374822852 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374822852 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1636374823941 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374823941 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:43 2021 " "Processing started: Mon Nov 08 20:33:43 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374823941 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1636374823941 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1636374823941 ""}
|
|
||||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1636374824018 ""}
|
|
||||||
{ "Info" "0" "" "Project = PF1" { } { } 0 0 "Project = PF1" 0 0 "Fitter" 0 0 1636374824018 ""}
|
|
||||||
{ "Info" "0" "" "Revision = PF1" { } { } 0 0 "Revision = PF1" 0 0 "Fitter" 0 0 1636374824018 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1636374824069 ""}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1636374824070 ""}
|
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "PF1 EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"PF1\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1636374824071 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1636374824111 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1636374824111 ""}
|
|
||||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1636374824139 ""}
|
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1636374824143 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1636374824212 ""}
|
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PF1.sdc " "Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1636374824288 ""}
|
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1636374824289 ""}
|
|
||||||
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1636374824296 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1636374824296 ""}
|
|
||||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636374824296 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636374824296 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636374824296 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1636374824296 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1636374824305 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1636374824305 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1636374824314 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1636374824330 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1636374824330 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1636374824330 ""} } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1636374824330 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst_n " "Pin \"rst_n\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/miaow/Desktop/valve_board_kun/" { { 0 { 0 ""} 0 551 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1636374824331 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1636374824331 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1636374824334 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1636374824362 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1636374824411 ""}
|
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1636374824412 ""}
|
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1636374824412 ""}
|
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1636374824412 ""}
|
|
||||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374824449 ""}
|
|
||||||
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1636374824453 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1636374824558 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374824766 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1636374824768 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1636374825874 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374825874 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1636374825920 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X0_Y0 X8_Y11 " "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" { } { { "loc" "" { Generic "C:/Users/miaow/Desktop/valve_board_kun/" { { 1 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11"} { { 12 { 0 ""} 0 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1636374826111 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1636374826111 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1636374826404 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1636374826404 ""}
|
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374826406 ""}
|
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.39 " "Total time spent on timing analysis during the Fitter is 0.39 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1636374826418 ""}
|
|
||||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374826427 ""}
|
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg " "Generated suppressed messages file C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1636374826511 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5912 " "Peak virtual memory: 5912 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374826537 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:46 2021 " "Processing ended: Mon Nov 08 20:33:46 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374826537 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374826537 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374826537 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1636374826537 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1636374827486 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374827486 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:47 2021 " "Processing started: Mon Nov 08 20:33:47 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374827486 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1636374827486 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1636374827486 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1636374827684 ""}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1636374827725 ""}
|
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1636374827728 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4668 " "Peak virtual memory: 4668 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374827828 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:47 2021 " "Processing ended: Mon Nov 08 20:33:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374827828 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374827828 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374827828 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1636374827828 ""}
|
|
||||||
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1636374828415 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1636374828888 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374828888 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:48 2021 " "Processing started: Mon Nov 08 20:33:48 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374828888 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1636374828888 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta PF1 -c PF1 " "Command: quartus_sta PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1636374828888 ""}
|
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1636374828966 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1636374829062 ""}
|
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1636374829062 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829100 ""}
|
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829100 ""}
|
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1636374829151 ""}
|
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1636374829484 ""}
|
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PF1.sdc " "Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1636374829537 ""}
|
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829537 ""}
|
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1636374829538 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1636374829538 ""}
|
|
||||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1636374829542 ""}
|
|
||||||
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1636374829553 ""}
|
|
||||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1636374829554 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.012 " "Worst-case setup slack is -10.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829557 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829557 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.012 -2235.303 sys_clk " " -10.012 -2235.303 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829557 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829557 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.377 " "Worst-case hold slack is 1.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.377 0.000 sys_clk " " 1.377 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829562 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829562 ""}
|
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1636374829564 ""}
|
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1636374829568 ""}
|
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 sys_clk " " -2.289 -2.289 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829570 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829570 ""}
|
|
||||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1636374829584 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1636374829598 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1636374829598 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4687 " "Peak virtual memory: 4687 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374829638 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:49 2021 " "Processing ended: Mon Nov 08 20:33:49 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374829638 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374829638 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374829638 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1636374829638 ""}
|
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1636374830578 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374830578 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:50 2021 " "Processing started: Mon Nov 08 20:33:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374830578 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1636374830578 ""}
|
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1636374830578 ""}
|
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1636374830860 ""}
|
|
||||||
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "PF1.vo PF1_v.sdo C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/ simulation " "Generated files \"PF1.vo\" and \"PF1_v.sdo\" in directory \"C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204018 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1636374831008 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4628 " "Peak virtual memory: 4628 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374831026 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:51 2021 " "Processing ended: Mon Nov 08 20:33:51 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374831026 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374831026 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374831026 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1636374831026 ""}
|
|
||||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 10 s " "Quartus Prime Full Compilation was successful. 0 errors, 10 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1636374831619 ""}
|
|
||||||
File diff suppressed because one or more lines are too long
95
firmware/db/prev_cmp_valveboard_firmware.qmsg
Normal file
95
firmware/db/prev_cmp_valveboard_firmware.qmsg
Normal file
@ -0,0 +1,95 @@
|
|||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640336877070 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336877070 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:07:56 2021 " "Processing started: Fri Dec 24 17:07:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336877070 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336877070 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336877070 ""}
|
||||||
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1640336877625 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1640336877625 ""}
|
||||||
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 valveboard_firmware " "Found entity 1: valveboard_firmware" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640336891329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336891329 ""}
|
||||||
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_valveboard_firmware " "Found entity 1: tb_valveboard_firmware" { } { { "tb_valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/tb_valveboard_firmware.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640336891329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336891329 ""}
|
||||||
|
{ "Info" "ISGN_START_ELABORATION_TOP" "valveboard_firmware " "Elaborating entity \"valveboard_firmware\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1640336891389 ""}
|
||||||
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 valveboard_firmware.v(88) " "Verilog HDL assignment warning at valveboard_firmware.v(88): truncated value with size 32 to match size of target (5)" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1640336891406 "|valveboard_firmware"}
|
||||||
|
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 288 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 264 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 143 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 91 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1640336892331 ""}
|
||||||
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1640336892525 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1640336892525 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1640336892525 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1640336892525 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4707 " "Peak virtual memory: 4707 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336892797 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:12 2021 " "Processing ended: Fri Dec 24 17:08:12 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336892797 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336892797 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336892797 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336892797 ""}
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1640336894843 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336894845 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:08:13 2021 " "Processing started: Fri Dec 24 17:08:13 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336894845 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1640336894845 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1640336894845 ""}
|
||||||
|
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1640336895074 ""}
|
||||||
|
{ "Info" "0" "" "Project = valveboard_firmware" { } { } 0 0 "Project = valveboard_firmware" 0 0 "Fitter" 0 0 1640336895074 ""}
|
||||||
|
{ "Info" "0" "" "Revision = valveboard_firmware" { } { } 0 0 "Revision = valveboard_firmware" 0 0 "Fitter" 0 0 1640336895074 ""}
|
||||||
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1640336895171 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1640336895174 ""}
|
||||||
|
{ "Info" "IMPP_MPP_USER_DEVICE" "valveboard_firmware EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"valveboard_firmware\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1640336895182 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640336895234 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640336895234 ""}
|
||||||
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1640336895393 ""}
|
||||||
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1640336895416 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1640336895800 ""}
|
||||||
|
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "101 101 " "No exact pin location assignment(s) for 101 pins of 101 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1640336895878 ""}
|
||||||
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1640336895979 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1640336895979 ""}
|
||||||
|
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1640336895995 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1640336895995 ""}
|
||||||
|
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640336895995 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640336895995 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640336895995 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1640336895995 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640336896027 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640336896027 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640336896043 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640336896074 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock in PIN 20 " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock in PIN 20" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640336896074 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640336896074 ""} } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640336896074 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640336896074 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1640336896090 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1640336896121 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1640336896182 ""}
|
||||||
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1640336896182 ""}
|
||||||
|
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1640336896182 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1640336896198 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "99 unused 3.3V 3 96 0 " "Number of I/O pins in group: 99 (unused VREF, 3.3V VCCIO, 3 input, 96 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1640336896198 ""}
|
||||||
|
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 24 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 24 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 30 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 30 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 30 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1640336896198 ""}
|
||||||
|
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336896267 ""}
|
||||||
|
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1640336896272 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1640336896477 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336896817 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1640336896817 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1640336899127 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336899127 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1640336899172 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "10 " "Router estimated average interconnect usage is 10% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "14 X0_Y0 X8_Y11 " "Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" { } { { "loc" "" { Generic "C:/Users/guoyr/Desktop/qwert/" { { 1 { 0 "Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11"} { { 12 { 0 ""} 0 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1640336899476 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1640336899476 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1640336899890 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1640336899890 ""}
|
||||||
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336899890 ""}
|
||||||
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.47 " "Total time spent on timing analysis during the Fitter is 0.47 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1640336899915 ""}
|
||||||
|
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336899931 ""}
|
||||||
|
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1640336899978 ""}
|
||||||
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg " "Generated suppressed messages file C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1640336900065 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5080 " "Peak virtual memory: 5080 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336900127 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:20 2021 " "Processing ended: Fri Dec 24 17:08:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336900127 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336900127 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336900127 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1640336900127 ""}
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1640336901822 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336901822 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:08:21 2021 " "Processing started: Fri Dec 24 17:08:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336901822 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1640336901822 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1640336901822 ""}
|
||||||
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1640336902150 ""}
|
||||||
|
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1640336902281 ""}
|
||||||
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1640336902300 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336902543 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:22 2021 " "Processing ended: Fri Dec 24 17:08:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336902543 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336902543 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336902543 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1640336902543 ""}
|
||||||
|
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1640336903270 ""}
|
||||||
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1640336904213 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336904213 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:08:23 2021 " "Processing started: Fri Dec 24 17:08:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336904213 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1640336904213 ""}
|
||||||
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta valveboard_firmware -c valveboard_firmware " "Command: quartus_sta valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1640336904213 ""}
|
||||||
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1640336904372 ""}
|
||||||
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1640336904551 ""}
|
||||||
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1640336904551 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336904598 ""}
|
||||||
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336904598 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1640336904666 ""}
|
||||||
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1640336905141 ""}
|
||||||
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1640336905260 ""}
|
||||||
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905260 ""}
|
||||||
|
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1640336905261 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1640336905261 ""}
|
||||||
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1640336905265 ""}
|
||||||
|
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1640336905290 ""}
|
||||||
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1640336905292 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.630 " "Worst-case setup slack is -10.630" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.630 -2257.699 sys_clk " " -10.630 -2257.699 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905298 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905298 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.389 " "Worst-case hold slack is 1.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.389 0.000 sys_clk " " 1.389 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905307 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905307 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640336905320 ""}
|
||||||
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640336905323 ""}
|
||||||
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 sys_clk " " -2.289 -2.289 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905350 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905350 ""}
|
||||||
|
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1640336905378 ""}
|
||||||
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640336905400 ""}
|
||||||
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640336905403 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336905474 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:25 2021 " "Processing ended: Fri Dec 24 17:08:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336905474 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336905474 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336905474 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1640336905474 ""}
|
||||||
|
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Quartus Prime Full Compilation was successful. 0 errors, 11 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1640336906173 ""}
|
||||||
BIN
firmware/db/valveboard_firmware.(0).cnf.cdb
Normal file
BIN
firmware/db/valveboard_firmware.(0).cnf.cdb
Normal file
Binary file not shown.
BIN
firmware/db/valveboard_firmware.(0).cnf.hdb
Normal file
BIN
firmware/db/valveboard_firmware.(0).cnf.hdb
Normal file
Binary file not shown.
BIN
firmware/db/valveboard_firmware.ace_cmp.cdb
Normal file
BIN
firmware/db/valveboard_firmware.ace_cmp.cdb
Normal file
Binary file not shown.
BIN
firmware/db/valveboard_firmware.ace_cmp.hdb
Normal file
BIN
firmware/db/valveboard_firmware.ace_cmp.hdb
Normal file
Binary file not shown.
@ -1,7 +1,7 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1636621447972 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640495500861 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636621447972 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 11 17:04:07 2021 " "Processing started: Thu Nov 11 17:04:07 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636621447972 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1636621447972 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640495500861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 26 13:11:40 2021 " "Processing started: Sun Dec 26 13:11:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640495500861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1640495500861 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1636621447972 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1640495500861 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1636621448170 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1640495501233 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1636621448230 ""}
|
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1640495501358 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1636621448234 ""}
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1640495501358 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4668 " "Peak virtual memory: 4668 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636621448359 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 17:04:08 2021 " "Processing ended: Thu Nov 11 17:04:08 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636621448359 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636621448359 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636621448359 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1636621448359 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495501576 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:41 2021 " "Processing ended: Sun Dec 26 13:11:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495501576 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495501576 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495501576 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1640495501576 ""}
|
||||||
BIN
firmware/db/valveboard_firmware.asm.rdb
Normal file
BIN
firmware/db/valveboard_firmware.asm.rdb
Normal file
Binary file not shown.
BIN
firmware/db/valveboard_firmware.asm_labs.ddb
Normal file
BIN
firmware/db/valveboard_firmware.asm_labs.ddb
Normal file
Binary file not shown.
@ -1,5 +1,5 @@
|
|||||||
<?xml version="1.0" ?>
|
<?xml version="1.0" ?>
|
||||||
<LOG_ROOT>
|
<LOG_ROOT>
|
||||||
<PROJECT NAME="PF1">
|
<PROJECT NAME="valveboard_firmware">
|
||||||
</PROJECT>
|
</PROJECT>
|
||||||
</LOG_ROOT>
|
</LOG_ROOT>
|
||||||
BIN
firmware/db/valveboard_firmware.cmp.cdb
Normal file
BIN
firmware/db/valveboard_firmware.cmp.cdb
Normal file
Binary file not shown.
BIN
firmware/db/valveboard_firmware.cmp.hdb
Normal file
BIN
firmware/db/valveboard_firmware.cmp.hdb
Normal file
Binary file not shown.
BIN
firmware/db/valveboard_firmware.cmp.idb
Normal file
BIN
firmware/db/valveboard_firmware.cmp.idb
Normal file
Binary file not shown.
BIN
firmware/db/valveboard_firmware.cmp.rdb
Normal file
BIN
firmware/db/valveboard_firmware.cmp.rdb
Normal file
Binary file not shown.
BIN
firmware/db/valveboard_firmware.cmp0.ddb
Normal file
BIN
firmware/db/valveboard_firmware.cmp0.ddb
Normal file
Binary file not shown.
@ -1,3 +1,3 @@
|
|||||||
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||||
Version_Index = 520278016
|
Version_Index = 520278016
|
||||||
Creation_Time = Thu Nov 11 16:59:53 2021
|
Creation_Time = Sun Dec 26 13:10:10 2021
|
||||||
BIN
firmware/db/valveboard_firmware.eco.cdb
Normal file
BIN
firmware/db/valveboard_firmware.eco.cdb
Normal file
Binary file not shown.
@ -1,40 +1,41 @@
|
|||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1636621443746 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1640495495527 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1636621443749 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1640495495527 ""}
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "PF1 EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"PF1\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1636621443750 ""}
|
{ "Info" "IMPP_MPP_USER_DEVICE" "valveboard_firmware EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"valveboard_firmware\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1640495495527 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1636621443822 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640495495605 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1636621443822 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640495495605 ""}
|
||||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1636621443918 ""}
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1640495495699 ""}
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1636621443935 ""}
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1640495495714 ""}
|
||||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1636621444156 ""}
|
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1640495495917 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PF1.sdc " "Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1636621444324 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1640495496089 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1636621444326 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1640495496089 ""}
|
||||||
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1636621444340 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1636621444340 ""}
|
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1640495496105 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1640495496105 ""}
|
||||||
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636621444342 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636621444342 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636621444342 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1636621444342 ""}
|
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640495496105 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640495496105 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640495496105 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1640495496105 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1636621444356 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640495496120 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1636621444356 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640495496136 ""}
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1636621444368 ""}
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640495496152 ""}
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1636621444388 ""}
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640495496167 ""}
|
||||||
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1636621444388 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1636621444388 ""} } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1636621444388 ""}
|
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640495496167 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640495496167 ""} } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640495496167 ""}
|
||||||
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst_n " "Pin \"rst_n\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/miaow/Desktop/valve_board_kun/" { { 0 { 0 ""} 0 551 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1636621444388 ""}
|
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst_n " "Pin \"rst_n\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/guoyr/Desktop/qwert/" { { 0 { 0 ""} 0 551 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1640495496167 ""}
|
||||||
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1636621444388 ""}
|
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640495496167 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1636621444398 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1640495496183 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1636621444438 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1640495496230 ""}
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1636621444484 ""}
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1640495496292 ""}
|
||||||
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1636621444486 ""}
|
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1640495496292 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1636621444486 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1640495496292 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1636621444486 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1640495496292 ""}
|
||||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621444554 ""}
|
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495496402 ""}
|
||||||
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1636621444572 ""}
|
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1640495496433 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1636621444766 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1640495496636 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621444988 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495496998 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1636621445001 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1640495497013 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1636621446175 ""}
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1640495498476 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621446175 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495498476 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1636621446224 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1640495498539 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "13 X0_Y0 X8_Y11 " "Router estimated peak interconnect usage is 13% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" { } { { "loc" "" { Generic "C:/Users/miaow/Desktop/valve_board_kun/" { { 1 { 0 "Router estimated peak interconnect usage is 13% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11"} { { 12 { 0 ""} 0 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1636621446448 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1636621446448 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "11 " "Router estimated average interconnect usage is 11% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "12 X9_Y0 X17_Y11 " "Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11" { } { { "loc" "" { Generic "C:/Users/guoyr/Desktop/qwert/" { { 1 { 0 "Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11"} { { 12 { 0 ""} 9 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1640495498835 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1640495498835 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1636621446684 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1636621446684 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1640495499160 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1640495499160 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621446687 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495499160 ""}
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.38 " "Total time spent on timing analysis during the Fitter is 0.38 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1636621446708 ""}
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.46 " "Total time spent on timing analysis during the Fitter is 0.46 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1640495499206 ""}
|
||||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621446722 ""}
|
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495499222 ""}
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg " "Generated suppressed messages file C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1636621446830 ""}
|
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1640495499285 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5906 " "Peak virtual memory: 5906 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636621446859 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 17:04:06 2021 " "Processing ended: Thu Nov 11 17:04:06 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636621446859 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636621446859 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636621446859 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1636621446859 ""}
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg " "Generated suppressed messages file C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1640495499363 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5080 " "Peak virtual memory: 5080 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495499425 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:39 2021 " "Processing ended: Sun Dec 26 13:11:39 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495499425 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495499425 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495499425 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1640495499425 ""}
|
||||||
@ -1,4 +1,4 @@
|
|||||||
|PF1
|
|valveboard_firmware
|
||||||
sys_clk => signal_high_voltage[0]~reg0.CLK
|
sys_clk => signal_high_voltage[0]~reg0.CLK
|
||||||
sys_clk => signal_high_voltage[1]~reg0.CLK
|
sys_clk => signal_high_voltage[1]~reg0.CLK
|
||||||
sys_clk => signal_high_voltage[2]~reg0.CLK
|
sys_clk => signal_high_voltage[2]~reg0.CLK
|
||||||
BIN
firmware/db/valveboard_firmware.hif
Normal file
BIN
firmware/db/valveboard_firmware.hif
Normal file
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user