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valveboard/firmware/db/prev_cmp_PF1.fit.qmsg
Miaow 7bbb183258 init branch
2021-11-22 00:34:34 +08:00

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:50:52 2011 " "Info: Processing started: Mon Dec 26 14:50:52 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "PF1 EPM240T100C5 " "Info: Selected device EPM240T100C5 for design \"PF1\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Info: Device EPM240T100I5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Info: Device EPM240T100A5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Info: Device EPM570T100C5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Info: Device EPM570T100I5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Info: Device EPM570T100A5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} } { } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 12 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 12" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SCLK Global clock " "Info: Automatically promoted signal \"SCLK\" to use Global clock" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "SCLK " "Info: Pin \"SCLK\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { SCLK } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "SCLK" } } } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" { } { } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" { } { } 0 0 "Started processing fast register assignments" 0 0 "" 0 -1}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" { } { } 0 0 "Finished processing fast register assignments" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register cnt\[14\] register timer\[2\] -9.386 ns " "Info: Slack time is -9.386 ns between source register \"cnt\[14\]\" and destination register \"timer\[2\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.291 ns + Largest register register " "Info: + Largest register to register requirement is 0.291 ns" { } { } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.372 ns Shortest register " "Info: Shortest clock path from clock \"clk\" to destination register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK Unassigned 76 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns timer\[2\] 2 REG Unassigned 4 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'timer\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { clk timer[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.372 ns Longest register " "Info: Longest clock path from clock \"clk\" to destination register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK Unassigned 76 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns timer\[2\] 2 REG Unassigned 4 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'timer\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { clk timer[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.372 ns Shortest register " "Info: Shortest clock path from clock \"clk\" to source register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK Unassigned 76 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns cnt\[14\] 2 REG Unassigned 5 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'cnt\[14\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { clk cnt[14] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.372 ns Longest register " "Info: Longest clock path from clock \"clk\" to source register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK Unassigned 76 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns cnt\[14\] 2 REG Unassigned 5 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'cnt\[14\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { clk cnt[14] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns " "Info: Micro clock to output delay of source is 0.376 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns " "Info: Micro setup delay of destination is 0.333 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.677 ns - Longest register register " "Info: - Longest register to register delay is 9.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[14\] 1 REG Unassigned 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'cnt\[14\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[14] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.315 ns) + CELL(0.740 ns) 3.055 ns LessThan0~1 2 COMB Unassigned 1 " "Info: 2: + IC(2.315 ns) + CELL(0.740 ns) = 3.055 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'LessThan0~1'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.055 ns" { cnt[14] LessThan0~1 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 4.235 ns LessThan0~4 3 COMB Unassigned 1 " "Info: 3: + IC(0.440 ns) + CELL(0.740 ns) = 4.235 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'LessThan0~4'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~1 LessThan0~4 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 5.415 ns cnt\[20\]~44 4 COMB Unassigned 72 " "Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 5.415 ns; Loc. = Unassigned; Fanout = 72; COMB Node = 'cnt\[20\]~44'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~4 cnt[20]~44 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.323 ns) + CELL(0.914 ns) 7.652 ns S_PFr2\[29\]~144 5 COMB Unassigned 5 " "Info: 5: + IC(1.323 ns) + CELL(0.914 ns) = 7.652 ns; Loc. = Unassigned; Fanout = 5; COMB Node = 'S_PFr2\[29\]~144'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { cnt[20]~44 S_PFr2[29]~144 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(1.243 ns) 9.677 ns timer\[2\] 6 REG Unassigned 4 " "Info: 6: + IC(0.782 ns) + CELL(1.243 ns) = 9.677 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'timer\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.025 ns" { S_PFr2[29]~144 timer[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.551 ns ( 47.03 % ) " "Info: Total cell delay = 4.551 ns ( 47.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.126 ns ( 52.97 % ) " "Info: Total interconnect delay = 5.126 ns ( 52.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.677 ns" { cnt[14] LessThan0~1 LessThan0~4 cnt[20]~44 S_PFr2[29]~144 timer[2] } "NODE_NAME" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.677 ns" { cnt[14] LessThan0~1 LessThan0~4 cnt[20]~44 S_PFr2[29]~144 timer[2] } "NODE_NAME" } } } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.677 ns register register " "Info: Estimated most critical path is register to register delay of 9.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[14\] 1 REG LAB_X2_Y3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y3; Fanout = 5; REG Node = 'cnt\[14\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[14] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.315 ns) + CELL(0.740 ns) 3.055 ns LessThan0~1 2 COMB LAB_X5_Y4 1 " "Info: 2: + IC(2.315 ns) + CELL(0.740 ns) = 3.055 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'LessThan0~1'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.055 ns" { cnt[14] LessThan0~1 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 4.235 ns LessThan0~4 3 COMB LAB_X5_Y4 1 " "Info: 3: + IC(0.440 ns) + CELL(0.740 ns) = 4.235 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'LessThan0~4'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~1 LessThan0~4 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 5.415 ns cnt\[20\]~44 4 COMB LAB_X5_Y4 72 " "Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 5.415 ns; Loc. = LAB_X5_Y4; Fanout = 72; COMB Node = 'cnt\[20\]~44'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~4 cnt[20]~44 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.323 ns) + CELL(0.914 ns) 7.652 ns S_PFr2\[29\]~144 5 COMB LAB_X3_Y4 5 " "Info: 5: + IC(1.323 ns) + CELL(0.914 ns) = 7.652 ns; Loc. = LAB_X3_Y4; Fanout = 5; COMB Node = 'S_PFr2\[29\]~144'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { cnt[20]~44 S_PFr2[29]~144 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(1.243 ns) 9.677 ns timer\[2\] 6 REG LAB_X3_Y4 4 " "Info: 6: + IC(0.782 ns) + CELL(1.243 ns) = 9.677 ns; Loc. = LAB_X3_Y4; Fanout = 4; REG Node = 'timer\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.025 ns" { S_PFr2[29]~144 timer[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.551 ns ( 47.03 % ) " "Info: Total cell delay = 4.551 ns ( 47.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.126 ns ( 52.97 % ) " "Info: Total interconnect delay = 5.126 ns ( 52.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.677 ns" { cnt[14] LessThan0~1 LessThan0~4 cnt[20]~44 S_PFr2[29]~144 timer[2] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "22 " "Info: Average interconnect usage is 22% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/proj/quartus/TEA/PF_DS/PF1.fit.smsg " "Info: Generated suppressed messages file D:/proj/quartus/TEA/PF_DS/PF1.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "188 " "Info: Peak virtual memory: 188 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:50:54 2011 " "Info: Processing ended: Mon Dec 26 14:50:54 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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