diff --git a/README.md b/README.md index 9d3d84a..97dccf3 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # 阀板 -阀板接收上位机给的数据，按其要求控制高速喷阀的开启和关闭，用在棉花、烟叶、茶叶等分选机上，喷阀多用来吹走其中的杂质。因此阀板是分选步骤上控制最终执行机构的驱动板，要求高速、稳定 +阀板接收上位机给的数据，按其要求控制高速喷阀的开启和关闭，用在棉花、烟叶、茶叶等分选机上，喷阀多用来吹走其中的杂质。因此阀板是分选步骤上控制最终执行机构的驱动板，要求高速、稳定。**这个文件夹下为烟梗分选机阀板相关内容。** ## 目录结构 diff --git a/examples/README.md b/examples/README.md index 0b80846..b458ced 100644 --- a/examples/README.md +++ b/examples/README.md @@ -2,7 +2,7 @@ ## 概述 -按照阀板程序，这里为基于两个平台的发送端实现 +按照阀板程序，这里为基于三个平台的发送端实现 - stm32f103 @@ -11,6 +11,10 @@ - zynq7100 实现了发送模块，可直接例化 + +- epc9600 + + 基于嵌入式linux的程序，线程安全，具体板子为EPC-9600I-L，是广州致远电子有限公司开发的基于AM335x系列处理器的工控主板，处理器内核为800MHz的Arm Cortex-A8。 ## 作者 diff --git a/examples/epc9600/.gitignore b/examples/epc9600/.gitignore new file mode 100644 index 0000000..eac7352 --- /dev/null +++ b/examples/epc9600/.gitignore @@ -0,0 +1,65 @@ +# Prerequisites +*.d + +.vscode/* +!.vscode/settings.json +!.vscode/tasks.json +!.vscode/launch.json +!.vscode/extensions.json +!.vscode/*.code-snippets +build/* + +# Local History for Visual Studio Code +.history/ + +# Built Visual Studio Code Extensions +*.vsix +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf \ No newline at end of file diff --git a/examples/epc9600/.vscode/settings.json b/examples/epc9600/.vscode/settings.json new file mode 100644 index 0000000..55cafd3 --- /dev/null +++ b/examples/epc9600/.vscode/settings.json @@ -0,0 +1,24 @@ +{ + "files.associations": { + "stdlib.h": "c", + "assert.h": "c", + "valve_init.h": "c", + "gpio.h": "c", + "type_traits": "c", + "gpio_common.h": "c", + "unistd.h": "c", + "stdint.h": "c", + "stat.h": "c", + "types.h": "c", + "pthread.h": "c", + "pthreadtypes.h": "c", + "valve.h": "c" + }, + "makefile.launchConfigurations": [ + { + "cwd": "/home/miaow/zlg/two_tobacco", + "binaryPath": "/home/miaow/zlg/two_tobacco/gpio_test", + "binaryArgs": [] + } + ] +} \ No newline at end of file diff --git a/examples/epc9600/Makefile b/examples/epc9600/Makefile new file mode 100644 index 0000000..e31c22b --- /dev/null +++ b/examples/epc9600/Makefile @@ -0,0 +1,86 @@ +#makefile for file_ioctl +CROSS_COMPILE ?= /home/miaow/software/arm-2011.03/bin/arm-none-linux-gnueabi- +TARGET := main +BUILD_DIR := build + +ifeq ("$(origin V)", "command line") + KBUILD_VERBOSE = $(V) +endif +ifndef KBUILD_VERBOSE + KBUILD_VERBOSE = 0 +endif + +ifeq ($(KBUILD_VERBOSE),1) + quiet = + Q = +else + quiet=quiet_ + Q = @ +endif + +ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4 +ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),) + quiet=silent_ +endif +else # make-3.8x +ifneq ($(filter s% -s%,$(MAKEFLAGS)),) + quiet=silent_ +endif +endif + + +SRC := $(wildcard *.c) +ASM_SRC := $(wildcard *.s) +OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.o))) +ASM_OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.o))) +DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.dis))) +ASM_DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.dis))) + +_TARGET := $(BUILD_DIR)/$(TARGET) +TARGET_DIS := $(BUILD_DIR)/target.dis + +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +LDR = $(CROSS_COMPILE)ldr +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +CFLAGS = -g -std=gnu99 -Wall -I. +LDFLAGS = -lpthread -lc -lm -marmelf_linux_eabi + +.SECONDARY: + +.PHONY:all +all: $(_TARGET) $(DIS) $(ASM_DIS) $(TARGET_DIS) + +$(BUILD_DIR)/%.i:%.c Makefile | $(BUILD_DIR) + $(Q)$(CC) -E $(CFLAGS) $< -o $@ +$(BUILD_DIR)/%.s:$(BUILD_DIR)/%.i Makefile | $(BUILD_DIR) + $(Q)$(CC) -S $(CFLAGS) $< -o $@ +$(BUILD_DIR)/%.o:$(BUILD_DIR)/%.s Makefile | $(BUILD_DIR) + $(Q)$(CC) -c $(CFLAGS) $< -o $@ +$(BUILD_DIR)/%.o:%.s Makefile | $(BUILD_DIR) + $(Q)$(CC) -c $(CFLAGS) $< -o $@ +$(BUILD_DIR)/%.dis:$(BUILD_DIR)/%.o Makefile | $(BUILD_DIR) + $(Q)$(OBJDUMP) -s -d $< > $@ +$(TARGET_DIS):$(_TARGET) Makefile | $(BUILD_DIR) + $(Q)$(OBJDUMP) -s -d $< > $@ +$(_TARGET):$(OBJ) $(ASM_OBJ) Makefile | $(BUILD_DIR) + $(Q)$(CC) $(OBJ) $(ASM_OBJ) $(LDFLAGS) -o $@ + + +.PHONY:clean +clean: + $(Q)$(RM) $(BUILD_DIR)/* -f + +.PHONY:install +install:$(TARGET) + $(Q)chmod 777 $(TARGET) + +.PHONY:$(BUILD_DIR) +$(BUILD_DIR): + $(Q)if [ ! -d $(BUILD_DIR) ]; then mkdir -p $@; fi + + \ No newline at end of file diff --git a/examples/epc9600/delay.s b/examples/epc9600/delay.s new file mode 100644 index 0000000..d0258c0 --- /dev/null +++ b/examples/epc9600/delay.s @@ -0,0 +1,18 @@ +.global delay_us +.func delay_us +delay_us: + cmp r0, #0 + moveq pc, lr + stmfd sp!, {r1, r2, fp, lr} + mov r1, r0 + big_loop: + ldr r2, =266 + loop: + sub r2, r2, #1 + cmp r2, #0 + bne loop + sub r1, r1, #1 + cmp r1, #0 + bne big_loop + ldmfd sp!, {r1, r2, fp, pc} +.endfunc diff --git a/examples/epc9600/gpio_common.c b/examples/epc9600/gpio_common.c new file mode 100644 index 0000000..6d39ac8 --- /dev/null +++ b/examples/epc9600/gpio_common.c @@ -0,0 +1,60 @@ +/** + * @file gpio_common.c + * @brief Operate the GPIO port of Zhou Ligong linux industrial control board + * @details is_file_exist(const char *file_path) determine whether the specified file exists + * print_array(int *array, int count) used to print out the value of the queue buffer, easy to debug and use + * @mainpage github.com/NanjingForestryUniversity + * @author miaow + * @email 3703781@qq.com + * @version v0.9.0 + * @date 2021/12/25 merry christmas + */ +#include + +char perror_buffer[1024] = {0}; + +char *gpio_value_file_gpo_list[8] = {GPIO_GET_VALUE_FILE(52), GPIO_GET_VALUE_FILE(53), + GPIO_GET_VALUE_FILE(54), GPIO_GET_VALUE_FILE(55), + GPIO_GET_VALUE_FILE(56), GPIO_GET_VALUE_FILE(57), + GPIO_GET_VALUE_FILE(58), GPIO_GET_VALUE_FILE(59)}; + +char *gpio_pin_str[8] = {"52", "53", "54", "55", "56", "57", "58", "59"}; +int gpio_pin_str_len[8] = {2, 2, 2, 2, 2, 2, 2, 2}; +char *gpio_pin_value_str[2] = {"0", "1"}; +int gpio_pin_value_str_len[2] = {1, 1}; +int gpo_value_fd[8] = {0}; + +/** + * @brief determine whether the specified file exists + * @param file_path file path + * @return 1 - success, -1 - error + */ +int is_file_exist(const char *file_path) +{ + if (file_path == NULL) + return -1; + if (access(file_path, F_OK) == 0) + return 1; + return -1; +} + +/** + * @brief Put the processed host computer data into the queue + * @param array Buffer pointer in the queue + * @param count The number of data in the buffer + */ +void print_array(int *array, int count) +{ + if (count == 0) + { + printf("[]\r\n"); + return; + } + printf("["); + int i; + for (i = 0; i < count - 1; i++) + { + printf("%d,", array[i]); + } + printf("%d]\r\n", array[i]); +} diff --git a/examples/epc9600/gpio_common.h b/examples/epc9600/gpio_common.h new file mode 100644 index 0000000..41f370f --- /dev/null +++ b/examples/epc9600/gpio_common.h @@ -0,0 +1,79 @@ +#ifndef __GPIO_H +#define __GPIO_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_EXPORT_PATH "/sys/class/gpio/export" +#define GPIO_GET_PIN_STR(pin) #pin +#define GPIO_GET_VALUE_FILE(pin) "/sys/class/gpio/gpio" #pin "/value" +#define GPIO_PINDEF_TO_INDEX(pin_t) ((int)pin_t) +#define GPIO_VALUEDEF_TO_INDEX(value_t) ((int)value_t) + +#define ON_ERROR(res, message1, message2) \ + if (res < 0) \ + { \ + sprintf(perror_buffer, "error %d at %s:%d, %s, %s", res, __FILE__, __LINE__, message1, message2); \ + perror(perror_buffer); \ + } + +#define ON_ERROR_RET_VOID(res, message1, message2) \ + ON_ERROR(res, message1, message2); \ + if (res < 0) \ + return; + +#define ON_ERROR_RET(res, message1, message2, retval) \ + ON_ERROR(res, message1, message2); \ + if (res < 0) \ + return retval; + +typedef enum +{ + GPO0 = 0, + GPO1 = 1, + GPO2 = 2, + GPO3 = 3, + GPO4 = 4, + GPO5 = 5, + GPO6 = 6, + GPO7 = 7 +} gpo_pin_enum_t; + +typedef enum +{ + GPI0 = 8, + GPI1 = 9, + GPI2 = 10, + GPI3 = 11, + GPI4 = 12, + GPI5 = 13, + GPI6 = 14, + GPI7 = 15 +} gpi_pin_enum_t; + +typedef enum +{ + GPIO_VALUE_LOW = 0, + GPIO_VALUE_HIGH = 1 +}gpio_value_enum_t; + + +int is_file_exist(const char *file_path); +extern char perror_buffer[]; +extern char *gpio_value_file_gpo_list[]; +extern char *gpio_pin_str[]; +extern int gpio_pin_str_len[]; +extern char *gpio_pin_value_str[]; +extern int gpo_value_fd[]; +extern int gpio_pin_value_str_len[]; +void print_array(int *array, int count); + +#endif \ No newline at end of file diff --git a/examples/epc9600/main.c b/examples/epc9600/main.c new file mode 100644 index 0000000..82402c1 --- /dev/null +++ b/examples/epc9600/main.c @@ -0,0 +1,29 @@ +#include +#include +#include +#include + +queue_msg_t queue_msg = {NULL, 1024, 0, 0, 0, 0, 0}; +valvedata_t valvedata = {0}; +queue_msg_t queue = {0}; + +#define ROTATE_UINT64_RIGHT(x, n) ((x) >> (n)) | ((x) << ((64) - (n))) +#define ROTATE_UINT64_LEFT(x, n) ((x) << (n)) | ((x) >> ((64) - (n))) + +int main(int argc, char *argv[]) +{ + uint64_t aaa = (uint64_t)pow(2.0, 48.0); + printf(motd); + queue_init(&queue, 1024); + valve_init(); + valvedata.valvedata_1 = 1; + for (uint64_t i = 0; i < aaa; i++) + { + valvedata.valvedata_1 = i; // ROTATE_UINT64_RIGHT(valvedata.valvedata_1, 1); + valve_sendmsg(&valvedata); + } + queue_deinit(&queue); + valve_deinit(); + printf(motd2); + return 0; +} diff --git a/examples/epc9600/valve.c b/examples/epc9600/valve.c new file mode 100644 index 0000000..496ebc5 --- /dev/null +++ b/examples/epc9600/valve.c @@ -0,0 +1,220 @@ +/** + * @file valve.c + * @brief Operate the valveboard with Linux application + * @details Call valve_init() paired with valve_deinit() as their names imply, valve_send() can be executed several times to operate up to 6 valveboards between valve_init() and valve_deinit() + * @mainpage github.com/NanjingForestryUniversity + * @author miaow + * @email 3703781@qq.com + * @version v0.9.0 + * @date 2021/12/25 merry christmas + */ + +#include +#include +#include +#include + + +// Write to the file desc (global variable `gpo_value_fd` in gpio_common.c) to operate a gpio. +// So gpo_value_fd should be initialized in valve_init with great care. +// Also, gpo_value_fd/gpi_value_fd is used in other .c files (read pluse of encoder, etc). +#define __GPO_SET_BIT(pin_t) __GPO_SET(pin_t, GPIO_VALUE_HIGH) +#define __GPO_CLR_BIT(pin_t) __GPO_SET(pin_t, GPIO_VALUE_LOW) +#define __GPO_SET(pin_t, value_t) write(gpo_value_fd[GPIO_PINDEF_TO_INDEX(pin_t)], gpio_pin_value_str[GPIO_VALUEDEF_TO_INDEX(value_t)], gpio_pin_value_str_len[GPIO_VALUEDEF_TO_INDEX(value_t)]) + +typedef struct +{ + int need_send; // Set this variable to 1 will cause a packet of sending + pthread_mutex_t need_send_mutex; + uint64_t data[6]; // Encoded data for sending + pthread_mutex_t data_mutex; // don't use, use need_send_mutex instead + int need_exit; // loop_thread joins to parent-thread at need_exit==1 + pthread_mutex_t need_exit_mutex; // don't use, use need_send_mutex instead + pthread_t loop_thread; // The sending thread + pthread_cond_t is_sending; +} valve_global_t; + +static valve_global_t _global_structure; +valve_pin_enum_t valveboard_x_sdata[] = {VALVE_SDATA_1, VALVE_SDATA_2, VALVE_SDATA_3, VALVE_SDATA_4, VALVE_SDATA_5, VALVE_SDATA_6}; + +static const int _delay = 1000 / SCLK_FREQUENCE_KHZ + 1; +static const int _delay_on_2 = 500 / SCLK_FREQUENCE_KHZ + 1; + +extern int delay_us(int us); +void *loop_thread_func(void *param); + +/** + * @brief Initialize valve-related gpos and start loop_thread which keeps communicating with valveboards, SEN/SCLK/SDATA1/SDATA2/SDATA3/SDATA4/SDATA5/SDATA6 + * @return 0 - success, -1 - error + */ +int valve_init() +{ + //打开GPIO + int fd_export = open(GPIO_EXPORT_PATH, O_WRONLY); + ON_ERROR_RET(fd_export, GPIO_EXPORT_PATH, "export in valve_init()", -1); + for (int i = 0; i < 8; i++) + { + if (is_file_exist(gpio_value_file_gpo_list[i])) + continue; + int ret = write(fd_export, gpio_pin_str[i], gpio_pin_str_len[i]); + ON_ERROR_RET(ret, gpio_pin_str[i], "open value file in valve_init()", -1); + } + for (int i = 0; i < 8; i++) + { + gpo_value_fd[i] = open(gpio_value_file_gpo_list[i], O_RDWR); + ON_ERROR_RET(gpo_value_fd[i], gpio_value_file_gpo_list[i], "open value file in valve_init()", -1); + } + + close(fd_export); + pthread_mutex_init(&_global_structure.need_send_mutex, NULL); + pthread_mutex_init(&_global_structure.data_mutex, NULL); + pthread_mutex_init(&_global_structure.need_exit_mutex, NULL); + pthread_cond_init(&_global_structure.is_sending, NULL); + + int ret = pthread_create(&_global_structure.loop_thread, NULL, loop_thread_func, NULL); + ON_ERROR_RET(ret, "thread create error in valve_init()", "", -1); + + return 0; +} + +/** + * @brief This function runs in child thread and handles communication with valveboard + */ +void *loop_thread_func(void *param) +{ + printf("loop_thread in %s start\r\n", __FILE__); + int need_exit = 0; + while (!need_exit) + { + pthread_mutex_lock(&_global_structure.need_send_mutex); + + + if (_global_structure.need_send == 0) + { + __GPO_CLR_BIT(VALVE_SCLK); + + delay_us(_delay); + __GPO_SET_BIT(VALVE_SCLK); + delay_us(_delay); + } + else + { + delay_us(_delay); + int i = 48; + + __GPO_SET_BIT(VALVE_SEN); + + while (i--) + { + + __GPO_CLR_BIT(VALVE_SCLK); + delay_us(_delay_on_2); + __GPO_SET(VALVE_SDATA_1, (_global_structure.data[0] & 1UL)); + __GPO_SET(VALVE_SDATA_2, (_global_structure.data[1] & 1UL)); + __GPO_SET(VALVE_SDATA_3, (_global_structure.data[2] & 1UL)); + __GPO_SET(VALVE_SDATA_4, (_global_structure.data[3] & 1UL)); + __GPO_SET(VALVE_SDATA_5, (_global_structure.data[4] & 1UL)); + __GPO_SET(VALVE_SDATA_6, (_global_structure.data[5] & 1UL)); + _global_structure.data[0] >>= 1; + _global_structure.data[1] >>= 1; + _global_structure.data[2] >>= 1; + _global_structure.data[3] >>= 1; + _global_structure.data[4] >>= 1; + _global_structure.data[5] >>= 1; + delay_us(_delay_on_2); + __GPO_SET_BIT(VALVE_SCLK); + delay_us(_delay); + } + __GPO_CLR_BIT(VALVE_SEN); + _global_structure.need_send = 0; + pthread_cond_signal(&_global_structure.is_sending); + } + + // pthread_mutex_lock(&_global_structure.need_exit_mutex); + need_exit = _global_structure.need_exit; + // pthread_mutex_unlock(&_global_structure.need_exit_mutex); + + pthread_mutex_unlock(&_global_structure.need_send_mutex); + } + printf("loop_thread in %s exit\r\n", __FILE__); + return NULL; +} + +/** + * @brief Set valve valve in forms of array. + * @param valve_data An array with size of 6, + * for example, valve_data[0]=64'h0000_FFFF_FFFF_FFFF represents the first valveboard all on + * valve_data[5]=64'h0000_0000_0000_0001 represents the last valveboard turn on its first valve + * @return 0 - success, -1 - error + */ +int valve_send(uint64_t *valve_data) +{ + pthread_mutex_lock(&_global_structure.need_send_mutex); + while (_global_structure.need_send == 1) + pthread_cond_wait(&_global_structure.is_sending, &_global_structure.need_send_mutex); + + for (int i = 0; i < 6; i++) + { + _global_structure.data[i] = ~valve_data[i]; // 1 represents on in parameter of this function while off when putting data on the bus + } + _global_structure.need_send = 1; // Set this variable to 1 will cause a sending packet + pthread_mutex_unlock(&_global_structure.need_send_mutex); + return 0; +} + +/** + * @brief Set valve valve in forms of struct. + * @param valve_data the valve_data struct + * @return 0 - success, -1 - error + */ +int valve_sendmsg(valvedata_t *valve_data) +{ + pthread_mutex_lock(&_global_structure.need_send_mutex); + while (_global_structure.need_send == 1) + pthread_cond_wait(&_global_structure.is_sending, &_global_structure.need_send_mutex); + + _global_structure.data[0] = ~valve_data->valvedata_1; // 1 represents on in parameter of this function while off when putting data on the bus + _global_structure.data[1] = ~valve_data->valvedata_2; + _global_structure.data[2] = ~valve_data->valvedata_3; + _global_structure.data[3] = ~valve_data->valvedata_4; + _global_structure.data[4] = ~valve_data->valvedata_5; + _global_structure.data[5] = ~valve_data->valvedata_6; + + _global_structure.need_send = 1; // Set this variable to 1 will cause a sending packet + pthread_mutex_unlock(&_global_structure.need_send_mutex); + return 0; +} + +/** + * @brief Deinitialize and turn off all the valve. + * @param valve_data An array with size of 6, + * for example, valve_data[0]=64'h0000_FFFF_FFFF_FFFF represents the first valveboard all on + * valve_data[5]=64'h0000_0000_0000_0001 represents the last valveboard turn on its first valve + * @note This function DOES BLOCKS 100000 us at least and DOES NOT UNEXPORT gpos + * @return 0 - success, -1 - error + */ +int valve_deinit() +{ + uint64_t tmp[6] = {0}; + valve_send(tmp); + usleep(100000); + pthread_mutex_lock(&_global_structure.need_send_mutex); + _global_structure.need_exit = 1; + pthread_mutex_unlock(&_global_structure.need_send_mutex); + pthread_join(_global_structure.loop_thread, NULL); + pthread_mutex_destroy(&_global_structure.need_exit_mutex); + pthread_mutex_destroy(&_global_structure.need_send_mutex); + pthread_mutex_destroy(&_global_structure.data_mutex); + pthread_cond_destroy(&_global_structure.is_sending); + memset((void *)_global_structure.data, 0, sizeof(_global_structure.data)); + _global_structure.need_exit = 0; + _global_structure.need_send = 0; + + int ret; + for (int i = 0; i < 8; i++) + { + ret = close(gpo_value_fd[i]); + ON_ERROR_RET(ret, "close value file in valve_init()", "", -1); + } + return 0; +} \ No newline at end of file diff --git a/examples/epc9600/valve.h b/examples/epc9600/valve.h new file mode 100644 index 0000000..4e1f710 --- /dev/null +++ b/examples/epc9600/valve.h @@ -0,0 +1,35 @@ +#ifndef __VALVE_INIT_H +#define __VALVE_INIT_H +#include + +typedef enum +{ + VALVE_SEN=GPIO_PINDEF_TO_INDEX(GPO1), + VALVE_SCLK=GPIO_PINDEF_TO_INDEX(GPO2), + VALVE_SDATA_1=GPIO_PINDEF_TO_INDEX(GPO0), + VALVE_SDATA_2=GPIO_PINDEF_TO_INDEX(GPO3), + VALVE_SDATA_3=GPIO_PINDEF_TO_INDEX(GPO4), + VALVE_SDATA_4=GPIO_PINDEF_TO_INDEX(GPO5), + VALVE_SDATA_5=GPIO_PINDEF_TO_INDEX(GPO6), + VALVE_SDATA_6=GPIO_PINDEF_TO_INDEX(GPO7) +}valve_pin_enum_t; + +typedef struct +{ + uint64_t valvedata_1; + uint64_t valvedata_2; + uint64_t valvedata_3; + uint64_t valvedata_4; + uint64_t valvedata_5; + uint64_t valvedata_6; +} valvedata_t; + + +#define SCLK_FREQUENCE_KHZ 10000 + +int valve_init(void); +int valve_send(uint64_t* valve_data); +int valve_deinit(void); +int valve_sendmsg(valvedata_t* valve_data); + +#endif \ No newline at end of file diff --git a/firmware/.qsys_edit/filters.xml b/firmware/.qsys_edit/filters.xml deleted file mode 100644 index 54a56c4..0000000 --- a/firmware/.qsys_edit/filters.xml +++ /dev/null @@ -1,2 +0,0 @@ - - diff --git a/firmware/.qsys_edit/preferences.xml b/firmware/.qsys_edit/preferences.xml deleted file mode 100644 index 3ca8577..0000000 --- a/firmware/.qsys_edit/preferences.xml +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - diff --git a/firmware/2016-02-01-0.6ms.pof b/firmware/2016-02-01-0.6ms.pof deleted file mode 100644 index 5a6ad7b..0000000 Binary files a/firmware/2016-02-01-0.6ms.pof and /dev/null differ diff --git a/firmware/2016-02-01-148-0.4ms.pof b/firmware/2016-02-01-148-0.4ms.pof deleted file mode 100644 index 021620c..0000000 Binary files a/firmware/2016-02-01-148-0.4ms.pof and /dev/null differ diff --git a/firmware/2016-02-01-148-1ms.pof b/firmware/2016-02-01-148-1ms.pof deleted file mode 100644 index f6b4fff..0000000 Binary files a/firmware/2016-02-01-148-1ms.pof and /dev/null differ diff --git a/firmware/2016-02-15-48-0.7ms.pof b/firmware/2016-02-15-48-0.7ms.pof deleted file mode 100644 index b12dc26..0000000 Binary files a/firmware/2016-02-15-48-0.7ms.pof and /dev/null differ diff --git a/firmware/2016-02-15-48-0.8ms.pof b/firmware/2016-02-15-48-0.8ms.pof deleted file mode 100644 index 0e18c4c..0000000 Binary files a/firmware/2016-02-15-48-0.8ms.pof and /dev/null differ diff --git a/firmware/2016-02-15-48-0.9ms.pof b/firmware/2016-02-15-48-0.9ms.pof deleted file mode 100644 index b34a65b..0000000 Binary files a/firmware/2016-02-15-48-0.9ms.pof and /dev/null differ diff --git a/firmware/2016-02-15-48-1ms.pof b/firmware/2016-02-15-48-1ms.pof deleted file mode 100644 index f6b4fff..0000000 Binary files a/firmware/2016-02-15-48-1ms.pof and /dev/null differ diff --git a/firmware/2016-03-09-HighVoltage-2ms.pof b/firmware/2016-03-09-HighVoltage-2ms.pof deleted file mode 100644 index d0a6829..0000000 Binary files a/firmware/2016-03-09-HighVoltage-2ms.pof and /dev/null differ diff --git a/firmware/2016-03-09-HighVoltage-3ms.pof b/firmware/2016-03-09-HighVoltage-3ms.pof deleted file mode 100644 index b6fcbb5..0000000 Binary files a/firmware/2016-03-09-HighVoltage-3ms.pof and /dev/null differ diff --git a/firmware/2016-03-09-HighVoltage-4ms.pof b/firmware/2016-03-09-HighVoltage-4ms.pof deleted file mode 100644 index 7de53db..0000000 Binary files a/firmware/2016-03-09-HighVoltage-4ms.pof and /dev/null differ diff --git a/firmware/LPM.qip b/firmware/LPM.qip deleted file mode 100644 index e69de29..0000000 diff --git a/firmware/PF1-10-17-481-0.37ms.pof b/firmware/PF1-10-17-481-0.37ms.pof deleted file mode 100644 index b38b104..0000000 Binary files a/firmware/PF1-10-17-481-0.37ms.pof and /dev/null differ diff --git a/firmware/PF1.done b/firmware/PF1.done deleted file mode 100644 index bc9e680..0000000 --- a/firmware/PF1.done +++ /dev/null @@ -1 +0,0 @@ -Thu Nov 11 17:04:12 2021 diff --git a/firmware/PF1.drc.rpt b/firmware/PF1.drc.rpt deleted file mode 100644 index ae0f89c..0000000 --- a/firmware/PF1.drc.rpt +++ /dev/null @@ -1,111 +0,0 @@ -Design Assistant report for PF1 -Thu Nov 04 10:40:09 2021 -Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Design Assistant Summary - 3. Design Assistant Settings - 4. Design Assistant Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2020 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+-------------------------------------------------------------------------+ -; Design Assistant Summary ; -+-----------------------------------+-------------------------------------+ -; Design Assistant Status ; Analyzed - Thu Nov 04 10:40:09 2021 ; -; Revision Name ; PF1 ; -; Top-level Entity Name ; PF1 ; -; Family ; MAX II ; -; Total Critical Violations ; 0 ; -; Total High Violations ; 0 ; -; Total Medium Violations ; 0 ; -; Total Information only Violations ; 0 ; -+-----------------------------------+-------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Design Assistant Settings ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ -; Option ; Setting ; To ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ -; Design Assistant mode ; Post-Fitting ; ; -; Threshold value for clock net not mapped to clock spines rule ; 25 ; ; -; Minimum number of clock port feed by gated clocks ; 30 ; ; -; Minimum number of node fan-out ; 30 ; ; -; Maximum number of nodes to report ; 50 ; ; -; Rule C101: Gated clock should be implemented according to the Intel FPGA standard scheme ; On ; ; -; Rule C102: Logic cell should not be used to generate an inverted clock signal ; On ; ; -; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; On ; ; -; Rule C104: Clock signal source should drive only clock input ports ; On ; ; -; Rule C105: Clock signal should be a global signal ; On ; ; -; Rule C106: Clock signal source should not drive registers triggered by different clock edges ; On ; ; -; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ; -; Rule R102: External reset signals should be synchronized using two cascaded registers ; On ; ; -; Rule R103: External reset signal should be correctly synchronized ; On ; ; -; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized ; On ; ; -; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized ; On ; ; -; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ; -; Rule T102: Top nodes with the highest number of fan-outs ; On ; ; -; Rule A101: Design should not contain combinational loops ; On ; ; -; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ; -; Rule A103: Design should not contain delay chains ; On ; ; -; Rule A104: Design should not contain ripple clock structures ; On ; ; -; Rule A105: Pulses should not be implemented asynchronously ; On ; ; -; Rule A106: Multiple pulses should not be generated in design ; On ; ; -; Rule A107: Design should not contain SR latches ; On ; ; -; Rule A108: Design should not contain latches ; On ; ; -; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ; -; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ; -; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source ; On ; ; -; Rule S104: Clock port and any other port of a register should not be driven by the same signal source ; On ; ; -; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ; -; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ; -; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ - - -+---------------------------+ -; Design Assistant Messages ; -+---------------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime Design Assistant - Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Thu Nov 04 10:40:08 2021 -Info: Command: quartus_drc PF1 -c PF1 -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Critical Warning (332012): Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Info (332144): No user constrained base clocks found in the design -Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. -Warning (332068): No clocks defined in design. -Info (308007): Design Assistant information: finished post-fitting analysis of current design -- generated 0 information messages and 0 warning messages -Info: Quartus Prime Design Assistant was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 4625 megabytes - Info: Processing ended: Thu Nov 04 10:40:09 2021 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:00 - - diff --git a/firmware/PF1.eda.rpt b/firmware/PF1.eda.rpt deleted file mode 100644 index e170d12..0000000 --- a/firmware/PF1.eda.rpt +++ /dev/null @@ -1,96 +0,0 @@ -EDA Netlist Writer report for PF1 -Thu Nov 11 17:04:11 2021 -Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. EDA Netlist Writer Summary - 3. Simulation Settings - 4. Simulation Generated Files - 5. EDA Netlist Writer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2020 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+-------------------------------------------------------------------+ -; EDA Netlist Writer Summary ; -+---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Thu Nov 11 17:04:11 2021 ; -; Revision Name ; PF1 ; -; Top-level Entity Name ; PF1 ; -; Family ; MAX II ; -; Simulation Files Creation ; Successful ; -+---------------------------+---------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Simulation Settings ; -+---------------------------------------------------------------------------------------------------+---------------------------+ -; Option ; Setting ; -+---------------------------------------------------------------------------------------------------+---------------------------+ -; Tool Name ; ModelSim-Altera (Verilog) ; -; Generate functional simulation netlist ; Off ; -; Time scale ; 1 ps ; -; Truncate long hierarchy paths ; Off ; -; Map illegal HDL characters ; Off ; -; Flatten buses into individual nodes ; Off ; -; Maintain hierarchy ; Off ; -; Bring out device-wide set/reset signals as ports ; Off ; -; Enable glitch filtering ; Off ; -; Do not write top level VHDL entity ; Off ; -; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; -; Architecture name in VHDL output netlist ; structure ; -; Generate third-party EDA tool command script for RTL functional simulation ; Off ; -; Generate third-party EDA tool command script for gate-level simulation ; Off ; -+---------------------------------------------------------------------------------------------------+---------------------------+ - - -+----------------------------------------------------------------------+ -; Simulation Generated Files ; -+----------------------------------------------------------------------+ -; Generated Files ; -+----------------------------------------------------------------------+ -; C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/PF1.vo ; -; C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/PF1_v.sdo ; -+----------------------------------------------------------------------+ - - -+-----------------------------+ -; EDA Netlist Writer Messages ; -+-----------------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime EDA Netlist Writer - Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Thu Nov 11 17:04:11 2021 -Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1 -Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (204018): Generated files "PF1.vo" and "PF1_v.sdo" in directory "C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/" for EDA simulation tool -Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 4628 megabytes - Info: Processing ended: Thu Nov 11 17:04:11 2021 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:01 - - diff --git a/firmware/PF1.jdi b/firmware/PF1.jdi deleted file mode 100644 index 74edcc7..0000000 --- a/firmware/PF1.jdi +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/firmware/PF1.map.smsg b/firmware/PF1.map.smsg deleted file mode 100644 index 7988cf9..0000000 --- a/firmware/PF1.map.smsg +++ /dev/null @@ -1,4 +0,0 @@ -Warning (10268): Verilog HDL information at PF1.v(161): always construct contains both blocking and non-blocking assignments -Warning (10268): Verilog HDL information at PF1.v(206): always construct contains both blocking and non-blocking assignments -Warning (10268): Verilog HDL information at PF1.v(250): always construct contains both blocking and non-blocking assignments -Warning (10268): Verilog HDL information at PF1.v(294): always construct contains both blocking and non-blocking assignments diff --git a/firmware/PF1.pof b/firmware/PF1.pof deleted file mode 100644 index befefc6..0000000 Binary files a/firmware/PF1.pof and /dev/null differ diff --git a/firmware/PF1.qpf b/firmware/PF1.qpf deleted file mode 100644 index 09259db..0000000 --- a/firmware/PF1.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2010 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version -# Date created = 13:42:56 December 10, 2011 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "9.1" -DATE = "13:42:56 December 10, 2011" - -# Revisions - -PROJECT_REVISION = "PF1" diff --git a/firmware/PF1.tan.rpt b/firmware/PF1.tan.rpt deleted file mode 100644 index de692fa..0000000 --- a/firmware/PF1.tan.rpt +++ /dev/null @@ -1,910 +0,0 @@ -Classic Timing Analyzer report for PF1 -Tue Jan 03 15:28:03 2012 -Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Timing Analyzer Settings - 4. Clock Settings Summary - 5. Parallel Compilation - 6. Clock Setup: 'clk' - 7. Clock Setup: 'SCLK' - 8. tsu - 9. tco - 10. th - 11. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+------------------------------+-------+---------------+----------------------------------+-----------+------------+------------+----------+--------------+ -; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; -+------------------------------+-------+---------------+----------------------------------+-----------+------------+------------+----------+--------------+ -; Worst-case tsu ; N/A ; None ; 3.893 ns ; SEN ; S_PFr[44] ; -- ; SCLK ; 0 ; -; Worst-case tco ; N/A ; None ; 8.833 ns ; S_PFr2[5] ; S_PF[5] ; clk ; -- ; 0 ; -; Worst-case th ; N/A ; None ; 0.072 ns ; SEN ; i[4] ; -- ; SCLK ; 0 ; -; Clock Setup: 'clk' ; N/A ; None ; 95.93 MHz ( period = 10.424 ns ) ; cnt[17] ; S_PFr2[41] ; clk ; clk ; 0 ; -; Clock Setup: 'SCLK' ; N/A ; None ; 126.07 MHz ( period = 7.932 ns ) ; i[4] ; S_PFr[44] ; SCLK ; SCLK ; 0 ; -; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; -+------------------------------+-------+---------------+----------------------------------+-----------+------------+------------+----------+--------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Settings ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Option ; Setting ; From ; To ; Entity Name ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ -; Device Name ; EPM240T100C5 ; ; ; ; -; Timing Models ; Final ; ; ; ; -; Default hold multicycle ; Same as Multicycle ; ; ; ; -; Cut paths between unrelated clock domains ; On ; ; ; ; -; Cut off read during write signal paths ; On ; ; ; ; -; Cut off feedback from I/O pins ; On ; ; ; ; -; Report Combined Fast/Slow Timing ; Off ; ; ; ; -; Ignore Clock Settings ; Off ; ; ; ; -; Analyze latches as synchronous elements ; On ; ; ; ; -; Enable Recovery/Removal analysis ; Off ; ; ; ; -; Enable Clock Latency ; Off ; ; ; ; -; Use TimeQuest Timing Analyzer ; Off ; ; ; ; -; Minimum Core Junction Temperature ; 0 ; ; ; ; -; Maximum Core Junction Temperature ; 85 ; ; ; ; -; Number of source nodes to report per destination node ; 10 ; ; ; ; -; Number of destination nodes to report ; 10 ; ; ; ; -; Number of paths to report ; 200 ; ; ; ; -; Report Minimum Timing Checks ; Off ; ; ; ; -; Use Fast Timing Models ; Off ; ; ; ; -; Report IO Paths Separately ; Off ; ; ; ; -; Perform Multicorner Analysis ; Off ; ; ; ; -; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; -; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; -; Output I/O Timing Endpoint ; Near End ; ; ; ; -+---------------------------------------------------------------------+--------------------+------+----+-------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Settings Summary ; -+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ -; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; -+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ -; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; -; SCLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; -+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 2 ; -; Maximum allowed ; 2 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; 1 processor ; 100.0% ; -; 2 processors ; 0.0% ; -+----------------------------+-------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'clk' ; -+-----------------------------------------+-----------------------------------------------------+---------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+---------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+ -; N/A ; 95.93 MHz ( period = 10.424 ns ) ; cnt[17] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.715 ns ; -; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[2] ; clk ; clk ; None ; None ; 9.250 ns ; -; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[5] ; clk ; clk ; None ; None ; 9.250 ns ; -; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[3] ; clk ; clk ; None ; None ; 9.250 ns ; -; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[4] ; clk ; clk ; None ; None ; 9.250 ns ; -; N/A ; 100.41 MHz ( period = 9.959 ns ) ; cnt[17] ; timer[1] ; clk ; clk ; None ; None ; 9.250 ns ; -; N/A ; 100.67 MHz ( period = 9.933 ns ) ; cnt[11] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.224 ns ; -; N/A ; 101.11 MHz ( period = 9.890 ns ) ; cnt[3] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.181 ns ; -; N/A ; 101.15 MHz ( period = 9.886 ns ) ; cnt[17] ; S_PFr2[13] ; clk ; clk ; None ; None ; 9.177 ns ; -; N/A ; 101.16 MHz ( period = 9.885 ns ) ; cnt[17] ; S_PFr2[36] ; clk ; clk ; None ; None ; 9.176 ns ; -; N/A ; 101.19 MHz ( period = 9.882 ns ) ; cnt[17] ; S_PFr2[44] ; clk ; clk ; None ; None ; 9.173 ns ; -; N/A ; 101.26 MHz ( period = 9.876 ns ) ; cnt[17] ; S_PFr2[37] ; clk ; clk ; None ; None ; 9.167 ns ; -; N/A ; 101.90 MHz ( period = 9.814 ns ) ; cnt[17] ; cnt[3] ; clk ; clk ; None ; None ; 9.105 ns ; -; N/A ; 101.92 MHz ( period = 9.812 ns ) ; cnt[2] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.103 ns ; -; N/A ; 102.26 MHz ( period = 9.779 ns ) ; cnt[7] ; S_PFr2[41] ; clk ; clk ; None ; None ; 9.070 ns ; -; N/A ; 102.43 MHz ( period = 9.763 ns ) ; cnt[17] ; cnt[14] ; clk ; clk ; None ; None ; 9.054 ns ; -; N/A ; 102.43 MHz ( period = 9.763 ns ) ; cnt[17] ; cnt[2] ; clk ; clk ; None ; None ; 9.054 ns ; -; N/A ; 103.52 MHz ( period = 9.660 ns ) ; cnt[6] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.951 ns ; -; N/A ; 103.70 MHz ( period = 9.643 ns ) ; cnt[17] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.934 ns ; -; N/A ; 103.71 MHz ( period = 9.642 ns ) ; cnt[17] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.933 ns ; -; N/A ; 103.78 MHz ( period = 9.636 ns ) ; cnt[17] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.927 ns ; -; N/A ; 103.79 MHz ( period = 9.635 ns ) ; cnt[17] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.926 ns ; -; N/A ; 103.95 MHz ( period = 9.620 ns ) ; cnt[1] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.911 ns ; -; N/A ; 104.07 MHz ( period = 9.609 ns ) ; cnt[17] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.900 ns ; -; N/A ; 104.08 MHz ( period = 9.608 ns ) ; cnt[17] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.899 ns ; -; N/A ; 104.09 MHz ( period = 9.607 ns ) ; cnt[17] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.898 ns ; -; N/A ; 104.16 MHz ( period = 9.601 ns ) ; cnt[17] ; cnt[12] ; clk ; clk ; None ; None ; 8.892 ns ; -; N/A ; 104.18 MHz ( period = 9.599 ns ) ; cnt[17] ; cnt[7] ; clk ; clk ; None ; None ; 8.890 ns ; -; N/A ; 104.78 MHz ( period = 9.544 ns ) ; cnt[17] ; cnt[13] ; clk ; clk ; None ; None ; 8.835 ns ; -; N/A ; 105.03 MHz ( period = 9.521 ns ) ; cnt[16] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.812 ns ; -; N/A ; 105.45 MHz ( period = 9.483 ns ) ; cnt[5] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.774 ns ; -; N/A ; 105.50 MHz ( period = 9.479 ns ) ; cnt[17] ; S_PFr2[46] ; clk ; clk ; None ; None ; 8.770 ns ; -; N/A ; 105.53 MHz ( period = 9.476 ns ) ; cnt[17] ; S_PFr2[10] ; clk ; clk ; None ; None ; 8.767 ns ; -; N/A ; 105.53 MHz ( period = 9.476 ns ) ; cnt[0] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.767 ns ; -; N/A ; 105.59 MHz ( period = 9.471 ns ) ; cnt[17] ; S_PFr2[12] ; clk ; clk ; None ; None ; 8.762 ns ; -; N/A ; 105.59 MHz ( period = 9.471 ns ) ; cnt[17] ; S_PFr2[15] ; clk ; clk ; None ; None ; 8.762 ns ; -; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[2] ; clk ; clk ; None ; None ; 8.759 ns ; -; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[5] ; clk ; clk ; None ; None ; 8.759 ns ; -; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[3] ; clk ; clk ; None ; None ; 8.759 ns ; -; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[4] ; clk ; clk ; None ; None ; 8.759 ns ; -; N/A ; 105.62 MHz ( period = 9.468 ns ) ; cnt[11] ; timer[1] ; clk ; clk ; None ; None ; 8.759 ns ; -; N/A ; 105.86 MHz ( period = 9.446 ns ) ; cnt[4] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.737 ns ; -; N/A ; 106.02 MHz ( period = 9.432 ns ) ; cnt[17] ; cnt[11] ; clk ; clk ; None ; None ; 8.723 ns ; -; N/A ; 106.03 MHz ( period = 9.431 ns ) ; cnt[17] ; cnt[15] ; clk ; clk ; None ; None ; 8.722 ns ; -; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[2] ; clk ; clk ; None ; None ; 8.716 ns ; -; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[5] ; clk ; clk ; None ; None ; 8.716 ns ; -; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[3] ; clk ; clk ; None ; None ; 8.716 ns ; -; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[4] ; clk ; clk ; None ; None ; 8.716 ns ; -; N/A ; 106.10 MHz ( period = 9.425 ns ) ; cnt[3] ; timer[1] ; clk ; clk ; None ; None ; 8.716 ns ; -; N/A ; 106.15 MHz ( period = 9.421 ns ) ; cnt[17] ; S_PFr2[27] ; clk ; clk ; None ; None ; 8.712 ns ; -; N/A ; 106.16 MHz ( period = 9.420 ns ) ; cnt[17] ; cnt[6] ; clk ; clk ; None ; None ; 8.711 ns ; -; N/A ; 106.44 MHz ( period = 9.395 ns ) ; cnt[11] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.686 ns ; -; N/A ; 106.45 MHz ( period = 9.394 ns ) ; cnt[11] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.685 ns ; -; N/A ; 106.48 MHz ( period = 9.391 ns ) ; cnt[11] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.682 ns ; -; N/A ; 106.55 MHz ( period = 9.385 ns ) ; cnt[11] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.676 ns ; -; N/A ; 106.68 MHz ( period = 9.374 ns ) ; cnt[17] ; S_PFr2[28] ; clk ; clk ; None ; None ; 8.665 ns ; -; N/A ; 106.69 MHz ( period = 9.373 ns ) ; cnt[17] ; cnt[1] ; clk ; clk ; None ; None ; 8.664 ns ; -; N/A ; 106.76 MHz ( period = 9.367 ns ) ; cnt[17] ; S_PFr2[25] ; clk ; clk ; None ; None ; 8.658 ns ; -; N/A ; 106.78 MHz ( period = 9.365 ns ) ; cnt[17] ; S_PFr2[21] ; clk ; clk ; None ; None ; 8.656 ns ; -; N/A ; 106.79 MHz ( period = 9.364 ns ) ; cnt[17] ; S_PFr2[3] ; clk ; clk ; None ; None ; 8.655 ns ; -; N/A ; 106.88 MHz ( period = 9.356 ns ) ; cnt[17] ; S_PFr2[18] ; clk ; clk ; None ; None ; 8.647 ns ; -; N/A ; 106.93 MHz ( period = 9.352 ns ) ; cnt[3] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.643 ns ; -; N/A ; 106.94 MHz ( period = 9.351 ns ) ; cnt[3] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.642 ns ; -; N/A ; 106.97 MHz ( period = 9.348 ns ) ; cnt[3] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.639 ns ; -; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[2] ; clk ; clk ; None ; None ; 8.638 ns ; -; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[5] ; clk ; clk ; None ; None ; 8.638 ns ; -; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[3] ; clk ; clk ; None ; None ; 8.638 ns ; -; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[4] ; clk ; clk ; None ; None ; 8.638 ns ; -; N/A ; 106.99 MHz ( period = 9.347 ns ) ; cnt[2] ; timer[1] ; clk ; clk ; None ; None ; 8.638 ns ; -; N/A ; 107.01 MHz ( period = 9.345 ns ) ; cnt[17] ; cnt[4] ; clk ; clk ; None ; None ; 8.636 ns ; -; N/A ; 107.01 MHz ( period = 9.345 ns ) ; cnt[17] ; cnt[0] ; clk ; clk ; None ; None ; 8.636 ns ; -; N/A ; 107.04 MHz ( period = 9.342 ns ) ; cnt[3] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.633 ns ; -; N/A ; 107.04 MHz ( period = 9.342 ns ) ; cnt[17] ; cnt[5] ; clk ; clk ; None ; None ; 8.633 ns ; -; N/A ; 107.07 MHz ( period = 9.340 ns ) ; cnt[17] ; S_PFr2[26] ; clk ; clk ; None ; None ; 8.631 ns ; -; N/A ; 107.26 MHz ( period = 9.323 ns ) ; cnt[11] ; cnt[3] ; clk ; clk ; None ; None ; 8.614 ns ; -; N/A ; 107.30 MHz ( period = 9.320 ns ) ; cnt[17] ; S_PFr2[43] ; clk ; clk ; None ; None ; 8.611 ns ; -; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[2] ; clk ; clk ; None ; None ; 8.605 ns ; -; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[5] ; clk ; clk ; None ; None ; 8.605 ns ; -; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[3] ; clk ; clk ; None ; None ; 8.605 ns ; -; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[4] ; clk ; clk ; None ; None ; 8.605 ns ; -; N/A ; 107.37 MHz ( period = 9.314 ns ) ; cnt[7] ; timer[1] ; clk ; clk ; None ; None ; 8.605 ns ; -; N/A ; 107.76 MHz ( period = 9.280 ns ) ; cnt[3] ; cnt[3] ; clk ; clk ; None ; None ; 8.571 ns ; -; N/A ; 107.83 MHz ( period = 9.274 ns ) ; cnt[2] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.565 ns ; -; N/A ; 107.84 MHz ( period = 9.273 ns ) ; cnt[2] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.564 ns ; -; N/A ; 107.84 MHz ( period = 9.273 ns ) ; cnt[9] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.564 ns ; -; N/A ; 107.85 MHz ( period = 9.272 ns ) ; cnt[11] ; cnt[14] ; clk ; clk ; None ; None ; 8.563 ns ; -; N/A ; 107.85 MHz ( period = 9.272 ns ) ; cnt[11] ; cnt[2] ; clk ; clk ; None ; None ; 8.563 ns ; -; N/A ; 107.87 MHz ( period = 9.270 ns ) ; cnt[2] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.561 ns ; -; N/A ; 107.94 MHz ( period = 9.264 ns ) ; cnt[2] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.555 ns ; -; N/A ; 108.21 MHz ( period = 9.241 ns ) ; cnt[7] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.532 ns ; -; N/A ; 108.23 MHz ( period = 9.240 ns ) ; cnt[7] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.531 ns ; -; N/A ; 108.26 MHz ( period = 9.237 ns ) ; cnt[7] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.528 ns ; -; N/A ; 108.31 MHz ( period = 9.233 ns ) ; cnt[17] ; S_PFr2[16] ; clk ; clk ; None ; None ; 8.524 ns ; -; N/A ; 108.33 MHz ( period = 9.231 ns ) ; cnt[7] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.522 ns ; -; N/A ; 108.35 MHz ( period = 9.229 ns ) ; cnt[3] ; cnt[14] ; clk ; clk ; None ; None ; 8.520 ns ; -; N/A ; 108.35 MHz ( period = 9.229 ns ) ; cnt[3] ; cnt[2] ; clk ; clk ; None ; None ; 8.520 ns ; -; N/A ; 108.39 MHz ( period = 9.226 ns ) ; cnt[17] ; S_PFr2[17] ; clk ; clk ; None ; None ; 8.517 ns ; -; N/A ; 108.42 MHz ( period = 9.223 ns ) ; cnt[17] ; cnt[17] ; clk ; clk ; None ; None ; 8.514 ns ; -; N/A ; 108.67 MHz ( period = 9.202 ns ) ; cnt[2] ; cnt[3] ; clk ; clk ; None ; None ; 8.493 ns ; -; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[2] ; clk ; clk ; None ; None ; 8.486 ns ; -; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[5] ; clk ; clk ; None ; None ; 8.486 ns ; -; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[3] ; clk ; clk ; None ; None ; 8.486 ns ; -; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[4] ; clk ; clk ; None ; None ; 8.486 ns ; -; N/A ; 108.75 MHz ( period = 9.195 ns ) ; cnt[6] ; timer[1] ; clk ; clk ; None ; None ; 8.486 ns ; -; N/A ; 109.06 MHz ( period = 9.169 ns ) ; cnt[7] ; cnt[3] ; clk ; clk ; None ; None ; 8.460 ns ; -; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[2] ; clk ; clk ; None ; None ; 8.446 ns ; -; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[5] ; clk ; clk ; None ; None ; 8.446 ns ; -; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[3] ; clk ; clk ; None ; None ; 8.446 ns ; -; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[4] ; clk ; clk ; None ; None ; 8.446 ns ; -; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[17] ; cnt[16] ; clk ; clk ; None ; None ; 8.446 ns ; -; N/A ; 109.23 MHz ( period = 9.155 ns ) ; cnt[1] ; timer[1] ; clk ; clk ; None ; None ; 8.446 ns ; -; N/A ; 109.27 MHz ( period = 9.152 ns ) ; cnt[11] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.443 ns ; -; N/A ; 109.28 MHz ( period = 9.151 ns ) ; cnt[11] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.442 ns ; -; N/A ; 109.28 MHz ( period = 9.151 ns ) ; cnt[2] ; cnt[14] ; clk ; clk ; None ; None ; 8.442 ns ; -; N/A ; 109.28 MHz ( period = 9.151 ns ) ; cnt[2] ; cnt[2] ; clk ; clk ; None ; None ; 8.442 ns ; -; N/A ; 109.35 MHz ( period = 9.145 ns ) ; cnt[11] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.436 ns ; -; N/A ; 109.36 MHz ( period = 9.144 ns ) ; cnt[11] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.435 ns ; -; N/A ; 109.43 MHz ( period = 9.138 ns ) ; cnt[17] ; cnt[19] ; clk ; clk ; None ; None ; 8.429 ns ; -; N/A ; 109.63 MHz ( period = 9.122 ns ) ; cnt[6] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.413 ns ; -; N/A ; 109.64 MHz ( period = 9.121 ns ) ; cnt[6] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.412 ns ; -; N/A ; 109.67 MHz ( period = 9.118 ns ) ; cnt[11] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.409 ns ; -; N/A ; 109.67 MHz ( period = 9.118 ns ) ; cnt[6] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.409 ns ; -; N/A ; 109.67 MHz ( period = 9.118 ns ) ; cnt[7] ; cnt[14] ; clk ; clk ; None ; None ; 8.409 ns ; -; N/A ; 109.67 MHz ( period = 9.118 ns ) ; cnt[7] ; cnt[2] ; clk ; clk ; None ; None ; 8.409 ns ; -; N/A ; 109.69 MHz ( period = 9.117 ns ) ; cnt[11] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.408 ns ; -; N/A ; 109.69 MHz ( period = 9.117 ns ) ; cnt[16] ; cnt[16] ; clk ; clk ; None ; None ; 8.408 ns ; -; N/A ; 109.70 MHz ( period = 9.116 ns ) ; cnt[11] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.407 ns ; -; N/A ; 109.75 MHz ( period = 9.112 ns ) ; cnt[6] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.403 ns ; -; N/A ; 109.77 MHz ( period = 9.110 ns ) ; cnt[11] ; cnt[12] ; clk ; clk ; None ; None ; 8.401 ns ; -; N/A ; 109.78 MHz ( period = 9.109 ns ) ; cnt[3] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.400 ns ; -; N/A ; 109.79 MHz ( period = 9.108 ns ) ; cnt[3] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.399 ns ; -; N/A ; 109.79 MHz ( period = 9.108 ns ) ; cnt[11] ; cnt[7] ; clk ; clk ; None ; None ; 8.399 ns ; -; N/A ; 109.87 MHz ( period = 9.102 ns ) ; cnt[3] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.393 ns ; -; N/A ; 109.88 MHz ( period = 9.101 ns ) ; cnt[3] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.392 ns ; -; N/A ; 109.99 MHz ( period = 9.092 ns ) ; cnt[7] ; cnt[19] ; clk ; clk ; None ; None ; 8.383 ns ; -; N/A ; 110.11 MHz ( period = 9.082 ns ) ; cnt[1] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.373 ns ; -; N/A ; 110.12 MHz ( period = 9.081 ns ) ; cnt[1] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.372 ns ; -; N/A ; 110.16 MHz ( period = 9.078 ns ) ; cnt[1] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.369 ns ; -; N/A ; 110.19 MHz ( period = 9.075 ns ) ; cnt[3] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.366 ns ; -; N/A ; 110.20 MHz ( period = 9.074 ns ) ; cnt[3] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.365 ns ; -; N/A ; 110.22 MHz ( period = 9.073 ns ) ; cnt[3] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.364 ns ; -; N/A ; 110.23 MHz ( period = 9.072 ns ) ; cnt[1] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.363 ns ; -; N/A ; 110.29 MHz ( period = 9.067 ns ) ; cnt[3] ; cnt[12] ; clk ; clk ; None ; None ; 8.358 ns ; -; N/A ; 110.31 MHz ( period = 9.065 ns ) ; cnt[3] ; cnt[7] ; clk ; clk ; None ; None ; 8.356 ns ; -; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[2] ; clk ; clk ; None ; None ; 8.347 ns ; -; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[5] ; clk ; clk ; None ; None ; 8.347 ns ; -; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[3] ; clk ; clk ; None ; None ; 8.347 ns ; -; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[4] ; clk ; clk ; None ; None ; 8.347 ns ; -; N/A ; 110.42 MHz ( period = 9.056 ns ) ; cnt[16] ; timer[1] ; clk ; clk ; None ; None ; 8.347 ns ; -; N/A ; 110.46 MHz ( period = 9.053 ns ) ; cnt[11] ; cnt[13] ; clk ; clk ; None ; None ; 8.344 ns ; -; N/A ; 110.50 MHz ( period = 9.050 ns ) ; cnt[6] ; cnt[3] ; clk ; clk ; None ; None ; 8.341 ns ; -; N/A ; 110.58 MHz ( period = 9.043 ns ) ; cnt[17] ; timer[0] ; clk ; clk ; None ; None ; 8.334 ns ; -; N/A ; 110.73 MHz ( period = 9.031 ns ) ; cnt[2] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.322 ns ; -; N/A ; 110.74 MHz ( period = 9.030 ns ) ; cnt[2] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.321 ns ; -; N/A ; 110.82 MHz ( period = 9.024 ns ) ; cnt[10] ; S_PFr2[41] ; clk ; clk ; None ; None ; 8.315 ns ; -; N/A ; 110.82 MHz ( period = 9.024 ns ) ; cnt[2] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.315 ns ; -; N/A ; 110.83 MHz ( period = 9.023 ns ) ; cnt[2] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.314 ns ; -; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[2] ; clk ; clk ; None ; None ; 8.309 ns ; -; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[5] ; clk ; clk ; None ; None ; 8.309 ns ; -; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[3] ; clk ; clk ; None ; None ; 8.309 ns ; -; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[4] ; clk ; clk ; None ; None ; 8.309 ns ; -; N/A ; 110.89 MHz ( period = 9.018 ns ) ; cnt[5] ; timer[1] ; clk ; clk ; None ; None ; 8.309 ns ; -; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[2] ; clk ; clk ; None ; None ; 8.302 ns ; -; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[5] ; clk ; clk ; None ; None ; 8.302 ns ; -; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[3] ; clk ; clk ; None ; None ; 8.302 ns ; -; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[4] ; clk ; clk ; None ; None ; 8.302 ns ; -; N/A ; 110.98 MHz ( period = 9.011 ns ) ; cnt[0] ; timer[1] ; clk ; clk ; None ; None ; 8.302 ns ; -; N/A ; 110.99 MHz ( period = 9.010 ns ) ; cnt[3] ; cnt[13] ; clk ; clk ; None ; None ; 8.301 ns ; -; N/A ; 110.99 MHz ( period = 9.010 ns ) ; cnt[1] ; cnt[3] ; clk ; clk ; None ; None ; 8.301 ns ; -; N/A ; 111.12 MHz ( period = 8.999 ns ) ; cnt[6] ; cnt[14] ; clk ; clk ; None ; None ; 8.290 ns ; -; N/A ; 111.12 MHz ( period = 8.999 ns ) ; cnt[6] ; cnt[2] ; clk ; clk ; None ; None ; 8.290 ns ; -; N/A ; 111.14 MHz ( period = 8.998 ns ) ; cnt[7] ; S_PFr2[6] ; clk ; clk ; None ; None ; 8.289 ns ; -; N/A ; 111.15 MHz ( period = 8.997 ns ) ; cnt[2] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.288 ns ; -; N/A ; 111.15 MHz ( period = 8.997 ns ) ; cnt[7] ; S_PFr2[11] ; clk ; clk ; None ; None ; 8.288 ns ; -; N/A ; 111.16 MHz ( period = 8.996 ns ) ; cnt[2] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.287 ns ; -; N/A ; 111.17 MHz ( period = 8.995 ns ) ; cnt[2] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.286 ns ; -; N/A ; 111.22 MHz ( period = 8.991 ns ) ; cnt[7] ; S_PFr2[45] ; clk ; clk ; None ; None ; 8.282 ns ; -; N/A ; 111.23 MHz ( period = 8.990 ns ) ; cnt[7] ; S_PFr2[35] ; clk ; clk ; None ; None ; 8.281 ns ; -; N/A ; 111.25 MHz ( period = 8.989 ns ) ; cnt[2] ; cnt[12] ; clk ; clk ; None ; None ; 8.280 ns ; -; N/A ; 111.26 MHz ( period = 8.988 ns ) ; cnt[11] ; S_PFr2[46] ; clk ; clk ; None ; None ; 8.279 ns ; -; N/A ; 111.27 MHz ( period = 8.987 ns ) ; cnt[2] ; cnt[7] ; clk ; clk ; None ; None ; 8.278 ns ; -; N/A ; 111.30 MHz ( period = 8.985 ns ) ; cnt[11] ; S_PFr2[10] ; clk ; clk ; None ; None ; 8.276 ns ; -; N/A ; 111.32 MHz ( period = 8.983 ns ) ; cnt[16] ; S_PFr2[13] ; clk ; clk ; None ; None ; 8.274 ns ; -; N/A ; 111.33 MHz ( period = 8.982 ns ) ; cnt[16] ; S_PFr2[36] ; clk ; clk ; None ; None ; 8.273 ns ; -; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[2] ; clk ; clk ; None ; None ; 8.272 ns ; -; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[5] ; clk ; clk ; None ; None ; 8.272 ns ; -; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[3] ; clk ; clk ; None ; None ; 8.272 ns ; -; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[4] ; clk ; clk ; None ; None ; 8.272 ns ; -; N/A ; 111.35 MHz ( period = 8.981 ns ) ; cnt[4] ; timer[1] ; clk ; clk ; None ; None ; 8.272 ns ; -; N/A ; 111.36 MHz ( period = 8.980 ns ) ; cnt[11] ; S_PFr2[12] ; clk ; clk ; None ; None ; 8.271 ns ; -; N/A ; 111.36 MHz ( period = 8.980 ns ) ; cnt[11] ; S_PFr2[15] ; clk ; clk ; None ; None ; 8.271 ns ; -; N/A ; 111.37 MHz ( period = 8.979 ns ) ; cnt[16] ; S_PFr2[44] ; clk ; clk ; None ; None ; 8.270 ns ; -; N/A ; 111.45 MHz ( period = 8.973 ns ) ; cnt[16] ; S_PFr2[37] ; clk ; clk ; None ; None ; 8.264 ns ; -; N/A ; 111.56 MHz ( period = 8.964 ns ) ; cnt[7] ; S_PFr2[7] ; clk ; clk ; None ; None ; 8.255 ns ; -; N/A ; 111.57 MHz ( period = 8.963 ns ) ; cnt[7] ; S_PFr2[1] ; clk ; clk ; None ; None ; 8.254 ns ; -; N/A ; 111.58 MHz ( period = 8.962 ns ) ; cnt[7] ; S_PFr2[5] ; clk ; clk ; None ; None ; 8.253 ns ; -; N/A ; 111.62 MHz ( period = 8.959 ns ) ; cnt[1] ; cnt[14] ; clk ; clk ; None ; None ; 8.250 ns ; -; N/A ; 111.62 MHz ( period = 8.959 ns ) ; cnt[1] ; cnt[2] ; clk ; clk ; None ; None ; 8.250 ns ; -; N/A ; 111.66 MHz ( period = 8.956 ns ) ; cnt[7] ; cnt[12] ; clk ; clk ; None ; None ; 8.247 ns ; -; N/A ; 111.68 MHz ( period = 8.954 ns ) ; cnt[7] ; cnt[7] ; clk ; clk ; None ; None ; 8.245 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+---------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'SCLK' ; -+-----------------------------------------+-----------------------------------------------------+------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+ -; N/A ; 126.07 MHz ( period = 7.932 ns ) ; i[4] ; S_PFr[44] ; SCLK ; SCLK ; None ; None ; 7.223 ns ; -; N/A ; 130.94 MHz ( period = 7.637 ns ) ; i[4] ; S_PFr[14] ; SCLK ; SCLK ; None ; None ; 6.928 ns ; -; N/A ; 131.03 MHz ( period = 7.632 ns ) ; i[4] ; S_PFr[12] ; SCLK ; SCLK ; None ; None ; 6.923 ns ; -; N/A ; 131.06 MHz ( period = 7.630 ns ) ; i[4] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 6.921 ns ; -; N/A ; 131.48 MHz ( period = 7.606 ns ) ; i[4] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 6.897 ns ; -; N/A ; 131.58 MHz ( period = 7.600 ns ) ; i[4] ; S_PFr[36] ; SCLK ; SCLK ; None ; None ; 6.891 ns ; -; N/A ; 132.17 MHz ( period = 7.566 ns ) ; i[4] ; S_PFr[34] ; SCLK ; SCLK ; None ; None ; 6.857 ns ; -; N/A ; 132.36 MHz ( period = 7.555 ns ) ; i[4] ; S_PFr[32] ; SCLK ; SCLK ; None ; None ; 6.846 ns ; -; N/A ; 134.16 MHz ( period = 7.454 ns ) ; i[4] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 6.745 ns ; -; N/A ; 135.41 MHz ( period = 7.385 ns ) ; i[5] ; S_PFr[14] ; SCLK ; SCLK ; None ; None ; 6.676 ns ; -; N/A ; 135.48 MHz ( period = 7.381 ns ) ; i[0] ; S_PFr[44] ; SCLK ; SCLK ; None ; None ; 6.672 ns ; -; N/A ; 135.50 MHz ( period = 7.380 ns ) ; i[5] ; S_PFr[12] ; SCLK ; SCLK ; None ; None ; 6.671 ns ; -; N/A ; 135.54 MHz ( period = 7.378 ns ) ; i[5] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 6.669 ns ; -; N/A ; 135.63 MHz ( period = 7.373 ns ) ; i[4] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 6.664 ns ; -; N/A ; 136.04 MHz ( period = 7.351 ns ) ; i[0] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 6.642 ns ; -; N/A ; 136.05 MHz ( period = 7.350 ns ) ; i[2] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 6.641 ns ; -; N/A ; 136.84 MHz ( period = 7.308 ns ) ; i[4] ; S_PFr[5] ; SCLK ; SCLK ; None ; None ; 6.599 ns ; -; N/A ; 137.38 MHz ( period = 7.279 ns ) ; i[0] ; S_PFr[14] ; SCLK ; SCLK ; None ; None ; 6.570 ns ; -; N/A ; 137.48 MHz ( period = 7.274 ns ) ; i[0] ; S_PFr[12] ; SCLK ; SCLK ; None ; None ; 6.565 ns ; -; N/A ; 137.51 MHz ( period = 7.272 ns ) ; i[0] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 6.563 ns ; -; N/A ; 137.82 MHz ( period = 7.256 ns ) ; i[4] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 6.547 ns ; -; N/A ; 138.06 MHz ( period = 7.243 ns ) ; i[4] ; S_PFr[39] ; SCLK ; SCLK ; None ; None ; 6.534 ns ; -; N/A ; 139.06 MHz ( period = 7.191 ns ) ; i[4] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 6.482 ns ; -; N/A ; 139.88 MHz ( period = 7.149 ns ) ; i[4] ; S_PFr[21] ; SCLK ; SCLK ; None ; None ; 6.440 ns ; -; N/A ; 139.88 MHz ( period = 7.149 ns ) ; i[4] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 6.440 ns ; -; N/A ; 139.90 MHz ( period = 7.148 ns ) ; i[2] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 6.439 ns ; -; N/A ; 139.94 MHz ( period = 7.146 ns ) ; i[5] ; S_PFr[5] ; SCLK ; SCLK ; None ; None ; 6.437 ns ; -; N/A ; 139.98 MHz ( period = 7.144 ns ) ; i[2] ; S_PFr[23] ; SCLK ; SCLK ; None ; None ; 6.435 ns ; -; N/A ; 140.10 MHz ( period = 7.138 ns ) ; i[2] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 6.429 ns ; -; N/A ; 140.23 MHz ( period = 7.131 ns ) ; i[2] ; S_PFr[0] ; SCLK ; SCLK ; None ; None ; 6.422 ns ; -; N/A ; 141.88 MHz ( period = 7.048 ns ) ; i[5] ; S_PFr[44] ; SCLK ; SCLK ; None ; None ; 6.339 ns ; -; N/A ; 141.92 MHz ( period = 7.046 ns ) ; i[0] ; S_PFr[21] ; SCLK ; SCLK ; None ; None ; 6.337 ns ; -; N/A ; 141.92 MHz ( period = 7.046 ns ) ; i[0] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 6.337 ns ; -; N/A ; 142.69 MHz ( period = 7.008 ns ) ; i[5] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 6.299 ns ; -; N/A ; 143.86 MHz ( period = 6.951 ns ) ; i[3] ; S_PFr[5] ; SCLK ; SCLK ; None ; None ; 6.242 ns ; -; N/A ; 144.22 MHz ( period = 6.934 ns ) ; i[5] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 6.225 ns ; -; N/A ; 144.89 MHz ( period = 6.902 ns ) ; i[3] ; S_PFr[44] ; SCLK ; SCLK ; None ; None ; 6.193 ns ; -; N/A ; 145.07 MHz ( period = 6.893 ns ) ; i[4] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 6.184 ns ; -; N/A ; 145.12 MHz ( period = 6.891 ns ) ; i[4] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 6.182 ns ; -; N/A ; 145.22 MHz ( period = 6.886 ns ) ; i[3] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 6.177 ns ; -; N/A ; 145.29 MHz ( period = 6.883 ns ) ; i[3] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 6.174 ns ; -; N/A ; 145.35 MHz ( period = 6.880 ns ) ; i[4] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 6.171 ns ; -; N/A ; 145.35 MHz ( period = 6.880 ns ) ; i[4] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 6.171 ns ; -; N/A ; 145.41 MHz ( period = 6.877 ns ) ; i[4] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 6.168 ns ; -; N/A ; 145.52 MHz ( period = 6.872 ns ) ; i[3] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 6.163 ns ; -; N/A ; 145.58 MHz ( period = 6.869 ns ) ; i[3] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 6.160 ns ; -; N/A ; 145.62 MHz ( period = 6.867 ns ) ; i[1] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 6.158 ns ; -; N/A ; 146.71 MHz ( period = 6.816 ns ) ; i[2] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 6.107 ns ; -; N/A ; 146.78 MHz ( period = 6.813 ns ) ; i[2] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 6.104 ns ; -; N/A ; 146.97 MHz ( period = 6.804 ns ) ; i[2] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 6.095 ns ; -; N/A ; 147.04 MHz ( period = 6.801 ns ) ; i[2] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 6.092 ns ; -; N/A ; 147.86 MHz ( period = 6.763 ns ) ; i[0] ; S_PFr[5] ; SCLK ; SCLK ; None ; None ; 6.054 ns ; -; N/A ; 148.04 MHz ( period = 6.755 ns ) ; i[4] ; S_PFr[13] ; SCLK ; SCLK ; None ; None ; 6.046 ns ; -; N/A ; 148.37 MHz ( period = 6.740 ns ) ; i[4] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 6.031 ns ; -; N/A ; 148.43 MHz ( period = 6.737 ns ) ; i[4] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 6.028 ns ; -; N/A ; 148.85 MHz ( period = 6.718 ns ) ; i[5] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 6.009 ns ; -; N/A ; 148.85 MHz ( period = 6.718 ns ) ; i[5] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 6.009 ns ; -; N/A ; 149.12 MHz ( period = 6.706 ns ) ; i[3] ; S_PFr[36] ; SCLK ; SCLK ; None ; None ; 5.997 ns ; -; N/A ; 149.14 MHz ( period = 6.705 ns ) ; i[0] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 5.996 ns ; -; N/A ; 149.77 MHz ( period = 6.677 ns ) ; i[1] ; S_PFr[26] ; SCLK ; SCLK ; None ; None ; 5.968 ns ; -; N/A ; 149.81 MHz ( period = 6.675 ns ) ; i[1] ; S_PFr[27] ; SCLK ; SCLK ; None ; None ; 5.966 ns ; -; N/A ; 149.88 MHz ( period = 6.672 ns ) ; i[3] ; S_PFr[34] ; SCLK ; SCLK ; None ; None ; 5.963 ns ; -; N/A ; 149.88 MHz ( period = 6.672 ns ) ; i[4] ; S_PFr[38] ; SCLK ; SCLK ; None ; None ; 5.963 ns ; -; N/A ; 149.97 MHz ( period = 6.668 ns ) ; i[3] ; S_PFr[26] ; SCLK ; SCLK ; None ; None ; 5.959 ns ; -; N/A ; 150.02 MHz ( period = 6.666 ns ) ; i[3] ; S_PFr[27] ; SCLK ; SCLK ; None ; None ; 5.957 ns ; -; N/A ; 150.13 MHz ( period = 6.661 ns ) ; i[3] ; S_PFr[32] ; SCLK ; SCLK ; None ; None ; 5.952 ns ; -; N/A ; 150.20 MHz ( period = 6.658 ns ) ; i[5] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 5.949 ns ; -; N/A ; 150.26 MHz ( period = 6.655 ns ) ; i[1] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 5.946 ns ; -; N/A ; 150.35 MHz ( period = 6.651 ns ) ; i[3] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 5.942 ns ; -; N/A ; 150.42 MHz ( period = 6.648 ns ) ; i[1] ; S_PFr[0] ; SCLK ; SCLK ; None ; None ; 5.939 ns ; -; N/A ; 150.58 MHz ( period = 6.641 ns ) ; i[5] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 5.932 ns ; -; N/A ; 150.63 MHz ( period = 6.639 ns ) ; i[5] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.930 ns ; -; N/A ; 150.65 MHz ( period = 6.638 ns ) ; i[3] ; S_PFr[39] ; SCLK ; SCLK ; None ; None ; 5.929 ns ; -; N/A ; 150.94 MHz ( period = 6.625 ns ) ; i[5] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 5.916 ns ; -; N/A ; 151.24 MHz ( period = 6.612 ns ) ; i[1] ; S_PFr[30] ; SCLK ; SCLK ; None ; None ; 5.903 ns ; -; N/A ; 151.26 MHz ( period = 6.611 ns ) ; i[4] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 5.902 ns ; -; N/A ; 151.42 MHz ( period = 6.604 ns ) ; i[3] ; S_PFr[30] ; SCLK ; SCLK ; None ; None ; 5.895 ns ; -; N/A ; 151.49 MHz ( period = 6.601 ns ) ; i[1] ; S_PFr[31] ; SCLK ; SCLK ; None ; None ; 5.892 ns ; -; N/A ; 151.61 MHz ( period = 6.596 ns ) ; i[2] ; S_PFr[41] ; SCLK ; SCLK ; None ; None ; 5.887 ns ; -; N/A ; 151.68 MHz ( period = 6.593 ns ) ; i[3] ; S_PFr[31] ; SCLK ; SCLK ; None ; None ; 5.884 ns ; -; N/A ; 151.70 MHz ( period = 6.592 ns ) ; i[5] ; S_PFr[13] ; SCLK ; SCLK ; None ; None ; 5.883 ns ; -; N/A ; 151.77 MHz ( period = 6.589 ns ) ; i[3] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.880 ns ; -; N/A ; 151.84 MHz ( period = 6.586 ns ) ; i[5] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 5.877 ns ; -; N/A ; 152.07 MHz ( period = 6.576 ns ) ; i[2] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 5.867 ns ; -; N/A ; 152.44 MHz ( period = 6.560 ns ) ; i[0] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 5.851 ns ; -; N/A ; 152.70 MHz ( period = 6.549 ns ) ; i[2] ; S_PFr[26] ; SCLK ; SCLK ; None ; None ; 5.840 ns ; -; N/A ; 152.70 MHz ( period = 6.549 ns ) ; i[4] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 5.840 ns ; -; N/A ; 152.74 MHz ( period = 6.547 ns ) ; i[2] ; S_PFr[27] ; SCLK ; SCLK ; None ; None ; 5.838 ns ; -; N/A ; 153.02 MHz ( period = 6.535 ns ) ; i[0] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 5.826 ns ; -; N/A ; 153.07 MHz ( period = 6.533 ns ) ; i[0] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.824 ns ; -; N/A ; 153.30 MHz ( period = 6.523 ns ) ; i[3] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 5.814 ns ; -; N/A ; 153.30 MHz ( period = 6.523 ns ) ; i[3] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 5.814 ns ; -; N/A ; 153.40 MHz ( period = 6.519 ns ) ; i[0] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 5.810 ns ; -; N/A ; 153.54 MHz ( period = 6.513 ns ) ; i[2] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.804 ns ; -; N/A ; 153.54 MHz ( period = 6.513 ns ) ; i[1] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 5.804 ns ; -; N/A ; 153.70 MHz ( period = 6.506 ns ) ; i[0] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 5.797 ns ; -; N/A ; 153.75 MHz ( period = 6.504 ns ) ; i[3] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 5.795 ns ; -; N/A ; 153.87 MHz ( period = 6.499 ns ) ; i[0] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 5.790 ns ; -; N/A ; 154.08 MHz ( period = 6.490 ns ) ; i[5] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 5.781 ns ; -; N/A ; 154.23 MHz ( period = 6.484 ns ) ; i[2] ; S_PFr[30] ; SCLK ; SCLK ; None ; None ; 5.775 ns ; -; N/A ; 154.25 MHz ( period = 6.483 ns ) ; i[5] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 5.774 ns ; -; N/A ; 154.32 MHz ( period = 6.480 ns ) ; i[5] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 5.771 ns ; -; N/A ; 154.49 MHz ( period = 6.473 ns ) ; i[2] ; S_PFr[31] ; SCLK ; SCLK ; None ; None ; 5.764 ns ; -; N/A ; 154.94 MHz ( period = 6.454 ns ) ; i[1] ; S_PFr[4] ; SCLK ; SCLK ; None ; None ; 5.745 ns ; -; N/A ; 154.99 MHz ( period = 6.452 ns ) ; i[0] ; S_PFr[39] ; SCLK ; SCLK ; None ; None ; 5.743 ns ; -; N/A ; 155.01 MHz ( period = 6.451 ns ) ; i[1] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 5.742 ns ; -; N/A ; 155.09 MHz ( period = 6.448 ns ) ; i[5] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 5.739 ns ; -; N/A ; 155.23 MHz ( period = 6.442 ns ) ; i[1] ; S_PFr[8] ; SCLK ; SCLK ; None ; None ; 5.733 ns ; -; N/A ; 155.30 MHz ( period = 6.439 ns ) ; i[1] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 5.730 ns ; -; N/A ; 155.81 MHz ( period = 6.418 ns ) ; i[3] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 5.709 ns ; -; N/A ; 155.88 MHz ( period = 6.415 ns ) ; i[2] ; S_PFr[35] ; SCLK ; SCLK ; None ; None ; 5.706 ns ; -; N/A ; 155.96 MHz ( period = 6.412 ns ) ; i[2] ; S_PFr[11] ; SCLK ; SCLK ; None ; None ; 5.703 ns ; -; N/A ; 155.98 MHz ( period = 6.411 ns ) ; i[2] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 5.702 ns ; -; N/A ; 156.40 MHz ( period = 6.394 ns ) ; i[2] ; S_PFr[9] ; SCLK ; SCLK ; None ; None ; 5.685 ns ; -; N/A ; 156.62 MHz ( period = 6.385 ns ) ; i[2] ; S_PFr[10] ; SCLK ; SCLK ; None ; None ; 5.676 ns ; -; N/A ; 156.62 MHz ( period = 6.385 ns ) ; i[3] ; S_PFr[13] ; SCLK ; SCLK ; None ; None ; 5.676 ns ; -; N/A ; 156.67 MHz ( period = 6.383 ns ) ; i[2] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 5.674 ns ; -; N/A ; 156.94 MHz ( period = 6.372 ns ) ; i[5] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 5.663 ns ; -; N/A ; 157.41 MHz ( period = 6.353 ns ) ; i[5] ; S_PFr[21] ; SCLK ; SCLK ; None ; None ; 5.644 ns ; -; N/A ; 157.41 MHz ( period = 6.353 ns ) ; i[5] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 5.644 ns ; -; N/A ; 157.70 MHz ( period = 6.341 ns ) ; i[1] ; S_PFr[29] ; SCLK ; SCLK ; None ; None ; 5.632 ns ; -; N/A ; 157.73 MHz ( period = 6.340 ns ) ; i[0] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 5.631 ns ; -; N/A ; 157.75 MHz ( period = 6.339 ns ) ; i[3] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 5.630 ns ; -; N/A ; 157.80 MHz ( period = 6.337 ns ) ; i[1] ; S_PFr[28] ; SCLK ; SCLK ; None ; None ; 5.628 ns ; -; N/A ; 157.85 MHz ( period = 6.335 ns ) ; i[0] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 5.626 ns ; -; N/A ; 157.85 MHz ( period = 6.335 ns ) ; i[0] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 5.626 ns ; -; N/A ; 157.93 MHz ( period = 6.332 ns ) ; i[3] ; S_PFr[29] ; SCLK ; SCLK ; None ; None ; 5.623 ns ; -; N/A ; 158.03 MHz ( period = 6.328 ns ) ; i[3] ; S_PFr[28] ; SCLK ; SCLK ; None ; None ; 5.619 ns ; -; N/A ; 158.81 MHz ( period = 6.297 ns ) ; i[4] ; S_PFr[35] ; SCLK ; SCLK ; None ; None ; 5.588 ns ; -; N/A ; 159.11 MHz ( period = 6.285 ns ) ; i[5] ; S_PFr[39] ; SCLK ; SCLK ; None ; None ; 5.576 ns ; -; N/A ; 159.82 MHz ( period = 6.257 ns ) ; i[5] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 5.548 ns ; -; N/A ; 160.23 MHz ( period = 6.241 ns ) ; i[3] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 5.532 ns ; -; N/A ; 160.41 MHz ( period = 6.234 ns ) ; i[5] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 5.525 ns ; -; N/A ; 160.62 MHz ( period = 6.226 ns ) ; i[3] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 5.517 ns ; -; N/A ; 160.95 MHz ( period = 6.213 ns ) ; i[2] ; S_PFr[29] ; SCLK ; SCLK ; None ; None ; 5.504 ns ; -; N/A ; 161.06 MHz ( period = 6.209 ns ) ; i[2] ; S_PFr[28] ; SCLK ; SCLK ; None ; None ; 5.500 ns ; -; N/A ; 161.45 MHz ( period = 6.194 ns ) ; i[1] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 5.485 ns ; -; N/A ; 161.50 MHz ( period = 6.192 ns ) ; i[0] ; S_PFr[13] ; SCLK ; SCLK ; None ; None ; 5.483 ns ; -; N/A ; 161.55 MHz ( period = 6.190 ns ) ; i[1] ; S_PFr[23] ; SCLK ; SCLK ; None ; None ; 5.481 ns ; -; N/A ; 161.58 MHz ( period = 6.189 ns ) ; i[4] ; S_PFr[37] ; SCLK ; SCLK ; None ; None ; 5.480 ns ; -; N/A ; 162.55 MHz ( period = 6.152 ns ) ; i[1] ; S_PFr[2] ; SCLK ; SCLK ; None ; None ; 5.443 ns ; -; N/A ; 163.59 MHz ( period = 6.113 ns ) ; i[1] ; S_PFr[41] ; SCLK ; SCLK ; None ; None ; 5.404 ns ; -; N/A ; 163.69 MHz ( period = 6.109 ns ) ; i[0] ; S_PFr[24] ; SCLK ; SCLK ; None ; None ; 5.400 ns ; -; N/A ; 163.75 MHz ( period = 6.107 ns ) ; i[0] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 5.398 ns ; -; N/A ; 163.77 MHz ( period = 6.106 ns ) ; i[0] ; S_PFr[20] ; SCLK ; SCLK ; None ; None ; 5.397 ns ; -; N/A ; 164.18 MHz ( period = 6.091 ns ) ; i[4] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 5.382 ns ; -; N/A ; 164.20 MHz ( period = 6.090 ns ) ; i[4] ; S_PFr[6] ; SCLK ; SCLK ; None ; None ; 5.381 ns ; -; N/A ; 164.28 MHz ( period = 6.087 ns ) ; i[4] ; S_PFr[41] ; SCLK ; SCLK ; None ; None ; 5.378 ns ; -; N/A ; 164.28 MHz ( period = 6.087 ns ) ; i[4] ; S_PFr[42] ; SCLK ; SCLK ; None ; None ; 5.378 ns ; -; N/A ; 164.34 MHz ( period = 6.085 ns ) ; i[4] ; S_PFr[45] ; SCLK ; SCLK ; None ; None ; 5.376 ns ; -; N/A ; 164.42 MHz ( period = 6.082 ns ) ; i[0] ; S_PFr[23] ; SCLK ; SCLK ; None ; None ; 5.373 ns ; -; N/A ; 164.55 MHz ( period = 6.077 ns ) ; i[0] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 5.368 ns ; -; N/A ; 165.21 MHz ( period = 6.053 ns ) ; i[4] ; S_PFr[16] ; SCLK ; SCLK ; None ; None ; 5.344 ns ; -; N/A ; 165.34 MHz ( period = 6.048 ns ) ; i[0] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 5.339 ns ; -; N/A ; 167.34 MHz ( period = 5.976 ns ) ; i[3] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 5.267 ns ; -; N/A ; 167.48 MHz ( period = 5.971 ns ) ; i[3] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 5.262 ns ; -; N/A ; 168.24 MHz ( period = 5.944 ns ) ; i[3] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 5.235 ns ; -; N/A ; 168.27 MHz ( period = 5.943 ns ) ; i[0] ; S_PFr[36] ; SCLK ; SCLK ; None ; None ; 5.234 ns ; -; N/A ; 168.58 MHz ( period = 5.932 ns ) ; i[1] ; S_PFr[35] ; SCLK ; SCLK ; None ; None ; 5.223 ns ; -; N/A ; 168.66 MHz ( period = 5.929 ns ) ; i[5] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 5.220 ns ; -; N/A ; 168.66 MHz ( period = 5.929 ns ) ; i[1] ; S_PFr[11] ; SCLK ; SCLK ; None ; None ; 5.220 ns ; -; N/A ; 168.69 MHz ( period = 5.928 ns ) ; i[1] ; S_PFr[3] ; SCLK ; SCLK ; None ; None ; 5.219 ns ; -; N/A ; 169.00 MHz ( period = 5.917 ns ) ; i[3] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 5.208 ns ; -; N/A ; 169.18 MHz ( period = 5.911 ns ) ; i[1] ; S_PFr[9] ; SCLK ; SCLK ; None ; None ; 5.202 ns ; -; N/A ; 169.23 MHz ( period = 5.909 ns ) ; i[0] ; S_PFr[34] ; SCLK ; SCLK ; None ; None ; 5.200 ns ; -; N/A ; 169.49 MHz ( period = 5.900 ns ) ; i[1] ; S_PFr[1] ; SCLK ; SCLK ; None ; None ; 5.191 ns ; -; N/A ; 169.49 MHz ( period = 5.900 ns ) ; i[2] ; S_PFr[19] ; SCLK ; SCLK ; None ; None ; 5.191 ns ; -; N/A ; 169.55 MHz ( period = 5.898 ns ) ; i[0] ; S_PFr[32] ; SCLK ; SCLK ; None ; None ; 5.189 ns ; -; N/A ; 169.64 MHz ( period = 5.895 ns ) ; i[2] ; S_PFr[18] ; SCLK ; SCLK ; None ; None ; 5.186 ns ; -; N/A ; 171.32 MHz ( period = 5.837 ns ) ; i[3] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 5.128 ns ; -; N/A ; 172.09 MHz ( period = 5.811 ns ) ; i[4] ; S_PFr[11] ; SCLK ; SCLK ; None ; None ; 5.102 ns ; -; N/A ; 172.12 MHz ( period = 5.810 ns ) ; i[5] ; S_PFr[23] ; SCLK ; SCLK ; None ; None ; 5.101 ns ; -; N/A ; 172.27 MHz ( period = 5.805 ns ) ; i[2] ; S_PFr[6] ; SCLK ; SCLK ; None ; None ; 5.096 ns ; -; N/A ; 172.44 MHz ( period = 5.799 ns ) ; i[4] ; S_PFr[9] ; SCLK ; SCLK ; None ; None ; 5.090 ns ; -; N/A ; 172.53 MHz ( period = 5.796 ns ) ; i[2] ; S_PFr[43] ; SCLK ; SCLK ; None ; None ; 5.087 ns ; -; N/A ; 173.07 MHz ( period = 5.778 ns ) ; i[3] ; S_PFr[38] ; SCLK ; SCLK ; None ; None ; 5.069 ns ; -; N/A ; 173.34 MHz ( period = 5.769 ns ) ; i[2] ; S_PFr[25] ; SCLK ; SCLK ; None ; None ; 5.060 ns ; -; N/A ; 173.67 MHz ( period = 5.758 ns ) ; i[3] ; S_PFr[17] ; SCLK ; SCLK ; None ; None ; 5.049 ns ; -; N/A ; 173.67 MHz ( period = 5.758 ns ) ; i[0] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 5.049 ns ; -; N/A ; 174.40 MHz ( period = 5.734 ns ) ; i[3] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 5.025 ns ; -; N/A ; 175.69 MHz ( period = 5.692 ns ) ; i[3] ; S_PFr[35] ; SCLK ; SCLK ; None ; None ; 4.983 ns ; -; N/A ; 176.15 MHz ( period = 5.677 ns ) ; i[2] ; S_PFr[40] ; SCLK ; SCLK ; None ; None ; 4.968 ns ; -; N/A ; 176.30 MHz ( period = 5.672 ns ) ; i[2] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 4.963 ns ; -; N/A ; 176.40 MHz ( period = 5.669 ns ) ; i[2] ; S_PFr[15] ; SCLK ; SCLK ; None ; None ; 4.960 ns ; -; N/A ; 176.43 MHz ( period = 5.668 ns ) ; i[4] ; S_PFr[40] ; SCLK ; SCLK ; None ; None ; 4.959 ns ; -; N/A ; 176.49 MHz ( period = 5.666 ns ) ; i[2] ; S_PFr[47] ; SCLK ; SCLK ; None ; None ; 4.957 ns ; -; N/A ; 176.55 MHz ( period = 5.664 ns ) ; i[2] ; S_PFr[46] ; SCLK ; SCLK ; None ; None ; 4.955 ns ; -; N/A ; 177.05 MHz ( period = 5.648 ns ) ; i[5] ; S_PFr[11] ; SCLK ; SCLK ; None ; None ; 4.939 ns ; -; N/A ; 177.43 MHz ( period = 5.636 ns ) ; i[5] ; S_PFr[9] ; SCLK ; SCLK ; None ; None ; 4.927 ns ; -; N/A ; 177.59 MHz ( period = 5.631 ns ) ; i[4] ; S_PFr[22] ; SCLK ; SCLK ; None ; None ; 4.922 ns ; -; N/A ; 177.87 MHz ( period = 5.622 ns ) ; i[1] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 4.913 ns ; -; N/A ; 178.41 MHz ( period = 5.605 ns ) ; i[4] ; S_PFr[31] ; SCLK ; SCLK ; None ; None ; 4.896 ns ; -; N/A ; 178.44 MHz ( period = 5.604 ns ) ; i[4] ; S_PFr[30] ; SCLK ; SCLK ; None ; None ; 4.895 ns ; -; N/A ; 178.51 MHz ( period = 5.602 ns ) ; i[4] ; S_PFr[28] ; SCLK ; SCLK ; None ; None ; 4.893 ns ; -; N/A ; 178.57 MHz ( period = 5.600 ns ) ; i[4] ; S_PFr[27] ; SCLK ; SCLK ; None ; None ; 4.891 ns ; -; N/A ; 178.57 MHz ( period = 5.600 ns ) ; i[4] ; S_PFr[29] ; SCLK ; SCLK ; None ; None ; 4.891 ns ; -; N/A ; 178.73 MHz ( period = 5.595 ns ) ; i[4] ; S_PFr[26] ; SCLK ; SCLK ; None ; None ; 4.886 ns ; -; N/A ; 178.86 MHz ( period = 5.591 ns ) ; i[5] ; S_PFr[33] ; SCLK ; SCLK ; None ; None ; 4.882 ns ; -; N/A ; 179.08 MHz ( period = 5.584 ns ) ; i[3] ; S_PFr[37] ; SCLK ; SCLK ; None ; None ; 4.875 ns ; -; N/A ; 180.31 MHz ( period = 5.546 ns ) ; i[0] ; S_PFr[7] ; SCLK ; SCLK ; None ; None ; 4.837 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+ - - -+------------------------------------------------------------------+ -; tsu ; -+-------+--------------+------------+-------+-----------+----------+ -; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; -+-------+--------------+------------+-------+-----------+----------+ -; N/A ; None ; 3.893 ns ; SEN ; S_PFr[44] ; SCLK ; -; N/A ; None ; 3.567 ns ; SEN ; S_PFr[47] ; SCLK ; -; N/A ; None ; 3.561 ns ; SEN ; S_PFr[36] ; SCLK ; -; N/A ; None ; 3.527 ns ; SEN ; S_PFr[34] ; SCLK ; -; N/A ; None ; 3.516 ns ; SEN ; S_PFr[32] ; SCLK ; -; N/A ; None ; 3.334 ns ; SEN ; S_PFr[43] ; SCLK ; -; N/A ; None ; 3.269 ns ; SEN ; S_PFr[5] ; SCLK ; -; N/A ; None ; 3.217 ns ; SEN ; S_PFr[46] ; SCLK ; -; N/A ; None ; 3.204 ns ; SEN ; S_PFr[39] ; SCLK ; -; N/A ; None ; 2.841 ns ; SEN ; S_PFr[1] ; SCLK ; -; N/A ; None ; 2.841 ns ; SEN ; S_PFr[3] ; SCLK ; -; N/A ; None ; 2.716 ns ; SEN ; S_PFr[13] ; SCLK ; -; N/A ; None ; 2.655 ns ; SEN ; S_PFr[19] ; SCLK ; -; N/A ; None ; 2.633 ns ; SEN ; S_PFr[38] ; SCLK ; -; N/A ; None ; 2.572 ns ; SEN ; S_PFr[15] ; SCLK ; -; N/A ; None ; 2.510 ns ; SEN ; S_PFr[33] ; SCLK ; -; N/A ; None ; 2.390 ns ; SEN ; S_PFr[18] ; SCLK ; -; N/A ; None ; 2.350 ns ; SEN ; S_PFr[21] ; SCLK ; -; N/A ; None ; 2.350 ns ; SEN ; S_PFr[25] ; SCLK ; -; N/A ; None ; 2.258 ns ; SEN ; S_PFr[35] ; SCLK ; -; N/A ; None ; 2.150 ns ; SEN ; S_PFr[37] ; SCLK ; -; N/A ; None ; 2.138 ns ; SEN ; S_PFr[16] ; SCLK ; -; N/A ; None ; 2.134 ns ; SEN ; S_PFr[17] ; SCLK ; -; N/A ; None ; 2.052 ns ; SEN ; S_PFr[7] ; SCLK ; -; N/A ; None ; 2.051 ns ; SEN ; S_PFr[6] ; SCLK ; -; N/A ; None ; 2.048 ns ; SEN ; S_PFr[14] ; SCLK ; -; N/A ; None ; 2.048 ns ; SEN ; S_PFr[41] ; SCLK ; -; N/A ; None ; 2.048 ns ; SEN ; S_PFr[42] ; SCLK ; -; N/A ; None ; 2.046 ns ; SEN ; S_PFr[45] ; SCLK ; -; N/A ; None ; 2.043 ns ; SEN ; S_PFr[12] ; SCLK ; -; N/A ; None ; 2.041 ns ; SEN ; S_PFr[10] ; SCLK ; -; N/A ; None ; 1.939 ns ; SEN ; S_PFr[24] ; SCLK ; -; N/A ; None ; 1.936 ns ; SEN ; S_PFr[20] ; SCLK ; -; N/A ; None ; 1.772 ns ; SEN ; S_PFr[11] ; SCLK ; -; N/A ; None ; 1.760 ns ; SEN ; S_PFr[9] ; SCLK ; -; N/A ; None ; 1.716 ns ; SEN ; S_PFr[22] ; SCLK ; -; N/A ; None ; 1.710 ns ; SEN ; S_PFr[23] ; SCLK ; -; N/A ; None ; 1.629 ns ; SEN ; S_PFr[40] ; SCLK ; -; N/A ; None ; 1.617 ns ; SDATA ; S_PFr[31] ; SCLK ; -; N/A ; None ; 1.616 ns ; SDATA ; S_PFr[26] ; SCLK ; -; N/A ; None ; 1.612 ns ; SDATA ; S_PFr[29] ; SCLK ; -; N/A ; None ; 1.608 ns ; SDATA ; S_PFr[28] ; SCLK ; -; N/A ; None ; 1.606 ns ; SDATA ; S_PFr[30] ; SCLK ; -; N/A ; None ; 1.605 ns ; SDATA ; S_PFr[27] ; SCLK ; -; N/A ; None ; 1.597 ns ; SDATA ; S_PFr[1] ; SCLK ; -; N/A ; None ; 1.597 ns ; SDATA ; S_PFr[3] ; SCLK ; -; N/A ; None ; 1.596 ns ; SDATA ; S_PFr[11] ; SCLK ; -; N/A ; None ; 1.592 ns ; SDATA ; S_PFr[35] ; SCLK ; -; N/A ; None ; 1.581 ns ; SDATA ; S_PFr[9] ; SCLK ; -; N/A ; None ; 1.553 ns ; SDATA ; S_PFr[23] ; SCLK ; -; N/A ; None ; 1.547 ns ; SDATA ; S_PFr[16] ; SCLK ; -; N/A ; None ; 1.498 ns ; SDATA ; S_PFr[17] ; SCLK ; -; N/A ; None ; 1.491 ns ; SDATA ; S_PFr[22] ; SCLK ; -; N/A ; None ; 1.452 ns ; SEN ; S_PFr[0] ; SCLK ; -; N/A ; None ; 1.438 ns ; SDATA ; S_PFr[41] ; SCLK ; -; N/A ; None ; 1.304 ns ; SEN ; S_PFr[8] ; SCLK ; -; N/A ; None ; 1.302 ns ; SEN ; S_PFr[2] ; SCLK ; -; N/A ; None ; 1.299 ns ; SDATA ; S_PFr[21] ; SCLK ; -; N/A ; None ; 1.299 ns ; SDATA ; S_PFr[25] ; SCLK ; -; N/A ; None ; 1.288 ns ; SEN ; S_PFr[4] ; SCLK ; -; N/A ; None ; 1.197 ns ; SDATA ; S_PFr[45] ; SCLK ; -; N/A ; None ; 1.115 ns ; SDATA ; S_PFr[7] ; SCLK ; -; N/A ; None ; 1.076 ns ; SDATA ; S_PFr[36] ; SCLK ; -; N/A ; None ; 1.041 ns ; SDATA ; S_PFr[38] ; SCLK ; -; N/A ; None ; 1.013 ns ; SDATA ; S_PFr[10] ; SCLK ; -; N/A ; None ; 1.012 ns ; SDATA ; S_PFr[12] ; SCLK ; -; N/A ; None ; 1.003 ns ; SDATA ; S_PFr[14] ; SCLK ; -; N/A ; None ; 0.969 ns ; SDATA ; S_PFr[6] ; SCLK ; -; N/A ; None ; 0.910 ns ; SDATA ; S_PFr[0] ; SCLK ; -; N/A ; None ; 0.841 ns ; SDATA ; S_PFr[4] ; SCLK ; -; N/A ; None ; 0.839 ns ; SDATA ; S_PFr[20] ; SCLK ; -; N/A ; None ; 0.835 ns ; SDATA ; S_PFr[24] ; SCLK ; -; N/A ; None ; 0.833 ns ; SDATA ; S_PFr[2] ; SCLK ; -; N/A ; None ; 0.826 ns ; SDATA ; S_PFr[8] ; SCLK ; -; N/A ; None ; 0.824 ns ; SDATA ; S_PFr[19] ; SCLK ; -; N/A ; None ; 0.813 ns ; SDATA ; S_PFr[18] ; SCLK ; -; N/A ; None ; 0.810 ns ; SDATA ; S_PFr[42] ; SCLK ; -; N/A ; None ; 0.809 ns ; SDATA ; S_PFr[34] ; SCLK ; -; N/A ; None ; 0.806 ns ; SEN ; S_PFr[31] ; SCLK ; -; N/A ; None ; 0.803 ns ; SEN ; S_PFr[30] ; SCLK ; -; N/A ; None ; 0.801 ns ; SEN ; S_PFr[27] ; SCLK ; -; N/A ; None ; 0.801 ns ; SEN ; S_PFr[28] ; SCLK ; -; N/A ; None ; 0.801 ns ; SEN ; S_PFr[29] ; SCLK ; -; N/A ; None ; 0.798 ns ; SDATA ; S_PFr[43] ; SCLK ; -; N/A ; None ; 0.794 ns ; SEN ; S_PFr[26] ; SCLK ; -; N/A ; None ; 0.776 ns ; SDATA ; S_PFr[37] ; SCLK ; -; N/A ; None ; 0.775 ns ; SDATA ; S_PFr[44] ; SCLK ; -; N/A ; None ; 0.774 ns ; SDATA ; S_PFr[13] ; SCLK ; -; N/A ; None ; 0.765 ns ; SDATA ; S_PFr[5] ; SCLK ; -; N/A ; None ; 0.743 ns ; SDATA ; S_PFr[47] ; SCLK ; -; N/A ; None ; 0.741 ns ; SDATA ; S_PFr[39] ; SCLK ; -; N/A ; None ; 0.740 ns ; SDATA ; S_PFr[46] ; SCLK ; -; N/A ; None ; 0.730 ns ; SDATA ; S_PFr[15] ; SCLK ; -; N/A ; None ; 0.598 ns ; SDATA ; S_PFr[33] ; SCLK ; -; N/A ; None ; 0.590 ns ; SDATA ; S_PFr[40] ; SCLK ; -; N/A ; None ; 0.527 ns ; SDATA ; S_PFr[32] ; SCLK ; -; N/A ; None ; 0.482 ns ; SEN ; i[2] ; SCLK ; -; N/A ; None ; 0.482 ns ; SEN ; i[1] ; SCLK ; -; N/A ; None ; 0.482 ns ; SEN ; i[0] ; SCLK ; -; N/A ; None ; 0.482 ns ; SEN ; i[5] ; SCLK ; -; N/A ; None ; 0.482 ns ; SEN ; i[3] ; SCLK ; -; N/A ; None ; 0.482 ns ; SEN ; i[4] ; SCLK ; -+-------+--------------+------------+-------+-----------+----------+ - - -+------------------------------------------------------------------------+ -; tco ; -+-------+--------------+------------+------------+----------+------------+ -; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; -+-------+--------------+------------+------------+----------+------------+ -; N/A ; None ; 8.833 ns ; S_PFr2[5] ; S_PF[5] ; clk ; -; N/A ; None ; 8.819 ns ; S_PFr2[14] ; S_PF[14] ; clk ; -; N/A ; None ; 8.802 ns ; S_PFr2[26] ; S_PF[26] ; clk ; -; N/A ; None ; 8.785 ns ; S_PFr2[9] ; S_PF[9] ; clk ; -; N/A ; None ; 8.773 ns ; S_PFr2[6] ; S_PF[6] ; clk ; -; N/A ; None ; 8.755 ns ; S_PFr2[36] ; S_PF[36] ; clk ; -; N/A ; None ; 8.750 ns ; S_PFr2[11] ; S_PF[11] ; clk ; -; N/A ; None ; 8.738 ns ; S_PFr2[35] ; S_PF[35] ; clk ; -; N/A ; None ; 8.729 ns ; S_PFr2[28] ; S_PF[28] ; clk ; -; N/A ; None ; 8.703 ns ; S_PFr2[30] ; S_PF[30] ; clk ; -; N/A ; None ; 8.696 ns ; S_PFr2[4] ; S_PF[4] ; clk ; -; N/A ; None ; 8.685 ns ; S_PFr2[31] ; S_PF[31] ; clk ; -; N/A ; None ; 8.674 ns ; S_PFr2[23] ; S_PF[23] ; clk ; -; N/A ; None ; 8.662 ns ; S_PFr2[2] ; S_PF[2] ; clk ; -; N/A ; None ; 8.650 ns ; S_PFr2[27] ; S_PF[27] ; clk ; -; N/A ; None ; 8.578 ns ; S_PFr2[13] ; S_PF[13] ; clk ; -; N/A ; None ; 8.569 ns ; S_PFr2[33] ; S_PF[33] ; clk ; -; N/A ; None ; 8.564 ns ; S_PFr2[22] ; S_PF[22] ; clk ; -; N/A ; None ; 8.556 ns ; S_PFr2[29] ; S_PF[29] ; clk ; -; N/A ; None ; 8.540 ns ; S_PFr2[20] ; S_PF[20] ; clk ; -; N/A ; None ; 8.465 ns ; S_PFr2[7] ; S_PF[7] ; clk ; -; N/A ; None ; 8.460 ns ; S_PFr2[0] ; S_PF[0] ; clk ; -; N/A ; None ; 8.392 ns ; S_PFr2[34] ; S_PF[34] ; clk ; -; N/A ; None ; 8.349 ns ; S_PFr2[17] ; S_PF[17] ; clk ; -; N/A ; None ; 8.334 ns ; S_PFr2[39] ; S_PF[39] ; clk ; -; N/A ; None ; 8.311 ns ; S_PFr2[45] ; S_PF[45] ; clk ; -; N/A ; None ; 8.231 ns ; S_PFr2[38] ; S_PF[38] ; clk ; -; N/A ; None ; 8.211 ns ; S_PFr2[16] ; S_PF[16] ; clk ; -; N/A ; None ; 8.204 ns ; S_PFr2[41] ; S_PF[41] ; clk ; -; N/A ; None ; 8.204 ns ; S_PFr2[1] ; S_PF[1] ; clk ; -; N/A ; None ; 8.202 ns ; S_PFr2[47] ; S_PF[47] ; clk ; -; N/A ; None ; 8.129 ns ; S_PFr2[46] ; S_PF[46] ; clk ; -; N/A ; None ; 8.103 ns ; S_PFr2[32] ; S_PF[32] ; clk ; -; N/A ; None ; 8.101 ns ; S_PFr2[12] ; S_PF[12] ; clk ; -; N/A ; None ; 8.095 ns ; S_PFr2[3] ; S_PF[3] ; clk ; -; N/A ; None ; 8.094 ns ; S_PFr2[15] ; S_PF[15] ; clk ; -; N/A ; None ; 8.090 ns ; S_PFr2[40] ; S_PF[40] ; clk ; -; N/A ; None ; 8.078 ns ; S_PFr2[37] ; S_PF[37] ; clk ; -; N/A ; None ; 8.072 ns ; S_PFr2[25] ; S_PF[25] ; clk ; -; N/A ; None ; 8.070 ns ; S_PFr2[44] ; S_PF[44] ; clk ; -; N/A ; None ; 8.066 ns ; S_PFr2[8] ; S_PF[8] ; clk ; -; N/A ; None ; 8.024 ns ; S_PFr2[18] ; S_PF[18] ; clk ; -; N/A ; None ; 7.910 ns ; S_PFr2[19] ; S_PF[19] ; clk ; -; N/A ; None ; 7.886 ns ; S_PFr2[24] ; S_PF[24] ; clk ; -; N/A ; None ; 6.854 ns ; S_PFr2[10] ; S_PF[10] ; clk ; -; N/A ; None ; 6.848 ns ; S_PFr2[21] ; S_PF[21] ; clk ; -; N/A ; None ; 6.820 ns ; S_PFr2[43] ; S_PF[43] ; clk ; -; N/A ; None ; 6.814 ns ; S_PFr2[42] ; S_PF[42] ; clk ; -+-------+--------------+------------+------------+----------+------------+ - - -+------------------------------------------------------------------------+ -; th ; -+---------------+-------------+-----------+-------+-----------+----------+ -; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; -+---------------+-------------+-----------+-------+-----------+----------+ -; N/A ; None ; 0.072 ns ; SEN ; i[2] ; SCLK ; -; N/A ; None ; 0.072 ns ; SEN ; i[1] ; SCLK ; -; N/A ; None ; 0.072 ns ; SEN ; i[0] ; SCLK ; -; N/A ; None ; 0.072 ns ; SEN ; i[5] ; SCLK ; -; N/A ; None ; 0.072 ns ; SEN ; i[3] ; SCLK ; -; N/A ; None ; 0.072 ns ; SEN ; i[4] ; SCLK ; -; N/A ; None ; 0.027 ns ; SDATA ; S_PFr[32] ; SCLK ; -; N/A ; None ; -0.036 ns ; SDATA ; S_PFr[40] ; SCLK ; -; N/A ; None ; -0.044 ns ; SDATA ; S_PFr[33] ; SCLK ; -; N/A ; None ; -0.176 ns ; SDATA ; S_PFr[15] ; SCLK ; -; N/A ; None ; -0.186 ns ; SDATA ; S_PFr[46] ; SCLK ; -; N/A ; None ; -0.187 ns ; SDATA ; S_PFr[39] ; SCLK ; -; N/A ; None ; -0.189 ns ; SDATA ; S_PFr[47] ; SCLK ; -; N/A ; None ; -0.211 ns ; SDATA ; S_PFr[5] ; SCLK ; -; N/A ; None ; -0.220 ns ; SDATA ; S_PFr[13] ; SCLK ; -; N/A ; None ; -0.221 ns ; SDATA ; S_PFr[44] ; SCLK ; -; N/A ; None ; -0.222 ns ; SDATA ; S_PFr[37] ; SCLK ; -; N/A ; None ; -0.240 ns ; SEN ; S_PFr[26] ; SCLK ; -; N/A ; None ; -0.244 ns ; SDATA ; S_PFr[43] ; SCLK ; -; N/A ; None ; -0.247 ns ; SEN ; S_PFr[27] ; SCLK ; -; N/A ; None ; -0.247 ns ; SEN ; S_PFr[28] ; SCLK ; -; N/A ; None ; -0.247 ns ; SEN ; S_PFr[29] ; SCLK ; -; N/A ; None ; -0.249 ns ; SEN ; S_PFr[30] ; SCLK ; -; N/A ; None ; -0.252 ns ; SEN ; S_PFr[31] ; SCLK ; -; N/A ; None ; -0.255 ns ; SDATA ; S_PFr[34] ; SCLK ; -; N/A ; None ; -0.256 ns ; SDATA ; S_PFr[42] ; SCLK ; -; N/A ; None ; -0.259 ns ; SDATA ; S_PFr[18] ; SCLK ; -; N/A ; None ; -0.270 ns ; SDATA ; S_PFr[19] ; SCLK ; -; N/A ; None ; -0.272 ns ; SDATA ; S_PFr[8] ; SCLK ; -; N/A ; None ; -0.279 ns ; SDATA ; S_PFr[2] ; SCLK ; -; N/A ; None ; -0.281 ns ; SDATA ; S_PFr[24] ; SCLK ; -; N/A ; None ; -0.285 ns ; SDATA ; S_PFr[20] ; SCLK ; -; N/A ; None ; -0.287 ns ; SDATA ; S_PFr[4] ; SCLK ; -; N/A ; None ; -0.356 ns ; SDATA ; S_PFr[0] ; SCLK ; -; N/A ; None ; -0.415 ns ; SDATA ; S_PFr[6] ; SCLK ; -; N/A ; None ; -0.449 ns ; SDATA ; S_PFr[14] ; SCLK ; -; N/A ; None ; -0.458 ns ; SDATA ; S_PFr[12] ; SCLK ; -; N/A ; None ; -0.459 ns ; SDATA ; S_PFr[10] ; SCLK ; -; N/A ; None ; -0.487 ns ; SDATA ; S_PFr[38] ; SCLK ; -; N/A ; None ; -0.522 ns ; SDATA ; S_PFr[36] ; SCLK ; -; N/A ; None ; -0.561 ns ; SDATA ; S_PFr[7] ; SCLK ; -; N/A ; None ; -0.643 ns ; SDATA ; S_PFr[45] ; SCLK ; -; N/A ; None ; -0.734 ns ; SEN ; S_PFr[4] ; SCLK ; -; N/A ; None ; -0.745 ns ; SDATA ; S_PFr[21] ; SCLK ; -; N/A ; None ; -0.745 ns ; SDATA ; S_PFr[25] ; SCLK ; -; N/A ; None ; -0.748 ns ; SEN ; S_PFr[2] ; SCLK ; -; N/A ; None ; -0.750 ns ; SEN ; S_PFr[8] ; SCLK ; -; N/A ; None ; -0.884 ns ; SDATA ; S_PFr[41] ; SCLK ; -; N/A ; None ; -0.898 ns ; SEN ; S_PFr[0] ; SCLK ; -; N/A ; None ; -0.937 ns ; SDATA ; S_PFr[22] ; SCLK ; -; N/A ; None ; -0.944 ns ; SDATA ; S_PFr[17] ; SCLK ; -; N/A ; None ; -0.993 ns ; SDATA ; S_PFr[16] ; SCLK ; -; N/A ; None ; -0.999 ns ; SDATA ; S_PFr[23] ; SCLK ; -; N/A ; None ; -1.027 ns ; SDATA ; S_PFr[9] ; SCLK ; -; N/A ; None ; -1.038 ns ; SDATA ; S_PFr[35] ; SCLK ; -; N/A ; None ; -1.042 ns ; SDATA ; S_PFr[11] ; SCLK ; -; N/A ; None ; -1.043 ns ; SDATA ; S_PFr[1] ; SCLK ; -; N/A ; None ; -1.043 ns ; SDATA ; S_PFr[3] ; SCLK ; -; N/A ; None ; -1.051 ns ; SDATA ; S_PFr[27] ; SCLK ; -; N/A ; None ; -1.052 ns ; SDATA ; S_PFr[30] ; SCLK ; -; N/A ; None ; -1.054 ns ; SDATA ; S_PFr[28] ; SCLK ; -; N/A ; None ; -1.058 ns ; SDATA ; S_PFr[29] ; SCLK ; -; N/A ; None ; -1.062 ns ; SDATA ; S_PFr[26] ; SCLK ; -; N/A ; None ; -1.063 ns ; SDATA ; S_PFr[31] ; SCLK ; -; N/A ; None ; -1.075 ns ; SEN ; S_PFr[40] ; SCLK ; -; N/A ; None ; -1.156 ns ; SEN ; S_PFr[23] ; SCLK ; -; N/A ; None ; -1.162 ns ; SEN ; S_PFr[22] ; SCLK ; -; N/A ; None ; -1.206 ns ; SEN ; S_PFr[9] ; SCLK ; -; N/A ; None ; -1.218 ns ; SEN ; S_PFr[11] ; SCLK ; -; N/A ; None ; -1.382 ns ; SEN ; S_PFr[20] ; SCLK ; -; N/A ; None ; -1.385 ns ; SEN ; S_PFr[24] ; SCLK ; -; N/A ; None ; -1.487 ns ; SEN ; S_PFr[10] ; SCLK ; -; N/A ; None ; -1.489 ns ; SEN ; S_PFr[12] ; SCLK ; -; N/A ; None ; -1.492 ns ; SEN ; S_PFr[45] ; SCLK ; -; N/A ; None ; -1.494 ns ; SEN ; S_PFr[14] ; SCLK ; -; N/A ; None ; -1.494 ns ; SEN ; S_PFr[41] ; SCLK ; -; N/A ; None ; -1.494 ns ; SEN ; S_PFr[42] ; SCLK ; -; N/A ; None ; -1.497 ns ; SEN ; S_PFr[6] ; SCLK ; -; N/A ; None ; -1.498 ns ; SEN ; S_PFr[7] ; SCLK ; -; N/A ; None ; -1.580 ns ; SEN ; S_PFr[17] ; SCLK ; -; N/A ; None ; -1.584 ns ; SEN ; S_PFr[16] ; SCLK ; -; N/A ; None ; -1.596 ns ; SEN ; S_PFr[37] ; SCLK ; -; N/A ; None ; -1.704 ns ; SEN ; S_PFr[35] ; SCLK ; -; N/A ; None ; -1.796 ns ; SEN ; S_PFr[21] ; SCLK ; -; N/A ; None ; -1.796 ns ; SEN ; S_PFr[25] ; SCLK ; -; N/A ; None ; -1.836 ns ; SEN ; S_PFr[18] ; SCLK ; -; N/A ; None ; -1.956 ns ; SEN ; S_PFr[33] ; SCLK ; -; N/A ; None ; -2.018 ns ; SEN ; S_PFr[15] ; SCLK ; -; N/A ; None ; -2.079 ns ; SEN ; S_PFr[38] ; SCLK ; -; N/A ; None ; -2.101 ns ; SEN ; S_PFr[19] ; SCLK ; -; N/A ; None ; -2.162 ns ; SEN ; S_PFr[13] ; SCLK ; -; N/A ; None ; -2.287 ns ; SEN ; S_PFr[1] ; SCLK ; -; N/A ; None ; -2.287 ns ; SEN ; S_PFr[3] ; SCLK ; -; N/A ; None ; -2.650 ns ; SEN ; S_PFr[39] ; SCLK ; -; N/A ; None ; -2.663 ns ; SEN ; S_PFr[46] ; SCLK ; -; N/A ; None ; -2.715 ns ; SEN ; S_PFr[5] ; SCLK ; -; N/A ; None ; -2.780 ns ; SEN ; S_PFr[43] ; SCLK ; -; N/A ; None ; -2.962 ns ; SEN ; S_PFr[32] ; SCLK ; -; N/A ; None ; -2.973 ns ; SEN ; S_PFr[34] ; SCLK ; -; N/A ; None ; -3.007 ns ; SEN ; S_PFr[36] ; SCLK ; -; N/A ; None ; -3.013 ns ; SEN ; S_PFr[47] ; SCLK ; -; N/A ; None ; -3.339 ns ; SEN ; S_PFr[44] ; SCLK ; -+---------------+-------------+-----------+-------+-----------+----------+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Classic Timing Analyzer - Info: Version 9.0 Build 132 02/25/2009 SJ Full Version - Info: Processing started: Tue Jan 03 15:28:01 2012 -Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PF1 -c PF1 -Info: Parallel compilation is enabled and will use 2 of the 2 processors detected -Info: Started post-fitting delay annotation -Info: Delay annotation completed successfully -Warning: Found pins functioning as undefined clocks and/or memory enables - Info: Assuming node "clk" is an undefined clock - Info: Assuming node "SCLK" is an undefined clock -Info: Clock "clk" has Internal fmax of 95.93 MHz between source register "cnt[17]" and destination register "S_PFr2[41]" (period= 10.424 ns) - Info: + Longest register to register delay is 9.715 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N9; Fanout = 5; REG Node = 'cnt[17]' - Info: 2: + IC(3.167 ns) + CELL(0.200 ns) = 3.367 ns; Loc. = LC_X5_Y4_N2; Fanout = 1; COMB Node = 'LessThan0~0' - Info: 3: + IC(0.741 ns) + CELL(0.740 ns) = 4.848 ns; Loc. = LC_X5_Y4_N6; Fanout = 1; COMB Node = 'LessThan0~4' - Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.353 ns; Loc. = LC_X5_Y4_N7; Fanout = 72; COMB Node = 'cnt[20]~44' - Info: 5: + IC(3.771 ns) + CELL(0.591 ns) = 9.715 ns; Loc. = LC_X3_Y1_N5; Fanout = 2; REG Node = 'S_PFr2[41]' - Info: Total cell delay = 1.731 ns ( 17.82 % ) - Info: Total interconnect delay = 7.984 ns ( 82.18 % ) - Info: - Smallest clock skew is 0.000 ns - Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns - Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk' - Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y1_N5; Fanout = 2; REG Node = 'S_PFr2[41]' - Info: Total cell delay = 2.081 ns ( 62.16 % ) - Info: Total interconnect delay = 1.267 ns ( 37.84 % ) - Info: - Longest clock path from clock "clk" to source register is 3.348 ns - Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk' - Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N9; Fanout = 5; REG Node = 'cnt[17]' - Info: Total cell delay = 2.081 ns ( 62.16 % ) - Info: Total interconnect delay = 1.267 ns ( 37.84 % ) - Info: + Micro clock to output delay of source is 0.376 ns - Info: + Micro setup delay of destination is 0.333 ns -Info: Clock "SCLK" has Internal fmax of 126.07 MHz between source register "i[4]" and destination register "S_PFr[44]" (period= 7.932 ns) - Info: + Longest register to register delay is 7.223 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'i[4]' - Info: 2: + IC(1.018 ns) + CELL(0.511 ns) = 1.529 ns; Loc. = LC_X3_Y2_N9; Fanout = 7; COMB Node = 'Decoder0~1' - Info: 3: + IC(2.334 ns) + CELL(0.200 ns) = 4.063 ns; Loc. = LC_X6_Y1_N2; Fanout = 4; COMB Node = 'Decoder0~23' - Info: 4: + IC(2.569 ns) + CELL(0.591 ns) = 7.223 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr[44]' - Info: Total cell delay = 1.302 ns ( 18.03 % ) - Info: Total interconnect delay = 5.921 ns ( 81.97 % ) - Info: - Smallest clock skew is 0.000 ns - Info: + Shortest clock path from clock "SCLK" to destination register is 6.206 ns - Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK' - Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr[44]' - Info: Total cell delay = 2.050 ns ( 33.03 % ) - Info: Total interconnect delay = 4.156 ns ( 66.97 % ) - Info: - Longest clock path from clock "SCLK" to source register is 6.206 ns - Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK' - Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'i[4]' - Info: Total cell delay = 2.050 ns ( 33.03 % ) - Info: Total interconnect delay = 4.156 ns ( 66.97 % ) - Info: + Micro clock to output delay of source is 0.376 ns - Info: + Micro setup delay of destination is 0.333 ns -Info: tsu for register "S_PFr[44]" (data pin = "SEN", clock pin = "SCLK") is 3.893 ns - Info: + Longest pin to register delay is 9.766 ns - Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 8; PIN Node = 'SEN' - Info: 2: + IC(2.740 ns) + CELL(0.200 ns) = 4.072 ns; Loc. = LC_X3_Y2_N9; Fanout = 7; COMB Node = 'Decoder0~1' - Info: 3: + IC(2.334 ns) + CELL(0.200 ns) = 6.606 ns; Loc. = LC_X6_Y1_N2; Fanout = 4; COMB Node = 'Decoder0~23' - Info: 4: + IC(2.569 ns) + CELL(0.591 ns) = 9.766 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr[44]' - Info: Total cell delay = 2.123 ns ( 21.74 % ) - Info: Total interconnect delay = 7.643 ns ( 78.26 % ) - Info: + Micro setup delay of destination is 0.333 ns - Info: - Shortest clock path from clock "SCLK" to destination register is 6.206 ns - Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK' - Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr[44]' - Info: Total cell delay = 2.050 ns ( 33.03 % ) - Info: Total interconnect delay = 4.156 ns ( 66.97 % ) -Info: tco from clock "clk" to destination pin "S_PF[5]" through register "S_PFr2[5]" is 8.833 ns - Info: + Longest clock path from clock "clk" to source register is 3.348 ns - Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk' - Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; REG Node = 'S_PFr2[5]' - Info: Total cell delay = 2.081 ns ( 62.16 % ) - Info: Total interconnect delay = 1.267 ns ( 37.84 % ) - Info: + Micro clock to output delay of source is 0.376 ns - Info: + Longest register to pin delay is 5.109 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; REG Node = 'S_PFr2[5]' - Info: 2: + IC(2.787 ns) + CELL(2.322 ns) = 5.109 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'S_PF[5]' - Info: Total cell delay = 2.322 ns ( 45.45 % ) - Info: Total interconnect delay = 2.787 ns ( 54.55 % ) -Info: th for register "i[2]" (data pin = "SEN", clock pin = "SCLK") is 0.072 ns - Info: + Longest clock path from clock "SCLK" to destination register is 6.206 ns - Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK' - Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X3_Y2_N3; Fanout = 13; REG Node = 'i[2]' - Info: Total cell delay = 2.050 ns ( 33.03 % ) - Info: Total interconnect delay = 4.156 ns ( 66.97 % ) - Info: + Micro hold delay of destination is 0.221 ns - Info: - Shortest pin to register delay is 6.355 ns - Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 8; PIN Node = 'SEN' - Info: 2: + IC(3.463 ns) + CELL(1.760 ns) = 6.355 ns; Loc. = LC_X3_Y2_N3; Fanout = 13; REG Node = 'i[2]' - Info: Total cell delay = 2.892 ns ( 45.51 % ) - Info: Total interconnect delay = 3.463 ns ( 54.49 % ) -Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 130 megabytes - Info: Processing ended: Tue Jan 03 15:28:03 2012 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 - - diff --git a/firmware/PF1.tan.summary b/firmware/PF1.tan.summary deleted file mode 100644 index 3499758..0000000 --- a/firmware/PF1.tan.summary +++ /dev/null @@ -1,66 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tsu -Slack : N/A -Required Time : None -Actual Time : 3.893 ns -From : SEN -To : S_PFr[44] -From Clock : -- -To Clock : SCLK -Failed Paths : 0 - -Type : Worst-case tco -Slack : N/A -Required Time : None -Actual Time : 8.833 ns -From : S_PFr2[5] -To : S_PF[5] -From Clock : clk -To Clock : -- -Failed Paths : 0 - -Type : Worst-case th -Slack : N/A -Required Time : None -Actual Time : 0.072 ns -From : SEN -To : i[4] -From Clock : -- -To Clock : SCLK -Failed Paths : 0 - -Type : Clock Setup: 'clk' -Slack : N/A -Required Time : None -Actual Time : 95.93 MHz ( period = 10.424 ns ) -From : cnt[17] -To : S_PFr2[41] -From Clock : clk -To Clock : clk -Failed Paths : 0 - -Type : Clock Setup: 'SCLK' -Slack : N/A -Required Time : None -Actual Time : 126.07 MHz ( period = 7.932 ns ) -From : i[4] -To : S_PFr[44] -From Clock : SCLK -To Clock : SCLK -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 0 - --------------------------------------------------------------------------------------- - diff --git a/firmware/PF1.v.bak b/firmware/PF1.v.bak deleted file mode 100644 index 324c6ff..0000000 --- a/firmware/PF1.v.bak +++ /dev/null @@ -1,153 +0,0 @@ -module PF1( - clk,rst_n, - S_PF, - SCLK, - SEN, - SDATA, - ); - -input clk; //50MHz -input rst_n; //͵ƽλź -input SCLK; -input SEN; -input SDATA; - -output[47:0] S_PF; - -reg[21:0] cnt; -reg[5:0] timer; -reg[47:0] S_PFr; -reg[6:0] i; -reg[47:0] S_PFr2; - -//always @ (posedge clk or negedge rst_n) -// if(!rst_n) cnt <= 18'd0; -// else -// begin -// cnt <= cnt+1'b1; -// if(cnt == 5001) cnt <= 0; -// end - -reg r_data_in0; -reg o_rising_edge; - - always@(posedge clk or negedge rst_n) -begin - if (!rst_n) - r_data_in0 <= 0; - else begin - r_data_in0 <= SCLK; - if ({r_data_in0, SCLK} == 2'b01) - o_rising_edge <= 1; - else - o_rising_edge <= 0; - end -end - - - -always @ (posedge clk) - if(cnt<20'hfffff) - begin - cnt <= cnt + 1'b1; - end - else if (timer<60) - begin - cnt <= 0; - timer <= timer + 1'b1; - S_PFr2 <= 48'hffffffffffff; - end - else - begin - S_PFr2 <= S_PFr; - end - -always @ (posedge SCLK) - if (!SEN) - begin - i <= 0; - end - else - if(timer==60) - begin - i <= i+1'b1; - S_PFr[i] <= SDATA; - /* case(i) - 6'd0: S_PFr[0] <= SDATA; - 6'd1: S_PFr[1] <= SDATA; - 6'd2: S_PFr[2] <= SDATA; - 6'd3: S_PFr[3] <= SDATA; - 6'd4: S_PFr[4] <= SDATA; - 6'd5: S_PFr[5] <= SDATA; - 6'd6: S_PFr[6] <= SDATA; - 6'd7: S_PFr[7] <= SDATA; - 6'd8: S_PFr[8] <= SDATA; - 6'd9: S_PFr[9] <= SDATA; - 6'd10: S_PFr[10] <= SDATA; - 6'd11: S_PFr[11] <= SDATA; - 6'd12: S_PFr[12] <= SDATA; - 6'd13: S_PFr[13] <= SDATA; - 6'd14: S_PFr[14] <= SDATA; - 6'd15: S_PFr[15] <= SDATA; - 6'd16: S_PFr[16] <= SDATA; - 6'd17: S_PFr[17] <= SDATA; - 6'd18: S_PFr[18] <= SDATA; - 6'd19: S_PFr[19] <= SDATA; - 6'd20: S_PFr[20] <= SDATA; - 6'd21: S_PFr[21] <= SDATA; - 6'd22: S_PFr[22] <= SDATA; - 6'd23: S_PFr[23] <= SDATA; - 6'd24: S_PFr[24] <= SDATA; - 6'd25: S_PFr[25] <= SDATA; - 6'd26: S_PFr[26] <= SDATA; - 6'd27: S_PFr[27] <= SDATA; - 6'd28: S_PFr[28] <= SDATA; - 6'd29: S_PFr[29] <= SDATA; - 6'd30: S_PFr[30] <= SDATA; - 6'd31: S_PFr[31] <= SDATA; - 6'd32: S_PFr[32] <= SDATA; - 6'd33: S_PFr[33] <= SDATA; - 6'd34: S_PFr[34] <= SDATA; - 6'd35: S_PFr[35] <= SDATA; - 6'd36: S_PFr[36] <= SDATA; - 6'd37: S_PFr[37] <= SDATA; - 6'd38: S_PFr[38] <= SDATA; - 6'd39: S_PFr[39] <= SDATA; - 6'd40: S_PFr[40] <= SDATA; - 6'd41: S_PFr[41] <= SDATA; - 6'd42: S_PFr[42] <= SDATA; - 6'd43: S_PFr[43] <= SDATA; - 6'd44: S_PFr[44] <= SDATA; - 6'd45: S_PFr[45] <= SDATA; - 6'd46: S_PFr[46] <= SDATA; - 6'd47: S_PFr[47] <= SDATA; - default: ; - endcase*/ - end - - - -/*always @ (negedge SEN or negedge rst_n) - if(!rst_n) S_PFr2 <= 48'hffffffffffff; - else if(!SEN) - begin - S_PFr2 <= S_PFr; - end - */ -// else if(cnt == 5000) -// begin -// timer <= timer+1'b1; //ÿ0.1msһ -// if(!SEN) -// begin -// case(timer) -// 1: S_PFr2 <= S_PFr; -// 17: timer <= 1'b0; -// default: ; -// endcase -// end -// end - -assign S_PF = S_PFr2; - -endmodule - \ No newline at end of file diff --git a/firmware/PF1_assignment_defaults.qdf b/firmware/PF1_assignment_defaults.qdf deleted file mode 100644 index 6c1421c..0000000 --- a/firmware/PF1_assignment_defaults.qdf +++ /dev/null @@ -1,692 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2011 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 11.0 Build 157 04/27/2011 SJ Full Version -# Date created = 21:56:36 February 04, 2012 -# -# -------------------------------------------------------------------------- # -# -# Note: -# -# 1) Do not modify this file. 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-set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name CASCADE_CHAIN_LENGTH 2 -set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 -set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 -set_global_assignment -name AUTO_CARRY_CHAINS On -set_global_assignment -name AUTO_CASCADE_CHAINS On -set_global_assignment -name AUTO_PARALLEL_EXPANDERS On -set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off -set_global_assignment -name AUTO_ROM_RECOGNITION On -set_global_assignment -name AUTO_RAM_RECOGNITION On -set_global_assignment -name AUTO_DSP_RECOGNITION On -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto -set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On -set_global_assignment -name STRICT_RAM_RECOGNITION Off -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On -set_global_assignment -name FORCE_SYNCH_CLEAR Off -set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On -set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off -set_global_assignment -name AUTO_RESOURCE_SHARING Off -set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off -set_global_assignment -name MAX7000_FANIN_PER_CELL 100 -set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On -set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" -set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off -set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Arria II GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy III" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone IV GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone IV E" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III LS" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix III" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Arria II GX" -set_global_assignment -name REPORT_PARAMETER_SETTINGS On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On -set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" -set_global_assignment -name HDL_MESSAGE_LEVEL Level2 -set_global_assignment -name USE_HIGH_SPEED_ADDER Auto -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 -set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 -set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off -set_global_assignment -name BLOCK_DESIGN_NAMING Auto -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off -set_global_assignment -name SYNTHESIS_EFFORT Auto -set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On -set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off -set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium -set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" -set_global_assignment -name MAX_LABS "-1 (Unlimited)" -set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On -set_global_assignment -name SYNTHESIS_SEED 1 -set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" -set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off -set_global_assignment -name AUTO_MERGE_PLLS On -set_global_assignment -name IGNORE_MODE_FOR_MERGE Off -set_global_assignment -name TXPMA_SLEW_RATE Low -set_global_assignment -name ADCE_ENABLED Auto -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 -set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off -set_global_assignment -name DEVICE AUTO -set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off -set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off -set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On -set_global_assignment -name ENABLE_NCEO_OUTPUT Off -set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name STRATIXIII_UPDATE_MODE Standard -set_global_assignment -name STRATIX_UPDATE_MODE Standard -set_global_assignment -name CVP_MODE Off -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name ARRIAV_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name USER_START_UP_CLOCK Off -set_global_assignment -name ENABLE_VREFA_PIN Off -set_global_assignment -name ENABLE_VREFB_PIN Off -set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off -set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off -set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" -set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off -set_global_assignment -name INIT_DONE_OPEN_DRAIN On -set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name CRC_ERROR_CHECKING Off -set_global_assignment -name INTERNAL_SCRUBBING Off -set_global_assignment -name PR_ERROR_OPEN_DRAIN On -set_global_assignment -name PR_READY_OPEN_DRAIN On -set_global_assignment -name ENABLE_CVP_CONFDONE Off -set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed" -set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 -set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" -set_global_assignment -name OPTIMIZE_SSN Off -set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" -set_global_assignment -name ECO_OPTIMIZE_TIMING Off -set_global_assignment -name ECO_REGENERATE_REPORT Off -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING -value ON -set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically -set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically -set_global_assignment -name SEED 1 -set_global_assignment -name SLOW_SLEW_RATE Off -set_global_assignment -name PCI_IO Off -set_global_assignment -name TURBO_BIT On -set_global_assignment -name WEAK_PULL_UP_RESISTOR Off -set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off -set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off -set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On -set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO -set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO -set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto -set_global_assignment -name AUTO_PACKED_REGISTERS Off -set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO -set_global_assignment -name NORMAL_LCELL_INSERT On -set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On -set_global_assignment -name AUTO_DELAY_CHAINS On -set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off -set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off -set_global_assignment -name AUTO_TURBO_BIT ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off -set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On -set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off -set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off -set_global_assignment -name FITTER_EFFORT "Auto Fit" -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO -set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO -set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off -set_global_assignment -name AUTO_GLOBAL_CLOCK On -set_global_assignment -name AUTO_GLOBAL_OE On -set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic -set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off -set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" -set_global_assignment -name ENABLE_HOLD_BACK_OFF On -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto -set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off -set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value ON -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III" -set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" -set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off -set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On -set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off -set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off -set_global_assignment -name PR_DONE_OPEN_DRAIN On -set_global_assignment -name NCEO_OPEN_DRAIN On -set_global_assignment -name ENABLE_CRC_ERROR_PIN Off -set_global_assignment -name ENABLE_PR_PINS Off -set_global_assignment -name CLAMPING_DIODE Off -set_global_assignment -name TRI_STATE_SPI_PINS Off -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On -set_global_assignment -name COMPRESSION_MODE Off -set_global_assignment -name CLOCK_SOURCE Internal -set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" -set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 -set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off -set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF -set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F -set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name SECURITY_BIT Off -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto -set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On -set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off -set_global_assignment -name GENERATE_TTF_FILE Off -set_global_assignment -name GENERATE_RBF_FILE Off -set_global_assignment -name GENERATE_HEX_FILE Off -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 -set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" -set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off -set_global_assignment -name AUTO_RESTART_CONFIGURATION On -set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off -set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On -set_global_assignment -name ENABLE_OCT_DONE Off -set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off -set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off -set_global_assignment -name START_TIME 0ns -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On -set_global_assignment -name SETUP_HOLD_DETECTION Off -set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -set_global_assignment -name CHECK_OUTPUTS Off -set_global_assignment -name SIMULATION_COVERAGE On -set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name GLITCH_DETECTION Off -set_global_assignment -name GLITCH_INTERVAL 1ns -set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off -set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On -set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off -set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE -set_global_assignment -name SIMULATION_NETLIST_VIEWER Off -set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off -set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO -set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO -set_global_assignment -name DRC_TOP_FANOUT 50 -set_global_assignment -name DRC_FANOUT_EXCEEDING 30 -set_global_assignment -name DRC_GATED_CLOCK_FEED 30 -set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY -set_global_assignment -name ENABLE_DRC_SETTINGS Off -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 -set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 -set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 -set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 -set_global_assignment -name MERGE_HEX_FILE Off -set_global_assignment -name GENERATE_SVF_FILE Off -set_global_assignment -name GENERATE_ISC_FILE Off -set_global_assignment -name GENERATE_JAM_FILE Off -set_global_assignment -name GENERATE_JBC_FILE Off -set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off -set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off -set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" -set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off -set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off -set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_USE_PVA On -set_global_assignment -name POWER_USE_INPUT_FILE "No File" -set_global_assignment -name POWER_USE_INPUT_FILES Off -set_global_assignment -name POWER_VCD_FILTER_GLITCHES On -set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off -set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off -set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -set_global_assignment -name POWER_TJ_VALUE 25 -set_global_assignment -name POWER_USE_TA_VALUE 25 -set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off -set_global_assignment -name POWER_BOARD_TEMPERATURE 25 -set_global_assignment -name IGNORE_PARTITIONS Off -set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off -set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" -set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On -set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On -set_global_assignment -name RTLV_GROUP_RELATED_NODES On -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off -set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On -set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On -set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On -set_global_assignment -name EQC_BBOX_MERGE On -set_global_assignment -name EQC_LVDS_MERGE On -set_global_assignment -name EQC_RAM_UNMERGING On -set_global_assignment -name EQC_DFF_SS_EMULATION On -set_global_assignment -name EQC_RAM_REGISTER_UNPACK On -set_global_assignment -name EQC_MAC_REGISTER_UNPACK On -set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On -set_global_assignment -name EQC_STRUCTURE_MATCHING On -set_global_assignment -name EQC_AUTO_BREAK_CONE On -set_global_assignment -name EQC_POWER_UP_COMPARE Off -set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On -set_global_assignment -name EQC_AUTO_INVERSION On -set_global_assignment -name EQC_AUTO_TERMINATE On -set_global_assignment -name EQC_SUB_CONE_REPORT Off -set_global_assignment -name EQC_RENAMING_RULES On -set_global_assignment -name EQC_PARAMETER_CHECK On -set_global_assignment -name EQC_AUTO_PORTSWAP On -set_global_assignment -name EQC_DETECT_DONT_CARES On -set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off -set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? -set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? -set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? -set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? -set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? -set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? -set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? -set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? -set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? -set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? -set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? -set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? -set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? -set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? -set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? -set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? -set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? -set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? -set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? -set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ? -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? -set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? -set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? -set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? -set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? -set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? -set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? -set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? -set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? -set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? -set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? -set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? -set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? diff --git a/firmware/PF1_nativelink_simulation.rpt b/firmware/PF1_nativelink_simulation.rpt deleted file mode 100644 index 9107913..0000000 --- a/firmware/PF1_nativelink_simulation.rpt +++ /dev/null @@ -1,23 +0,0 @@ -Info: Start Nativelink Simulation process -Info: NativeLink has detected Verilog design -- Verilog simulation models will be used - -========= EDA Simulation Settings ===================== - -Sim Mode : RTL -Family : maxii -Quartus root : c:/programdata/intelfpga_lite/20.1/quartus/bin64/ -Quartus sim root : c:/programdata/intelfpga_lite/20.1/quartus/eda/sim_lib -Simulation Tool : modelsim-altera -Simulation Language : verilog -Simulation Mode : GUI -Sim Output File : -Sim SDF file : -Sim dir : simulation\modelsim - -======================================================= - -Info: Starting NativeLink simulation with ModelSim-Altera software -Sourced NativeLink script c:/programdata/intelfpga_lite/20.1/quartus/common/tcl/internal/nativelink/modelsim.tcl -Warning: File PF1_run_msim_rtl_verilog.do already exists - backing up current file as PF1_run_msim_rtl_verilog.do.bak11 -Info: Spawning ModelSim-Altera Simulation software -Info: NativeLink simulation flow was successful diff --git a/firmware/README.md b/firmware/README.md index e6a3da8..f3ca0de 100644 --- a/firmware/README.md +++ b/firmware/README.md @@ -1,6 +1,6 @@ # 阀板固件 -这是阀板上CPLD的固件，严格意义上也属于硬件，因为是描述的硬件结构。这个固件是按照通信协议写的，但比通信协议能适应更广的传输速度，`SCLK`从5MHz到2Hz都可以 +这是阀板上CPLD的固件，严格意义上也属于硬件，因为是描述的硬件结构。这个固件是按照通信协议写的，但比通信协议能适应更广的传输速度，**烟梗分选机上`SCLK`为1MHz，高电平时间为0.37ms** ## 如何烧录 diff --git a/firmware/SDC1.sdc b/firmware/SDC1.sdc deleted file mode 100644 index e69de29..0000000 diff --git a/firmware/cr_ie_info.json b/firmware/cr_ie_info.json new file mode 100644 index 0000000..422530a --- /dev/null +++ b/firmware/cr_ie_info.json @@ -0,0 +1,22 @@ +{ + "system" : { + "platform" : "windows64", + "os_name" : "Windows 10", + "os_version" : "10.0" + }, + "error" : { + "executable" : "quartus_map", + "comment" : "not_applicable", + "error_message" : "Key not defined in data file: INT_PAD_COUNT", + "source_file" : "/quartus/ddb/dev/dev_pad_info_body.cpp", + "line" : "358", + "stack_trace" : "\t0x7ff8680a4263: DDB_DEV + 0x44263 (DEV_PAD_INFO::get_number_of_pads + 0x17cd3)\n\t0x7ff86637350d: db_cut + 0x29350d (?get_user_pins_available@CUT_RPT_UTILITY@@SAHXZ + 0x7d)\n\t0x7ff866396f2e: db_cut + 0x2b6f2e (?update_summary@CUT_RPT_UTILITY@@QEAAXW4CUT_SUMMARY_TYPE@@W4CUT_PROCESSING_STATUS@@_N222HH@Z + 0x3cde)\n\t0x7ff77e623f84: quartus_map + 0x23f84 (?write_reports@QSYN_FRAMEWORK@@UEAA_N_NPEBD@Z + 0x644)\n\t0x7ff885541587: comp_qexe + 0x11587 (qexe_do_normal + 0x267)\n\t0x7ff885546622: comp_qexe + 0x16622 (qexe_run + 0x432)\n\t0x7ff885547371: comp_qexe + 0x17371 (?qexe_standard_main@@YAHPEAVQEXE_FRAMEWORK@@PEAPEBUQEXE_OPTION_DEFINITION@@HPEAPEBD@Z + 0xc1)\n\t0x7ff77e61b42b: quartus_map + 0x1b42b (?qsyn_main@@YAHHPEAPEBD@Z + 0x53b)\n\t0x7ff890783258: CCL_MSG + 0x13258 (?msg_main_thread@@YAPEAXPEAX@Z + 0x18)\n\t0x7ff890784a5e: CCL_MSG + 0x14a5e (?msg_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x6e)\n\t0x7ff890896af0: ccl_mem + 0x16af0 (?mem_thread_wrapper@@YAPEAXP6APEAXPEAX@Z0@Z + 0x70)\n\t0x7ff890782af1: CCL_MSG + 0x12af1 (?msg_exe_main@@YAHHPEAPEBDP6AHH0@Z@Z + 0xa1)\n\t0x7ff77e62a236: quartus_map + 0x2a236 (__tmainCRTStartup + 0x10e)\n\t0x7ff8b24f7033: KERNEL32 + 0x17033 (BaseThreadInitThunk + 0x13)\n\t0x7ff8b3162650: ntdll + 0x52650 (RtlUserThreadStart + 0x20)\n", + "subsystem" : "DEV" + }, + "quartus" : { + "quartus_bits" : "64", + "version" : "20.1.0", + "build" : "711", + "edition" : "Lite Edition" + } +} \ No newline at end of file diff --git a/firmware/db/.cmp.kpt b/firmware/db/.cmp.kpt index 0711e42..0483fd3 100644 Binary files a/firmware/db/.cmp.kpt and b/firmware/db/.cmp.kpt differ diff --git a/firmware/db/PF1.(0).cnf.cdb b/firmware/db/PF1.(0).cnf.cdb deleted file mode 100644 index e373c12..0000000 Binary files a/firmware/db/PF1.(0).cnf.cdb and /dev/null differ diff --git a/firmware/db/PF1.(0).cnf.hdb b/firmware/db/PF1.(0).cnf.hdb deleted file mode 100644 index ebfbe91..0000000 Binary files a/firmware/db/PF1.(0).cnf.hdb and /dev/null differ diff --git a/firmware/db/PF1.ace_cmp.cdb b/firmware/db/PF1.ace_cmp.cdb deleted file mode 100644 index 49727f0..0000000 Binary files a/firmware/db/PF1.ace_cmp.cdb and /dev/null differ diff --git a/firmware/db/PF1.ace_cmp.hdb b/firmware/db/PF1.ace_cmp.hdb deleted file mode 100644 index 7fcb1b1..0000000 Binary files a/firmware/db/PF1.ace_cmp.hdb and /dev/null differ diff --git a/firmware/db/PF1.asm.rdb b/firmware/db/PF1.asm.rdb deleted file mode 100644 index baf65f7..0000000 Binary files a/firmware/db/PF1.asm.rdb and /dev/null differ diff --git a/firmware/db/PF1.asm_labs.ddb b/firmware/db/PF1.asm_labs.ddb deleted file mode 100644 index fe0c789..0000000 Binary files a/firmware/db/PF1.asm_labs.ddb and /dev/null differ diff --git a/firmware/db/PF1.cmp.cdb b/firmware/db/PF1.cmp.cdb deleted file mode 100644 index 416902f..0000000 Binary files a/firmware/db/PF1.cmp.cdb and /dev/null differ diff --git a/firmware/db/PF1.cmp.hdb b/firmware/db/PF1.cmp.hdb deleted file mode 100644 index 58f9670..0000000 Binary files a/firmware/db/PF1.cmp.hdb and /dev/null differ diff --git a/firmware/db/PF1.cmp.idb b/firmware/db/PF1.cmp.idb deleted file mode 100644 index cbf2f7e..0000000 Binary files a/firmware/db/PF1.cmp.idb and /dev/null differ diff --git a/firmware/db/PF1.cmp.rdb b/firmware/db/PF1.cmp.rdb deleted file mode 100644 index 2339a72..0000000 Binary files a/firmware/db/PF1.cmp.rdb and /dev/null differ diff --git a/firmware/db/PF1.cmp0.ddb b/firmware/db/PF1.cmp0.ddb deleted file mode 100644 index dfcfc89..0000000 Binary files a/firmware/db/PF1.cmp0.ddb and /dev/null differ diff --git a/firmware/db/PF1.drc.qmsg b/firmware/db/PF1.drc.qmsg deleted file mode 100644 index 5f078ea..0000000 --- a/firmware/db/PF1.drc.qmsg +++ /dev/null @@ -1,10 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1635993608838 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Design Assistant Quartus Prime " "Running Quartus Prime Design Assistant" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1635993608838 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 04 10:40:08 2021 " "Processing started: Thu Nov 04 10:40:08 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1635993608838 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Assistant" 0 -1 1635993608838 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_drc PF1 -c PF1 " "Command: quartus_drc PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Design Assistant" 0 -1 1635993608838 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Assistant" 0 -1 1635993609081 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PF1.sdc " "Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Design Assistant" 0 -1 1635993609137 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Design Assistant" 0 -1 1635993609137 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Design Assistant" 0 -1 1635993609137 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Design Assistant" 0 -1 1635993609139 ""} -{ "Info" "IDRC_REPORT_HEALTH_POST_FITTER" "0 0 " "Design Assistant information: finished post-fitting analysis of current design -- generated 0 information messages and 0 warning messages" { } { } 2 308007 "Design Assistant information: finished post-fitting analysis of current design -- generated %1!d! information messages and %2!d! warning messages" 0 0 "Design Assistant" 0 -1 1635993609144 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Design Assistant 0 s 3 s Quartus Prime " "Quartus Prime Design Assistant was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4625 " "Peak virtual memory: 4625 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1635993609162 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 04 10:40:09 2021 " "Processing ended: Thu Nov 04 10:40:09 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1635993609162 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1635993609162 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1635993609162 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Assistant" 0 -1 1635993609162 ""} diff --git a/firmware/db/PF1.eco.cdb b/firmware/db/PF1.eco.cdb deleted file mode 100644 index 45d262d..0000000 Binary files a/firmware/db/PF1.eco.cdb and /dev/null differ diff --git a/firmware/db/PF1.eda.qmsg b/firmware/db/PF1.eda.qmsg deleted file mode 100644 index 9dda7ec..0000000 --- a/firmware/db/PF1.eda.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1636621451390 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636621451390 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 11 17:04:11 2021 " "Processing started: Thu Nov 11 17:04:11 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636621451390 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1636621451390 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1636621451390 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1636621451686 ""} -{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "PF1.vo PF1_v.sdo C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/ simulation " "Generated files \"PF1.vo\" and \"PF1_v.sdo\" in directory \"C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204018 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1636621451832 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4628 " "Peak virtual memory: 4628 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636621451851 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 17:04:11 2021 " "Processing ended: Thu Nov 11 17:04:11 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636621451851 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636621451851 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636621451851 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1636621451851 ""} diff --git a/firmware/db/PF1.hif b/firmware/db/PF1.hif deleted file mode 100644 index ab9e067..0000000 Binary files a/firmware/db/PF1.hif and /dev/null differ diff --git a/firmware/db/PF1.map.cdb b/firmware/db/PF1.map.cdb deleted file mode 100644 index a12e007..0000000 Binary files a/firmware/db/PF1.map.cdb and /dev/null differ diff --git a/firmware/db/PF1.map.hdb b/firmware/db/PF1.map.hdb deleted file mode 100644 index 1c7a7bc..0000000 Binary files a/firmware/db/PF1.map.hdb and /dev/null differ diff --git a/firmware/db/PF1.map.qmsg b/firmware/db/PF1.map.qmsg deleted file mode 100644 index a4303ae..0000000 --- a/firmware/db/PF1.map.qmsg +++ /dev/null @@ -1,12 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1636621433177 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636621433179 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 11 17:03:53 2021 " "Processing started: Thu Nov 11 17:03:53 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636621433179 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621433179 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621433179 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1636621433564 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1636621433564 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_pf1.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_pf1.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_PF1 " "Found entity 1: tb_PF1" { } { { "tb_PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1636621440103 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621440103 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pf1.v 1 1 " "Found 1 design units, including 1 entities, in source file pf1.v" { { "Info" "ISGN_ENTITY_NAME" "1 PF1 " "Found entity 1: PF1" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1636621440106 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621440106 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "PF1 " "Elaborating entity \"PF1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1636621440151 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 PF1.v(88) " "Verilog HDL assignment warning at PF1.v(88): truncated value with size 32 to match size of target (5)" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1636621440167 "|PF1"} -{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 288 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 264 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 143 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 91 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1636621440797 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1636621440977 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1636621440977 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1636621440977 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1636621440977 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4712 " "Peak virtual memory: 4712 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636621441175 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 17:04:01 2021 " "Processing ended: Thu Nov 11 17:04:01 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636621441175 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636621441175 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636621441175 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1636621441175 ""} diff --git a/firmware/db/PF1.map.rdb b/firmware/db/PF1.map.rdb deleted file mode 100644 index 070f764..0000000 Binary files a/firmware/db/PF1.map.rdb and /dev/null differ diff --git a/firmware/db/PF1.pplq.rdb b/firmware/db/PF1.pplq.rdb deleted file mode 100644 index 88e295c..0000000 Binary files a/firmware/db/PF1.pplq.rdb and /dev/null differ diff --git a/firmware/db/PF1.pre_map.hdb b/firmware/db/PF1.pre_map.hdb deleted file mode 100644 index 96d3629..0000000 Binary files a/firmware/db/PF1.pre_map.hdb and /dev/null differ diff --git a/firmware/db/PF1.root_partition.map.reg_db.cdb b/firmware/db/PF1.root_partition.map.reg_db.cdb deleted file mode 100644 index 5351586..0000000 Binary files a/firmware/db/PF1.root_partition.map.reg_db.cdb and /dev/null differ diff --git a/firmware/db/PF1.routing.rdb b/firmware/db/PF1.routing.rdb deleted file mode 100644 index ebb6bd6..0000000 Binary files a/firmware/db/PF1.routing.rdb and /dev/null differ diff --git a/firmware/db/PF1.rtlv.hdb b/firmware/db/PF1.rtlv.hdb deleted file mode 100644 index a596156..0000000 Binary files a/firmware/db/PF1.rtlv.hdb and /dev/null differ diff --git a/firmware/db/PF1.sta.rdb b/firmware/db/PF1.sta.rdb deleted file mode 100644 index 9714601..0000000 Binary files a/firmware/db/PF1.sta.rdb and /dev/null differ diff --git a/firmware/db/PF1.sta_cmp.5_slow.tdb b/firmware/db/PF1.sta_cmp.5_slow.tdb deleted file mode 100644 index e2fb2dd..0000000 Binary files a/firmware/db/PF1.sta_cmp.5_slow.tdb and /dev/null differ diff --git a/firmware/db/PF1.taw.rdb b/firmware/db/PF1.taw.rdb deleted file mode 100644 index 36ebfa3..0000000 Binary files a/firmware/db/PF1.taw.rdb and /dev/null differ diff --git a/firmware/db/PF1.tmw_info b/firmware/db/PF1.tmw_info deleted file mode 100644 index dfbeade..0000000 --- a/firmware/db/PF1.tmw_info +++ /dev/null @@ -1,7 +0,0 @@ -start_full_compilation:s:00:00:20 -start_analysis_synthesis:s:00:00:09-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:06-start_full_compilation -start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:02-start_full_compilation -start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/firmware/db/PF1_global_asgn_op.abo b/firmware/db/PF1_global_asgn_op.abo deleted file mode 100644 index fd95f7d..0000000 --- a/firmware/db/PF1_global_asgn_op.abo +++ /dev/null @@ -1,9041 +0,0 @@ -Version: - 9.0 Build 132 02/25/2009 SJ Full Version - -Chip Device Options: - Device Name: EPM240T100C5 - Device JTAG code: ffffffff - Programming_mode: Passive Serial - NWS_NRS_NCS: UNRESERVED - RDYNBUSY: UNRESERVED - DATA 7 to 1: UNRESERVED - nCEO: UNRESERVED - UNUSED PINS: RESERVED_GND - Default IO Standard:: 3.3-V LVTTL - User Start-up Clock: 0 - Auto Restart on Error: 0 - Release Clears Before Tristates: 0 - Device Clear: 0 - Test And Scan: 0 - Device OE: 0 - Enable Lock Output: 0 - Enable Init Done: 0 - Enable JTAG BST: 0 - Enable Vref A: 0 - Enable Vref B: 0 - - - -**************************** -******Individual Atoms****** -**************************** - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[0] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 49 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[0] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[1] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 50 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[1] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[2] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 51 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[2] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[3] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 52 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[3] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[4] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 53 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[4] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[5] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 54 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[5] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[6] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 55 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[6] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[7] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 56 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[7] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[8] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 57 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[8] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[9] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 58 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[9] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[10] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 59 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[10] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[10] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[10] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[11] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 60 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[11] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[11] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[11] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[12] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 61 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[12] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[12] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[12] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[13] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 62 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[13] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[13] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[13] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[14] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 63 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[14] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[14] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[14] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[15] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 64 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[15] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[15] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[15] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[16] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 65 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[16] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[16] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[16] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[17] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 66 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[17] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[17] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[17] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[18] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 67 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[18] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[18] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[18] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[19] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 68 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[19] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[19] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[19] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[20] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 69 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[20] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[20] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[20] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[21] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 70 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[21] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[21] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[21] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[22] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 71 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[22] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[22] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[22] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[23] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 72 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[23] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[23] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[23] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[24] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 73 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[24] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[24] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[24] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[25] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 74 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[25] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[25] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[25] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[26] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 75 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[26] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[26] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[26] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[27] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 76 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[27] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[27] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[27] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[28] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 77 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[28] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[28] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[28] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[29] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 78 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[29] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[29] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[29] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[30] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 79 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[30] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[30] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[30] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[31] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 80 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[31] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[31] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[31] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[32] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 81 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[32] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[32] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[32] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[33] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 82 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[33] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[33] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[33] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[34] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 83 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[34] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[34] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[34] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[35] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 84 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[35] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[35] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[35] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[36] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 85 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[36] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[36] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[36] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[37] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 86 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[37] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[37] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[37] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[38] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 87 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[38] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[38] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[38] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[39] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 88 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[39] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[39] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[39] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[40] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 89 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[40] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[40] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[40] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[41] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 90 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[41] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[41] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[41] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[42] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 91 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[42] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[42] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[42] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[43] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 92 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[43] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[43] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[43] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[44] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 93 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[44] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[44] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[44] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[45] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 94 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[45] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[45] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[45] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[46] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 95 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[46] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[46] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[46] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[47] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 96 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[47] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] S_PFr2[47] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr2[47] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eefa - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[19] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 97 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~63 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[19] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[19] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[18] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 98 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~65 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[18] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[18] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[17] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 99 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~67 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[17] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[17] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[16] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 100 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~69 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[16] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[16] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: LessThan0~0 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 101 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[19] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[18] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] cnt[17] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[16] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] LessThan0~0 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 7fff - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[15] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 102 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~71 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[15] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[15] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[14] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 103 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~73 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[14] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[14] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[13] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 104 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~75 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[13] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[13] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[12] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 105 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~77 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[12] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[12] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: LessThan0~1 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 106 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[15] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[14] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] cnt[13] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[12] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] LessThan0~1 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 7fff - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[11] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 107 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~79 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[11] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[11] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[10] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 108 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~81 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[10] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[10] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[9] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 109 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~83 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[9] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[8] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 110 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~85 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[8] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: LessThan0~2 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 111 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[11] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[10] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] cnt[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] LessThan0~2 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 7fff - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[7] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 112 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~87 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[7] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[6] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 113 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~89 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[6] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[5] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 114 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~91 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[5] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[4] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 115 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~93 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[4] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: LessThan0~3 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 116 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] cnt[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] LessThan0~3 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 7fff - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: LessThan0~4 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 117 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] LessThan0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] LessThan0~1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] LessThan0~2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] LessThan0~3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] LessThan0~4 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = fffe - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[3] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 118 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~95 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[3] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[2] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 119 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~97 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[2] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[1] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 120 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~99 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[1] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[0] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 121 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Add0~101 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[0] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = aac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: LessThan0~5 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 122 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] cnt[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] LessThan0~5 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 7fff - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[21] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 123 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[21] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Add0~103 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[21] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[20] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 124 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] cnt[20] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Add0~105 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] cnt[20] LIT INDEX 0 FANOUTS 3 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = eac0 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: cnt[20]~44 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 125 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] LessThan0~4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] LessThan0~5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] cnt[21] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] cnt[20] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] cnt[20]~44 LIT INDEX 0 FANOUTS 72 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 000e - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[0] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 126 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[0] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: timer[2] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 127 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] timer[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: [ENA] S_PFr2[29]~144 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 10: [CIN] timer[1]~15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] timer[2] LIT INDEX 0 FANOUTS 2 REGED POS - 2: [COUT] timer[2]~7 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: timer[3] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 128 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] timer[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: [ENA] S_PFr2[29]~144 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 10: [CIN] timer[2]~7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] timer[3] LIT INDEX 0 FANOUTS 2 REGED POS - 2: [COUT] timer[3]~9 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: timer[4] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 129 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] timer[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: [ENA] S_PFr2[29]~144 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 10: [CIN] timer[3]~9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] timer[4] LIT INDEX 0 FANOUTS 2 REGED POS - 2: [COUT] timer[4]~11 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: timer[5] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 130 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] timer[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: [ENA] S_PFr2[29]~144 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 10: [CIN] timer[4]~11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] timer[5] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a5a5 - cin_used = true - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: Equal0~0 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 131 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] timer[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] timer[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] timer[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] timer[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Equal0~0 LIT INDEX 0 FANOUTS 75 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 8000 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[1] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 133 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[1] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[2] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 134 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[2] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[3] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 135 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[3] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[4] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 136 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[4] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[5] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 137 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[5] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[6] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 138 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[6] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[7] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 139 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~3 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[7] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[8] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 140 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[8] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[9] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 141 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[9] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[10] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 142 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[10] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[10] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[11] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 143 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[11] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[11] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[12] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 144 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[12] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[12] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[13] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 145 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[13] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[13] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[14] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 146 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[14] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~5 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[14] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[15] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 147 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[15] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~12 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[15] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[16] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 148 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[16] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[16] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[17] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 149 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[17] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[17] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[18] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 150 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[18] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[18] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[19] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 151 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[19] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~6 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[19] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[20] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 152 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[20] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[20] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[21] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 153 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[21] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~8 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[21] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[22] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 154 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[22] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[22] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[23] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 155 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[23] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~18 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[23] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[24] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 156 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[24] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[24] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[25] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 157 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[25] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~11 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[25] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[26] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 158 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[26] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[26] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[27] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 159 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[27] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~13 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[27] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[28] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 160 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[28] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[28] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[29] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 161 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[29] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~14 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[29] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[30] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 162 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[30] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[30] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[31] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 163 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[31] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~20 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[31] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[32] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 164 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[32] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~21 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[32] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[33] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 165 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[33] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~22 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[33] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[34] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 166 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[34] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~21 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[34] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[35] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 167 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[35] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~22 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[35] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[36] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 168 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[36] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~21 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[36] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[37] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 169 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[37] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~22 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[37] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[38] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 170 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[38] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~21 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[38] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[39] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 171 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[39] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~22 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[39] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[40] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 172 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[40] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~23 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[40] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[41] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 173 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[41] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~24 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[41] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[42] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 174 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[42] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~23 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[42] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[43] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 175 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[43] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~7 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~24 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[43] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[44] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 176 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[44] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~23 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[44] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[45] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 177 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[45] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~9 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~24 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[45] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[46] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 178 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[46] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~23 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[46] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr[47] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 179 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] SDATA LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] S_PFr[47] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~10 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~24 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] S_PFr[47] LIT INDEX 0 FANOUTS 2 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = accc - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~63 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 180 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[19] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~66 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~63 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~64 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~65 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 181 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[18] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~68 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~65 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~66 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~67 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 182 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[17] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~70 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~67 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~68 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~69 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 183 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[16] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~72 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~69 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~70 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~71 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 184 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[15] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~74 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~71 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~72 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~73 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 185 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[14] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~76 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~73 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~74 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~75 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 186 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[13] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~78 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~75 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~76 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~77 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 187 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[12] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~80 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~77 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~78 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~79 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 188 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[11] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~82 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~79 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~80 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~81 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 189 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[10] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~84 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~81 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~82 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~83 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 190 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~86 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~83 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~84 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~85 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 191 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~88 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~85 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~86 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~87 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 192 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~90 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~87 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~88 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~89 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 193 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~92 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~89 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~90 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~91 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 194 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~94 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~91 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~92 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~93 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 195 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~96 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~93 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~94 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~95 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 196 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~98 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~95 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~96 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~97 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 197 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~100 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~97 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~98 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~99 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 198 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~102 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~99 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~100 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~101 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 199 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~101 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~102 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 55aa - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~103 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 200 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[21] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~106 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~103 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Add0~105 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 201 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[20] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: [CIN] Add0~64 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Add0~105 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: [COUT] Add0~106 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: i[1] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 203 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: [SCLR] !(SEN) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 8: NO ITERM - 9: [ENA] DISCONNECTED - 10: [CIN] i[0]~25 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] i[1] LIT INDEX 0 FANOUTS 11 REGED POS - 2: [COUT] i[1]~15 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = on - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: i[2] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 204 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: [SCLR] !(SEN) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 8: NO ITERM - 9: [ENA] DISCONNECTED - 10: [CIN] i[1]~15 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] i[2] LIT INDEX 0 FANOUTS 11 REGED POS - 2: [COUT] i[2]~17 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = on - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~0 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 205 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: NO ITERM - 2: NO ITERM - 3: [DATAC] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~0 LIT INDEX 0 FANOUTS 9 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 000f - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: timer[1] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 207 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] timer[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] timer[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: [ENA] S_PFr2[29]~144 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] timer[1] LIT INDEX 0 FANOUTS 4 REGED POS - 2: [COUT] timer[1]~15 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 6688 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: timer[0] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 208 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] clk LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: [DATAB] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] timer[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] timer[0] LIT INDEX 0 FANOUTS 5 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = fc03 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: Equal0~1 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 209 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: NO ITERM - 2: NO ITERM - 3: [DATAC] timer[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] timer[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Equal0~1 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 000f - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: i[4] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 210 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] i[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: [SCLR] !(SEN) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 8: NO ITERM - 9: [ENA] DISCONNECTED - 10: [CIN] i[3]~21 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] i[4] LIT INDEX 0 FANOUTS 6 REGED POS - 2: [COUT] i[4]~19 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = on - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = a50a - cin_used = true - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~1 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 211 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] SEN LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Equal0~1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~1 LIT INDEX 0 FANOUTS 7 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0080 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: i[3] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 212 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: [SCLR] !(SEN) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 8: NO ITERM - 9: [ENA] DISCONNECTED - 10: [CIN] i[2]~17 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] i[3] LIT INDEX 0 FANOUTS 16 REGED POS - 2: [COUT] i[3]~21 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = on - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5f - cin_used = true - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: i[5] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 213 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: [SCLR] !(SEN) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 8: NO ITERM - 9: [ENA] DISCONNECTED - 10: [CIN] i[4]~19 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] i[5] LIT INDEX 0 FANOUTS 12 REGED POS - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = on - register_cascade_mode = off - sum_lutc_input = cin - lut_mask = 5a5a - cin_used = true - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: i[0] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 214 - Atom Type: stratix_lcell (WYSIWYG) - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: [CLK] SCLK LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: [DATAA] Equal0~2 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: NO ITERM - 4: NO ITERM - 5: [ACLR] ~ VCC LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 6: NO ITERM - 7: [SCLR] !(SEN) LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 8: NO ITERM - 9: [ENA] DISCONNECTED - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [REGOUT] i[0] LIT INDEX 0 FANOUTS 13 REGED POS - 2: [COUT] i[0]~25 LIT INDEX 0 FANOUTS 1 - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = arithmetic - synch_mode = on - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 6688 - output_mode = reg_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~2 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 215 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] Decoder0~1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~2 LIT INDEX 0 FANOUTS 2 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0002 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: S_PFr2[29]~144 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 217 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] cnt[20]~44 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] S_PFr2[29]~144 LIT INDEX 0 FANOUTS 5 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 1111 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~3 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 218 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] Decoder0~1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~3 LIT INDEX 0 FANOUTS 4 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0008 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~4 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 219 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] SEN LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] timer[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] timer[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~4 LIT INDEX 0 FANOUTS 5 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0008 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~5 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 220 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] Decoder0~4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~5 LIT INDEX 0 FANOUTS 6 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0002 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~6 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 221 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: [DATAC] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~6 LIT INDEX 0 FANOUTS 3 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 000a - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~7 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 222 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: [DATAD] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~7 LIT INDEX 0 FANOUTS 6 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 00aa - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~8 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 223 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: [DATAC] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~8 LIT INDEX 0 FANOUTS 3 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 000a - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~9 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 224 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: [DATAD] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~9 LIT INDEX 0 FANOUTS 6 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 00aa - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~10 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 225 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: NO ITERM - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~10 LIT INDEX 0 FANOUTS 9 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 8888 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~11 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 226 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: [DATAC] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~11 LIT INDEX 0 FANOUTS 3 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 000a - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~12 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 227 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~12 LIT INDEX 0 FANOUTS 4 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0080 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~13 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 228 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: NO ITERM - 4: [DATAD] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~13 LIT INDEX 0 FANOUTS 3 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0088 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~14 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 229 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: NO ITERM - 4: [DATAD] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~14 LIT INDEX 0 FANOUTS 3 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0088 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~15 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 230 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: NO ITERM - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~15 LIT INDEX 0 FANOUTS 3 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 8080 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~16 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 231 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: NO ITERM - 4: [DATAD] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~16 LIT INDEX 0 FANOUTS 2 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 00aa - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~17 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 232 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] Decoder0~4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] Decoder0~16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~17 LIT INDEX 0 FANOUTS 2 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0008 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~18 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 233 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] Decoder0~4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~16 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~18 LIT INDEX 0 FANOUTS 2 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0080 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~19 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 234 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] Decoder0~4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~19 LIT INDEX 0 FANOUTS 6 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0008 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~20 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 235 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~4 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~20 LIT INDEX 0 FANOUTS 6 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0080 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~21 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 236 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] Decoder0~1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~21 LIT INDEX 0 FANOUTS 4 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0008 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~22 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 237 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~22 LIT INDEX 0 FANOUTS 4 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0080 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~23 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 238 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] Decoder0~1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~23 LIT INDEX 0 FANOUTS 4 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 0080 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Decoder0~24 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 239 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] i[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: [DATAB] i[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 3: [DATAC] i[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] Decoder0~1 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Decoder0~24 LIT INDEX 0 FANOUTS 4 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 8000 - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: Equal0~2 -- NON-UNIQUE - Atom Hier Name: - Atom Id: 240 - Atom Type: stratix_lcell - - Assembler Lutmask : I very much like HEX numbers. - power up = low - - INPUTS (Driven By): - 0: NO ITERM - 1: [DATAA] Equal0~0 LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 2: NO ITERM - 3: [DATAC] timer[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 4: [DATAD] timer[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 5: NO ITERM - 6: NO ITERM - 7: NO ITERM - 8: NO ITERM - 9: NO ITERM - 10: NO ITERM - 11: NO ITERM - 12: NO ITERM - 13: NO ITERM - 14: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] Equal0~2 LIT INDEX 0 FANOUTS 1 - 1: NONE - 2: NONE - 3: NONE - 4: NONE - - PARAMETER LIST: - operation_mode = normal - synch_mode = off - register_cascade_mode = off - sum_lutc_input = datac - lut_mask = 000a - output_mode = comb_only - - -- ATOM ------------------------ - ATOM_NAME: rst_n -- NON-UNIQUE - Atom Hier Name: - Atom Id: 0 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: NO ITERM - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] rst_n LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = input - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: clk -- NON-UNIQUE - Atom Hier Name: - Atom Id: 132 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: NO ITERM - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] clk LIT INDEX 0 FANOUTS 76 - 1: [PADIO] clk LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = input - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: SDATA -- NON-UNIQUE - Atom Hier Name: - Atom Id: 202 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: NO ITERM - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] SDATA LIT INDEX 0 FANOUTS 48 - 1: [PADIO] SDATA LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = input - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: SEN -- NON-UNIQUE - Atom Hier Name: - Atom Id: 206 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: NO ITERM - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] SEN LIT INDEX 0 FANOUTS 8 - 1: [PADIO] SEN LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = input - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: SCLK -- NON-UNIQUE - Atom Hier Name: - Atom Id: 216 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: NO ITERM - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: [COMBOUT] SCLK LIT INDEX 0 FANOUTS 54 - 1: [PADIO] SCLK LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = input - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[0] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 1 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[0] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[0] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[1] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 2 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[1] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[1] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[2] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 3 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[2] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[2] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[3] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 4 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[3] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[3] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[4] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 5 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[4] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[4] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[5] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 6 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[5] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[5] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[6] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 7 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[6] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[6] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[7] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 8 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[7] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[7] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[8] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 9 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[8] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[8] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[9] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 10 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[9] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[9] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[10] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 11 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[10] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[10] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[11] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 12 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[11] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[11] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[12] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 13 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[12] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[12] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[13] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 14 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[13] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[13] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[14] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 15 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[14] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[14] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[15] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 16 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[15] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[15] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[16] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 17 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[16] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[16] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[17] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 18 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[17] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[17] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[18] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 19 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[18] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[18] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[19] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 20 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[19] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[19] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[20] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 21 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[20] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[20] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[21] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 22 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[21] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[21] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[22] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 23 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[22] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[22] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[23] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 24 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[23] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[23] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[24] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 25 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[24] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[24] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[25] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 26 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[25] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[25] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[26] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 27 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[26] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[26] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[27] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 28 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[27] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[27] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[28] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 29 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[28] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[28] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[29] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 30 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[29] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[29] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[30] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 31 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[30] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[30] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[31] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 32 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[31] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[31] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[32] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 33 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[32] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[32] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[33] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 34 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[33] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[33] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[34] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 35 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[34] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[34] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[35] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 36 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[35] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[35] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[36] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 37 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[36] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[36] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[37] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 38 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[37] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[37] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[38] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 39 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[38] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[38] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[39] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 40 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[39] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[39] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[40] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 41 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[40] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[40] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[41] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 42 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[41] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[41] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[42] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 43 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[42] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[42] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[43] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 44 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[43] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[43] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[44] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 45 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[44] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[44] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[45] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 46 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[45] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[45] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[46] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 47 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[46] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[46] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - -- ATOM ------------------------ - ATOM_NAME: S_PF[47] -- NON-UNIQUE - Atom Hier Name: - Atom Id: 48 - Atom Type: maxii_io - - INPUTS (Driven By): - 0: [DATAIN] S_PFr2[47] LIT INDEX 0 GLOBAL:DONT_CARE DELAY_CHAIN:UNCONNECTED - 1: NO ITERM - 2: NO ITERM - OUTPUTS (Int. Connections): - 0: NONE - 1: [PADIO] S_PF[47] LIT INDEX 0 FANOUTS 0 - - PARAMETER LIST: - operation_mode = output - - DELAY CHAINS: - PAD TO CORE 0: OFF - - IO STANDARD: 3.3-V LVTTL - CURRENT STRENGTH: DEFAULT - PCI DIODE: OFF - diff --git a/firmware/db/logic_util_heursitic.dat b/firmware/db/logic_util_heursitic.dat deleted file mode 100644 index c7300e4..0000000 Binary files a/firmware/db/logic_util_heursitic.dat and /dev/null differ diff --git a/firmware/db/prev_cmp_PF1.asm.qmsg b/firmware/db/prev_cmp_PF1.asm.qmsg deleted file mode 100644 index 0f5c648..0000000 --- a/firmware/db/prev_cmp_PF1.asm.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:50:56 2011 " "Info: Processing started: Mon Dec 26 14:50:56 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Peak virtual memory: 144 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:50:59 2011 " "Info: Processing ended: Mon Dec 26 14:50:59 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/firmware/db/prev_cmp_PF1.eda.qmsg b/firmware/db/prev_cmp_PF1.eda.qmsg deleted file mode 100644 index ea79380..0000000 --- a/firmware/db/prev_cmp_PF1.eda.qmsg +++ /dev/null @@ -1,6 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:51:03 2011 " "Info: Processing started: Mon Dec 26 14:51:03 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Warning" "WVLGO_INVALID_TIMESCALE_SELECTED_FOR_PLL_DESIGN" "" "Warning: An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." { } { } 0 0 "An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool." 0 0 "" 0 -1} -{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "PF1.vo PF1_v.sdo D:/proj/quartus/TEA/PF_DS/simulation/modelsim/ simulation " "Info: Generated files \"PF1.vo\" and \"PF1_v.sdo\" in directory \"D:/proj/quartus/TEA/PF_DS/simulation/modelsim/\" for EDA simulation tool" { } { } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Peak virtual memory: 124 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:51:04 2011 " "Info: Processing ended: Mon Dec 26 14:51:04 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/firmware/db/prev_cmp_PF1.fit.qmsg b/firmware/db/prev_cmp_PF1.fit.qmsg deleted file mode 100644 index f83e6fb..0000000 --- a/firmware/db/prev_cmp_PF1.fit.qmsg +++ /dev/null @@ -1,40 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:50:52 2011 " "Info: Processing started: Mon Dec 26 14:50:52 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IMPP_MPP_USER_DEVICE" "PF1 EPM240T100C5 " "Info: Selected device EPM240T100C5 for design \"PF1\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Info: Device EPM240T100I5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Info: Device EPM240T100A5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Info: Device EPM570T100C5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Info: Device EPM570T100I5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Info: Device EPM570T100A5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} -{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} -{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} } { } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 12 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 12" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SCLK Global clock " "Info: Automatically promoted signal \"SCLK\" to use Global clock" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "SCLK " "Info: Pin \"SCLK\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/90/quartus/bin/pin_planner.ppl" { SCLK } } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "SCLK" } } } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "" 0 -1} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" { } { } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0 -1} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" { } { } 0 0 "Started processing fast register assignments" 0 0 "" 0 -1} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" { } { } 0 0 "Finished processing fast register assignments" 0 0 "" 0 -1} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0 -1} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { } { } 0 0 "Finished register packing" 0 0 "" 0 -1} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register cnt\[14\] register timer\[2\] -9.386 ns " "Info: Slack time is -9.386 ns between source register \"cnt\[14\]\" and destination register \"timer\[2\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.291 ns + Largest register register " "Info: + Largest register to register requirement is 0.291 ns" { } { } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.372 ns Shortest register " "Info: Shortest clock path from clock \"clk\" to destination register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK Unassigned 76 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns timer\[2\] 2 REG Unassigned 4 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'timer\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { clk timer[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.372 ns Longest register " "Info: Longest clock path from clock \"clk\" to destination register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK Unassigned 76 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns timer\[2\] 2 REG Unassigned 4 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'timer\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { clk timer[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.372 ns Shortest register " "Info: Shortest clock path from clock \"clk\" to source register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK Unassigned 76 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns cnt\[14\] 2 REG Unassigned 5 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'cnt\[14\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { clk cnt[14] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.372 ns Longest register " "Info: Longest clock path from clock \"clk\" to source register is 3.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK Unassigned 76 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = Unassigned; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.918 ns) 3.372 ns cnt\[14\] 2 REG Unassigned 5 " "Info: 2: + IC(1.322 ns) + CELL(0.918 ns) = 3.372 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'cnt\[14\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.240 ns" { clk cnt[14] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 60.79 % ) " "Info: Total cell delay = 2.050 ns ( 60.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 39.21 % ) " "Info: Total interconnect delay = 1.322 ns ( 39.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns " "Info: Micro clock to output delay of source is 0.376 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns " "Info: Micro setup delay of destination is 0.333 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.677 ns - Longest register register " "Info: - Longest register to register delay is 9.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[14\] 1 REG Unassigned 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 5; REG Node = 'cnt\[14\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[14] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.315 ns) + CELL(0.740 ns) 3.055 ns LessThan0~1 2 COMB Unassigned 1 " "Info: 2: + IC(2.315 ns) + CELL(0.740 ns) = 3.055 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'LessThan0~1'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.055 ns" { cnt[14] LessThan0~1 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 4.235 ns LessThan0~4 3 COMB Unassigned 1 " "Info: 3: + IC(0.440 ns) + CELL(0.740 ns) = 4.235 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'LessThan0~4'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~1 LessThan0~4 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 5.415 ns cnt\[20\]~44 4 COMB Unassigned 72 " "Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 5.415 ns; Loc. = Unassigned; Fanout = 72; COMB Node = 'cnt\[20\]~44'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~4 cnt[20]~44 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.323 ns) + CELL(0.914 ns) 7.652 ns S_PFr2\[29\]~144 5 COMB Unassigned 5 " "Info: 5: + IC(1.323 ns) + CELL(0.914 ns) = 7.652 ns; Loc. = Unassigned; Fanout = 5; COMB Node = 'S_PFr2\[29\]~144'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { cnt[20]~44 S_PFr2[29]~144 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(1.243 ns) 9.677 ns timer\[2\] 6 REG Unassigned 4 " "Info: 6: + IC(0.782 ns) + CELL(1.243 ns) = 9.677 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'timer\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.025 ns" { S_PFr2[29]~144 timer[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.551 ns ( 47.03 % ) " "Info: Total cell delay = 4.551 ns ( 47.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.126 ns ( 52.97 % ) " "Info: Total interconnect delay = 5.126 ns ( 52.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.677 ns" { cnt[14] LessThan0~1 LessThan0~4 cnt[20]~44 S_PFr2[29]~144 timer[2] } "NODE_NAME" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.677 ns" { cnt[14] LessThan0~1 LessThan0~4 cnt[20]~44 S_PFr2[29]~144 timer[2] } "NODE_NAME" } } } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.677 ns register register " "Info: Estimated most critical path is register to register delay of 9.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[14\] 1 REG LAB_X2_Y3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y3; Fanout = 5; REG Node = 'cnt\[14\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[14] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.315 ns) + CELL(0.740 ns) 3.055 ns LessThan0~1 2 COMB LAB_X5_Y4 1 " "Info: 2: + IC(2.315 ns) + CELL(0.740 ns) = 3.055 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'LessThan0~1'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.055 ns" { cnt[14] LessThan0~1 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 4.235 ns LessThan0~4 3 COMB LAB_X5_Y4 1 " "Info: 3: + IC(0.440 ns) + CELL(0.740 ns) = 4.235 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'LessThan0~4'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~1 LessThan0~4 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 5.415 ns cnt\[20\]~44 4 COMB LAB_X5_Y4 72 " "Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 5.415 ns; Loc. = LAB_X5_Y4; Fanout = 72; COMB Node = 'cnt\[20\]~44'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~4 cnt[20]~44 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.323 ns) + CELL(0.914 ns) 7.652 ns S_PFr2\[29\]~144 5 COMB LAB_X3_Y4 5 " "Info: 5: + IC(1.323 ns) + CELL(0.914 ns) = 7.652 ns; Loc. = LAB_X3_Y4; Fanout = 5; COMB Node = 'S_PFr2\[29\]~144'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.237 ns" { cnt[20]~44 S_PFr2[29]~144 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(1.243 ns) 9.677 ns timer\[2\] 6 REG LAB_X3_Y4 4 " "Info: 6: + IC(0.782 ns) + CELL(1.243 ns) = 9.677 ns; Loc. = LAB_X3_Y4; Fanout = 4; REG Node = 'timer\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.025 ns" { S_PFr2[29]~144 timer[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.551 ns ( 47.03 % ) " "Info: Total cell delay = 4.551 ns ( 47.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.126 ns ( 52.97 % ) " "Info: Total interconnect delay = 5.126 ns ( 52.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.677 ns" { cnt[14] LessThan0~1 LessThan0~4 cnt[20]~44 S_PFr2[29]~144 timer[2] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "22 " "Info: Average interconnect usage is 22% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/proj/quartus/TEA/PF_DS/PF1.fit.smsg " "Info: Generated suppressed messages file D:/proj/quartus/TEA/PF_DS/PF1.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "188 " "Info: Peak virtual memory: 188 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:50:54 2011 " "Info: Processing ended: Mon Dec 26 14:50:54 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/firmware/db/prev_cmp_PF1.map.qmsg b/firmware/db/prev_cmp_PF1.map.qmsg deleted file mode 100644 index 661638c..0000000 --- a/firmware/db/prev_cmp_PF1.map.qmsg +++ /dev/null @@ -1,11 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:50:47 2011 " "Info: Processing started: Mon Dec 26 14:50:47 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "PF1 PF1.v(7) " "Warning (10238): Verilog Module Declaration warning at PF1.v(7): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"PF1\"" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 7 0 0 } } } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0 "" 0 -1} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PF1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file PF1.v" { { "Info" "ISGN_ENTITY_NAME" "1 PF1 " "Info: Found entity 1: PF1" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} -{ "Info" "ISGN_START_ELABORATION_TOP" "PF1 " "Info: Elaborating entity \"PF1\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "o_rising_edge PF1.v(32) " "Warning (10036): Verilog HDL or VHDL warning at PF1.v(32): object \"o_rising_edge\" assigned a value but never read" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 32 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "i\[6\] " "Info: Register \"i\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_n " "Warning (15610): No output dependent on input pin \"rst_n\"" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 10 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1} -{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Info: Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "48 " "Info: Implemented 48 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "188 " "Info: Implemented 188 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Peak virtual memory: 171 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:50:50 2011 " "Info: Processing ended: Mon Dec 26 14:50:50 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/firmware/db/prev_cmp_PF1.qmsg b/firmware/db/prev_cmp_PF1.qmsg deleted file mode 100644 index d52f6c3..0000000 --- a/firmware/db/prev_cmp_PF1.qmsg +++ /dev/null @@ -1,98 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1636374815481 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374815481 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:35 2021 " "Processing started: Mon Nov 08 20:33:35 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374815481 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374815481 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 " "Command: quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374815481 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1636374815734 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1636374815734 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_pf1.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_pf1.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_PF1 " "Found entity 1: tb_PF1" { } { { "tb_PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1636374822193 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374822193 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pf1.v 1 1 " "Found 1 design units, including 1 entities, in source file pf1.v" { { "Info" "ISGN_ENTITY_NAME" "1 PF1 " "Found entity 1: PF1" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1636374822195 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374822195 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "PF1 " "Elaborating entity \"PF1\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1636374822215 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 PF1.v(88) " "Verilog HDL assignment warning at PF1.v(88): truncated value with size 32 to match size of target (5)" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1636374822219 "|PF1"} -{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 288 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 264 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 143 -1 0 } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 91 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1636374822704 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1636374822800 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1636374822800 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1636374822800 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1636374822800 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4712 " "Peak virtual memory: 4712 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374822852 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:42 2021 " "Processing ended: Mon Nov 08 20:33:42 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374822852 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374822852 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374822852 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1636374822852 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1636374823941 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374823941 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:43 2021 " "Processing started: Mon Nov 08 20:33:43 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374823941 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1636374823941 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1636374823941 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1636374824018 ""} -{ "Info" "0" "" "Project = PF1" { } { } 0 0 "Project = PF1" 0 0 "Fitter" 0 0 1636374824018 ""} -{ "Info" "0" "" "Revision = PF1" { } { } 0 0 "Revision = PF1" 0 0 "Fitter" 0 0 1636374824018 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1636374824069 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1636374824070 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "PF1 EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"PF1\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1636374824071 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1636374824111 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1636374824111 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1636374824139 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1636374824143 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636374824212 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1636374824212 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PF1.sdc " "Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1636374824288 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1636374824289 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1636374824296 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1636374824296 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636374824296 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636374824296 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636374824296 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1636374824296 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1636374824305 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1636374824305 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1636374824314 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1636374824330 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1636374824330 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1636374824330 ""} } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1636374824330 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst_n " "Pin \"rst_n\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/miaow/Desktop/valve_board_kun/" { { 0 { 0 ""} 0 551 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1636374824331 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1636374824331 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1636374824334 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1636374824362 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1636374824411 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1636374824412 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1636374824412 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1636374824412 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374824449 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1636374824453 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1636374824558 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374824766 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1636374824768 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1636374825874 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374825874 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1636374825920 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X0_Y0 X8_Y11 " "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" { } { { "loc" "" { Generic "C:/Users/miaow/Desktop/valve_board_kun/" { { 1 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11"} { { 12 { 0 ""} 0 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1636374826111 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1636374826111 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1636374826404 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1636374826404 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374826406 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.39 " "Total time spent on timing analysis during the Fitter is 0.39 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1636374826418 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636374826427 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg " "Generated suppressed messages file C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1636374826511 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5912 " "Peak virtual memory: 5912 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374826537 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:46 2021 " "Processing ended: Mon Nov 08 20:33:46 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374826537 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374826537 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374826537 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1636374826537 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1636374827486 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374827486 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:47 2021 " "Processing started: Mon Nov 08 20:33:47 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374827486 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1636374827486 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1636374827486 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1636374827684 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1636374827725 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1636374827728 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4668 " "Peak virtual memory: 4668 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374827828 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:47 2021 " "Processing ended: Mon Nov 08 20:33:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374827828 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374827828 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374827828 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1636374827828 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1636374828415 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1636374828888 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374828888 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:48 2021 " "Processing started: Mon Nov 08 20:33:48 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374828888 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1636374828888 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta PF1 -c PF1 " "Command: quartus_sta PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1636374828888 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1636374828966 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1636374829062 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1636374829062 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829100 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829100 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1636374829151 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1636374829484 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PF1.sdc " "Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1636374829537 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829537 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1636374829538 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1636374829538 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1636374829542 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1636374829553 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1636374829554 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.012 " "Worst-case setup slack is -10.012" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829557 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829557 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.012 -2235.303 sys_clk " " -10.012 -2235.303 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829557 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829557 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.377 " "Worst-case hold slack is 1.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.377 0.000 sys_clk " " 1.377 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829562 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829562 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1636374829564 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1636374829568 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 sys_clk " " -2.289 -2.289 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636374829570 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636374829570 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1636374829584 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1636374829598 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1636374829598 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4687 " "Peak virtual memory: 4687 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374829638 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:49 2021 " "Processing ended: Mon Nov 08 20:33:49 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374829638 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374829638 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374829638 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1636374829638 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1636374830578 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636374830578 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 08 20:33:50 2021 " "Processing started: Mon Nov 08 20:33:50 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636374830578 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1636374830578 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1636374830578 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1636374830860 ""} -{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "PF1.vo PF1_v.sdo C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/ simulation " "Generated files \"PF1.vo\" and \"PF1_v.sdo\" in directory \"C:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204018 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1636374831008 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4628 " "Peak virtual memory: 4628 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636374831026 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 08 20:33:51 2021 " "Processing ended: Mon Nov 08 20:33:51 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636374831026 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636374831026 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636374831026 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1636374831026 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 10 s " "Quartus Prime Full Compilation was successful. 0 errors, 10 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1636374831619 ""} diff --git a/firmware/db/prev_cmp_PF1.tan.qmsg b/firmware/db/prev_cmp_PF1.tan.qmsg deleted file mode 100644 index 01f7dd9..0000000 --- a/firmware/db/prev_cmp_PF1.tan.qmsg +++ /dev/null @@ -1,13 +0,0 @@ -{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:51:01 2011 " "Info: Processing started: Mon Dec 26 14:51:01 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} -{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} -{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "SCLK " "Info: Assuming node \"SCLK\" is an undefined clock" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "SCLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[17\] register S_PFr2\[41\] 95.93 MHz 10.424 ns Internal " "Info: Clock \"clk\" has Internal fmax of 95.93 MHz between source register \"cnt\[17\]\" and destination register \"S_PFr2\[41\]\" (period= 10.424 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.715 ns + Longest register register " "Info: + Longest register to register delay is 9.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[17\] 1 REG LC_X5_Y3_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N9; Fanout = 5; REG Node = 'cnt\[17\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[17] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.167 ns) + CELL(0.200 ns) 3.367 ns LessThan0~0 2 COMB LC_X5_Y4_N2 1 " "Info: 2: + IC(3.167 ns) + CELL(0.200 ns) = 3.367 ns; Loc. = LC_X5_Y4_N2; Fanout = 1; COMB Node = 'LessThan0~0'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.367 ns" { cnt[17] LessThan0~0 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.741 ns) + CELL(0.740 ns) 4.848 ns LessThan0~4 3 COMB LC_X5_Y4_N6 1 " "Info: 3: + IC(0.741 ns) + CELL(0.740 ns) = 4.848 ns; Loc. = LC_X5_Y4_N6; Fanout = 1; COMB Node = 'LessThan0~4'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.481 ns" { LessThan0~0 LessThan0~4 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.353 ns cnt\[20\]~44 4 COMB LC_X5_Y4_N7 72 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.353 ns; Loc. = LC_X5_Y4_N7; Fanout = 72; COMB Node = 'cnt\[20\]~44'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan0~4 cnt[20]~44 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.771 ns) + CELL(0.591 ns) 9.715 ns S_PFr2\[41\] 5 REG LC_X3_Y1_N5 2 " "Info: 5: + IC(3.771 ns) + CELL(0.591 ns) = 9.715 ns; Loc. = LC_X3_Y1_N5; Fanout = 2; REG Node = 'S_PFr2\[41\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.362 ns" { cnt[20]~44 S_PFr2[41] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.731 ns ( 17.82 % ) " "Info: Total cell delay = 1.731 ns ( 17.82 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.984 ns ( 82.18 % ) " "Info: Total interconnect delay = 7.984 ns ( 82.18 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.715 ns" { cnt[17] LessThan0~0 LessThan0~4 cnt[20]~44 S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.715 ns" { cnt[17] {} LessThan0~0 {} LessThan0~4 {} cnt[20]~44 {} S_PFr2[41] {} } { 0.000ns 3.167ns 0.741ns 0.305ns 3.771ns } { 0.000ns 0.200ns 0.740ns 0.200ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns S_PFr2\[41\] 2 REG LC_X3_Y1_N5 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y1_N5; Fanout = 2; REG Node = 'S_PFr2\[41\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk S_PFr2[41] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[41] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt\[17\] 2 REG LC_X5_Y3_N9 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N9; Fanout = 5; REG Node = 'cnt\[17\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt[17] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[17] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} cnt[17] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[41] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[17] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} cnt[17] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.715 ns" { cnt[17] LessThan0~0 LessThan0~4 cnt[20]~44 S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.715 ns" { cnt[17] {} LessThan0~0 {} LessThan0~4 {} cnt[20]~44 {} S_PFr2[41] {} } { 0.000ns 3.167ns 0.741ns 0.305ns 3.771ns } { 0.000ns 0.200ns 0.740ns 0.200ns 0.591ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[41] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[17] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} cnt[17] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SCLK register i\[4\] register S_PFr\[44\] 126.07 MHz 7.932 ns Internal " "Info: Clock \"SCLK\" has Internal fmax of 126.07 MHz between source register \"i\[4\]\" and destination register \"S_PFr\[44\]\" (period= 7.932 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.223 ns + Longest register register " "Info: + Longest register to register delay is 7.223 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i\[4\] 1 REG LC_X3_Y2_N5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'i\[4\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { i[4] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.511 ns) 1.529 ns Decoder0~1 2 COMB LC_X3_Y2_N9 7 " "Info: 2: + IC(1.018 ns) + CELL(0.511 ns) = 1.529 ns; Loc. = LC_X3_Y2_N9; Fanout = 7; COMB Node = 'Decoder0~1'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.529 ns" { i[4] Decoder0~1 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.334 ns) + CELL(0.200 ns) 4.063 ns Decoder0~23 3 COMB LC_X6_Y1_N2 4 " "Info: 3: + IC(2.334 ns) + CELL(0.200 ns) = 4.063 ns; Loc. = LC_X6_Y1_N2; Fanout = 4; COMB Node = 'Decoder0~23'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.534 ns" { Decoder0~1 Decoder0~23 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.569 ns) + CELL(0.591 ns) 7.223 ns S_PFr\[44\] 4 REG LC_X4_Y2_N7 2 " "Info: 4: + IC(2.569 ns) + CELL(0.591 ns) = 7.223 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr\[44\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.160 ns" { Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.302 ns ( 18.03 % ) " "Info: Total cell delay = 1.302 ns ( 18.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.921 ns ( 81.97 % ) " "Info: Total interconnect delay = 5.921 ns ( 81.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.223 ns" { i[4] Decoder0~1 Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.223 ns" { i[4] {} Decoder0~1 {} Decoder0~23 {} S_PFr[44] {} } { 0.000ns 1.018ns 2.334ns 2.569ns } { 0.000ns 0.511ns 0.200ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SCLK destination 6.206 ns + Shortest register " "Info: + Shortest clock path from clock \"SCLK\" to destination register is 6.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SCLK 1 CLK PIN_41 54 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.156 ns) + CELL(0.918 ns) 6.206 ns S_PFr\[44\] 2 REG LC_X4_Y2_N7 2 " "Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr\[44\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.074 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 33.03 % ) " "Info: Total cell delay = 2.050 ns ( 33.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.156 ns ( 66.97 % ) " "Info: Total interconnect delay = 4.156 ns ( 66.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SCLK source 6.206 ns - Longest register " "Info: - Longest clock path from clock \"SCLK\" to source register is 6.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SCLK 1 CLK PIN_41 54 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.156 ns) + CELL(0.918 ns) 6.206 ns i\[4\] 2 REG LC_X3_Y2_N5 8 " "Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'i\[4\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.074 ns" { SCLK i[4] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 33.03 % ) " "Info: Total cell delay = 2.050 ns ( 33.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.156 ns ( 66.97 % ) " "Info: Total interconnect delay = 4.156 ns ( 66.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[4] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[4] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.223 ns" { i[4] Decoder0~1 Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.223 ns" { i[4] {} Decoder0~1 {} Decoder0~23 {} S_PFr[44] {} } { 0.000ns 1.018ns 2.334ns 2.569ns } { 0.000ns 0.511ns 0.200ns 0.591ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[4] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1} -{ "Info" "ITDB_TSU_RESULT" "S_PFr\[44\] SEN SCLK 3.893 ns register " "Info: tsu for register \"S_PFr\[44\]\" (data pin = \"SEN\", clock pin = \"SCLK\") is 3.893 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.766 ns + Longest pin register " "Info: + Longest pin to register delay is 9.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SEN 1 PIN PIN_40 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 8; PIN Node = 'SEN'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEN } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.740 ns) + CELL(0.200 ns) 4.072 ns Decoder0~1 2 COMB LC_X3_Y2_N9 7 " "Info: 2: + IC(2.740 ns) + CELL(0.200 ns) = 4.072 ns; Loc. = LC_X3_Y2_N9; Fanout = 7; COMB Node = 'Decoder0~1'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.940 ns" { SEN Decoder0~1 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.334 ns) + CELL(0.200 ns) 6.606 ns Decoder0~23 3 COMB LC_X6_Y1_N2 4 " "Info: 3: + IC(2.334 ns) + CELL(0.200 ns) = 6.606 ns; Loc. = LC_X6_Y1_N2; Fanout = 4; COMB Node = 'Decoder0~23'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.534 ns" { Decoder0~1 Decoder0~23 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.569 ns) + CELL(0.591 ns) 9.766 ns S_PFr\[44\] 4 REG LC_X4_Y2_N7 2 " "Info: 4: + IC(2.569 ns) + CELL(0.591 ns) = 9.766 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr\[44\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.160 ns" { Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.123 ns ( 21.74 % ) " "Info: Total cell delay = 2.123 ns ( 21.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.643 ns ( 78.26 % ) " "Info: Total interconnect delay = 7.643 ns ( 78.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.766 ns" { SEN Decoder0~1 Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.766 ns" { SEN {} SEN~combout {} Decoder0~1 {} Decoder0~23 {} S_PFr[44] {} } { 0.000ns 0.000ns 2.740ns 2.334ns 2.569ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SCLK destination 6.206 ns - Shortest register " "Info: - Shortest clock path from clock \"SCLK\" to destination register is 6.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SCLK 1 CLK PIN_41 54 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.156 ns) + CELL(0.918 ns) 6.206 ns S_PFr\[44\] 2 REG LC_X4_Y2_N7 2 " "Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr\[44\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.074 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 33.03 % ) " "Info: Total cell delay = 2.050 ns ( 33.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.156 ns ( 66.97 % ) " "Info: Total interconnect delay = 4.156 ns ( 66.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.766 ns" { SEN Decoder0~1 Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.766 ns" { SEN {} SEN~combout {} Decoder0~1 {} Decoder0~23 {} S_PFr[44] {} } { 0.000ns 0.000ns 2.740ns 2.334ns 2.569ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.591ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} -{ "Info" "ITDB_FULL_TCO_RESULT" "clk S_PF\[5\] S_PFr2\[5\] 8.833 ns register " "Info: tco from clock \"clk\" to destination pin \"S_PF\[5\]\" through register \"S_PFr2\[5\]\" is 8.833 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns S_PFr2\[5\] 2 REG LC_X6_Y2_N1 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; REG Node = 'S_PFr2\[5\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk S_PFr2[5] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[5] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.109 ns + Longest register pin " "Info: + Longest register to pin delay is 5.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns S_PFr2\[5\] 1 REG LC_X6_Y2_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; REG Node = 'S_PFr2\[5\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { S_PFr2[5] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.787 ns) + CELL(2.322 ns) 5.109 ns S_PF\[5\] 2 PIN PIN_5 0 " "Info: 2: + IC(2.787 ns) + CELL(2.322 ns) = 5.109 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'S_PF\[5\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.109 ns" { S_PFr2[5] S_PF[5] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 45.45 % ) " "Info: Total cell delay = 2.322 ns ( 45.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.787 ns ( 54.55 % ) " "Info: Total interconnect delay = 2.787 ns ( 54.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.109 ns" { S_PFr2[5] S_PF[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.109 ns" { S_PFr2[5] {} S_PF[5] {} } { 0.000ns 2.787ns } { 0.000ns 2.322ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[5] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.109 ns" { S_PFr2[5] S_PF[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.109 ns" { S_PFr2[5] {} S_PF[5] {} } { 0.000ns 2.787ns } { 0.000ns 2.322ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} -{ "Info" "ITDB_TH_RESULT" "i\[2\] SEN SCLK 0.072 ns register " "Info: th for register \"i\[2\]\" (data pin = \"SEN\", clock pin = \"SCLK\") is 0.072 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SCLK destination 6.206 ns + Longest register " "Info: + Longest clock path from clock \"SCLK\" to destination register is 6.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SCLK 1 CLK PIN_41 54 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.156 ns) + CELL(0.918 ns) 6.206 ns i\[2\] 2 REG LC_X3_Y2_N3 13 " "Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X3_Y2_N3; Fanout = 13; REG Node = 'i\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.074 ns" { SCLK i[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 33.03 % ) " "Info: Total cell delay = 2.050 ns ( 33.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.156 ns ( 66.97 % ) " "Info: Total interconnect delay = 4.156 ns ( 66.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[2] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[2] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.355 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SEN 1 PIN PIN_40 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 8; PIN Node = 'SEN'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEN } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.463 ns) + CELL(1.760 ns) 6.355 ns i\[2\] 2 REG LC_X3_Y2_N3 13 " "Info: 2: + IC(3.463 ns) + CELL(1.760 ns) = 6.355 ns; Loc. = LC_X3_Y2_N3; Fanout = 13; REG Node = 'i\[2\]'" { } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.223 ns" { SEN i[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.892 ns ( 45.51 % ) " "Info: Total cell delay = 2.892 ns ( 45.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.463 ns ( 54.49 % ) " "Info: Total interconnect delay = 3.463 ns ( 54.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.355 ns" { SEN i[2] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.355 ns" { SEN {} SEN~combout {} i[2] {} } { 0.000ns 0.000ns 3.463ns } { 0.000ns 1.132ns 1.760ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[2] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[2] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.355 ns" { SEN i[2] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.355 ns" { SEN {} SEN~combout {} i[2] {} } { 0.000ns 0.000ns 3.463ns } { 0.000ns 1.132ns 1.760ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} -{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "130 " "Info: Peak virtual memory: 130 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:51:02 2011 " "Info: Processing ended: Mon Dec 26 14:51:02 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} diff --git a/firmware/db/prev_cmp_valveboard_firmware.qmsg b/firmware/db/prev_cmp_valveboard_firmware.qmsg new file mode 100644 index 0000000..153d51a --- /dev/null +++ b/firmware/db/prev_cmp_valveboard_firmware.qmsg @@ -0,0 +1,95 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640336877070 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336877070 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:07:56 2021 " "Processing started: Fri Dec 24 17:07:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336877070 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336877070 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336877070 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1640336877625 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1640336877625 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 valveboard_firmware " "Found entity 1: valveboard_firmware" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640336891329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336891329 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_valveboard_firmware " "Found entity 1: tb_valveboard_firmware" { } { { "tb_valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/tb_valveboard_firmware.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640336891329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336891329 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "valveboard_firmware " "Elaborating entity \"valveboard_firmware\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1640336891389 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 valveboard_firmware.v(88) " "Verilog HDL assignment warning at valveboard_firmware.v(88): truncated value with size 32 to match size of target (5)" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1640336891406 "|valveboard_firmware"} +{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 288 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 264 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 143 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 91 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1640336892331 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1640336892525 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1640336892525 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1640336892525 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1640336892525 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4707 " "Peak virtual memory: 4707 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336892797 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:12 2021 " "Processing ended: Fri Dec 24 17:08:12 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336892797 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336892797 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336892797 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336892797 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1640336894843 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336894845 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:08:13 2021 " "Processing started: Fri Dec 24 17:08:13 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336894845 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1640336894845 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1640336894845 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1640336895074 ""} +{ "Info" "0" "" "Project = valveboard_firmware" { } { } 0 0 "Project = valveboard_firmware" 0 0 "Fitter" 0 0 1640336895074 ""} +{ "Info" "0" "" "Revision = valveboard_firmware" { } { } 0 0 "Revision = valveboard_firmware" 0 0 "Fitter" 0 0 1640336895074 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1640336895171 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1640336895174 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "valveboard_firmware EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"valveboard_firmware\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1640336895182 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640336895234 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640336895234 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1640336895393 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1640336895416 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1640336895800 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "101 101 " "No exact pin location assignment(s) for 101 pins of 101 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1640336895878 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1640336895979 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1640336895979 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1640336895995 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1640336895995 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640336895995 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640336895995 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640336895995 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1640336895995 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640336896027 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640336896027 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640336896043 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640336896074 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock in PIN 20 " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock in PIN 20" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640336896074 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640336896074 ""} } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640336896074 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640336896074 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1640336896090 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1640336896121 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1640336896182 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1640336896182 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1640336896182 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1640336896198 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "99 unused 3.3V 3 96 0 " "Number of I/O pins in group: 99 (unused VREF, 3.3V VCCIO, 3 input, 96 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1640336896198 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 24 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 24 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 30 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 30 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 30 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1640336896198 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336896267 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1640336896272 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1640336896477 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336896817 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1640336896817 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1640336899127 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336899127 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1640336899172 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "10 " "Router estimated average interconnect usage is 10% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "14 X0_Y0 X8_Y11 " "Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" { } { { "loc" "" { Generic "C:/Users/guoyr/Desktop/qwert/" { { 1 { 0 "Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11"} { { 12 { 0 ""} 0 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1640336899476 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1640336899476 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1640336899890 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1640336899890 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336899890 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.47 " "Total time spent on timing analysis during the Fitter is 0.47 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1640336899915 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336899931 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1640336899978 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg " "Generated suppressed messages file C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1640336900065 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5080 " "Peak virtual memory: 5080 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336900127 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:20 2021 " "Processing ended: Fri Dec 24 17:08:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336900127 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336900127 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336900127 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1640336900127 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1640336901822 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336901822 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:08:21 2021 " "Processing started: Fri Dec 24 17:08:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336901822 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1640336901822 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1640336901822 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1640336902150 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1640336902281 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1640336902300 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336902543 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:22 2021 " "Processing ended: Fri Dec 24 17:08:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336902543 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336902543 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336902543 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1640336902543 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1640336903270 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1640336904213 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336904213 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:08:23 2021 " "Processing started: Fri Dec 24 17:08:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336904213 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1640336904213 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta valveboard_firmware -c valveboard_firmware " "Command: quartus_sta valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1640336904213 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1640336904372 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1640336904551 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1640336904551 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336904598 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336904598 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1640336904666 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1640336905141 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1640336905260 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905260 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1640336905261 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1640336905261 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1640336905265 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1640336905290 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1640336905292 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.630 " "Worst-case setup slack is -10.630" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.630 -2257.699 sys_clk " " -10.630 -2257.699 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905298 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905298 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.389 " "Worst-case hold slack is 1.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.389 0.000 sys_clk " " 1.389 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905307 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905307 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640336905320 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640336905323 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 sys_clk " " -2.289 -2.289 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905350 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905350 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1640336905378 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640336905400 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640336905403 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336905474 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:25 2021 " "Processing ended: Fri Dec 24 17:08:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336905474 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336905474 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336905474 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1640336905474 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Quartus Prime Full Compilation was successful. 0 errors, 11 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1640336906173 ""} diff --git a/firmware/db/valveboard_firmware.(0).cnf.cdb b/firmware/db/valveboard_firmware.(0).cnf.cdb new file mode 100644 index 0000000..9344c79 Binary files /dev/null and b/firmware/db/valveboard_firmware.(0).cnf.cdb differ diff --git a/firmware/db/valveboard_firmware.(0).cnf.hdb b/firmware/db/valveboard_firmware.(0).cnf.hdb new file mode 100644 index 0000000..5da6699 Binary files /dev/null and b/firmware/db/valveboard_firmware.(0).cnf.hdb differ diff --git a/firmware/db/valveboard_firmware.ace_cmp.cdb b/firmware/db/valveboard_firmware.ace_cmp.cdb new file mode 100644 index 0000000..afa6584 Binary files /dev/null and b/firmware/db/valveboard_firmware.ace_cmp.cdb differ diff --git a/firmware/db/valveboard_firmware.ace_cmp.hdb b/firmware/db/valveboard_firmware.ace_cmp.hdb new file mode 100644 index 0000000..657dd92 Binary files /dev/null and b/firmware/db/valveboard_firmware.ace_cmp.hdb differ diff --git a/firmware/db/PF1.asm.qmsg b/firmware/db/valveboard_firmware.asm.qmsg similarity index 50% rename from firmware/db/PF1.asm.qmsg rename to firmware/db/valveboard_firmware.asm.qmsg index 0b9060c..a6ff6ca 100644 --- a/firmware/db/PF1.asm.qmsg +++ b/firmware/db/valveboard_firmware.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1636621447972 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636621447972 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 11 17:04:07 2021 " "Processing started: Thu Nov 11 17:04:07 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636621447972 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1636621447972 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1636621447972 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1636621448170 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1636621448230 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1636621448234 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4668 " "Peak virtual memory: 4668 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636621448359 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 17:04:08 2021 " "Processing ended: Thu Nov 11 17:04:08 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636621448359 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636621448359 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636621448359 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1636621448359 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640495500861 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640495500861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 26 13:11:40 2021 " "Processing started: Sun Dec 26 13:11:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640495500861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1640495500861 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1640495500861 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1640495501233 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1640495501358 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1640495501358 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495501576 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:41 2021 " "Processing ended: Sun Dec 26 13:11:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495501576 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495501576 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495501576 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1640495501576 ""} diff --git a/firmware/db/valveboard_firmware.asm.rdb b/firmware/db/valveboard_firmware.asm.rdb new file mode 100644 index 0000000..4c7ec45 Binary files /dev/null and b/firmware/db/valveboard_firmware.asm.rdb differ diff --git a/firmware/db/valveboard_firmware.asm_labs.ddb b/firmware/db/valveboard_firmware.asm_labs.ddb new file mode 100644 index 0000000..1a4ca5f Binary files /dev/null and b/firmware/db/valveboard_firmware.asm_labs.ddb differ diff --git a/firmware/db/PF1.cbx.xml b/firmware/db/valveboard_firmware.cbx.xml similarity index 60% rename from firmware/db/PF1.cbx.xml rename to firmware/db/valveboard_firmware.cbx.xml index c675900..5f5a4cf 100644 --- a/firmware/db/PF1.cbx.xml +++ b/firmware/db/valveboard_firmware.cbx.xml @@ -1,5 +1,5 @@ - + diff --git a/firmware/db/valveboard_firmware.cmp.cdb b/firmware/db/valveboard_firmware.cmp.cdb new file mode 100644 index 0000000..556dbb6 Binary files /dev/null and b/firmware/db/valveboard_firmware.cmp.cdb differ diff --git a/firmware/db/valveboard_firmware.cmp.hdb b/firmware/db/valveboard_firmware.cmp.hdb new file mode 100644 index 0000000..5a74bb6 Binary files /dev/null and b/firmware/db/valveboard_firmware.cmp.hdb differ diff --git a/firmware/db/valveboard_firmware.cmp.idb b/firmware/db/valveboard_firmware.cmp.idb new file mode 100644 index 0000000..8f17c62 Binary files /dev/null and b/firmware/db/valveboard_firmware.cmp.idb differ diff --git a/firmware/db/PF1.cmp.logdb b/firmware/db/valveboard_firmware.cmp.logdb similarity index 100% rename from firmware/db/PF1.cmp.logdb rename to firmware/db/valveboard_firmware.cmp.logdb diff --git a/firmware/db/valveboard_firmware.cmp.rdb b/firmware/db/valveboard_firmware.cmp.rdb new file mode 100644 index 0000000..57d7c78 Binary files /dev/null and b/firmware/db/valveboard_firmware.cmp.rdb differ diff --git a/firmware/db/valveboard_firmware.cmp0.ddb b/firmware/db/valveboard_firmware.cmp0.ddb new file mode 100644 index 0000000..ee61cd7 Binary files /dev/null and b/firmware/db/valveboard_firmware.cmp0.ddb differ diff --git a/firmware/db/PF1.db_info b/firmware/db/valveboard_firmware.db_info similarity index 70% rename from firmware/db/PF1.db_info rename to firmware/db/valveboard_firmware.db_info index 3f4c374..d705ce5 100644 --- a/firmware/db/PF1.db_info +++ b/firmware/db/valveboard_firmware.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Version_Index = 520278016 -Creation_Time = Thu Nov 11 16:59:53 2021 +Creation_Time = Sun Dec 26 13:10:10 2021 diff --git a/firmware/db/valveboard_firmware.eco.cdb b/firmware/db/valveboard_firmware.eco.cdb new file mode 100644 index 0000000..ba49857 Binary files /dev/null and b/firmware/db/valveboard_firmware.eco.cdb differ diff --git a/firmware/db/PF1.fit.qmsg b/firmware/db/valveboard_firmware.fit.qmsg similarity index 51% rename from firmware/db/PF1.fit.qmsg rename to firmware/db/valveboard_firmware.fit.qmsg index 50bc79a..c916772 100644 --- a/firmware/db/PF1.fit.qmsg +++ b/firmware/db/valveboard_firmware.fit.qmsg @@ -1,40 +1,41 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1636621443746 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1636621443749 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "PF1 EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"PF1\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1636621443750 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1636621443822 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1636621443822 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1636621443918 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1636621443935 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1636621444156 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1636621444156 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PF1.sdc " "Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1636621444324 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1636621444326 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1636621444340 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1636621444340 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636621444342 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636621444342 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1636621444342 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1636621444342 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1636621444356 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1636621444356 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1636621444368 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1636621444388 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1636621444388 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1636621444388 ""} } { { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1636621444388 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst_n " "Pin \"rst_n\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "PF1.v" "" { Text "C:/Users/miaow/Desktop/valve_board_kun/PF1.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/miaow/Desktop/valve_board_kun/" { { 0 { 0 ""} 0 551 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1636621444388 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1636621444388 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1636621444398 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1636621444438 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1636621444484 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1636621444486 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1636621444486 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1636621444486 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621444554 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1636621444572 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1636621444766 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621444988 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1636621445001 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1636621446175 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621446175 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1636621446224 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "13 X0_Y0 X8_Y11 " "Router estimated peak interconnect usage is 13% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" { } { { "loc" "" { Generic "C:/Users/miaow/Desktop/valve_board_kun/" { { 1 { 0 "Router estimated peak interconnect usage is 13% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11"} { { 12 { 0 ""} 0 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1636621446448 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1636621446448 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1636621446684 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1636621446684 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621446687 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.38 " "Total time spent on timing analysis during the Fitter is 0.38 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1636621446708 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1636621446722 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg " "Generated suppressed messages file C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1636621446830 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5906 " "Peak virtual memory: 5906 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636621446859 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 17:04:06 2021 " "Processing ended: Thu Nov 11 17:04:06 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636621446859 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636621446859 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636621446859 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1636621446859 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1640495495527 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1640495495527 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "valveboard_firmware EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"valveboard_firmware\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1640495495527 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640495495605 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640495495605 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1640495495699 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1640495495714 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1640495495917 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1640495496089 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1640495496089 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1640495496105 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1640495496105 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640495496105 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640495496105 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640495496105 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1640495496105 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640495496120 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640495496136 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640495496152 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640495496167 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640495496167 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640495496167 ""} } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640495496167 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst_n " "Pin \"rst_n\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/guoyr/Desktop/qwert/" { { 0 { 0 ""} 0 551 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1640495496167 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640495496167 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1640495496183 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1640495496230 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1640495496292 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1640495496292 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1640495496292 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1640495496292 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495496402 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1640495496433 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1640495496636 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495496998 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1640495497013 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1640495498476 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495498476 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1640495498539 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "11 " "Router estimated average interconnect usage is 11% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "12 X9_Y0 X17_Y11 " "Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11" { } { { "loc" "" { Generic "C:/Users/guoyr/Desktop/qwert/" { { 1 { 0 "Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11"} { { 12 { 0 ""} 9 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1640495498835 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1640495498835 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1640495499160 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1640495499160 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495499160 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.46 " "Total time spent on timing analysis during the Fitter is 0.46 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1640495499206 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495499222 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1640495499285 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg " "Generated suppressed messages file C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1640495499363 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5080 " "Peak virtual memory: 5080 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495499425 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:39 2021 " "Processing ended: Sun Dec 26 13:11:39 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495499425 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495499425 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495499425 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1640495499425 ""} diff --git a/firmware/db/PF1.hier_info b/firmware/db/valveboard_firmware.hier_info similarity index 99% rename from firmware/db/PF1.hier_info rename to firmware/db/valveboard_firmware.hier_info index 18a74d6..cbb95aa 100644 --- a/firmware/db/PF1.hier_info +++ b/firmware/db/valveboard_firmware.hier_info @@ -1,4 +1,4 @@ -|PF1 +|valveboard_firmware sys_clk => signal_high_voltage[0]~reg0.CLK sys_clk => signal_high_voltage[1]~reg0.CLK sys_clk => signal_high_voltage[2]~reg0.CLK diff --git a/firmware/db/valveboard_firmware.hif b/firmware/db/valveboard_firmware.hif new file mode 100644 index 0000000..d3d4b14 Binary files /dev/null and b/firmware/db/valveboard_firmware.hif differ diff --git a/firmware/db/PF1.lpc.html b/firmware/db/valveboard_firmware.lpc.html similarity index 100% rename from firmware/db/PF1.lpc.html rename to firmware/db/valveboard_firmware.lpc.html diff --git a/firmware/db/PF1.lpc.rdb b/firmware/db/valveboard_firmware.lpc.rdb similarity index 100% rename from firmware/db/PF1.lpc.rdb rename to firmware/db/valveboard_firmware.lpc.rdb diff --git a/firmware/db/PF1.lpc.txt b/firmware/db/valveboard_firmware.lpc.txt similarity index 100% rename from firmware/db/PF1.lpc.txt rename to firmware/db/valveboard_firmware.lpc.txt diff --git a/firmware/db/valveboard_firmware.map.cdb b/firmware/db/valveboard_firmware.map.cdb new file mode 100644 index 0000000..47d096c Binary files /dev/null and b/firmware/db/valveboard_firmware.map.cdb differ diff --git a/firmware/db/valveboard_firmware.map.hdb b/firmware/db/valveboard_firmware.map.hdb new file mode 100644 index 0000000..c5c7f1d Binary files /dev/null and b/firmware/db/valveboard_firmware.map.hdb differ diff --git a/firmware/db/PF1.map.logdb b/firmware/db/valveboard_firmware.map.logdb similarity index 100% rename from firmware/db/PF1.map.logdb rename to firmware/db/valveboard_firmware.map.logdb diff --git a/firmware/db/valveboard_firmware.map.qmsg b/firmware/db/valveboard_firmware.map.qmsg new file mode 100644 index 0000000..87971c2 --- /dev/null +++ b/firmware/db/valveboard_firmware.map.qmsg @@ -0,0 +1,12 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640495479244 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640495479244 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 26 13:11:19 2021 " "Processing started: Sun Dec 26 13:11:19 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640495479244 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495479244 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495479244 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1640495479775 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1640495479775 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 valveboard_firmware " "Found entity 1: valveboard_firmware" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640495492300 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495492300 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_valveboard_firmware " "Found entity 1: tb_valveboard_firmware" { } { { "tb_valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/tb_valveboard_firmware.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640495492300 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495492300 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "valveboard_firmware " "Elaborating entity \"valveboard_firmware\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1640495492362 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 valveboard_firmware.v(88) " "Verilog HDL assignment warning at valveboard_firmware.v(88): truncated value with size 32 to match size of target (5)" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1640495492362 "|valveboard_firmware"} +{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 288 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 264 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 143 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 91 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1640495493222 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1640495493456 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1640495493456 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1640495493456 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1640495493456 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4700 " "Peak virtual memory: 4700 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495493628 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:33 2021 " "Processing ended: Sun Dec 26 13:11:33 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495493628 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495493628 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495493628 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495493628 ""} diff --git a/firmware/db/valveboard_firmware.map.rdb b/firmware/db/valveboard_firmware.map.rdb new file mode 100644 index 0000000..87c7b0d Binary files /dev/null and b/firmware/db/valveboard_firmware.map.rdb differ diff --git a/firmware/db/valveboard_firmware.pplq.rdb b/firmware/db/valveboard_firmware.pplq.rdb new file mode 100644 index 0000000..a1c9842 Binary files /dev/null and b/firmware/db/valveboard_firmware.pplq.rdb differ diff --git a/firmware/db/valveboard_firmware.pre_map.hdb b/firmware/db/valveboard_firmware.pre_map.hdb new file mode 100644 index 0000000..a17f7fe Binary files /dev/null and b/firmware/db/valveboard_firmware.pre_map.hdb differ diff --git a/firmware/db/valveboard_firmware.root_partition.map.reg_db.cdb b/firmware/db/valveboard_firmware.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..8874da2 Binary files /dev/null and b/firmware/db/valveboard_firmware.root_partition.map.reg_db.cdb differ diff --git a/firmware/db/valveboard_firmware.routing.rdb b/firmware/db/valveboard_firmware.routing.rdb new file mode 100644 index 0000000..3a41fe5 Binary files /dev/null and b/firmware/db/valveboard_firmware.routing.rdb differ diff --git a/firmware/db/valveboard_firmware.rtlv.hdb b/firmware/db/valveboard_firmware.rtlv.hdb new file mode 100644 index 0000000..ea22bf1 Binary files /dev/null and b/firmware/db/valveboard_firmware.rtlv.hdb differ diff --git a/firmware/db/PF1.rtlv_sg.cdb b/firmware/db/valveboard_firmware.rtlv_sg.cdb similarity index 95% rename from firmware/db/PF1.rtlv_sg.cdb rename to firmware/db/valveboard_firmware.rtlv_sg.cdb index a582ec8..c3f7dc5 100644 Binary files a/firmware/db/PF1.rtlv_sg.cdb and b/firmware/db/valveboard_firmware.rtlv_sg.cdb differ diff --git a/firmware/db/PF1.rtlv_sg_swap.cdb b/firmware/db/valveboard_firmware.rtlv_sg_swap.cdb similarity index 100% rename from firmware/db/PF1.rtlv_sg_swap.cdb rename to firmware/db/valveboard_firmware.rtlv_sg_swap.cdb diff --git a/firmware/db/PF1.sld_design_entry.sci b/firmware/db/valveboard_firmware.sld_design_entry.sci similarity index 100% rename from firmware/db/PF1.sld_design_entry.sci rename to firmware/db/valveboard_firmware.sld_design_entry.sci diff --git a/firmware/db/PF1.sld_design_entry_dsc.sci b/firmware/db/valveboard_firmware.sld_design_entry_dsc.sci similarity index 100% rename from firmware/db/PF1.sld_design_entry_dsc.sci rename to firmware/db/valveboard_firmware.sld_design_entry_dsc.sci diff --git a/firmware/db/PF1.smart_action.txt b/firmware/db/valveboard_firmware.smart_action.txt similarity index 100% rename from firmware/db/PF1.smart_action.txt rename to firmware/db/valveboard_firmware.smart_action.txt diff --git a/firmware/db/PF1.sta.qmsg b/firmware/db/valveboard_firmware.sta.qmsg similarity index 58% rename from firmware/db/PF1.sta.qmsg rename to firmware/db/valveboard_firmware.sta.qmsg index cc2590c..b847ece 100644 --- a/firmware/db/PF1.sta.qmsg +++ b/firmware/db/valveboard_firmware.sta.qmsg @@ -1,25 +1,25 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1636621449569 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1636621449569 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 11 17:04:09 2021 " "Processing started: Thu Nov 11 17:04:09 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1636621449569 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1636621449569 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta PF1 -c PF1 " "Command: quartus_sta PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1636621449569 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1636621449666 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1636621449762 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1636621449762 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636621449800 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636621449800 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1636621449849 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1636621450190 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "PF1.sdc " "Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1636621450242 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1636621450242 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1636621450245 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1636621450245 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1636621450248 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1636621450266 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1636621450268 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.907 " "Worst-case setup slack is -10.907" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636621450273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636621450273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.907 -2294.822 sys_clk " " -10.907 -2294.822 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636621450273 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636621450273 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.386 " "Worst-case hold slack is 1.386" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636621450276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636621450276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.386 0.000 sys_clk " " 1.386 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636621450276 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636621450276 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1636621450280 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1636621450284 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636621450288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636621450288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 sys_clk " " -2.289 -2.289 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1636621450288 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1636621450288 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1636621450314 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1636621450336 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1636621450336 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4687 " "Peak virtual memory: 4687 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1636621450366 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 11 17:04:10 2021 " "Processing ended: Thu Nov 11 17:04:10 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1636621450366 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1636621450366 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1636621450366 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1636621450366 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640495503198 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640495503214 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 26 13:11:42 2021 " "Processing started: Sun Dec 26 13:11:42 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640495503214 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1640495503214 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta valveboard_firmware -c valveboard_firmware " "Command: quartus_sta valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1640495503214 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1640495503432 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1640495503716 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1640495503716 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495503841 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495503841 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1640495503962 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1640495504494 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1640495504592 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495504592 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1640495504592 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1640495504592 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1640495504607 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1640495504623 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1640495504639 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -11.085 " "Worst-case setup slack is -11.085" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.085 -2239.564 sys_clk " " -11.085 -2239.564 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495504639 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.386 " "Worst-case hold slack is 1.386" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.386 0.000 sys_clk " " 1.386 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495504639 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640495504639 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640495504654 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 sys_clk " " -2.289 -2.289 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504670 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495504670 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1640495504701 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640495504748 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640495504748 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495504811 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:44 2021 " "Processing ended: Sun Dec 26 13:11:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495504811 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495504811 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495504811 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1640495504811 ""} diff --git a/firmware/db/valveboard_firmware.sta.rdb b/firmware/db/valveboard_firmware.sta.rdb new file mode 100644 index 0000000..3fef8dc Binary files /dev/null and b/firmware/db/valveboard_firmware.sta.rdb differ diff --git a/firmware/db/valveboard_firmware.sta_cmp.5_slow.tdb b/firmware/db/valveboard_firmware.sta_cmp.5_slow.tdb new file mode 100644 index 0000000..00c719f Binary files /dev/null and b/firmware/db/valveboard_firmware.sta_cmp.5_slow.tdb differ diff --git a/firmware/db/PF1.tis_db_list.ddb b/firmware/db/valveboard_firmware.tis_db_list.ddb similarity index 100% rename from firmware/db/PF1.tis_db_list.ddb rename to firmware/db/valveboard_firmware.tis_db_list.ddb diff --git a/firmware/db/valveboard_firmware.tmw_info b/firmware/db/valveboard_firmware.tmw_info new file mode 100644 index 0000000..7f69c7c --- /dev/null +++ b/firmware/db/valveboard_firmware.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:27 +start_analysis_synthesis:s:00:00:16-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:06-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:03-start_full_compilation diff --git a/firmware/db/PF1.vpr.ammdb b/firmware/db/valveboard_firmware.vpr.ammdb similarity index 100% rename from firmware/db/PF1.vpr.ammdb rename to firmware/db/valveboard_firmware.vpr.ammdb diff --git a/firmware/greybox_tmp/cbx_args.txt b/firmware/greybox_tmp/cbx_args.txt deleted file mode 100644 index cbbea97..0000000 --- a/firmware/greybox_tmp/cbx_args.txt +++ /dev/null @@ -1,7 +0,0 @@ -LPM_DIRECTION=LEFT -LPM_TYPE=LPM_SHIFTREG -LPM_WIDTH=8 -DEVICE_FAMILY="MAX II" -clock -shiftin -q diff --git a/firmware/incremental_db/compiled_partitions/PF1.root_partition.map.kpt b/firmware/incremental_db/compiled_partitions/PF1.root_partition.map.kpt deleted file mode 100644 index 99fa5a9..0000000 Binary files a/firmware/incremental_db/compiled_partitions/PF1.root_partition.map.kpt and /dev/null differ diff --git a/firmware/incremental_db/compiled_partitions/PF1.db_info b/firmware/incremental_db/compiled_partitions/valveboard_firmware.db_info similarity index 70% rename from firmware/incremental_db/compiled_partitions/PF1.db_info rename to firmware/incremental_db/compiled_partitions/valveboard_firmware.db_info index 028e208..52a7d04 100644 --- a/firmware/incremental_db/compiled_partitions/PF1.db_info +++ b/firmware/incremental_db/compiled_partitions/valveboard_firmware.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Version_Index = 520278016 -Creation_Time = Wed Nov 03 20:06:07 2021 +Creation_Time = Fri Dec 24 17:19:42 2021 diff --git a/firmware/incremental_db/compiled_partitions/valveboard_firmware.root_partition.map.kpt b/firmware/incremental_db/compiled_partitions/valveboard_firmware.root_partition.map.kpt new file mode 100644 index 0000000..5073d4a Binary files /dev/null and b/firmware/incremental_db/compiled_partitions/valveboard_firmware.root_partition.map.kpt differ diff --git a/firmware/PF1.asm.rpt b/firmware/output_files/valveboard_firmware.asm.rpt similarity index 64% rename from firmware/PF1.asm.rpt rename to firmware/output_files/valveboard_firmware.asm.rpt index 0431165..a25ae03 100644 --- a/firmware/PF1.asm.rpt +++ b/firmware/output_files/valveboard_firmware.asm.rpt @@ -1,5 +1,5 @@ -Assembler report for PF1 -Thu Nov 11 17:04:08 2021 +Assembler report for valveboard_firmware +Sun Dec 26 13:11:41 2021 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -10,7 +10,7 @@ Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: C:/Users/miaow/Desktop/valve_board_kun/PF1.pof + 5. Assembler Device Options: C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.pof 6. Assembler Messages @@ -38,9 +38,9 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Nov 11 17:04:08 2021 ; -; Revision Name ; PF1 ; -; Top-level Entity Name ; PF1 ; +; Assembler Status ; Successful - Sun Dec 26 13:11:41 2021 ; +; Revision Name ; valveboard_firmware ; +; Top-level Entity Name ; valveboard_firmware ; ; Family ; MAX II ; ; Device ; EPM1270T144C5 ; +-----------------------+---------------------------------------+ @@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula. +--------+---------+---------------+ -+------------------------------------------------+ -; Assembler Generated Files ; -+------------------------------------------------+ -; File Name ; -+------------------------------------------------+ -; C:/Users/miaow/Desktop/valve_board_kun/PF1.pof ; -+------------------------------------------------+ ++-------------------------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------------------------+ +; File Name ; ++-------------------------------------------------------------------+ +; C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.pof ; ++-------------------------------------------------------------------+ -+--------------------------------------------------------------------------+ -; Assembler Device Options: C:/Users/miaow/Desktop/valve_board_kun/PF1.pof ; -+----------------+---------------------------------------------------------+ -; Option ; Setting ; -+----------------+---------------------------------------------------------+ -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x005D354D ; -+----------------+---------------------------------------------------------+ ++---------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.pof ; ++----------------+----------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------------------------+ +; JTAG usercode ; 0x005D43EC ; +; Checksum ; 0x005D4406 ; ++----------------+----------------------------------------------------------------------------+ +--------------------+ @@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Thu Nov 11 17:04:07 2021 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1 + Info: Processing started: Sun Dec 26 13:11:40 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 4668 megabytes - Info: Processing ended: Thu Nov 11 17:04:08 2021 + Info: Peak virtual memory: 4662 megabytes + Info: Processing ended: Sun Dec 26 13:11:41 2021 Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/firmware/PF1.cdf b/firmware/output_files/valveboard_firmware.cdf similarity index 52% rename from firmware/PF1.cdf rename to firmware/output_files/valveboard_firmware.cdf index b408833..9bcc741 100644 --- a/firmware/PF1.cdf +++ b/firmware/output_files/valveboard_firmware.cdf @@ -4,7 +4,7 @@ JedecChain; DefaultMfr(6E); P ActionCode(Cfg) - Device PartName(EPM1270T144) Path("C:/Users/miaow/Desktop/valve_board_kun/") File("PF1.pof") MfrSpec(OpMask(23) SEC_Device(EPM1270T144) Child_OpMask(2 7 7)); + Device PartName(EPM1270T144) Path("C:/Users/guoyr/Desktop/qwert/output_files/") File("valveboard_firmware.pof") MfrSpec(OpMask(23) SEC_Device(EPM1270T144) Child_OpMask(2 7 7)); ChainEnd; diff --git a/firmware/output_files/valveboard_firmware.done b/firmware/output_files/valveboard_firmware.done new file mode 100644 index 0000000..79f3bc0 --- /dev/null +++ b/firmware/output_files/valveboard_firmware.done @@ -0,0 +1 @@ +Sun Dec 26 13:11:45 2021 diff --git a/firmware/PF1.fit.rpt b/firmware/output_files/valveboard_firmware.fit.rpt similarity index 91% rename from firmware/PF1.fit.rpt rename to firmware/output_files/valveboard_firmware.fit.rpt index 0fff92f..9b941b2 100644 --- a/firmware/PF1.fit.rpt +++ b/firmware/output_files/valveboard_firmware.fit.rpt @@ -1,5 +1,5 @@ -Fitter report for PF1 -Thu Nov 11 17:04:06 2021 +Fitter report for valveboard_firmware +Sun Dec 26 13:11:39 2021 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -56,10 +56,10 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Thu Nov 11 17:04:06 2021 ; +; Fitter Status ; Successful - Sun Dec 26 13:11:39 2021 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; -; Revision Name ; PF1 ; -; Top-level Entity Name ; PF1 ; +; Revision Name ; valveboard_firmware ; +; Top-level Entity Name ; valveboard_firmware ; ; Family ; MAX II ; ; Device ; EPM1270T144C5 ; ; Timing Models ; Final ; @@ -79,7 +79,6 @@ https://fpgasoftware.intel.com/eula. ; Minimum Core Junction Temperature ; 0 ; ; ; Maximum Core Junction Temperature ; 85 ; ; ; Fit Attempts to Skip ; 0 ; 0.0 ; -; Device I/O Standard ; 3.3-V LVTTL ; ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; @@ -125,22 +124,22 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 12 ; -; Maximum allowed ; 12 ; +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; ; ; ; -; Average used ; 1.12 ; -; Maximum used ; 12 ; +; Average used ; 1.01 ; +; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processors 2-12 ; 1.1% ; +; Processor 2 ; 1.0% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.pin. +The pin-out file can be found in C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.pin. +---------------------------------------------------------------------+ @@ -165,11 +164,11 @@ The pin-out file can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.pin. ; -- arithmetic mode ; 93 ; ; -- qfbk mode ; 7 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 75 ; +; -- synchronous clear/load mode ; 77 ; ; -- asynchronous clear/load mode ; 311 ; ; ; ; ; Total registers ; 313 / 1,270 ( 25 % ) ; -; Total LABs ; 56 / 127 ( 44 % ) ; +; Total LABs ; 51 / 127 ( 40 % ) ; ; Logic elements in carry chains ; 96 ; ; Virtual pins ; 0 ; ; I/O pins ; 101 / 116 ( 87 % ) ; @@ -183,8 +182,8 @@ The pin-out file can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.pin. ; Global signals ; 2 ; ; -- Global clocks ; 2 / 4 ( 50 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 15.2% / 17.2% / 12.9% ; -; Peak interconnect usage (total/H/V) ; 16.1% / 17.8% / 14.3% ; +; Average interconnect usage (total/H/V) ; 14.5% / 16.0% / 12.9% ; +; Peak interconnect usage (total/H/V) ; 16.1% / 16.7% / 15.4% ; ; Maximum fan-out ; 313 ; ; Highest non-global fan-out ; 181 ; ; Total fan-out ; 2471 ; @@ -197,9 +196,9 @@ The pin-out file can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.pin. +------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ; +------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ -; line_sclk ; 40 ; 4 ; 3 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; line_sdata ; 41 ; 4 ; 3 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; -; line_sen ; 39 ; 4 ; 2 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; line_sclk ; 41 ; 4 ; 3 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; line_sdata ; 39 ; 4 ; 2 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +; line_sen ; 40 ; 4 ; 3 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; rst_n ; 37 ; 4 ; 1 ; 3 ; 0 ; 313 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; sys_clk ; 18 ; 1 ; 0 ; 7 ; 5 ; 313 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; +------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ @@ -256,7 +255,7 @@ The pin-out file can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.pin. ; signal_high_voltage[5] ; 55 ; 4 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; signal_high_voltage[6] ; 57 ; 4 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; signal_high_voltage[7] ; 58 ; 4 ; 9 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; signal_high_voltage[8] ; 63 ; 4 ; 10 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; signal_high_voltage[8] ; 63 ; 4 ; 10 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; ; signal_high_voltage[9] ; 66 ; 4 ; 12 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; signal_low_voltage[0] ; 49 ; 4 ; 7 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; signal_low_voltage[10] ; 71 ; 4 ; 16 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; @@ -300,10 +299,10 @@ The pin-out file can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.pin. ; signal_low_voltage[45] ; 22 ; 1 ; 0 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; signal_low_voltage[46] ; 23 ; 1 ; 0 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; signal_low_voltage[47] ; 24 ; 1 ; 0 ; 6 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; signal_low_voltage[4] ; 59 ; 4 ; 9 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; signal_low_voltage[5] ; 60 ; 4 ; 9 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; signal_low_voltage[4] ; 59 ; 4 ; 9 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; +; signal_low_voltage[5] ; 60 ; 4 ; 9 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; ; signal_low_voltage[6] ; 61 ; 4 ; 10 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; signal_low_voltage[7] ; 62 ; 4 ; 10 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +; signal_low_voltage[7] ; 62 ; 4 ; 10 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; ; signal_low_voltage[8] ; 69 ; 4 ; 14 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; signal_low_voltage[9] ; 70 ; 4 ; 15 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; +-------------------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -336,38 +335,38 @@ The pin-out file can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.pin. ; 8 ; 15 ; 1 ; signal_low_voltage[43] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 11 ; 20 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 11 ; 20 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; 12 ; 21 ; 1 ; signal_high_voltage[44] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 13 ; 22 ; 1 ; signal_high_voltage[45] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 14 ; 23 ; 1 ; signal_high_voltage[46] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 15 ; 24 ; 1 ; signal_high_voltage[47] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 16 ; 25 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 16 ; 25 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; 17 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; ; 18 ; 26 ; 1 ; sys_clk ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 19 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 20 ; 27 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 20 ; 27 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; 21 ; 28 ; 1 ; signal_low_voltage[44] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 22 ; 29 ; 1 ; signal_low_voltage[45] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 23 ; 30 ; 1 ; signal_low_voltage[46] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 24 ; 31 ; 1 ; signal_low_voltage[47] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 25 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; 26 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 27 ; 33 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 28 ; 36 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 29 ; 37 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 30 ; 41 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 31 ; 44 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 32 ; 47 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 27 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 28 ; 36 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 29 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 30 ; 41 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 31 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 32 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; 33 ; 50 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; ; 34 ; 51 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; ; 35 ; 52 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; ; 36 ; 53 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; ; 37 ; 56 ; 4 ; rst_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 38 ; 57 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 39 ; 60 ; 4 ; line_sen ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 40 ; 62 ; 4 ; line_sclk ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 41 ; 63 ; 4 ; line_sdata ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 42 ; 67 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 38 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 39 ; 60 ; 4 ; line_sdata ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 40 ; 62 ; 4 ; line_sen ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 41 ; 63 ; 4 ; line_sclk ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; 42 ; 67 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 43 ; 68 ; 4 ; signal_high_voltage[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 44 ; 69 ; 4 ; signal_high_voltage[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 45 ; 74 ; 4 ; signal_high_voltage[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; @@ -432,8 +431,8 @@ The pin-out file can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.pin. ; 104 ; 151 ; 3 ; signal_high_voltage[25] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 105 ; 152 ; 3 ; signal_high_voltage[26] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; ; 106 ; 154 ; 3 ; signal_high_voltage[27] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; 107 ; 156 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; -; 108 ; 158 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; +; 107 ; 156 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 108 ; 158 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ; 109 ; 164 ; 2 ; signal_low_voltage[24] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 110 ; 165 ; 2 ; signal_low_voltage[25] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 111 ; 166 ; 2 ; signal_low_voltage[26] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; @@ -468,8 +467,8 @@ The pin-out file can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.pin. ; 140 ; 204 ; 2 ; signal_low_voltage[37] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 141 ; 205 ; 2 ; signal_low_voltage[38] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; ; 142 ; 208 ; 2 ; signal_low_voltage[39] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 143 ; 212 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; -; 144 ; 215 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; +; 143 ; 212 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 144 ; 215 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +----------+------------+----------+-------------------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ Note: Pin directions (input, output or bidir) are based on device operating in user mode. @@ -491,13 +490,13 @@ Note: Pin directions (input, output or bidir) are based on device operating in u Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ -; |PF1 ; 460 (460) ; 313 ; 0 ; 101 ; 0 ; 147 (147) ; 10 (10) ; 303 (303) ; 96 (96) ; 7 (7) ; |PF1 ; PF1 ; work ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+ +; |valveboard_firmware ; 460 (460) ; 313 ; 0 ; 101 ; 0 ; 147 (147) ; 10 (10) ; 303 (303) ; 96 (96) ; 7 (7) ; |valveboard_firmware ; valveboard_firmware ; work ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -615,13 +614,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------------+--------------+---------+----------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +-----------------------------------+--------------+---------+----------------------------+--------+----------------------+------------------+ -; Equal0~1 ; LC_X2_Y7_N1 ; 34 ; Sync. clear ; no ; -- ; -- ; -; cache2_line_sdata[45]~50 ; LC_X9_Y8_N7 ; 48 ; Clock enable ; no ; -- ; -- ; -; cnt_for_high_voltage_time[18]~129 ; LC_X11_Y5_N0 ; 32 ; Clock enable ; no ; -- ; -- ; -; cnt_for_high_voltage_time~128 ; LC_X7_Y8_N5 ; 51 ; Sync. clear ; no ; -- ; -- ; -; fault_counter[26]~69 ; LC_X2_Y7_N5 ; 32 ; Clock enable ; no ; -- ; -- ; -; i[26]~68 ; LC_X7_Y7_N9 ; 32 ; Sync. clear ; no ; -- ; -- ; -; i[26]~69 ; LC_X7_Y7_N7 ; 32 ; Clock enable ; no ; -- ; -- ; +; Equal0~1 ; LC_X8_Y9_N2 ; 34 ; Sync. clear ; no ; -- ; -- ; +; cache2_line_sdata[45]~50 ; LC_X11_Y5_N8 ; 48 ; Clock enable ; no ; -- ; -- ; +; cnt_for_high_voltage_time[18]~129 ; LC_X14_Y5_N5 ; 32 ; Clock enable ; no ; -- ; -- ; +; cnt_for_high_voltage_time~128 ; LC_X10_Y6_N8 ; 51 ; Sync. clear ; no ; -- ; -- ; +; fault_counter[26]~69 ; LC_X9_Y10_N7 ; 32 ; Clock enable ; no ; -- ; -- ; +; i[26]~68 ; LC_X9_Y6_N8 ; 32 ; Sync. clear ; no ; -- ; -- ; +; i[26]~69 ; LC_X9_Y6_N9 ; 32 ; Clock enable ; no ; -- ; -- ; ; rst_n ; PIN_37 ; 313 ; Async. clear, Clock enable ; yes ; Global Clock ; GCLK3 ; ; sys_clk ; PIN_18 ; 313 ; Clock ; yes ; Global Clock ; GCLK0 ; +-----------------------------------+--------------+---------+----------------------------+--------+----------------------+------------------+ @@ -642,42 +641,42 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------+----------------------+ ; Routing Resource Type ; Usage ; +-----------------------+----------------------+ -; C4s ; 299 / 2,870 ( 10 % ) ; -; Direct links ; 81 / 3,938 ( 2 % ) ; +; C4s ; 301 / 2,870 ( 10 % ) ; +; Direct links ; 80 / 3,938 ( 2 % ) ; ; Global clocks ; 2 / 4 ( 50 % ) ; -; LAB clocks ; 30 / 72 ( 42 % ) ; -; LUT chains ; 48 / 1,143 ( 4 % ) ; -; Local interconnects ; 659 / 3,938 ( 17 % ) ; -; R4s ; 415 / 2,832 ( 15 % ) ; +; LAB clocks ; 24 / 72 ( 33 % ) ; +; LUT chains ; 57 / 1,143 ( 5 % ) ; +; Local interconnects ; 638 / 3,938 ( 16 % ) ; +; R4s ; 382 / 2,832 ( 13 % ) ; +-----------------------+----------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 8.21) ; Number of LABs (Total = 56) ; +; Number of Logic Elements (Average = 9.02) ; Number of LABs (Total = 51) ; +--------------------------------------------+------------------------------+ -; 1 ; 1 ; -; 2 ; 3 ; -; 3 ; 1 ; -; 4 ; 1 ; -; 5 ; 4 ; -; 6 ; 4 ; -; 7 ; 1 ; -; 8 ; 6 ; -; 9 ; 3 ; -; 10 ; 32 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 3 ; +; 7 ; 3 ; +; 8 ; 4 ; +; 9 ; 8 ; +; 10 ; 31 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 2.50) ; Number of LABs (Total = 56) ; +; LAB-wide Signals (Average = 2.63) ; Number of LABs (Total = 51) ; +------------------------------------+------------------------------+ -; 1 Async. clear ; 54 ; -; 1 Clock ; 54 ; -; 1 Clock enable ; 23 ; +; 1 Async. clear ; 47 ; +; 1 Clock ; 48 ; +; 1 Clock enable ; 30 ; ; 1 Sync. clear ; 9 ; +------------------------------------+------------------------------+ @@ -685,49 +684,46 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 8.34) ; Number of LABs (Total = 56) ; +; Number of Signals Sourced (Average = 9.16) ; Number of LABs (Total = 51) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 1 ; -; 2 ; 2 ; -; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 4 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; ; 6 ; 4 ; -; 7 ; 1 ; -; 8 ; 6 ; -; 9 ; 3 ; -; 10 ; 29 ; +; 7 ; 2 ; +; 8 ; 3 ; +; 9 ; 9 ; +; 10 ; 30 ; ; 11 ; 2 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 1 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 6.16) ; Number of LABs (Total = 56) ; +; Number of Signals Sourced Out (Average = 6.35) ; Number of LABs (Total = 51) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 5 ; -; 2 ; 3 ; -; 3 ; 2 ; -; 4 ; 3 ; -; 5 ; 9 ; -; 6 ; 11 ; -; 7 ; 2 ; -; 8 ; 7 ; +; 1 ; 3 ; +; 2 ; 1 ; +; 3 ; 3 ; +; 4 ; 6 ; +; 5 ; 3 ; +; 6 ; 10 ; +; 7 ; 8 ; +; 8 ; 5 ; ; 9 ; 5 ; -; 10 ; 9 ; +; 10 ; 7 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 11.29) ; Number of LABs (Total = 56) ; +; Number of Distinct Inputs (Average = 11.43) ; Number of LABs (Total = 51) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -735,51 +731,49 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 3 ; 2 ; ; 4 ; 1 ; ; 5 ; 5 ; -; 6 ; 3 ; -; 7 ; 2 ; +; 6 ; 0 ; +; 7 ; 0 ; ; 8 ; 3 ; -; 9 ; 5 ; -; 10 ; 5 ; -; 11 ; 7 ; +; 9 ; 8 ; +; 10 ; 6 ; +; 11 ; 5 ; ; 12 ; 3 ; ; 13 ; 4 ; -; 14 ; 6 ; +; 14 ; 2 ; ; 15 ; 1 ; -; 16 ; 2 ; -; 17 ; 1 ; -; 18 ; 2 ; +; 16 ; 4 ; +; 17 ; 3 ; +; 18 ; 1 ; ; 19 ; 0 ; ; 20 ; 0 ; ; 21 ; 0 ; ; 22 ; 0 ; -; 23 ; 2 ; -; 24 ; 1 ; -; 25 ; 0 ; -; 26 ; 0 ; -; 27 ; 1 ; +; 23 ; 1 ; +; 24 ; 0 ; +; 25 ; 2 ; +----------------------------------------------+------------------------------+ -+--------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+---------------------+ -; Option ; Setting ; -+----------------------------------------------+---------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Passive Serial ; -; Reserve all unused pins ; As input tri-stated ; -+----------------------------------------------+---------------------+ ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Reserve all unused pins ; As output driving ground ; ++----------------------------------------------+--------------------------+ +-----------------+ ; Fitter Messages ; +-----------------+ Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected -Info (119006): Selected device EPM1270T144C5 for design "PF1" +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (119006): Selected device EPM1270T144C5 for design "valveboard_firmware" Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time @@ -790,7 +784,7 @@ Info (176444): Device migration not selected. If you intend to use device migrat Info (176445): Device EPM570T144A5 is compatible Info (176445): Device EPM1270T144I5 is compatible Info (176445): Device EPM1270T144A5 is compatible -Critical Warning (332012): Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements Info (332127): Assuming a default timing requirement @@ -799,17 +793,17 @@ Info (332111): Found 1 clocks Info (332111): ======== ============ Info (332111): 1.000 sys_clk Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "sys_clk" to use Global clock in PIN 18 File: C:/Users/miaow/Desktop/valve_board_kun/PF1.v Line: 7 -Info (186216): Automatically promoted some destinations of signal "rst_n" to use Global clock File: C:/Users/miaow/Desktop/valve_board_kun/PF1.v Line: 8 - Info (186217): Destination "negedge_line_sen" may be non-global or may not use global clock File: C:/Users/miaow/Desktop/valve_board_kun/PF1.v Line: 104 - Info (186217): Destination "fiter_line_sdata" may be non-global or may not use global clock File: C:/Users/miaow/Desktop/valve_board_kun/PF1.v Line: 85 -Info (186228): Pin "rst_n" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/miaow/Desktop/valve_board_kun/PF1.v Line: 8 +Info (186215): Automatically promoted signal "sys_clk" to use Global clock in PIN 18 File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 7 +Info (186216): Automatically promoted some destinations of signal "rst_n" to use Global clock File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 8 + Info (186217): Destination "negedge_line_sen" may be non-global or may not use global clock File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 104 + Info (186217): Destination "fiter_line_sdata" may be non-global or may not use global clock File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 85 +Info (186228): Pin "rst_n" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 8 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -817,24 +811,25 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 12% of the available device resources - Info (170196): Router estimated peak interconnect usage is 13% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11 +Info (170195): Router estimated average interconnect usage is 11% of the available device resources + Info (170196): Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.38 seconds. +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.46 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg -Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 5906 megabytes - Info: Processing ended: Thu Nov 11 17:04:06 2021 - Info: Elapsed time: 00:00:04 - Info: Total CPU time (on all processors): 00:00:06 +Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info (144001): Generated suppressed messages file C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 5080 megabytes + Info: Processing ended: Sun Dec 26 13:11:39 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in C:/Users/miaow/Desktop/valve_board_kun/PF1.fit.smsg. +The suppressed messages can be found in C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg. diff --git a/firmware/PF1.fit.smsg b/firmware/output_files/valveboard_firmware.fit.smsg similarity index 100% rename from firmware/PF1.fit.smsg rename to firmware/output_files/valveboard_firmware.fit.smsg diff --git a/firmware/PF1.fit.summary b/firmware/output_files/valveboard_firmware.fit.summary similarity index 65% rename from firmware/PF1.fit.summary rename to firmware/output_files/valveboard_firmware.fit.summary index 6168504..763b757 100644 --- a/firmware/PF1.fit.summary +++ b/firmware/output_files/valveboard_firmware.fit.summary @@ -1,7 +1,7 @@ -Fitter Status : Successful - Thu Nov 11 17:04:06 2021 +Fitter Status : Successful - Sun Dec 26 13:11:39 2021 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition -Revision Name : PF1 -Top-level Entity Name : PF1 +Revision Name : valveboard_firmware +Top-level Entity Name : valveboard_firmware Family : MAX II Device : EPM1270T144C5 Timing Models : Final diff --git a/firmware/PF1.flow.rpt b/firmware/output_files/valveboard_firmware.flow.rpt similarity index 53% rename from firmware/PF1.flow.rpt rename to firmware/output_files/valveboard_firmware.flow.rpt index f5e5530..4741ebb 100644 --- a/firmware/PF1.flow.rpt +++ b/firmware/output_files/valveboard_firmware.flow.rpt @@ -1,5 +1,5 @@ -Flow report for PF1 -Thu Nov 11 17:04:11 2021 +Flow report for valveboard_firmware +Sun Dec 26 13:11:44 2021 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -41,10 +41,10 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Thu Nov 11 17:04:11 2021 ; +; Flow Status ; Successful - Sun Dec 26 13:11:41 2021 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; -; Revision Name ; PF1 ; -; Top-level Entity Name ; PF1 ; +; Revision Name ; valveboard_firmware ; +; Top-level Entity Name ; valveboard_firmware ; ; Family ; MAX II ; ; Device ; EPM1270T144C5 ; ; Timing Models ; Final ; @@ -60,38 +60,23 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 11/11/2021 17:03:53 ; +; Start date & time ; 12/26/2021 13:11:19 ; ; Main task ; Compilation ; -; Revision Name ; PF1 ; +; Revision Name ; valveboard_firmware ; +-------------------+---------------------+ -+--------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+---------------------------------------+-----------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+---------------------------------------+-----------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 52234233346.163662143303348 ; -- ; -- ; -- ; -; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; tb_PF1 ; -; EDA_DESIGN_INSTANCE_NAME ; i1 ; -- ; -- ; -- ; -; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; tb_PF1 ; -- ; -- ; eda_simulation ; -; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; -; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; -; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; -; EDA_TEST_BENCH_FILE ; tb_PF1.v ; -- ; -- ; tb_PF1 ; -; EDA_TEST_BENCH_FILE ; simulation/modelsim/PF1.vt ; -- ; -- ; -- ; -; EDA_TEST_BENCH_MODULE_NAME ; tb_PF1 ; -- ; -- ; tb_PF1 ; -; EDA_TEST_BENCH_MODULE_NAME ; PF1_vlg_tst ; -- ; -- ; -- ; -; EDA_TEST_BENCH_NAME ; PF1 ; -- ; -- ; eda_simulation ; -; EDA_TEST_BENCH_NAME ; tb_PF1 ; -- ; -- ; eda_simulation ; -; EDA_TEST_BENCH_RUN_SIM_FOR ; 5 ms ; -- ; -- ; tb_PF1 ; -; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; -; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -+---------------------------------------+-----------------------------+---------------+-------------+----------------+ ++----------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++---------------------------------------+-----------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++---------------------------------------+-----------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 91767680144.164049547909464 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++---------------------------------------+-----------------------------+---------------+-------------+------------+ +--------------------------------------------------------------------------------------------------------------------------+ @@ -99,12 +84,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 4712 MB ; 00:00:17 ; -; Fitter ; 00:00:04 ; 1.1 ; 5906 MB ; 00:00:06 ; -; Assembler ; 00:00:01 ; 1.0 ; 4667 MB ; 00:00:00 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 4687 MB ; 00:00:01 ; -; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4628 MB ; 00:00:01 ; -; Total ; 00:00:14 ; -- ; -- ; 00:00:25 ; +; Analysis & Synthesis ; 00:00:14 ; 1.0 ; 4700 MB ; 00:00:32 ; +; Fitter ; 00:00:05 ; 1.0 ; 5080 MB ; 00:00:05 ; +; Assembler ; 00:00:01 ; 1.0 ; 4658 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 4662 MB ; 00:00:02 ; +; Total ; 00:00:22 ; -- ; -- ; 00:00:40 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ @@ -113,22 +97,20 @@ https://fpgasoftware.intel.com/eula. +----------------------+------------------+------------+------------+----------------+ ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +----------------------+------------------+------------+------------+----------------+ -; Analysis & Synthesis ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; -; Fitter ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; -; Assembler ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; -; Timing Analyzer ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; -; EDA Netlist Writer ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; +; Analysis & Synthesis ; DESKTOP-2056RVF ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; DESKTOP-2056RVF ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; DESKTOP-2056RVF ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; DESKTOP-2056RVF ; Windows 10 ; 10.0 ; x86_64 ; +----------------------+------------------+------------+------------+----------------+ ------------ ; Flow Log ; ------------ -quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 -quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1 -quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1 -quartus_sta PF1 -c PF1 -quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1 +quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware +quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware +quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware +quartus_sta valveboard_firmware -c valveboard_firmware diff --git a/firmware/output_files/valveboard_firmware.jdi b/firmware/output_files/valveboard_firmware.jdi new file mode 100644 index 0000000..eaf9bcd --- /dev/null +++ b/firmware/output_files/valveboard_firmware.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/firmware/PF1.map.rpt b/firmware/output_files/valveboard_firmware.map.rpt similarity index 76% rename from firmware/PF1.map.rpt rename to firmware/output_files/valveboard_firmware.map.rpt index fd32df0..0c61c23 100644 --- a/firmware/PF1.map.rpt +++ b/firmware/output_files/valveboard_firmware.map.rpt @@ -1,5 +1,5 @@ -Analysis & Synthesis report for PF1 -Thu Nov 11 17:04:01 2021 +Analysis & Synthesis report for valveboard_firmware +Sun Dec 26 13:11:33 2021 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -16,7 +16,7 @@ Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition 8. General Register Statistics 9. Inverted Register Statistics 10. Multiplexer Restructuring Statistics (Restructuring Performed) - 11. Parameter Settings for User Entity Instance: Top-level Entity: |PF1 + 11. Parameter Settings for User Entity Instance: Top-level Entity: |valveboard_firmware 12. Analysis & Synthesis Messages @@ -44,10 +44,10 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Nov 11 17:04:01 2021 ; +; Analysis & Synthesis Status ; Successful - Sun Dec 26 13:11:33 2021 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; -; Revision Name ; PF1 ; -; Top-level Entity Name ; PF1 ; +; Revision Name ; valveboard_firmware ; +; Top-level Entity Name ; valveboard_firmware ; ; Family ; MAX II ; ; Total logic elements ; 468 ; ; Total pins ; 101 ; @@ -56,75 +56,75 @@ https://fpgasoftware.intel.com/eula. +-----------------------------+---------------------------------------------+ -+------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+------------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+------------------------------------------------------------------+--------------------+--------------------+ -; Device ; EPM1270T144C5 ; ; -; Top-level entity name ; PF1 ; PF1 ; -; Family name ; MAX II ; Cyclone IV GX ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Infer RAMs from Raw Logic ; On ; On ; -; Parallel Synthesis ; Off ; Off ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Report Parameter Settings ; On ; On ; -; Report Source Assignments ; On ; On ; -; Report Connectivity Checks ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Block Design Naming ; Auto ; Auto ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -+------------------------------------------------------------------+--------------------+--------------------+ ++--------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+---------------------+---------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+---------------------+---------------------+ +; Device ; EPM1270T144C5 ; ; +; Top-level entity name ; valveboard_firmware ; valveboard_firmware ; +; Family name ; MAX II ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ++------------------------------------------------------------------+---------------------+---------------------+ +------------------------------------------+ @@ -132,8 +132,8 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 12 ; -; Maximum allowed ; 12 ; +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 1 ; @@ -143,13 +143,13 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+------------------------+----------------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+------------------------+----------------------------------------------+---------+ -; PF1.v ; yes ; User Verilog HDL File ; C:/Users/miaow/Desktop/valve_board_kun/PF1.v ; ; -+----------------------------------+-----------------+------------------------+----------------------------------------------+---------+ ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+ +; valveboard_firmware.v ; yes ; User Verilog HDL File ; C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v ; ; ++----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+ +-------------------------------------------------------+ @@ -187,13 +187,13 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------+---------+ -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ -; |PF1 ; 468 (468) ; 313 ; 0 ; 101 ; 0 ; 155 (155) ; 18 (18) ; 295 (295) ; 96 (96) ; 0 (0) ; |PF1 ; PF1 ; work ; -+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+ +; |valveboard_firmware ; 468 (468) ; 313 ; 0 ; 101 ; 0 ; 155 (155) ; 18 (18) ; 295 (295) ; 96 (96) ; 0 (0) ; |valveboard_firmware ; valveboard_firmware ; work ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -322,28 +322,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi * Table truncated at 100 items. To change the number of inverted registers reported, set the "Number of Inverted Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+ -; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |PF1|fault_counter[26] ; -; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |PF1|i[26] ; -; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |PF1|cnt_for_high_voltage_time[18] ; -; 3:1 ; 48 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |PF1|signal_high_voltage[3]~reg0 ; -; 3:1 ; 48 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |PF1|cache2_line_sdata[45] ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------+ +; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |valveboard_firmware|fault_counter[26] ; +; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |valveboard_firmware|i[26] ; +; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |valveboard_firmware|cnt_for_high_voltage_time[18] ; +; 3:1 ; 48 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |valveboard_firmware|signal_high_voltage[3]~reg0 ; +; 3:1 ; 48 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |valveboard_firmware|cache2_line_sdata[45] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------+ +--------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Top-level Entity: |PF1 ; +; Parameter Settings for User Entity Instance: Top-level Entity: |valveboard_firmware ; +---------------------------------+----------------------------------+-----------------+ ; Parameter Name ; Value ; Type ; +---------------------------------+----------------------------------+-----------------+ ; CHANNEL_NUM ; 48 ; Signed Integer ; ; CHANNEL_NUM_MINUS_1 ; 47 ; Signed Integer ; -; HIGH_VOLTAGE_TIME ; 00000000000000001001110001000000 ; Unsigned Binary ; -; HIGH_VOLTAGE_TIME_MINUS_1 ; 00000000000000001001110000111111 ; Unsigned Binary ; +; HIGH_VOLTAGE_TIME ; 00000000000000000001110011101000 ; Unsigned Binary ; +; HIGH_VOLTAGE_TIME_MINUS_1 ; 00000000000000000001110011100111 ; Unsigned Binary ; ; FAULT_COUNTER_THRESHOLD ; 00000001001100010010110100000000 ; Unsigned Binary ; ; FAULT_COUNTER_THRESHOLD_MINUS_1 ; 00000001001100010010110011111111 ; Unsigned Binary ; ; FAULT_COUNTER_THRESHOLD_PLUS_1 ; 00000001001100010010110100000001 ; Unsigned Binary ; @@ -357,25 +357,25 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Thu Nov 11 17:03:53 2021 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 + Info: Processing started: Sun Dec 26 13:11:19 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected -Info (12021): Found 1 design units, including 1 entities, in source file tb_pf1.v - Info (12023): Found entity 1: tb_PF1 File: C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v Line: 2 -Info (12021): Found 1 design units, including 1 entities, in source file pf1.v - Info (12023): Found entity 1: PF1 File: C:/Users/miaow/Desktop/valve_board_kun/PF1.v Line: 6 -Info (12127): Elaborating entity "PF1" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at PF1.v(88): truncated value with size 32 to match size of target (5) File: C:/Users/miaow/Desktop/valve_board_kun/PF1.v Line: 88 -Info (18000): Registers with preset signals will power-up high File: C:/Users/miaow/Desktop/valve_board_kun/PF1.v Line: 288 +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file valveboard_firmware.v + Info (12023): Found entity 1: valveboard_firmware File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 6 +Info (12021): Found 1 design units, including 1 entities, in source file tb_valveboard_firmware.v + Info (12023): Found entity 1: tb_valveboard_firmware File: C:/Users/guoyr/Desktop/qwert/tb_valveboard_firmware.v Line: 2 +Info (12127): Elaborating entity "valveboard_firmware" for the top level hierarchy +Warning (10230): Verilog HDL assignment warning at valveboard_firmware.v(88): truncated value with size 32 to match size of target (5) File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 88 +Info (18000): Registers with preset signals will power-up high File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 288 Info (21057): Implemented 569 device resources after synthesis - the final resource count might be different Info (21058): Implemented 5 input pins Info (21059): Implemented 96 output pins Info (21061): Implemented 468 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 4712 megabytes - Info: Processing ended: Thu Nov 11 17:04:01 2021 - Info: Elapsed time: 00:00:08 - Info: Total CPU time (on all processors): 00:00:17 + Info: Peak virtual memory: 4700 megabytes + Info: Processing ended: Sun Dec 26 13:11:33 2021 + Info: Elapsed time: 00:00:14 + Info: Total CPU time (on all processors): 00:00:32 diff --git a/firmware/PF1.map.summary b/firmware/output_files/valveboard_firmware.map.summary similarity index 55% rename from firmware/PF1.map.summary rename to firmware/output_files/valveboard_firmware.map.summary index 616e8f8..707f9cd 100644 --- a/firmware/PF1.map.summary +++ b/firmware/output_files/valveboard_firmware.map.summary @@ -1,7 +1,7 @@ -Analysis & Synthesis Status : Successful - Thu Nov 11 17:04:01 2021 +Analysis & Synthesis Status : Successful - Sun Dec 26 13:11:33 2021 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition -Revision Name : PF1 -Top-level Entity Name : PF1 +Revision Name : valveboard_firmware +Top-level Entity Name : valveboard_firmware Family : MAX II Total logic elements : 468 Total pins : 101 diff --git a/firmware/PF1.pin b/firmware/output_files/valveboard_firmware.pin similarity index 93% rename from firmware/PF1.pin rename to firmware/output_files/valveboard_firmware.pin index 652185d..ac76d9e 100644 --- a/firmware/PF1.pin +++ b/firmware/output_files/valveboard_firmware.pin @@ -61,7 +61,7 @@ --------------------------------------------------------------------------------- Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition -CHIP "PF1" ASSIGNED TO AN: EPM1270T144C5 +CHIP "valveboard_firmware" ASSIGNED TO AN: EPM1270T144C5 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment ------------------------------------------------------------------------------------------------------------- @@ -75,38 +75,38 @@ signal_low_voltage[42] : 7 : output : 3.3-V LVTTL : signal_low_voltage[43] : 8 : output : 3.3-V LVTTL : : 1 : Y VCCIO1 : 9 : power : : 3.3V : 1 : GNDIO : 10 : gnd : : : : -RESERVED_INPUT : 11 : : : : 1 : +GND* : 11 : : : : 1 : signal_high_voltage[44] : 12 : output : 3.3-V LVTTL : : 1 : Y signal_high_voltage[45] : 13 : output : 3.3-V LVTTL : : 1 : Y signal_high_voltage[46] : 14 : output : 3.3-V LVTTL : : 1 : Y signal_high_voltage[47] : 15 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT : 16 : : : : 1 : +GND* : 16 : : : : 1 : GNDINT : 17 : gnd : : : : sys_clk : 18 : input : 3.3-V LVTTL : : 1 : Y VCCINT : 19 : power : : 2.5V/3.3V : : -RESERVED_INPUT : 20 : : : : 1 : +GND* : 20 : : : : 1 : signal_low_voltage[44] : 21 : output : 3.3-V LVTTL : : 1 : Y signal_low_voltage[45] : 22 : output : 3.3-V LVTTL : : 1 : Y signal_low_voltage[46] : 23 : output : 3.3-V LVTTL : : 1 : Y signal_low_voltage[47] : 24 : output : 3.3-V LVTTL : : 1 : Y VCCIO1 : 25 : power : : 3.3V : 1 : GNDIO : 26 : gnd : : : : -RESERVED_INPUT : 27 : : : : 1 : -RESERVED_INPUT : 28 : : : : 1 : -RESERVED_INPUT : 29 : : : : 1 : -RESERVED_INPUT : 30 : : : : 1 : -RESERVED_INPUT : 31 : : : : 1 : -RESERVED_INPUT : 32 : : : : 1 : +GND* : 27 : : : : 1 : +GND* : 28 : : : : 1 : +GND* : 29 : : : : 1 : +GND* : 30 : : : : 1 : +GND* : 31 : : : : 1 : +GND* : 32 : : : : 1 : TMS : 33 : input : : : 1 : TDI : 34 : input : : : 1 : TCK : 35 : input : : : 1 : TDO : 36 : output : : : 1 : rst_n : 37 : input : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT : 38 : : : : 4 : -line_sen : 39 : input : 3.3-V LVTTL : : 4 : Y -line_sclk : 40 : input : 3.3-V LVTTL : : 4 : Y -line_sdata : 41 : input : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT : 42 : : : : 4 : +GND* : 38 : : : : 4 : +line_sdata : 39 : input : 3.3-V LVTTL : : 4 : Y +line_sen : 40 : input : 3.3-V LVTTL : : 4 : Y +line_sclk : 41 : input : 3.3-V LVTTL : : 4 : Y +GND* : 42 : : : : 4 : signal_high_voltage[0] : 43 : output : 3.3-V LVTTL : : 4 : Y signal_high_voltage[1] : 44 : output : 3.3-V LVTTL : : 4 : Y signal_high_voltage[2] : 45 : output : 3.3-V LVTTL : : 4 : Y @@ -171,8 +171,8 @@ signal_high_voltage[24] : 103 : output : 3.3-V LVTTL : signal_high_voltage[25] : 104 : output : 3.3-V LVTTL : : 3 : Y signal_high_voltage[26] : 105 : output : 3.3-V LVTTL : : 3 : Y signal_high_voltage[27] : 106 : output : 3.3-V LVTTL : : 3 : Y -RESERVED_INPUT : 107 : : : : 3 : -RESERVED_INPUT : 108 : : : : 3 : +GND* : 107 : : : : 3 : +GND* : 108 : : : : 3 : signal_low_voltage[24] : 109 : output : 3.3-V LVTTL : : 2 : Y signal_low_voltage[25] : 110 : output : 3.3-V LVTTL : : 2 : Y signal_low_voltage[26] : 111 : output : 3.3-V LVTTL : : 2 : Y @@ -207,5 +207,5 @@ signal_low_voltage[36] : 139 : output : 3.3-V LVTTL : signal_low_voltage[37] : 140 : output : 3.3-V LVTTL : : 2 : Y signal_low_voltage[38] : 141 : output : 3.3-V LVTTL : : 2 : Y signal_low_voltage[39] : 142 : output : 3.3-V LVTTL : : 2 : Y -RESERVED_INPUT : 143 : : : : 2 : -RESERVED_INPUT : 144 : : : : 2 : +GND* : 143 : : : : 2 : +GND* : 144 : : : : 2 : diff --git a/firmware/output_files/valveboard_firmware.pof b/firmware/output_files/valveboard_firmware.pof new file mode 100644 index 0000000..dbb2228 Binary files /dev/null and b/firmware/output_files/valveboard_firmware.pof differ diff --git a/firmware/PF1.sld b/firmware/output_files/valveboard_firmware.sld similarity index 100% rename from firmware/PF1.sld rename to firmware/output_files/valveboard_firmware.sld diff --git a/firmware/PF1.sta.rpt b/firmware/output_files/valveboard_firmware.sta.rpt similarity index 55% rename from firmware/PF1.sta.rpt rename to firmware/output_files/valveboard_firmware.sta.rpt index fc3b1dc..e5435c5 100644 --- a/firmware/PF1.sta.rpt +++ b/firmware/output_files/valveboard_firmware.sta.rpt @@ -1,5 +1,5 @@ -Timing Analyzer report for PF1 -Thu Nov 11 17:04:10 2021 +Timing Analyzer report for valveboard_firmware +Sun Dec 26 13:11:44 2021 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula. +-----------------------+-----------------------------------------------------+ ; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Timing Analyzer ; Legacy Timing Analyzer ; -; Revision Name ; PF1 ; +; Revision Name ; valveboard_firmware ; ; Device Family ; MAX II ; ; Device Name ; EPM1270T144C5 ; ; Timing Models ; Final ; @@ -71,15 +71,14 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ -; Number detected on machine ; 12 ; -; Maximum allowed ; 12 ; +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; ; ; ; ; Average used ; 1.00 ; -; Maximum used ; 2 ; +; Maximum used ; 1 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.1% ; +----------------------------+-------------+ @@ -97,7 +96,7 @@ https://fpgasoftware.intel.com/eula. +-----------+-----------------+------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +-----------+-----------------+------------+------+ -; 83.98 MHz ; 83.98 MHz ; sys_clk ; ; +; 82.75 MHz ; 82.75 MHz ; sys_clk ; ; +-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -107,7 +106,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +---------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +---------+---------+---------------+ -; sys_clk ; -10.907 ; -2294.822 ; +; sys_clk ; -11.085 ; -2239.564 ; +---------+---------+---------------+ @@ -146,215 +145,215 @@ No paths to report. +---------+-----------+-----------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+-----------+-----------------------+--------------+-------------+--------------+------------+------------+ -; -10.907 ; i[7] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.574 ; -; -10.888 ; i[10] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.555 ; -; -10.718 ; i[12] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.385 ; -; -10.685 ; i[13] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.352 ; -; -10.570 ; i[6] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.237 ; -; -10.453 ; i[7] ; cache_line_sdata[7] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.120 ; -; -10.449 ; i[7] ; cache_line_sdata[3] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.116 ; -; -10.434 ; i[10] ; cache_line_sdata[7] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.101 ; -; -10.430 ; i[10] ; cache_line_sdata[3] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.097 ; -; -10.427 ; i[7] ; cache_line_sdata[0] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.094 ; -; -10.408 ; i[10] ; cache_line_sdata[0] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.075 ; -; -10.353 ; i[28] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.020 ; -; -10.328 ; i[7] ; cache2_line_sdata[8] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.995 ; -; -10.328 ; i[7] ; cache2_line_sdata[11] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.995 ; -; -10.328 ; i[7] ; cache2_line_sdata[12] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.995 ; -; -10.328 ; i[7] ; cache2_line_sdata[47] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.995 ; -; -10.309 ; i[10] ; cache2_line_sdata[8] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.976 ; -; -10.309 ; i[10] ; cache2_line_sdata[11] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.976 ; -; -10.309 ; i[10] ; cache2_line_sdata[12] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.976 ; -; -10.309 ; i[10] ; cache2_line_sdata[47] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.976 ; -; -10.289 ; i[15] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.956 ; -; -10.264 ; i[12] ; cache_line_sdata[7] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.931 ; -; -10.260 ; i[12] ; cache_line_sdata[3] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.927 ; -; -10.248 ; i[24] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.915 ; -; -10.238 ; i[12] ; cache_line_sdata[0] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.905 ; -; -10.231 ; i[13] ; cache_line_sdata[7] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.898 ; -; -10.227 ; i[13] ; cache_line_sdata[3] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.894 ; -; -10.223 ; i[11] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.890 ; -; -10.205 ; i[13] ; cache_line_sdata[0] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.872 ; -; -10.203 ; i[7] ; cache2_line_sdata[7] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.870 ; -; -10.203 ; i[7] ; cache2_line_sdata[36] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.870 ; -; -10.203 ; i[7] ; cache2_line_sdata[40] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.870 ; -; -10.197 ; i[7] ; cache2_line_sdata[5] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.864 ; -; -10.197 ; i[7] ; cache2_line_sdata[29] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.864 ; -; -10.197 ; i[7] ; cache2_line_sdata[35] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.864 ; -; -10.196 ; i[7] ; cache_line_sdata[35] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.863 ; -; -10.195 ; i[19] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.862 ; -; -10.186 ; i[7] ; cache2_line_sdata[3] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.853 ; -; -10.186 ; i[7] ; cache2_line_sdata[4] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.853 ; -; -10.186 ; i[7] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.853 ; -; -10.186 ; i[7] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.853 ; -; -10.186 ; i[7] ; cache2_line_sdata[28] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.853 ; -; -10.186 ; i[7] ; cache2_line_sdata[42] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.853 ; -; -10.186 ; i[7] ; cache2_line_sdata[44] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.853 ; -; -10.184 ; i[10] ; cache2_line_sdata[7] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.851 ; -; -10.184 ; i[10] ; cache2_line_sdata[36] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.851 ; -; -10.184 ; i[10] ; cache2_line_sdata[40] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.851 ; -; -10.178 ; i[10] ; cache2_line_sdata[5] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.845 ; -; -10.178 ; i[10] ; cache2_line_sdata[29] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.845 ; -; -10.178 ; i[10] ; cache2_line_sdata[35] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.845 ; -; -10.177 ; i[10] ; cache_line_sdata[35] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.844 ; -; -10.167 ; i[10] ; cache2_line_sdata[3] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.834 ; -; -10.167 ; i[10] ; cache2_line_sdata[4] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.834 ; -; -10.167 ; i[10] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.834 ; -; -10.167 ; i[10] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.834 ; -; -10.167 ; i[10] ; cache2_line_sdata[28] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.834 ; -; -10.167 ; i[10] ; cache2_line_sdata[42] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.834 ; -; -10.167 ; i[10] ; cache2_line_sdata[44] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.834 ; -; -10.139 ; i[12] ; cache2_line_sdata[8] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.806 ; -; -10.139 ; i[12] ; cache2_line_sdata[11] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.806 ; -; -10.139 ; i[12] ; cache2_line_sdata[12] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.806 ; -; -10.139 ; i[12] ; cache2_line_sdata[47] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.806 ; -; -10.134 ; i[7] ; cache2_line_sdata[6] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.801 ; -; -10.134 ; i[7] ; cache2_line_sdata[38] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.801 ; -; -10.134 ; i[7] ; cache2_line_sdata[46] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.801 ; -; -10.128 ; i[7] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.795 ; -; -10.128 ; i[7] ; cache2_line_sdata[23] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.795 ; -; -10.128 ; i[7] ; cache2_line_sdata[24] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.795 ; -; -10.128 ; i[7] ; cache2_line_sdata[39] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.795 ; -; -10.128 ; i[7] ; cache2_line_sdata[43] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.795 ; -; -10.124 ; i[7] ; cache2_line_sdata[9] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.791 ; -; -10.124 ; i[7] ; cache2_line_sdata[10] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.791 ; -; -10.124 ; i[7] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.791 ; -; -10.124 ; i[7] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.791 ; -; -10.124 ; i[7] ; cache2_line_sdata[16] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.791 ; -; -10.124 ; i[7] ; cache2_line_sdata[22] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.791 ; -; -10.124 ; i[7] ; cache2_line_sdata[27] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.791 ; -; -10.124 ; i[7] ; cache2_line_sdata[30] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.791 ; -; -10.118 ; i[7] ; cache2_line_sdata[18] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.785 ; -; -10.118 ; i[7] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.785 ; -; -10.118 ; i[7] ; cache2_line_sdata[26] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.785 ; -; -10.116 ; i[6] ; cache_line_sdata[7] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.783 ; -; -10.115 ; i[10] ; cache2_line_sdata[6] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.782 ; -; -10.115 ; i[10] ; cache2_line_sdata[38] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.782 ; -; -10.115 ; i[10] ; cache2_line_sdata[46] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.782 ; -; -10.112 ; i[6] ; cache_line_sdata[3] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.779 ; -; -10.109 ; i[10] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.776 ; -; -10.109 ; i[10] ; cache2_line_sdata[23] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.776 ; -; -10.109 ; i[10] ; cache2_line_sdata[24] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.776 ; -; -10.109 ; i[10] ; cache2_line_sdata[39] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.776 ; -; -10.109 ; i[10] ; cache2_line_sdata[43] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.776 ; -; -10.106 ; i[13] ; cache2_line_sdata[8] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.773 ; -; -10.106 ; i[13] ; cache2_line_sdata[11] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.773 ; -; -10.106 ; i[13] ; cache2_line_sdata[12] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.773 ; -; -10.106 ; i[13] ; cache2_line_sdata[47] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.773 ; -; -10.105 ; i[14] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.772 ; -; -10.105 ; i[10] ; cache2_line_sdata[9] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.772 ; -; -10.105 ; i[10] ; cache2_line_sdata[10] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.772 ; -; -10.105 ; i[10] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.772 ; -; -10.105 ; i[10] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 10.772 ; +; -11.085 ; i[29] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.752 ; +; -11.085 ; i[29] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.752 ; +; -11.085 ; i[29] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.752 ; +; -11.040 ; i[29] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.707 ; +; -11.040 ; i[29] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.707 ; +; -10.937 ; i[28] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.604 ; +; -10.937 ; i[28] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.604 ; +; -10.937 ; i[28] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.604 ; +; -10.902 ; i[29] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.569 ; +; -10.902 ; i[29] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.569 ; +; -10.902 ; i[29] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.569 ; +; -10.895 ; i[11] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.562 ; +; -10.895 ; i[11] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.562 ; +; -10.895 ; i[11] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.562 ; +; -10.892 ; i[28] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.559 ; +; -10.892 ; i[28] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.559 ; +; -10.862 ; i[25] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.529 ; +; -10.862 ; i[25] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.529 ; +; -10.862 ; i[25] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.529 ; +; -10.850 ; i[11] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.517 ; +; -10.850 ; i[11] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.517 ; +; -10.817 ; i[25] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.484 ; +; -10.817 ; i[25] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.484 ; +; -10.754 ; i[28] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.421 ; +; -10.754 ; i[28] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.421 ; +; -10.754 ; i[28] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.421 ; +; -10.753 ; i[3] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.420 ; +; -10.753 ; i[3] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.420 ; +; -10.753 ; i[3] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.420 ; +; -10.750 ; i[26] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.417 ; +; -10.750 ; i[26] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.417 ; +; -10.750 ; i[26] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.417 ; +; -10.712 ; i[11] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.379 ; +; -10.712 ; i[11] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.379 ; +; -10.712 ; i[11] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.379 ; +; -10.708 ; i[3] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.375 ; +; -10.708 ; i[3] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.375 ; +; -10.705 ; i[26] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.372 ; +; -10.705 ; i[26] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.372 ; +; -10.679 ; i[25] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.346 ; +; -10.679 ; i[25] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.346 ; +; -10.679 ; i[25] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.346 ; +; -10.670 ; i[15] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.337 ; +; -10.670 ; i[15] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.337 ; +; -10.670 ; i[15] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.337 ; +; -10.663 ; i[29] ; cache_line_sdata[11] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.330 ; +; -10.662 ; i[12] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.329 ; +; -10.662 ; i[12] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.329 ; +; -10.662 ; i[12] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.329 ; +; -10.634 ; i[24] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.301 ; +; -10.634 ; i[24] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.301 ; +; -10.634 ; i[24] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.301 ; +; -10.625 ; i[15] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.292 ; +; -10.625 ; i[15] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.292 ; +; -10.617 ; i[12] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.284 ; +; -10.617 ; i[12] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.284 ; +; -10.609 ; i[2] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.276 ; +; -10.609 ; i[2] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.276 ; +; -10.609 ; i[2] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.276 ; +; -10.604 ; i[1] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.271 ; +; -10.604 ; i[1] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.271 ; +; -10.604 ; i[1] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.271 ; +; -10.599 ; i[13] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.266 ; +; -10.599 ; i[13] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.266 ; +; -10.599 ; i[13] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.266 ; +; -10.589 ; i[24] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.256 ; +; -10.589 ; i[24] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.256 ; +; -10.580 ; i[20] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.247 ; +; -10.580 ; i[20] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.247 ; +; -10.580 ; i[20] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.247 ; +; -10.570 ; i[3] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.237 ; +; -10.570 ; i[3] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.237 ; +; -10.570 ; i[3] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.237 ; +; -10.567 ; i[26] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.234 ; +; -10.567 ; i[26] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.234 ; +; -10.567 ; i[26] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.234 ; +; -10.564 ; i[2] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.231 ; +; -10.564 ; i[2] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.231 ; +; -10.559 ; i[1] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.226 ; +; -10.559 ; i[1] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.226 ; +; -10.554 ; i[13] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ; +; -10.554 ; i[13] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ; +; -10.554 ; i[14] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ; +; -10.554 ; i[14] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ; +; -10.554 ; i[14] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ; +; -10.535 ; i[20] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.202 ; +; -10.535 ; i[20] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.202 ; +; -10.516 ; i[22] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.183 ; +; -10.516 ; i[22] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.183 ; +; -10.516 ; i[22] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.183 ; +; -10.515 ; i[28] ; cache_line_sdata[11] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.182 ; +; -10.509 ; i[14] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.176 ; +; -10.509 ; i[14] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.176 ; +; -10.504 ; i[17] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.171 ; +; -10.504 ; i[17] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.171 ; +; -10.504 ; i[17] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.171 ; +; -10.487 ; i[15] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.154 ; +; -10.487 ; i[15] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.154 ; +; -10.487 ; i[15] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.154 ; +; -10.479 ; i[12] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.146 ; +---------+-----------+-----------------------+--------------+-------------+--------------+------------+------------+ -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'sys_clk' ; -+-------+-------------------------+------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------+------------------------------+--------------+-------------+--------------+------------+------------+ -; 1.386 ; tmp_cache_line_sdata[1] ; tmp_cache_line_sdata[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.607 ; -; 1.389 ; tmp_cache_line_sdata[0] ; tmp_cache_line_sdata[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.610 ; -; 1.404 ; cache_line_sclk[1] ; cache_line_sclk[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.625 ; -; 1.406 ; cache_line_sclk[3] ; cache_line_sclk[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.627 ; -; 1.641 ; tmp_cache_line_sdata[3] ; tmp_cache_line_sdata[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.862 ; -; 1.644 ; tmp_cache_line_sdata[2] ; tmp_cache_line_sdata[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.865 ; -; 1.661 ; is_high_voltage_time ; signal_high_voltage[7]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.882 ; -; 1.661 ; cache2_line_sdata[26] ; signal_low_voltage[26]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.882 ; -; 1.661 ; cache_line_sclk[2] ; cache_line_sclk[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.882 ; -; 1.665 ; cache2_line_sdata[39] ; signal_high_voltage[39]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.886 ; -; 1.666 ; cache2_line_sdata[26] ; signal_high_voltage[26]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.887 ; -; 1.666 ; cache2_line_sdata[39] ; signal_low_voltage[39]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.887 ; -; 1.670 ; cache_line_sdata[11] ; cache2_line_sdata[11] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.891 ; -; 1.673 ; cache_line_sdata[1] ; cache2_line_sdata[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.894 ; -; 1.674 ; cache_line_sen[0] ; cache_line_sen[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.895 ; -; 1.679 ; cache_line_sdata[36] ; cache2_line_sdata[36] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.900 ; -; 1.684 ; cache_line_sdata[40] ; cache2_line_sdata[40] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.905 ; -; 1.702 ; cache_line_sen[1] ; cache_line_sen[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.923 ; -; 1.795 ; cache_line_sen[2] ; cache_line_sen[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.016 ; -; 1.898 ; cache_line_sdata[16] ; cache_line_sdata[16] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ; -; 1.898 ; cache_line_sdata[19] ; cache_line_sdata[19] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ; -; 1.898 ; cache_line_sdata[27] ; cache_line_sdata[27] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ; -; 1.898 ; cache_line_sdata[28] ; cache_line_sdata[28] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ; -; 1.898 ; cache_line_sdata[44] ; cache_line_sdata[44] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ; -; 1.899 ; cache_line_sdata[39] ; cache_line_sdata[39] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.120 ; -; 1.902 ; cache2_line_sdata[25] ; signal_high_voltage[25]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.123 ; -; 1.907 ; cache_line_sdata[9] ; cache_line_sdata[9] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.128 ; -; 1.907 ; cache_line_sdata[13] ; cache_line_sdata[13] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.128 ; -; 1.908 ; cache_line_sdata[43] ; cache_line_sdata[43] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.129 ; -; 1.909 ; cache_line_sdata[45] ; cache_line_sdata[45] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.130 ; -; 1.917 ; cache_line_sdata[0] ; cache_line_sdata[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.138 ; -; 1.917 ; cache_line_sdata[42] ; cache_line_sdata[42] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.138 ; -; 1.923 ; cache_line_sdata[41] ; cache2_line_sdata[41] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.144 ; -; 1.938 ; cache_line_sdata[6] ; cache_line_sdata[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.159 ; -; 2.029 ; cache_line_sdata[28] ; cache2_line_sdata[28] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.250 ; -; 2.037 ; cache_line_sclk[0] ; cache_line_sclk[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.258 ; -; 2.048 ; cache_line_sdata[44] ; cache2_line_sdata[44] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.269 ; -; 2.107 ; fault_counter[5] ; fault_counter[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ; -; 2.107 ; cache_line_sdata[26] ; cache_line_sdata[26] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ; -; 2.107 ; cache_line_sdata[33] ; cache_line_sdata[33] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ; -; 2.107 ; cache_line_sdata[35] ; cache_line_sdata[35] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ; -; 2.108 ; cache_line_sdata[30] ; cache_line_sdata[30] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.329 ; -; 2.108 ; cache_line_sdata[34] ; cache_line_sdata[34] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.329 ; -; 2.110 ; cache2_line_sdata[45] ; signal_high_voltage[45]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.331 ; -; 2.116 ; i[6] ; i[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ; -; 2.116 ; i[16] ; i[16] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ; -; 2.116 ; fault_counter[6] ; fault_counter[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ; -; 2.116 ; cache_line_sdata[12] ; cache_line_sdata[12] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ; -; 2.116 ; cache_line_sdata[29] ; cache_line_sdata[29] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ; -; 2.117 ; i[13] ; i[13] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; i[23] ; i[23] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; fault_counter[13] ; fault_counter[13] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; cache_line_sdata[7] ; cache_line_sdata[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; cache_line_sdata[8] ; cache_line_sdata[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; cache_line_sdata[25] ; cache_line_sdata[25] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; -; 2.120 ; cache2_line_sdata[18] ; signal_high_voltage[18]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.341 ; -; 2.123 ; cache2_line_sdata[18] ; signal_low_voltage[18]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.344 ; -; 2.125 ; fault_counter[16] ; fault_counter[16] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.346 ; -; 2.126 ; i[7] ; i[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; i[8] ; i[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; i[15] ; i[15] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; i[17] ; i[17] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; i[18] ; i[18] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; i[25] ; i[25] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; fault_counter[15] ; fault_counter[15] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; fault_counter[8] ; fault_counter[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; fault_counter[3] ; fault_counter[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; fault_counter[7] ; fault_counter[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; fault_counter[17] ; fault_counter[17] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; fault_counter[18] ; fault_counter[18] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; fault_counter[25] ; fault_counter[25] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; cache_line_sdata[5] ; cache_line_sdata[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.126 ; cache_line_sdata[14] ; cache_line_sdata[14] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; -; 2.127 ; cache2_line_sdata[33] ; signal_low_voltage[33]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ; -; 2.127 ; i[5] ; i[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ; -; 2.127 ; fault_counter[23] ; fault_counter[23] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ; -; 2.127 ; cache_line_sdata[47] ; cache_line_sdata[47] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ; -; 2.133 ; cache2_line_sdata[33] ; signal_high_voltage[33]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.354 ; -; 2.133 ; cache_line_sdata[14] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.354 ; -; 2.134 ; i[3] ; i[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.355 ; -; 2.134 ; i[26] ; i[26] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.355 ; -; 2.134 ; i[27] ; i[27] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.355 ; -; 2.134 ; fault_counter[26] ; fault_counter[26] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.355 ; -; 2.135 ; cache2_line_sdata[5] ; signal_high_voltage[5]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.356 ; -; 2.135 ; is_high_voltage_time ; signal_high_voltage[14]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.356 ; -; 2.135 ; cache_line_sdata[10] ; cache_line_sdata[10] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.356 ; -; 2.136 ; cache2_line_sdata[5] ; signal_low_voltage[5]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.357 ; -; 2.136 ; cache_line_sdata[1] ; cache_line_sdata[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.357 ; -; 2.136 ; cache_line_sdata[46] ; cache_line_sdata[46] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.357 ; -; 2.137 ; cache_line_sdata[46] ; cache2_line_sdata[46] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.358 ; -; 2.137 ; cache_line_sdata[11] ; cache_line_sdata[11] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.358 ; -; 2.143 ; fault_flag[0][0] ; fault_flag[0][0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.364 ; -; 2.143 ; fault_counter[28] ; fault_counter[28] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.364 ; -; 2.144 ; fault_counter[27] ; fault_counter[27] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.365 ; -; 2.144 ; cache_line_sen[0] ; negedge_line_sen ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.365 ; -; 2.144 ; cache_line_sdata[40] ; cache_line_sdata[40] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.365 ; -; 2.146 ; cache2_line_sdata[35] ; signal_high_voltage[35]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.367 ; -; 2.146 ; cache2_line_sdata[29] ; signal_low_voltage[29]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.367 ; -; 2.146 ; cache_line_sdata[36] ; cache_line_sdata[36] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.367 ; -; 2.147 ; cache2_line_sdata[35] ; signal_low_voltage[35]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.368 ; -+-------+-------------------------+------------------------------+--------------+-------------+--------------+------------+------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'sys_clk' ; ++-------+-----------------------------------------+-----------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------------------------------+-----------------------------------------+--------------+-------------+--------------+------------+------------+ +; 1.386 ; tmp_cache_line_sdata[1] ; tmp_cache_line_sdata[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.607 ; +; 1.387 ; tmp_cache_line_sdata[3] ; tmp_cache_line_sdata[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.608 ; +; 1.396 ; cache_line_sclk[1] ; cache_line_sclk[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.617 ; +; 1.412 ; cache_line_sen[3] ; cache_line_sen[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.633 ; +; 1.424 ; cache_line_sen[1] ; cache_line_sen[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.645 ; +; 1.642 ; tmp_cache_line_sdata[2] ; tmp_cache_line_sdata[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.863 ; +; 1.653 ; tmp_cache_line_sdata[4] ; fiter_line_sdata ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.874 ; +; 1.655 ; cache_line_sclk[0] ; cache_line_sclk[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.876 ; +; 1.656 ; tmp_cache_line_sdata[0] ; tmp_cache_line_sdata[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.877 ; +; 1.659 ; cache2_line_sdata[21] ; signal_low_voltage[21]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.880 ; +; 1.662 ; cache2_line_sdata[13] ; signal_high_voltage[13]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.883 ; +; 1.662 ; cache2_line_sdata[14] ; signal_low_voltage[14]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.883 ; +; 1.662 ; cache_line_sen[0] ; cache_line_sen[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.883 ; +; 1.662 ; cache_line_sclk[2] ; cache_line_sclk[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.883 ; +; 1.664 ; cache_line_sdata[35] ; cache2_line_sdata[35] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.885 ; +; 1.666 ; cache2_line_sdata[7] ; signal_high_voltage[7]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.887 ; +; 1.667 ; cache2_line_sdata[14] ; signal_high_voltage[14]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.888 ; +; 1.671 ; cache2_line_sdata[17] ; signal_low_voltage[17]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.892 ; +; 1.678 ; cache2_line_sdata[16] ; signal_low_voltage[16]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.899 ; +; 1.679 ; cache2_line_sdata[27] ; signal_high_voltage[27]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.900 ; +; 1.679 ; cache2_line_sdata[19] ; signal_low_voltage[19]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.900 ; +; 1.681 ; cache2_line_sdata[22] ; signal_low_voltage[22]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.902 ; +; 1.682 ; cache2_line_sdata[27] ; signal_low_voltage[27]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.903 ; +; 1.685 ; cache2_line_sdata[22] ; signal_high_voltage[22]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.906 ; +; 1.685 ; cache2_line_sdata[25] ; signal_low_voltage[25]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.906 ; +; 1.686 ; cache2_line_sdata[16] ; signal_high_voltage[16]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.907 ; +; 1.686 ; cache2_line_sdata[38] ; signal_low_voltage[38]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.907 ; +; 1.687 ; cache2_line_sdata[38] ; signal_high_voltage[38]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.908 ; +; 1.748 ; cache_line_sclk[3] ; cache_line_sclk[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.969 ; +; 1.867 ; cache_enable_count_high_voltage_time[0] ; cache_enable_count_high_voltage_time[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.088 ; +; 1.875 ; cache_line_sen[4] ; negedge_line_sen ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.096 ; +; 1.898 ; cache_line_sdata[14] ; cache_line_sdata[14] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ; +; 1.898 ; cache_line_sdata[26] ; cache_line_sdata[26] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ; +; 1.898 ; cache_line_sdata[42] ; cache_line_sdata[42] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ; +; 1.899 ; cache_line_sdata[9] ; cache_line_sdata[9] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.120 ; +; 1.907 ; cache_line_sdata[20] ; cache_line_sdata[20] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.128 ; +; 1.907 ; cache_line_sdata[21] ; cache_line_sdata[21] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.128 ; +; 1.908 ; cache_line_sdata[4] ; cache_line_sdata[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.129 ; +; 1.908 ; cache_line_sdata[12] ; cache_line_sdata[12] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.129 ; +; 1.908 ; cache_line_sdata[19] ; cache_line_sdata[19] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.129 ; +; 1.908 ; cache_line_sdata[28] ; cache_line_sdata[28] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.129 ; +; 1.909 ; cache_line_sdata[22] ; cache_line_sdata[22] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.130 ; +; 1.916 ; cache_line_sdata[45] ; cache_line_sdata[45] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.137 ; +; 1.918 ; cache_line_sdata[1] ; cache_line_sdata[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.139 ; +; 1.918 ; cache_line_sdata[17] ; cache_line_sdata[17] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.139 ; +; 1.919 ; cache_line_sdata[0] ; cache_line_sdata[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.140 ; +; 1.920 ; cache2_line_sdata[31] ; signal_high_voltage[31]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.141 ; +; 1.922 ; cache_line_sdata[0] ; cache2_line_sdata[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.143 ; +; 1.923 ; cache2_line_sdata[20] ; signal_high_voltage[20]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.144 ; +; 1.924 ; cache_line_sdata[1] ; cache2_line_sdata[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.145 ; +; 1.925 ; cache2_line_sdata[20] ; signal_low_voltage[20]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.146 ; +; 1.925 ; cache2_line_sdata[31] ; signal_low_voltage[31]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.146 ; +; 1.929 ; cache_line_sdata[32] ; cache_line_sdata[32] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.150 ; +; 1.930 ; cache_line_sdata[32] ; cache2_line_sdata[32] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.151 ; +; 1.934 ; cache_line_sdata[31] ; cache_line_sdata[31] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.155 ; +; 1.935 ; cache2_line_sdata[26] ; signal_high_voltage[26]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.156 ; +; 1.939 ; cache2_line_sdata[29] ; signal_high_voltage[29]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.160 ; +; 1.940 ; cache2_line_sdata[26] ; signal_low_voltage[26]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.161 ; +; 1.940 ; cache2_line_sdata[29] ; signal_low_voltage[29]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.161 ; +; 1.941 ; cache2_line_sdata[28] ; signal_low_voltage[28]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.162 ; +; 1.947 ; cache2_line_sdata[30] ; signal_low_voltage[30]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.168 ; +; 1.955 ; cache2_line_sdata[46] ; signal_high_voltage[46]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.176 ; +; 1.958 ; cache2_line_sdata[42] ; signal_high_voltage[42]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.179 ; +; 2.013 ; cache2_line_sdata[8] ; signal_low_voltage[8]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.234 ; +; 2.017 ; cache2_line_sdata[8] ; signal_high_voltage[8]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.238 ; +; 2.107 ; cache_line_sdata[8] ; cache_line_sdata[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ; +; 2.107 ; cache_line_sdata[25] ; cache_line_sdata[25] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ; +; 2.107 ; cache_line_sdata[30] ; cache_line_sdata[30] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ; +; 2.111 ; filter_line_sen ; filter_line_sen ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.332 ; +; 2.116 ; i[6] ; i[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ; +; 2.116 ; i[16] ; i[16] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ; +; 2.116 ; fault_counter[16] ; fault_counter[16] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ; +; 2.116 ; fault_counter[6] ; fault_counter[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ; +; 2.117 ; i[13] ; i[13] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; i[23] ; i[23] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; fault_counter[13] ; fault_counter[13] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; fault_counter[23] ; fault_counter[23] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; cache_line_sdata[2] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; cache_line_sdata[23] ; cache_line_sdata[23] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; cache_line_sdata[34] ; cache_line_sdata[34] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; cache_line_sdata[36] ; cache_line_sdata[36] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; +; 2.117 ; cache_line_sdata[44] ; cache_line_sdata[44] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ; +; 2.123 ; cache2_line_sdata[6] ; signal_low_voltage[6]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.344 ; +; 2.126 ; i[5] ; i[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; i[7] ; i[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; i[8] ; i[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; i[15] ; i[15] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; i[17] ; i[17] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; i[18] ; i[18] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; i[25] ; i[25] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; fault_counter[15] ; fault_counter[15] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; fault_counter[8] ; fault_counter[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; fault_counter[7] ; fault_counter[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; fault_counter[17] ; fault_counter[17] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; fault_counter[18] ; fault_counter[18] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; fault_counter[25] ; fault_counter[25] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; fault_counter[26] ; fault_counter[26] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ; +; 2.127 ; cache_line_sdata[7] ; cache_line_sdata[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ; +; 2.127 ; cache_line_sdata[24] ; cache_line_sdata[24] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ; +; 2.127 ; cache_line_sdata[33] ; cache_line_sdata[33] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ; ++-------+-----------------------------------------+-----------------------------------------+--------------+-------------+--------------+------------+------------+ +-------------------------------------------------------------------+ @@ -650,26 +649,26 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Thu Nov 11 17:04:09 2021 -Info: Command: quartus_sta PF1 -c PF1 + Info: Processing started: Sun Dec 26 13:11:42 2021 +Info: Command: quartus_sta valveboard_firmware -c valveboard_firmware Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected +Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Critical Warning (332012): Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name sys_clk sys_clk Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -10.907 +Info (332146): Worst-case setup slack is -11.085 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -10.907 -2294.822 sys_clk + Info (332119): -11.085 -2239.564 sys_clk Info (332146): Worst-case hold slack is 1.386 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== @@ -684,9 +683,9 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 4687 megabytes - Info: Processing ended: Thu Nov 11 17:04:10 2021 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:01 + Info: Peak virtual memory: 4662 megabytes + Info: Processing ended: Sun Dec 26 13:11:44 2021 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 diff --git a/firmware/PF1.sta.summary b/firmware/output_files/valveboard_firmware.sta.summary similarity index 91% rename from firmware/PF1.sta.summary rename to firmware/output_files/valveboard_firmware.sta.summary index 4b528db..92d4852 100644 --- a/firmware/PF1.sta.summary +++ b/firmware/output_files/valveboard_firmware.sta.summary @@ -3,8 +3,8 @@ Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'sys_clk' -Slack : -10.907 -TNS : -2294.822 +Slack : -11.085 +TNS : -2239.564 Type : Hold 'sys_clk' Slack : 1.386 diff --git a/firmware/simulation/modelsim/PF1.sft b/firmware/simulation/modelsim/PF1.sft deleted file mode 100644 index 1af44c8..0000000 --- a/firmware/simulation/modelsim/PF1.sft +++ /dev/null @@ -1,4 +0,0 @@ -set tool_name "ModelSim-Altera (Verilog)" -set corner_file_list { - {{"Slow Model"} {PF1.vo PF1_v.sdo}} -} diff --git a/firmware/simulation/modelsim/PF1.vo b/firmware/simulation/modelsim/PF1.vo deleted file mode 100644 index e1d3404..0000000 --- a/firmware/simulation/modelsim/PF1.vo +++ /dev/null @@ -1,18542 +0,0 @@ -// Copyright (C) 2020 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions -// and other software and tools, and any partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License -// Subscription Agreement, the Intel Quartus Prime License Agreement, -// the Intel FPGA IP License Agreement, or other applicable license -// agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by -// Intel and sold by Intel or its authorized distributors. Please -// refer to the applicable agreement for further details, at -// https://fpgasoftware.intel.com/eula. - -// VENDOR "Altera" -// PROGRAM "Quartus Prime" -// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" - -// DATE "11/11/2021 17:04:11" - -// -// Device: Altera EPM1270T144C5 Package TQFP144 -// - -// -// This Verilog file should be used for ModelSim-Altera (Verilog) only -// - -`timescale 1 ps/ 1 ps - -module PF1 ( - sys_clk, - rst_n, - line_sclk, - line_sen, - line_sdata, - signal_high_voltage, - signal_low_voltage); -input sys_clk; -input rst_n; -input line_sclk; -input line_sen; -input line_sdata; -output [47:0] signal_high_voltage; -output [47:0] signal_low_voltage; - -// Design Ports Information - - -wire gnd; -wire vcc; -wire unknown; - -assign gnd = 1'b0; -assign vcc = 1'b1; -assign unknown = 1'bx; - -tri1 devclrn; -tri1 devpor; -tri1 devoe; -// synopsys translate_off -initial $sdf_annotate("PF1_v.sdo"); -// synopsys translate_on - -wire \sys_clk~combout ; -wire \rst_n~combout ; -wire \line_sclk~combout ; -wire \Equal0~0 ; -wire \Equal0~1 ; -wire \fault_counter[0]~23 ; -wire \fault_counter[1]~25 ; -wire \fault_counter[1]~25COUT1_71 ; -wire \fault_counter[2]~27 ; -wire \fault_counter[2]~27COUT1_72 ; -wire \fault_counter[3]~29 ; -wire \fault_counter[3]~29COUT1_73 ; -wire \fault_counter[4]~31 ; -wire \fault_counter[4]~31COUT1_74 ; -wire \fault_counter[5]~33 ; -wire \fault_counter[6]~35 ; -wire \fault_counter[6]~35COUT1_75 ; -wire \fault_counter[7]~37 ; -wire \fault_counter[7]~37COUT1_76 ; -wire \fault_counter[8]~21 ; -wire \fault_counter[8]~21COUT1_77 ; -wire \fault_counter[9]~19 ; -wire \fault_counter[9]~19COUT1_78 ; -wire \fault_counter[10]~41 ; -wire \fault_counter[11]~39 ; -wire \fault_counter[11]~39COUT1_79 ; -wire \fault_counter[12]~13 ; -wire \fault_counter[12]~13COUT1_80 ; -wire \fault_counter[13]~11 ; -wire \fault_counter[13]~11COUT1_81 ; -wire \fault_counter[14]~15 ; -wire \fault_counter[14]~15COUT1_82 ; -wire \fault_counter[15]~17 ; -wire \fault_counter[16]~9 ; -wire \fault_counter[16]~9COUT1_83 ; -wire \fault_counter[17]~43 ; -wire \fault_counter[17]~43COUT1_84 ; -wire \fault_counter[18]~45 ; -wire \fault_counter[18]~45COUT1_85 ; -wire \fault_counter[19]~47 ; -wire \fault_counter[19]~47COUT1_86 ; -wire \fault_counter[20]~5 ; -wire \fault_counter[21]~7 ; -wire \fault_counter[21]~7COUT1_87 ; -wire \fault_counter[22]~49 ; -wire \fault_counter[22]~49COUT1_88 ; -wire \fault_counter[23]~51 ; -wire \fault_counter[23]~51COUT1_89 ; -wire \fault_counter[24]~3 ; -wire \fault_counter[24]~3COUT1_90 ; -wire \fault_counter[25]~53 ; -wire \fault_counter[26]~55 ; -wire \fault_counter[26]~55COUT1_91 ; -wire \fault_counter[27]~57 ; -wire \fault_counter[27]~57COUT1_92 ; -wire \fault_counter[28]~59 ; -wire \fault_counter[28]~59COUT1_93 ; -wire \fault_counter[29]~62 ; -wire \fault_counter[29]~62COUT1_94 ; -wire \fault_counter[30]~64 ; -wire \fault_counter[26]~60_combout ; -wire \fault_counter[26]~67_combout ; -wire \fault_flag~7_combout ; -wire \LessThan2~8_combout ; -wire \LessThan2~9_combout ; -wire \LessThan2~6_combout ; -wire \LessThan2~2_combout ; -wire \LessThan2~4_combout ; -wire \LessThan2~3_combout ; -wire \LessThan2~5_combout ; -wire \LessThan2~0_combout ; -wire \LessThan2~1_combout ; -wire \LessThan2~7_combout ; -wire \fault_counter[26]~68_combout ; -wire \fault_counter[26]~69_combout ; -wire \fault_flag~10_combout ; -wire \fault_flag~6_combout ; -wire \fault_flag~2_combout ; -wire \fault_flag~3_combout ; -wire \fault_flag~4_combout ; -wire \fault_flag~5_combout ; -wire \fault_flag~8_combout ; -wire \fault_flag~9_combout ; -wire \fault_flag[1][0]~regout ; -wire \line_sen~combout ; -wire \Equal1~0 ; -wire \Equal1~1 ; -wire \Equal2~0 ; -wire \Equal2~1 ; -wire \filter_line_sen~regout ; -wire \negedge_line_sen~regout ; -wire \i[26]~69_combout ; -wire \i[0]~9 ; -wire \i[1]~11 ; -wire \i[1]~11COUT1_71 ; -wire \i[2]~13 ; -wire \i[2]~13COUT1_72 ; -wire \i[3]~15 ; -wire \i[3]~15COUT1_73 ; -wire \posedge_line_sclk~regout ; -wire \i[26]~68_combout ; -wire \i[4]~5 ; -wire \i[4]~5COUT1_74 ; -wire \i[5]~7 ; -wire \i[6]~17 ; -wire \i[6]~17COUT1_75 ; -wire \i[7]~19 ; -wire \i[7]~19COUT1_76 ; -wire \i[8]~29 ; -wire \i[8]~29COUT1_77 ; -wire \i[9]~31 ; -wire \i[9]~31COUT1_78 ; -wire \i[10]~21 ; -wire \i[11]~23 ; -wire \i[11]~23COUT1_79 ; -wire \i[12]~25 ; -wire \i[12]~25COUT1_80 ; -wire \i[13]~27 ; -wire \i[13]~27COUT1_81 ; -wire \i[14]~33 ; -wire \i[14]~33COUT1_82 ; -wire \i[15]~35 ; -wire \i[16]~37 ; -wire \i[16]~37COUT1_83 ; -wire \recv_complete~4_combout ; -wire \i[17]~39 ; -wire \i[17]~39COUT1_84 ; -wire \i[18]~41 ; -wire \i[18]~41COUT1_85 ; -wire \i[19]~43 ; -wire \i[19]~43COUT1_86 ; -wire \i[20]~45 ; -wire \recv_complete~5_combout ; -wire \recv_complete~1_combout ; -wire \recv_complete~2_combout ; -wire \recv_complete~3_combout ; -wire \i[21]~47 ; -wire \i[21]~47COUT1_87 ; -wire \i[22]~49 ; -wire \i[22]~49COUT1_88 ; -wire \i[23]~51 ; -wire \i[23]~51COUT1_89 ; -wire \i[24]~53 ; -wire \i[24]~53COUT1_90 ; -wire \i[25]~55 ; -wire \i[26]~57 ; -wire \i[26]~57COUT1_91 ; -wire \i[27]~59 ; -wire \i[27]~59COUT1_92 ; -wire \i[28]~61 ; -wire \i[28]~61COUT1_93 ; -wire \i[29]~63 ; -wire \i[29]~63COUT1_94 ; -wire \i[30]~65 ; -wire \recv_complete~7_combout ; -wire \recv_complete~6_combout ; -wire \recv_complete~8_combout ; -wire \recv_complete~9_combout ; -wire \recv_complete~0_combout ; -wire \fault_flag~0_combout ; -wire \fault_flag[0][0]~regout ; -wire \cnt_for_high_voltage_time~128_combout ; -wire \line_sdata~combout ; -wire \fiter_line_sdata~regout ; -wire \Decoder0~65 ; -wire \Decoder0~101_combout ; -wire \recv_complete~10_combout ; -wire \recv_complete~11_combout ; -wire \cache2_line_sdata[45]~50_combout ; -wire \enable_count_high_voltage_time~regout ; -wire posedge_enable_count_high_voltage_time; -wire \Add2~0_combout ; -wire \cnt_for_high_voltage_time[18]~129_combout ; -wire \Add2~2 ; -wire \Add2~155_combout ; -wire \Add2~157 ; -wire \Add2~157COUT1_161 ; -wire \Add2~150_combout ; -wire \Add2~152 ; -wire \Add2~152COUT1_162 ; -wire \Add2~145_combout ; -wire \Add2~147 ; -wire \Add2~147COUT1_163 ; -wire \Add2~140_combout ; -wire \Add2~142 ; -wire \Add2~142COUT1_164 ; -wire \Add2~135_combout ; -wire \Add2~137 ; -wire \Add2~130_combout ; -wire \Add2~132 ; -wire \Add2~132COUT1_165 ; -wire \Add2~125_combout ; -wire \Add2~127 ; -wire \Add2~127COUT1_166 ; -wire \Add2~120_combout ; -wire \Add2~122 ; -wire \Add2~122COUT1_167 ; -wire \Add2~115_combout ; -wire \Add2~117 ; -wire \Add2~117COUT1_168 ; -wire \Add2~110_combout ; -wire \Add2~112 ; -wire \Add2~105_combout ; -wire \Equal4~6_combout ; -wire \Add2~107 ; -wire \Add2~107COUT1_169 ; -wire \Add2~100_combout ; -wire \Add2~102 ; -wire \Add2~102COUT1_170 ; -wire \Add2~95_combout ; -wire \Add2~97 ; -wire \Add2~97COUT1_171 ; -wire \Add2~90_combout ; -wire \Add2~92 ; -wire \Add2~92COUT1_172 ; -wire \Add2~85_combout ; -wire \Equal4~5_combout ; -wire \Equal4~7_combout ; -wire \Equal4~8_combout ; -wire \Add2~87 ; -wire \Add2~80_combout ; -wire \Add2~82 ; -wire \Add2~82COUT1_173 ; -wire \Add2~75_combout ; -wire \Add2~77 ; -wire \Add2~77COUT1_174 ; -wire \Add2~70_combout ; -wire \Add2~72 ; -wire \Add2~72COUT1_175 ; -wire \Add2~65_combout ; -wire \Equal4~3_combout ; -wire \Add2~67 ; -wire \Add2~67COUT1_176 ; -wire \Add2~60_combout ; -wire \Add2~62 ; -wire \Add2~55_combout ; -wire \Add2~57 ; -wire \Add2~57COUT1_177 ; -wire \Add2~50_combout ; -wire \Add2~52 ; -wire \Add2~52COUT1_178 ; -wire \Add2~45_combout ; -wire \Add2~47 ; -wire \Add2~47COUT1_179 ; -wire \Add2~40_combout ; -wire \Add2~42 ; -wire \Add2~42COUT1_180 ; -wire \Add2~35_combout ; -wire \Add2~37 ; -wire \Add2~30_combout ; -wire \Add2~32 ; -wire \Add2~32COUT1_181 ; -wire \Add2~25_combout ; -wire \Equal4~1_combout ; -wire \Equal4~2_combout ; -wire \Add2~27 ; -wire \Add2~27COUT1_182 ; -wire \Add2~20_combout ; -wire \Add2~22 ; -wire \Add2~22COUT1_183 ; -wire \Add2~15_combout ; -wire \Add2~17 ; -wire \Add2~17COUT1_184 ; -wire \Add2~10_combout ; -wire \Add2~12 ; -wire \Add2~5_combout ; -wire \Equal4~0_combout ; -wire \Equal4~4_combout ; -wire \Equal4~9_combout ; -wire \Equal4~10_combout ; -wire \is_high_voltage_time~regout ; -wire \signal_high_voltage[0]~reg0_regout ; -wire \Decoder0~66_combout ; -wire \signal_high_voltage[1]~reg0_regout ; -wire \Decoder0~64_combout ; -wire \always3~0_combout ; -wire \Decoder0~68_combout ; -wire \Decoder0~102_combout ; -wire \signal_high_voltage[2]~reg0_regout ; -wire \Decoder0~69_combout ; -wire \Decoder0~103_combout ; -wire \signal_high_voltage[3]~reg0_regout ; -wire \Decoder0~70_combout ; -wire \Decoder0~71_combout ; -wire \signal_high_voltage[4]~reg0_regout ; -wire \Decoder0~72_combout ; -wire \Decoder0~104_combout ; -wire \signal_high_voltage[5]~reg0_regout ; -wire \Decoder0~73_combout ; -wire \Decoder0~105_combout ; -wire \signal_high_voltage[6]~reg0_regout ; -wire \Decoder0~106_combout ; -wire \signal_high_voltage[7]~reg0_regout ; -wire \Decoder0~107_combout ; -wire \signal_high_voltage[8]~reg0_regout ; -wire \Decoder0~108_combout ; -wire \signal_high_voltage[9]~reg0_regout ; -wire \Decoder0~74_combout ; -wire \Decoder0~109_combout ; -wire \signal_high_voltage[10]~reg0_regout ; -wire \Decoder0~110_combout ; -wire \signal_high_voltage[11]~reg0_regout ; -wire \Decoder0~76_combout ; -wire \signal_high_voltage[12]~reg0_regout ; -wire \Decoder0~111_combout ; -wire \signal_high_voltage[13]~reg0_regout ; -wire \Decoder0~77_combout ; -wire \signal_high_voltage[14]~reg0_regout ; -wire \Decoder0~112_combout ; -wire \signal_high_voltage[15]~reg0_regout ; -wire \Decoder0~78_combout ; -wire \Decoder0~113_combout ; -wire \signal_high_voltage[16]~reg0_regout ; -wire \Decoder0~79_combout ; -wire \Decoder0~80_combout ; -wire \signal_high_voltage[17]~reg0_regout ; -wire \Decoder0~114_combout ; -wire \signal_high_voltage[18]~reg0_regout ; -wire \Decoder0~67_combout ; -wire \Decoder0~81_combout ; -wire \signal_high_voltage[19]~reg0_regout ; -wire \Decoder0~82_combout ; -wire \Decoder0~115_combout ; -wire \Decoder0~83_combout ; -wire \signal_high_voltage[20]~reg0_regout ; -wire \Decoder0~84_combout ; -wire \signal_high_voltage[21]~reg0_regout ; -wire \Decoder0~116_combout ; -wire \signal_high_voltage[22]~reg0_regout ; -wire \Decoder0~85_combout ; -wire \signal_high_voltage[23]~reg0_regout ; -wire \Decoder0~86_combout ; -wire \signal_high_voltage[24]~reg0_regout ; -wire \Decoder0~75_combout ; -wire \Decoder0~87_combout ; -wire \signal_high_voltage[25]~reg0_regout ; -wire \Decoder0~117_combout ; -wire \signal_high_voltage[26]~reg0_regout ; -wire \Decoder0~88_combout ; -wire \signal_high_voltage[27]~reg0_regout ; -wire \Decoder0~89_combout ; -wire \signal_high_voltage[28]~reg0_regout ; -wire \Decoder0~90_combout ; -wire \signal_high_voltage[29]~reg0_regout ; -wire \Decoder0~91_combout ; -wire \signal_high_voltage[30]~reg0_regout ; -wire \Decoder0~92_combout ; -wire \signal_high_voltage[31]~reg0_regout ; -wire \Decoder0~118_combout ; -wire \signal_high_voltage[32]~reg0_regout ; -wire \Decoder0~93_combout ; -wire \signal_high_voltage[33]~reg0_regout ; -wire \Decoder0~119_combout ; -wire \signal_high_voltage[34]~reg0_regout ; -wire \Decoder0~120_combout ; -wire \signal_high_voltage[35]~reg0_regout ; -wire \Decoder0~94_combout ; -wire \Decoder0~95_combout ; -wire \signal_high_voltage[36]~reg0_regout ; -wire \Decoder0~121_combout ; -wire \signal_high_voltage[37]~reg0_regout ; -wire \Decoder0~122_combout ; -wire \signal_high_voltage[38]~reg0_regout ; -wire \Decoder0~123_combout ; -wire \signal_high_voltage[39]~reg0_regout ; -wire \Decoder0~96_combout ; -wire \signal_high_voltage[40]~reg0_regout ; -wire \Decoder0~124_combout ; -wire \signal_high_voltage[41]~reg0_regout ; -wire \Decoder0~125_combout ; -wire \signal_high_voltage[42]~reg0_regout ; -wire \Decoder0~126_combout ; -wire \signal_high_voltage[43]~reg0_regout ; -wire \Decoder0~97_combout ; -wire \signal_high_voltage[44]~reg0_regout ; -wire \Decoder0~98_combout ; -wire \signal_high_voltage[45]~reg0_regout ; -wire \Decoder0~99_combout ; -wire \signal_high_voltage[46]~reg0_regout ; -wire \Decoder0~100_combout ; -wire \signal_high_voltage[47]~reg0_regout ; -wire \signal_low_voltage[0]~reg0_regout ; -wire \signal_low_voltage[1]~reg0_regout ; -wire \signal_low_voltage[2]~reg0_regout ; -wire \signal_low_voltage[3]~reg0_regout ; -wire \signal_low_voltage[4]~reg0_regout ; -wire \signal_low_voltage[5]~reg0_regout ; -wire \signal_low_voltage[6]~reg0_regout ; -wire \signal_low_voltage[7]~reg0_regout ; -wire \signal_low_voltage[8]~reg0_regout ; -wire \signal_low_voltage[9]~reg0_regout ; -wire \signal_low_voltage[10]~reg0_regout ; -wire \signal_low_voltage[11]~reg0_regout ; -wire \signal_low_voltage[12]~reg0_regout ; -wire \signal_low_voltage[13]~reg0_regout ; -wire \signal_low_voltage[14]~reg0_regout ; -wire \signal_low_voltage[15]~reg0_regout ; -wire \signal_low_voltage[16]~reg0_regout ; -wire \signal_low_voltage[17]~reg0_regout ; -wire \signal_low_voltage[18]~reg0_regout ; -wire \signal_low_voltage[19]~reg0_regout ; -wire \signal_low_voltage[20]~reg0_regout ; -wire \signal_low_voltage[21]~reg0_regout ; -wire \signal_low_voltage[22]~reg0_regout ; -wire \signal_low_voltage[23]~reg0_regout ; -wire \signal_low_voltage[24]~reg0_regout ; -wire \signal_low_voltage[25]~reg0_regout ; -wire \signal_low_voltage[26]~reg0_regout ; -wire \signal_low_voltage[27]~reg0_regout ; -wire \signal_low_voltage[28]~reg0_regout ; -wire \signal_low_voltage[29]~reg0_regout ; -wire \signal_low_voltage[30]~reg0_regout ; -wire \signal_low_voltage[31]~reg0_regout ; -wire \signal_low_voltage[32]~reg0_regout ; -wire \signal_low_voltage[33]~reg0_regout ; -wire \signal_low_voltage[34]~reg0_regout ; -wire \signal_low_voltage[35]~reg0_regout ; -wire \signal_low_voltage[36]~reg0_regout ; -wire \signal_low_voltage[37]~reg0_regout ; -wire \signal_low_voltage[38]~reg0_regout ; -wire \signal_low_voltage[39]~reg0_regout ; -wire \signal_low_voltage[40]~reg0_regout ; -wire \signal_low_voltage[41]~reg0_regout ; -wire \signal_low_voltage[42]~reg0_regout ; -wire \signal_low_voltage[43]~reg0_regout ; -wire \signal_low_voltage[44]~reg0_regout ; -wire \signal_low_voltage[45]~reg0_regout ; -wire \signal_low_voltage[46]~reg0_regout ; -wire \signal_low_voltage[47]~reg0_regout ; -wire [47:0] cache2_line_sdata; -wire [1:0] cache_enable_count_high_voltage_time; -wire [31:0] i; -wire [4:0] cache_line_sen; -wire [31:0] fault_counter; -wire [4:0] cache_line_sclk; -wire [47:0] cache_line_sdata; -wire [31:0] cnt_for_high_voltage_time; -wire [4:0] tmp_cache_line_sdata; - - -// Location: PIN_18, I/O Standard: 3.3-V LVTTL, Current Strength: Default -maxii_io \sys_clk~I ( - .datain(gnd), - .oe(gnd), - .combout(\sys_clk~combout ), - .padio(sys_clk)); -// synopsys translate_off -defparam \sys_clk~I .operation_mode = "input"; -// synopsys translate_on - -// Location: PIN_37, I/O Standard: 3.3-V LVTTL, Current Strength: Default -maxii_io \rst_n~I ( - .datain(gnd), - .oe(gnd), - .combout(\rst_n~combout ), - .padio(rst_n)); -// synopsys translate_off -defparam \rst_n~I .operation_mode = "input"; -// synopsys translate_on - -// Location: PIN_40, I/O Standard: 3.3-V LVTTL, Current Strength: Default -maxii_io \line_sclk~I ( - .datain(gnd), - .oe(gnd), - .combout(\line_sclk~combout ), - .padio(line_sclk)); -// synopsys translate_off -defparam \line_sclk~I .operation_mode = "input"; -// synopsys translate_on - -// Location: LC_X2_Y7_N1 -maxii_lcell \cache_line_sclk[0] ( -// Equation(s): -// \Equal0~1 = (\line_sclk~combout & (((cache_line_sclk[0] & \Equal0~0 )))) -// cache_line_sclk[0] = DFFEAS(\Equal0~1 , GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , \line_sclk~combout , , , VCC) - - .clk(\sys_clk~combout ), - .dataa(\line_sclk~combout ), - .datab(vcc), - .datac(\line_sclk~combout ), - .datad(\Equal0~0 ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal0~1 ), - .regout(cache_line_sclk[0]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sclk[0] .lut_mask = "a000"; -defparam \cache_line_sclk[0] .operation_mode = "normal"; -defparam \cache_line_sclk[0] .output_mode = "reg_and_comb"; -defparam \cache_line_sclk[0] .register_cascade_mode = "off"; -defparam \cache_line_sclk[0] .sum_lutc_input = "qfbk"; -defparam \cache_line_sclk[0] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X1_Y7_N7 -maxii_lcell \cache_line_sclk[1] ( -// Equation(s): -// cache_line_sclk[1] = DFFEAS((((cache_line_sclk[0]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(cache_line_sclk[0]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sclk[1]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sclk[1] .lut_mask = "ff00"; -defparam \cache_line_sclk[1] .operation_mode = "normal"; -defparam \cache_line_sclk[1] .output_mode = "reg_only"; -defparam \cache_line_sclk[1] .register_cascade_mode = "off"; -defparam \cache_line_sclk[1] .sum_lutc_input = "datac"; -defparam \cache_line_sclk[1] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X1_Y7_N8 -maxii_lcell \cache_line_sclk[2] ( -// Equation(s): -// cache_line_sclk[2] = DFFEAS(GND, GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , cache_line_sclk[1], , , VCC) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(cache_line_sclk[1]), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sclk[2]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sclk[2] .lut_mask = "0000"; -defparam \cache_line_sclk[2] .operation_mode = "normal"; -defparam \cache_line_sclk[2] .output_mode = "reg_only"; -defparam \cache_line_sclk[2] .register_cascade_mode = "off"; -defparam \cache_line_sclk[2] .sum_lutc_input = "datac"; -defparam \cache_line_sclk[2] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X1_Y7_N6 -maxii_lcell \cache_line_sclk[3] ( -// Equation(s): -// cache_line_sclk[3] = DFFEAS((((cache_line_sclk[2]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(cache_line_sclk[2]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sclk[3]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sclk[3] .lut_mask = "ff00"; -defparam \cache_line_sclk[3] .operation_mode = "normal"; -defparam \cache_line_sclk[3] .output_mode = "reg_only"; -defparam \cache_line_sclk[3] .register_cascade_mode = "off"; -defparam \cache_line_sclk[3] .sum_lutc_input = "datac"; -defparam \cache_line_sclk[3] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X1_Y7_N0 -maxii_lcell \cache_line_sclk[4] ( -// Equation(s): -// \Equal0~0 = (cache_line_sclk[3] & (cache_line_sclk[1] & (!cache_line_sclk[4] & cache_line_sclk[2]))) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sclk[3]), - .datab(cache_line_sclk[1]), - .datac(cache_line_sclk[3]), - .datad(cache_line_sclk[2]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal0~0 ), - .regout(cache_line_sclk[4]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sclk[4] .lut_mask = "0800"; -defparam \cache_line_sclk[4] .operation_mode = "normal"; -defparam \cache_line_sclk[4] .output_mode = "comb_only"; -defparam \cache_line_sclk[4] .register_cascade_mode = "off"; -defparam \cache_line_sclk[4] .sum_lutc_input = "qfbk"; -defparam \cache_line_sclk[4] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X3_Y7_N4 -maxii_lcell \fault_counter[0] ( -// Equation(s): -// fault_counter[0] = DFFEAS(((!fault_counter[0])), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , \Equal0~1 , ) -// \fault_counter[0]~23 = CARRY(((fault_counter[0]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[0]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[0]), - .cout(\fault_counter[0]~23 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[0] .lut_mask = "33cc"; -defparam \fault_counter[0] .operation_mode = "arithmetic"; -defparam \fault_counter[0] .output_mode = "reg_only"; -defparam \fault_counter[0] .register_cascade_mode = "off"; -defparam \fault_counter[0] .sum_lutc_input = "datac"; -defparam \fault_counter[0] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X3_Y7_N5 -maxii_lcell \fault_counter[1] ( -// Equation(s): -// fault_counter[1] = DFFEAS(fault_counter[1] $ ((((\fault_counter[0]~23 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , \Equal0~1 , ) -// \fault_counter[1]~25 = CARRY(((!\fault_counter[0]~23 )) # (!fault_counter[1])) -// \fault_counter[1]~25COUT1_71 = CARRY(((!\fault_counter[0]~23 )) # (!fault_counter[1])) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[1]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[0]~23 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[1]), - .cout(), - .cout0(\fault_counter[1]~25 ), - .cout1(\fault_counter[1]~25COUT1_71 )); -// synopsys translate_off -defparam \fault_counter[1] .cin_used = "true"; -defparam \fault_counter[1] .lut_mask = "5a5f"; -defparam \fault_counter[1] .operation_mode = "arithmetic"; -defparam \fault_counter[1] .output_mode = "reg_only"; -defparam \fault_counter[1] .register_cascade_mode = "off"; -defparam \fault_counter[1] .sum_lutc_input = "cin"; -defparam \fault_counter[1] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X3_Y7_N6 -maxii_lcell \fault_counter[2] ( -// Equation(s): -// fault_counter[2] = DFFEAS(fault_counter[2] $ ((((!(!\fault_counter[0]~23 & \fault_counter[1]~25 ) # (\fault_counter[0]~23 & \fault_counter[1]~25COUT1_71 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[2]~27 = CARRY((fault_counter[2] & ((!\fault_counter[1]~25 )))) -// \fault_counter[2]~27COUT1_72 = CARRY((fault_counter[2] & ((!\fault_counter[1]~25COUT1_71 )))) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[2]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[0]~23 ), - .cin0(\fault_counter[1]~25 ), - .cin1(\fault_counter[1]~25COUT1_71 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[2]), - .cout(), - .cout0(\fault_counter[2]~27 ), - .cout1(\fault_counter[2]~27COUT1_72 )); -// synopsys translate_off -defparam \fault_counter[2] .cin0_used = "true"; -defparam \fault_counter[2] .cin1_used = "true"; -defparam \fault_counter[2] .cin_used = "true"; -defparam \fault_counter[2] .lut_mask = "a50a"; -defparam \fault_counter[2] .operation_mode = "arithmetic"; -defparam \fault_counter[2] .output_mode = "reg_only"; -defparam \fault_counter[2] .register_cascade_mode = "off"; -defparam \fault_counter[2] .sum_lutc_input = "cin"; -defparam \fault_counter[2] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X3_Y7_N7 -maxii_lcell \fault_counter[3] ( -// Equation(s): -// fault_counter[3] = DFFEAS((fault_counter[3] $ (((!\fault_counter[0]~23 & \fault_counter[2]~27 ) # (\fault_counter[0]~23 & \fault_counter[2]~27COUT1_72 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[3]~29 = CARRY(((!\fault_counter[2]~27 ) # (!fault_counter[3]))) -// \fault_counter[3]~29COUT1_73 = CARRY(((!\fault_counter[2]~27COUT1_72 ) # (!fault_counter[3]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[3]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[0]~23 ), - .cin0(\fault_counter[2]~27 ), - .cin1(\fault_counter[2]~27COUT1_72 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[3]), - .cout(), - .cout0(\fault_counter[3]~29 ), - .cout1(\fault_counter[3]~29COUT1_73 )); -// synopsys translate_off -defparam \fault_counter[3] .cin0_used = "true"; -defparam \fault_counter[3] .cin1_used = "true"; -defparam \fault_counter[3] .cin_used = "true"; -defparam \fault_counter[3] .lut_mask = "3c3f"; -defparam \fault_counter[3] .operation_mode = "arithmetic"; -defparam \fault_counter[3] .output_mode = "reg_only"; -defparam \fault_counter[3] .register_cascade_mode = "off"; -defparam \fault_counter[3] .sum_lutc_input = "cin"; -defparam \fault_counter[3] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X3_Y7_N8 -maxii_lcell \fault_counter[4] ( -// Equation(s): -// fault_counter[4] = DFFEAS(fault_counter[4] $ ((((!(!\fault_counter[0]~23 & \fault_counter[3]~29 ) # (\fault_counter[0]~23 & \fault_counter[3]~29COUT1_73 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[4]~31 = CARRY((fault_counter[4] & ((!\fault_counter[3]~29 )))) -// \fault_counter[4]~31COUT1_74 = CARRY((fault_counter[4] & ((!\fault_counter[3]~29COUT1_73 )))) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[4]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[0]~23 ), - .cin0(\fault_counter[3]~29 ), - .cin1(\fault_counter[3]~29COUT1_73 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[4]), - .cout(), - .cout0(\fault_counter[4]~31 ), - .cout1(\fault_counter[4]~31COUT1_74 )); -// synopsys translate_off -defparam \fault_counter[4] .cin0_used = "true"; -defparam \fault_counter[4] .cin1_used = "true"; -defparam \fault_counter[4] .cin_used = "true"; -defparam \fault_counter[4] .lut_mask = "a50a"; -defparam \fault_counter[4] .operation_mode = "arithmetic"; -defparam \fault_counter[4] .output_mode = "reg_only"; -defparam \fault_counter[4] .register_cascade_mode = "off"; -defparam \fault_counter[4] .sum_lutc_input = "cin"; -defparam \fault_counter[4] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X3_Y7_N9 -maxii_lcell \fault_counter[5] ( -// Equation(s): -// fault_counter[5] = DFFEAS((fault_counter[5] $ (((!\fault_counter[0]~23 & \fault_counter[4]~31 ) # (\fault_counter[0]~23 & \fault_counter[4]~31COUT1_74 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[5]~33 = CARRY(((!\fault_counter[4]~31COUT1_74 ) # (!fault_counter[5]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[5]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[0]~23 ), - .cin0(\fault_counter[4]~31 ), - .cin1(\fault_counter[4]~31COUT1_74 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[5]), - .cout(\fault_counter[5]~33 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[5] .cin0_used = "true"; -defparam \fault_counter[5] .cin1_used = "true"; -defparam \fault_counter[5] .cin_used = "true"; -defparam \fault_counter[5] .lut_mask = "3c3f"; -defparam \fault_counter[5] .operation_mode = "arithmetic"; -defparam \fault_counter[5] .output_mode = "reg_only"; -defparam \fault_counter[5] .register_cascade_mode = "off"; -defparam \fault_counter[5] .sum_lutc_input = "cin"; -defparam \fault_counter[5] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N0 -maxii_lcell \fault_counter[6] ( -// Equation(s): -// fault_counter[6] = DFFEAS((fault_counter[6] $ ((!\fault_counter[5]~33 ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , \Equal0~1 , ) -// \fault_counter[6]~35 = CARRY(((fault_counter[6] & !\fault_counter[5]~33 ))) -// \fault_counter[6]~35COUT1_75 = CARRY(((fault_counter[6] & !\fault_counter[5]~33 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[6]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[5]~33 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[6]), - .cout(), - .cout0(\fault_counter[6]~35 ), - .cout1(\fault_counter[6]~35COUT1_75 )); -// synopsys translate_off -defparam \fault_counter[6] .cin_used = "true"; -defparam \fault_counter[6] .lut_mask = "c30c"; -defparam \fault_counter[6] .operation_mode = "arithmetic"; -defparam \fault_counter[6] .output_mode = "reg_only"; -defparam \fault_counter[6] .register_cascade_mode = "off"; -defparam \fault_counter[6] .sum_lutc_input = "cin"; -defparam \fault_counter[6] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N1 -maxii_lcell \fault_counter[7] ( -// Equation(s): -// fault_counter[7] = DFFEAS((fault_counter[7] $ (((!\fault_counter[5]~33 & \fault_counter[6]~35 ) # (\fault_counter[5]~33 & \fault_counter[6]~35COUT1_75 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[7]~37 = CARRY(((!\fault_counter[6]~35 ) # (!fault_counter[7]))) -// \fault_counter[7]~37COUT1_76 = CARRY(((!\fault_counter[6]~35COUT1_75 ) # (!fault_counter[7]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[7]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[5]~33 ), - .cin0(\fault_counter[6]~35 ), - .cin1(\fault_counter[6]~35COUT1_75 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[7]), - .cout(), - .cout0(\fault_counter[7]~37 ), - .cout1(\fault_counter[7]~37COUT1_76 )); -// synopsys translate_off -defparam \fault_counter[7] .cin0_used = "true"; -defparam \fault_counter[7] .cin1_used = "true"; -defparam \fault_counter[7] .cin_used = "true"; -defparam \fault_counter[7] .lut_mask = "3c3f"; -defparam \fault_counter[7] .operation_mode = "arithmetic"; -defparam \fault_counter[7] .output_mode = "reg_only"; -defparam \fault_counter[7] .register_cascade_mode = "off"; -defparam \fault_counter[7] .sum_lutc_input = "cin"; -defparam \fault_counter[7] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N2 -maxii_lcell \fault_counter[8] ( -// Equation(s): -// fault_counter[8] = DFFEAS((fault_counter[8] $ ((!(!\fault_counter[5]~33 & \fault_counter[7]~37 ) # (\fault_counter[5]~33 & \fault_counter[7]~37COUT1_76 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[8]~21 = CARRY(((fault_counter[8] & !\fault_counter[7]~37 ))) -// \fault_counter[8]~21COUT1_77 = CARRY(((fault_counter[8] & !\fault_counter[7]~37COUT1_76 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[8]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[5]~33 ), - .cin0(\fault_counter[7]~37 ), - .cin1(\fault_counter[7]~37COUT1_76 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[8]), - .cout(), - .cout0(\fault_counter[8]~21 ), - .cout1(\fault_counter[8]~21COUT1_77 )); -// synopsys translate_off -defparam \fault_counter[8] .cin0_used = "true"; -defparam \fault_counter[8] .cin1_used = "true"; -defparam \fault_counter[8] .cin_used = "true"; -defparam \fault_counter[8] .lut_mask = "c30c"; -defparam \fault_counter[8] .operation_mode = "arithmetic"; -defparam \fault_counter[8] .output_mode = "reg_only"; -defparam \fault_counter[8] .register_cascade_mode = "off"; -defparam \fault_counter[8] .sum_lutc_input = "cin"; -defparam \fault_counter[8] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N3 -maxii_lcell \fault_counter[9] ( -// Equation(s): -// fault_counter[9] = DFFEAS(fault_counter[9] $ (((((!\fault_counter[5]~33 & \fault_counter[8]~21 ) # (\fault_counter[5]~33 & \fault_counter[8]~21COUT1_77 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[9]~19 = CARRY(((!\fault_counter[8]~21 )) # (!fault_counter[9])) -// \fault_counter[9]~19COUT1_78 = CARRY(((!\fault_counter[8]~21COUT1_77 )) # (!fault_counter[9])) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[9]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[5]~33 ), - .cin0(\fault_counter[8]~21 ), - .cin1(\fault_counter[8]~21COUT1_77 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[9]), - .cout(), - .cout0(\fault_counter[9]~19 ), - .cout1(\fault_counter[9]~19COUT1_78 )); -// synopsys translate_off -defparam \fault_counter[9] .cin0_used = "true"; -defparam \fault_counter[9] .cin1_used = "true"; -defparam \fault_counter[9] .cin_used = "true"; -defparam \fault_counter[9] .lut_mask = "5a5f"; -defparam \fault_counter[9] .operation_mode = "arithmetic"; -defparam \fault_counter[9] .output_mode = "reg_only"; -defparam \fault_counter[9] .register_cascade_mode = "off"; -defparam \fault_counter[9] .sum_lutc_input = "cin"; -defparam \fault_counter[9] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N4 -maxii_lcell \fault_counter[10] ( -// Equation(s): -// fault_counter[10] = DFFEAS(fault_counter[10] $ ((((!(!\fault_counter[5]~33 & \fault_counter[9]~19 ) # (\fault_counter[5]~33 & \fault_counter[9]~19COUT1_78 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[10]~41 = CARRY((fault_counter[10] & ((!\fault_counter[9]~19COUT1_78 )))) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[10]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[5]~33 ), - .cin0(\fault_counter[9]~19 ), - .cin1(\fault_counter[9]~19COUT1_78 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[10]), - .cout(\fault_counter[10]~41 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[10] .cin0_used = "true"; -defparam \fault_counter[10] .cin1_used = "true"; -defparam \fault_counter[10] .cin_used = "true"; -defparam \fault_counter[10] .lut_mask = "a50a"; -defparam \fault_counter[10] .operation_mode = "arithmetic"; -defparam \fault_counter[10] .output_mode = "reg_only"; -defparam \fault_counter[10] .register_cascade_mode = "off"; -defparam \fault_counter[10] .sum_lutc_input = "cin"; -defparam \fault_counter[10] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N5 -maxii_lcell \fault_counter[11] ( -// Equation(s): -// fault_counter[11] = DFFEAS(fault_counter[11] $ ((((\fault_counter[10]~41 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , \Equal0~1 , ) -// \fault_counter[11]~39 = CARRY(((!\fault_counter[10]~41 )) # (!fault_counter[11])) -// \fault_counter[11]~39COUT1_79 = CARRY(((!\fault_counter[10]~41 )) # (!fault_counter[11])) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[11]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[10]~41 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[11]), - .cout(), - .cout0(\fault_counter[11]~39 ), - .cout1(\fault_counter[11]~39COUT1_79 )); -// synopsys translate_off -defparam \fault_counter[11] .cin_used = "true"; -defparam \fault_counter[11] .lut_mask = "5a5f"; -defparam \fault_counter[11] .operation_mode = "arithmetic"; -defparam \fault_counter[11] .output_mode = "reg_only"; -defparam \fault_counter[11] .register_cascade_mode = "off"; -defparam \fault_counter[11] .sum_lutc_input = "cin"; -defparam \fault_counter[11] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N6 -maxii_lcell \fault_counter[12] ( -// Equation(s): -// fault_counter[12] = DFFEAS(fault_counter[12] $ ((((!(!\fault_counter[10]~41 & \fault_counter[11]~39 ) # (\fault_counter[10]~41 & \fault_counter[11]~39COUT1_79 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , -// , \Equal0~1 , ) -// \fault_counter[12]~13 = CARRY((fault_counter[12] & ((!\fault_counter[11]~39 )))) -// \fault_counter[12]~13COUT1_80 = CARRY((fault_counter[12] & ((!\fault_counter[11]~39COUT1_79 )))) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[12]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[10]~41 ), - .cin0(\fault_counter[11]~39 ), - .cin1(\fault_counter[11]~39COUT1_79 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[12]), - .cout(), - .cout0(\fault_counter[12]~13 ), - .cout1(\fault_counter[12]~13COUT1_80 )); -// synopsys translate_off -defparam \fault_counter[12] .cin0_used = "true"; -defparam \fault_counter[12] .cin1_used = "true"; -defparam \fault_counter[12] .cin_used = "true"; -defparam \fault_counter[12] .lut_mask = "a50a"; -defparam \fault_counter[12] .operation_mode = "arithmetic"; -defparam \fault_counter[12] .output_mode = "reg_only"; -defparam \fault_counter[12] .register_cascade_mode = "off"; -defparam \fault_counter[12] .sum_lutc_input = "cin"; -defparam \fault_counter[12] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N7 -maxii_lcell \fault_counter[13] ( -// Equation(s): -// fault_counter[13] = DFFEAS((fault_counter[13] $ (((!\fault_counter[10]~41 & \fault_counter[12]~13 ) # (\fault_counter[10]~41 & \fault_counter[12]~13COUT1_80 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[13]~11 = CARRY(((!\fault_counter[12]~13 ) # (!fault_counter[13]))) -// \fault_counter[13]~11COUT1_81 = CARRY(((!\fault_counter[12]~13COUT1_80 ) # (!fault_counter[13]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[13]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[10]~41 ), - .cin0(\fault_counter[12]~13 ), - .cin1(\fault_counter[12]~13COUT1_80 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[13]), - .cout(), - .cout0(\fault_counter[13]~11 ), - .cout1(\fault_counter[13]~11COUT1_81 )); -// synopsys translate_off -defparam \fault_counter[13] .cin0_used = "true"; -defparam \fault_counter[13] .cin1_used = "true"; -defparam \fault_counter[13] .cin_used = "true"; -defparam \fault_counter[13] .lut_mask = "3c3f"; -defparam \fault_counter[13] .operation_mode = "arithmetic"; -defparam \fault_counter[13] .output_mode = "reg_only"; -defparam \fault_counter[13] .register_cascade_mode = "off"; -defparam \fault_counter[13] .sum_lutc_input = "cin"; -defparam \fault_counter[13] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N8 -maxii_lcell \fault_counter[14] ( -// Equation(s): -// fault_counter[14] = DFFEAS(fault_counter[14] $ ((((!(!\fault_counter[10]~41 & \fault_counter[13]~11 ) # (\fault_counter[10]~41 & \fault_counter[13]~11COUT1_81 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , -// , \Equal0~1 , ) -// \fault_counter[14]~15 = CARRY((fault_counter[14] & ((!\fault_counter[13]~11 )))) -// \fault_counter[14]~15COUT1_82 = CARRY((fault_counter[14] & ((!\fault_counter[13]~11COUT1_81 )))) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[14]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[10]~41 ), - .cin0(\fault_counter[13]~11 ), - .cin1(\fault_counter[13]~11COUT1_81 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[14]), - .cout(), - .cout0(\fault_counter[14]~15 ), - .cout1(\fault_counter[14]~15COUT1_82 )); -// synopsys translate_off -defparam \fault_counter[14] .cin0_used = "true"; -defparam \fault_counter[14] .cin1_used = "true"; -defparam \fault_counter[14] .cin_used = "true"; -defparam \fault_counter[14] .lut_mask = "a50a"; -defparam \fault_counter[14] .operation_mode = "arithmetic"; -defparam \fault_counter[14] .output_mode = "reg_only"; -defparam \fault_counter[14] .register_cascade_mode = "off"; -defparam \fault_counter[14] .sum_lutc_input = "cin"; -defparam \fault_counter[14] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X4_Y7_N9 -maxii_lcell \fault_counter[15] ( -// Equation(s): -// fault_counter[15] = DFFEAS((fault_counter[15] $ (((!\fault_counter[10]~41 & \fault_counter[14]~15 ) # (\fault_counter[10]~41 & \fault_counter[14]~15COUT1_82 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[15]~17 = CARRY(((!\fault_counter[14]~15COUT1_82 ) # (!fault_counter[15]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[15]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[10]~41 ), - .cin0(\fault_counter[14]~15 ), - .cin1(\fault_counter[14]~15COUT1_82 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[15]), - .cout(\fault_counter[15]~17 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[15] .cin0_used = "true"; -defparam \fault_counter[15] .cin1_used = "true"; -defparam \fault_counter[15] .cin_used = "true"; -defparam \fault_counter[15] .lut_mask = "3c3f"; -defparam \fault_counter[15] .operation_mode = "arithmetic"; -defparam \fault_counter[15] .output_mode = "reg_only"; -defparam \fault_counter[15] .register_cascade_mode = "off"; -defparam \fault_counter[15] .sum_lutc_input = "cin"; -defparam \fault_counter[15] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N0 -maxii_lcell \fault_counter[16] ( -// Equation(s): -// fault_counter[16] = DFFEAS((fault_counter[16] $ ((!\fault_counter[15]~17 ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , \Equal0~1 , ) -// \fault_counter[16]~9 = CARRY(((fault_counter[16] & !\fault_counter[15]~17 ))) -// \fault_counter[16]~9COUT1_83 = CARRY(((fault_counter[16] & !\fault_counter[15]~17 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[16]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[15]~17 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[16]), - .cout(), - .cout0(\fault_counter[16]~9 ), - .cout1(\fault_counter[16]~9COUT1_83 )); -// synopsys translate_off -defparam \fault_counter[16] .cin_used = "true"; -defparam \fault_counter[16] .lut_mask = "c30c"; -defparam \fault_counter[16] .operation_mode = "arithmetic"; -defparam \fault_counter[16] .output_mode = "reg_only"; -defparam \fault_counter[16] .register_cascade_mode = "off"; -defparam \fault_counter[16] .sum_lutc_input = "cin"; -defparam \fault_counter[16] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N1 -maxii_lcell \fault_counter[17] ( -// Equation(s): -// fault_counter[17] = DFFEAS((fault_counter[17] $ (((!\fault_counter[15]~17 & \fault_counter[16]~9 ) # (\fault_counter[15]~17 & \fault_counter[16]~9COUT1_83 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[17]~43 = CARRY(((!\fault_counter[16]~9 ) # (!fault_counter[17]))) -// \fault_counter[17]~43COUT1_84 = CARRY(((!\fault_counter[16]~9COUT1_83 ) # (!fault_counter[17]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[17]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[15]~17 ), - .cin0(\fault_counter[16]~9 ), - .cin1(\fault_counter[16]~9COUT1_83 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[17]), - .cout(), - .cout0(\fault_counter[17]~43 ), - .cout1(\fault_counter[17]~43COUT1_84 )); -// synopsys translate_off -defparam \fault_counter[17] .cin0_used = "true"; -defparam \fault_counter[17] .cin1_used = "true"; -defparam \fault_counter[17] .cin_used = "true"; -defparam \fault_counter[17] .lut_mask = "3c3f"; -defparam \fault_counter[17] .operation_mode = "arithmetic"; -defparam \fault_counter[17] .output_mode = "reg_only"; -defparam \fault_counter[17] .register_cascade_mode = "off"; -defparam \fault_counter[17] .sum_lutc_input = "cin"; -defparam \fault_counter[17] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N2 -maxii_lcell \fault_counter[18] ( -// Equation(s): -// fault_counter[18] = DFFEAS((fault_counter[18] $ ((!(!\fault_counter[15]~17 & \fault_counter[17]~43 ) # (\fault_counter[15]~17 & \fault_counter[17]~43COUT1_84 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[18]~45 = CARRY(((fault_counter[18] & !\fault_counter[17]~43 ))) -// \fault_counter[18]~45COUT1_85 = CARRY(((fault_counter[18] & !\fault_counter[17]~43COUT1_84 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[18]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[15]~17 ), - .cin0(\fault_counter[17]~43 ), - .cin1(\fault_counter[17]~43COUT1_84 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[18]), - .cout(), - .cout0(\fault_counter[18]~45 ), - .cout1(\fault_counter[18]~45COUT1_85 )); -// synopsys translate_off -defparam \fault_counter[18] .cin0_used = "true"; -defparam \fault_counter[18] .cin1_used = "true"; -defparam \fault_counter[18] .cin_used = "true"; -defparam \fault_counter[18] .lut_mask = "c30c"; -defparam \fault_counter[18] .operation_mode = "arithmetic"; -defparam \fault_counter[18] .output_mode = "reg_only"; -defparam \fault_counter[18] .register_cascade_mode = "off"; -defparam \fault_counter[18] .sum_lutc_input = "cin"; -defparam \fault_counter[18] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N3 -maxii_lcell \fault_counter[19] ( -// Equation(s): -// fault_counter[19] = DFFEAS(fault_counter[19] $ (((((!\fault_counter[15]~17 & \fault_counter[18]~45 ) # (\fault_counter[15]~17 & \fault_counter[18]~45COUT1_85 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , -// , \Equal0~1 , ) -// \fault_counter[19]~47 = CARRY(((!\fault_counter[18]~45 )) # (!fault_counter[19])) -// \fault_counter[19]~47COUT1_86 = CARRY(((!\fault_counter[18]~45COUT1_85 )) # (!fault_counter[19])) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[19]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[15]~17 ), - .cin0(\fault_counter[18]~45 ), - .cin1(\fault_counter[18]~45COUT1_85 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[19]), - .cout(), - .cout0(\fault_counter[19]~47 ), - .cout1(\fault_counter[19]~47COUT1_86 )); -// synopsys translate_off -defparam \fault_counter[19] .cin0_used = "true"; -defparam \fault_counter[19] .cin1_used = "true"; -defparam \fault_counter[19] .cin_used = "true"; -defparam \fault_counter[19] .lut_mask = "5a5f"; -defparam \fault_counter[19] .operation_mode = "arithmetic"; -defparam \fault_counter[19] .output_mode = "reg_only"; -defparam \fault_counter[19] .register_cascade_mode = "off"; -defparam \fault_counter[19] .sum_lutc_input = "cin"; -defparam \fault_counter[19] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N4 -maxii_lcell \fault_counter[20] ( -// Equation(s): -// fault_counter[20] = DFFEAS(fault_counter[20] $ ((((!(!\fault_counter[15]~17 & \fault_counter[19]~47 ) # (\fault_counter[15]~17 & \fault_counter[19]~47COUT1_86 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , -// , \Equal0~1 , ) -// \fault_counter[20]~5 = CARRY((fault_counter[20] & ((!\fault_counter[19]~47COUT1_86 )))) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[20]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[15]~17 ), - .cin0(\fault_counter[19]~47 ), - .cin1(\fault_counter[19]~47COUT1_86 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[20]), - .cout(\fault_counter[20]~5 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[20] .cin0_used = "true"; -defparam \fault_counter[20] .cin1_used = "true"; -defparam \fault_counter[20] .cin_used = "true"; -defparam \fault_counter[20] .lut_mask = "a50a"; -defparam \fault_counter[20] .operation_mode = "arithmetic"; -defparam \fault_counter[20] .output_mode = "reg_only"; -defparam \fault_counter[20] .register_cascade_mode = "off"; -defparam \fault_counter[20] .sum_lutc_input = "cin"; -defparam \fault_counter[20] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N5 -maxii_lcell \fault_counter[21] ( -// Equation(s): -// fault_counter[21] = DFFEAS(fault_counter[21] $ ((((\fault_counter[20]~5 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , \Equal0~1 , ) -// \fault_counter[21]~7 = CARRY(((!\fault_counter[20]~5 )) # (!fault_counter[21])) -// \fault_counter[21]~7COUT1_87 = CARRY(((!\fault_counter[20]~5 )) # (!fault_counter[21])) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[21]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[20]~5 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[21]), - .cout(), - .cout0(\fault_counter[21]~7 ), - .cout1(\fault_counter[21]~7COUT1_87 )); -// synopsys translate_off -defparam \fault_counter[21] .cin_used = "true"; -defparam \fault_counter[21] .lut_mask = "5a5f"; -defparam \fault_counter[21] .operation_mode = "arithmetic"; -defparam \fault_counter[21] .output_mode = "reg_only"; -defparam \fault_counter[21] .register_cascade_mode = "off"; -defparam \fault_counter[21] .sum_lutc_input = "cin"; -defparam \fault_counter[21] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N6 -maxii_lcell \fault_counter[22] ( -// Equation(s): -// fault_counter[22] = DFFEAS(fault_counter[22] $ ((((!(!\fault_counter[20]~5 & \fault_counter[21]~7 ) # (\fault_counter[20]~5 & \fault_counter[21]~7COUT1_87 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[22]~49 = CARRY((fault_counter[22] & ((!\fault_counter[21]~7 )))) -// \fault_counter[22]~49COUT1_88 = CARRY((fault_counter[22] & ((!\fault_counter[21]~7COUT1_87 )))) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[22]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[20]~5 ), - .cin0(\fault_counter[21]~7 ), - .cin1(\fault_counter[21]~7COUT1_87 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[22]), - .cout(), - .cout0(\fault_counter[22]~49 ), - .cout1(\fault_counter[22]~49COUT1_88 )); -// synopsys translate_off -defparam \fault_counter[22] .cin0_used = "true"; -defparam \fault_counter[22] .cin1_used = "true"; -defparam \fault_counter[22] .cin_used = "true"; -defparam \fault_counter[22] .lut_mask = "a50a"; -defparam \fault_counter[22] .operation_mode = "arithmetic"; -defparam \fault_counter[22] .output_mode = "reg_only"; -defparam \fault_counter[22] .register_cascade_mode = "off"; -defparam \fault_counter[22] .sum_lutc_input = "cin"; -defparam \fault_counter[22] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N7 -maxii_lcell \fault_counter[23] ( -// Equation(s): -// fault_counter[23] = DFFEAS((fault_counter[23] $ (((!\fault_counter[20]~5 & \fault_counter[22]~49 ) # (\fault_counter[20]~5 & \fault_counter[22]~49COUT1_88 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[23]~51 = CARRY(((!\fault_counter[22]~49 ) # (!fault_counter[23]))) -// \fault_counter[23]~51COUT1_89 = CARRY(((!\fault_counter[22]~49COUT1_88 ) # (!fault_counter[23]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[23]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[20]~5 ), - .cin0(\fault_counter[22]~49 ), - .cin1(\fault_counter[22]~49COUT1_88 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[23]), - .cout(), - .cout0(\fault_counter[23]~51 ), - .cout1(\fault_counter[23]~51COUT1_89 )); -// synopsys translate_off -defparam \fault_counter[23] .cin0_used = "true"; -defparam \fault_counter[23] .cin1_used = "true"; -defparam \fault_counter[23] .cin_used = "true"; -defparam \fault_counter[23] .lut_mask = "3c3f"; -defparam \fault_counter[23] .operation_mode = "arithmetic"; -defparam \fault_counter[23] .output_mode = "reg_only"; -defparam \fault_counter[23] .register_cascade_mode = "off"; -defparam \fault_counter[23] .sum_lutc_input = "cin"; -defparam \fault_counter[23] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N8 -maxii_lcell \fault_counter[24] ( -// Equation(s): -// fault_counter[24] = DFFEAS(fault_counter[24] $ ((((!(!\fault_counter[20]~5 & \fault_counter[23]~51 ) # (\fault_counter[20]~5 & \fault_counter[23]~51COUT1_89 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[24]~3 = CARRY((fault_counter[24] & ((!\fault_counter[23]~51 )))) -// \fault_counter[24]~3COUT1_90 = CARRY((fault_counter[24] & ((!\fault_counter[23]~51COUT1_89 )))) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[24]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[20]~5 ), - .cin0(\fault_counter[23]~51 ), - .cin1(\fault_counter[23]~51COUT1_89 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[24]), - .cout(), - .cout0(\fault_counter[24]~3 ), - .cout1(\fault_counter[24]~3COUT1_90 )); -// synopsys translate_off -defparam \fault_counter[24] .cin0_used = "true"; -defparam \fault_counter[24] .cin1_used = "true"; -defparam \fault_counter[24] .cin_used = "true"; -defparam \fault_counter[24] .lut_mask = "a50a"; -defparam \fault_counter[24] .operation_mode = "arithmetic"; -defparam \fault_counter[24] .output_mode = "reg_only"; -defparam \fault_counter[24] .register_cascade_mode = "off"; -defparam \fault_counter[24] .sum_lutc_input = "cin"; -defparam \fault_counter[24] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y7_N9 -maxii_lcell \fault_counter[25] ( -// Equation(s): -// fault_counter[25] = DFFEAS((fault_counter[25] $ (((!\fault_counter[20]~5 & \fault_counter[24]~3 ) # (\fault_counter[20]~5 & \fault_counter[24]~3COUT1_90 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[25]~53 = CARRY(((!\fault_counter[24]~3COUT1_90 ) # (!fault_counter[25]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[25]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[20]~5 ), - .cin0(\fault_counter[24]~3 ), - .cin1(\fault_counter[24]~3COUT1_90 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[25]), - .cout(\fault_counter[25]~53 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[25] .cin0_used = "true"; -defparam \fault_counter[25] .cin1_used = "true"; -defparam \fault_counter[25] .cin_used = "true"; -defparam \fault_counter[25] .lut_mask = "3c3f"; -defparam \fault_counter[25] .operation_mode = "arithmetic"; -defparam \fault_counter[25] .output_mode = "reg_only"; -defparam \fault_counter[25] .register_cascade_mode = "off"; -defparam \fault_counter[25] .sum_lutc_input = "cin"; -defparam \fault_counter[25] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y7_N0 -maxii_lcell \fault_counter[26] ( -// Equation(s): -// fault_counter[26] = DFFEAS((fault_counter[26] $ ((!\fault_counter[25]~53 ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , \Equal0~1 , ) -// \fault_counter[26]~55 = CARRY(((fault_counter[26] & !\fault_counter[25]~53 ))) -// \fault_counter[26]~55COUT1_91 = CARRY(((fault_counter[26] & !\fault_counter[25]~53 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[26]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[25]~53 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[26]), - .cout(), - .cout0(\fault_counter[26]~55 ), - .cout1(\fault_counter[26]~55COUT1_91 )); -// synopsys translate_off -defparam \fault_counter[26] .cin_used = "true"; -defparam \fault_counter[26] .lut_mask = "c30c"; -defparam \fault_counter[26] .operation_mode = "arithmetic"; -defparam \fault_counter[26] .output_mode = "reg_only"; -defparam \fault_counter[26] .register_cascade_mode = "off"; -defparam \fault_counter[26] .sum_lutc_input = "cin"; -defparam \fault_counter[26] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y7_N1 -maxii_lcell \fault_counter[27] ( -// Equation(s): -// fault_counter[27] = DFFEAS((fault_counter[27] $ (((!\fault_counter[25]~53 & \fault_counter[26]~55 ) # (\fault_counter[25]~53 & \fault_counter[26]~55COUT1_91 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[27]~57 = CARRY(((!\fault_counter[26]~55 ) # (!fault_counter[27]))) -// \fault_counter[27]~57COUT1_92 = CARRY(((!\fault_counter[26]~55COUT1_91 ) # (!fault_counter[27]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[27]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[25]~53 ), - .cin0(\fault_counter[26]~55 ), - .cin1(\fault_counter[26]~55COUT1_91 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[27]), - .cout(), - .cout0(\fault_counter[27]~57 ), - .cout1(\fault_counter[27]~57COUT1_92 )); -// synopsys translate_off -defparam \fault_counter[27] .cin0_used = "true"; -defparam \fault_counter[27] .cin1_used = "true"; -defparam \fault_counter[27] .cin_used = "true"; -defparam \fault_counter[27] .lut_mask = "3c3f"; -defparam \fault_counter[27] .operation_mode = "arithmetic"; -defparam \fault_counter[27] .output_mode = "reg_only"; -defparam \fault_counter[27] .register_cascade_mode = "off"; -defparam \fault_counter[27] .sum_lutc_input = "cin"; -defparam \fault_counter[27] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y7_N2 -maxii_lcell \fault_counter[28] ( -// Equation(s): -// fault_counter[28] = DFFEAS((fault_counter[28] $ ((!(!\fault_counter[25]~53 & \fault_counter[27]~57 ) # (\fault_counter[25]~53 & \fault_counter[27]~57COUT1_92 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , -// \Equal0~1 , ) -// \fault_counter[28]~59 = CARRY(((fault_counter[28] & !\fault_counter[27]~57 ))) -// \fault_counter[28]~59COUT1_93 = CARRY(((fault_counter[28] & !\fault_counter[27]~57COUT1_92 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(fault_counter[28]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[25]~53 ), - .cin0(\fault_counter[27]~57 ), - .cin1(\fault_counter[27]~57COUT1_92 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[28]), - .cout(), - .cout0(\fault_counter[28]~59 ), - .cout1(\fault_counter[28]~59COUT1_93 )); -// synopsys translate_off -defparam \fault_counter[28] .cin0_used = "true"; -defparam \fault_counter[28] .cin1_used = "true"; -defparam \fault_counter[28] .cin_used = "true"; -defparam \fault_counter[28] .lut_mask = "c30c"; -defparam \fault_counter[28] .operation_mode = "arithmetic"; -defparam \fault_counter[28] .output_mode = "reg_only"; -defparam \fault_counter[28] .register_cascade_mode = "off"; -defparam \fault_counter[28] .sum_lutc_input = "cin"; -defparam \fault_counter[28] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y7_N3 -maxii_lcell \fault_counter[29] ( -// Equation(s): -// fault_counter[29] = DFFEAS(fault_counter[29] $ (((((!\fault_counter[25]~53 & \fault_counter[28]~59 ) # (\fault_counter[25]~53 & \fault_counter[28]~59COUT1_93 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , -// , \Equal0~1 , ) -// \fault_counter[29]~62 = CARRY(((!\fault_counter[28]~59 )) # (!fault_counter[29])) -// \fault_counter[29]~62COUT1_94 = CARRY(((!\fault_counter[28]~59COUT1_93 )) # (!fault_counter[29])) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[29]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[25]~53 ), - .cin0(\fault_counter[28]~59 ), - .cin1(\fault_counter[28]~59COUT1_93 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[29]), - .cout(), - .cout0(\fault_counter[29]~62 ), - .cout1(\fault_counter[29]~62COUT1_94 )); -// synopsys translate_off -defparam \fault_counter[29] .cin0_used = "true"; -defparam \fault_counter[29] .cin1_used = "true"; -defparam \fault_counter[29] .cin_used = "true"; -defparam \fault_counter[29] .lut_mask = "5a5f"; -defparam \fault_counter[29] .operation_mode = "arithmetic"; -defparam \fault_counter[29] .output_mode = "reg_only"; -defparam \fault_counter[29] .register_cascade_mode = "off"; -defparam \fault_counter[29] .sum_lutc_input = "cin"; -defparam \fault_counter[29] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y7_N4 -maxii_lcell \fault_counter[30] ( -// Equation(s): -// fault_counter[30] = DFFEAS(fault_counter[30] $ ((((!(!\fault_counter[25]~53 & \fault_counter[29]~62 ) # (\fault_counter[25]~53 & \fault_counter[29]~62COUT1_94 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , -// , \Equal0~1 , ) -// \fault_counter[30]~64 = CARRY((fault_counter[30] & ((!\fault_counter[29]~62COUT1_94 )))) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[30]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[25]~53 ), - .cin0(\fault_counter[29]~62 ), - .cin1(\fault_counter[29]~62COUT1_94 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[30]), - .cout(\fault_counter[30]~64 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[30] .cin0_used = "true"; -defparam \fault_counter[30] .cin1_used = "true"; -defparam \fault_counter[30] .cin_used = "true"; -defparam \fault_counter[30] .lut_mask = "a50a"; -defparam \fault_counter[30] .operation_mode = "arithmetic"; -defparam \fault_counter[30] .output_mode = "reg_only"; -defparam \fault_counter[30] .register_cascade_mode = "off"; -defparam \fault_counter[30] .sum_lutc_input = "cin"; -defparam \fault_counter[30] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y7_N5 -maxii_lcell \fault_counter[31] ( -// Equation(s): -// fault_counter[31] = DFFEAS(fault_counter[31] $ ((((\fault_counter[30]~64 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \fault_counter[26]~69_combout , , , \Equal0~1 , ) - - .clk(\sys_clk~combout ), - .dataa(fault_counter[31]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\Equal0~1 ), - .sload(gnd), - .ena(\fault_counter[26]~69_combout ), - .cin(\fault_counter[30]~64 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(fault_counter[31]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[31] .cin_used = "true"; -defparam \fault_counter[31] .lut_mask = "5a5a"; -defparam \fault_counter[31] .operation_mode = "normal"; -defparam \fault_counter[31] .output_mode = "reg_only"; -defparam \fault_counter[31] .register_cascade_mode = "off"; -defparam \fault_counter[31] .sum_lutc_input = "cin"; -defparam \fault_counter[31] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y7_N8 -maxii_lcell \fault_counter[26]~60 ( -// Equation(s): -// \fault_counter[26]~60_combout = (!fault_counter[25] & (!fault_counter[28] & (!fault_counter[26] & !fault_counter[27]))) - - .clk(gnd), - .dataa(fault_counter[25]), - .datab(fault_counter[28]), - .datac(fault_counter[26]), - .datad(fault_counter[27]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_counter[26]~60_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[26]~60 .lut_mask = "0001"; -defparam \fault_counter[26]~60 .operation_mode = "normal"; -defparam \fault_counter[26]~60 .output_mode = "comb_only"; -defparam \fault_counter[26]~60 .register_cascade_mode = "off"; -defparam \fault_counter[26]~60 .sum_lutc_input = "datac"; -defparam \fault_counter[26]~60 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y7_N9 -maxii_lcell \fault_counter[26]~67 ( -// Equation(s): -// \fault_counter[26]~67_combout = (!fault_counter[29] & (!fault_counter[30] & (!fault_counter[31] & \fault_counter[26]~60_combout ))) - - .clk(gnd), - .dataa(fault_counter[29]), - .datab(fault_counter[30]), - .datac(fault_counter[31]), - .datad(\fault_counter[26]~60_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_counter[26]~67_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[26]~67 .lut_mask = "0100"; -defparam \fault_counter[26]~67 .operation_mode = "normal"; -defparam \fault_counter[26]~67 .output_mode = "comb_only"; -defparam \fault_counter[26]~67 .register_cascade_mode = "off"; -defparam \fault_counter[26]~67 .sum_lutc_input = "datac"; -defparam \fault_counter[26]~67 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X2_Y7_N2 -maxii_lcell \fault_flag~7 ( -// Equation(s): -// \fault_flag~7_combout = ((!fault_counter[17] & (!fault_counter[18] & !fault_counter[19]))) - - .clk(gnd), - .dataa(vcc), - .datab(fault_counter[17]), - .datac(fault_counter[18]), - .datad(fault_counter[19]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~7_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~7 .lut_mask = "0003"; -defparam \fault_flag~7 .operation_mode = "normal"; -defparam \fault_flag~7 .output_mode = "comb_only"; -defparam \fault_flag~7 .register_cascade_mode = "off"; -defparam \fault_flag~7 .sum_lutc_input = "datac"; -defparam \fault_flag~7 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X2_Y7_N3 -maxii_lcell \LessThan2~8 ( -// Equation(s): -// \LessThan2~8_combout = ((fault_counter[21] & ((fault_counter[16]) # (!\fault_flag~7_combout )))) - - .clk(gnd), - .dataa(vcc), - .datab(fault_counter[21]), - .datac(fault_counter[16]), - .datad(\fault_flag~7_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~8_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~8 .lut_mask = "c0cc"; -defparam \LessThan2~8 .operation_mode = "normal"; -defparam \LessThan2~8 .output_mode = "comb_only"; -defparam \LessThan2~8 .register_cascade_mode = "off"; -defparam \LessThan2~8 .sum_lutc_input = "datac"; -defparam \LessThan2~8 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X2_Y7_N0 -maxii_lcell \LessThan2~9 ( -// Equation(s): -// \LessThan2~9_combout = (!fault_counter[23] & (!fault_counter[22] & ((!\LessThan2~8_combout ) # (!fault_counter[20])))) - - .clk(gnd), - .dataa(fault_counter[20]), - .datab(fault_counter[23]), - .datac(fault_counter[22]), - .datad(\LessThan2~8_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~9_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~9 .lut_mask = "0103"; -defparam \LessThan2~9 .operation_mode = "normal"; -defparam \LessThan2~9 .output_mode = "comb_only"; -defparam \LessThan2~9 .register_cascade_mode = "off"; -defparam \LessThan2~9 .sum_lutc_input = "datac"; -defparam \LessThan2~9 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X1_Y7_N5 -maxii_lcell \LessThan2~6 ( -// Equation(s): -// \LessThan2~6_combout = (!fault_counter[12] & (((!fault_counter[9] & !fault_counter[8])) # (!fault_counter[10]))) - - .clk(gnd), - .dataa(fault_counter[10]), - .datab(fault_counter[12]), - .datac(fault_counter[9]), - .datad(fault_counter[8]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~6_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~6 .lut_mask = "1113"; -defparam \LessThan2~6 .operation_mode = "normal"; -defparam \LessThan2~6 .output_mode = "comb_only"; -defparam \LessThan2~6 .register_cascade_mode = "off"; -defparam \LessThan2~6 .sum_lutc_input = "datac"; -defparam \LessThan2~6 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y7_N2 -maxii_lcell \LessThan2~2 ( -// Equation(s): -// \LessThan2~2_combout = (((!fault_counter[11] & !fault_counter[12])) # (!fault_counter[13])) - - .clk(gnd), - .dataa(vcc), - .datab(fault_counter[11]), - .datac(fault_counter[12]), - .datad(fault_counter[13]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~2_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~2 .lut_mask = "03ff"; -defparam \LessThan2~2 .operation_mode = "normal"; -defparam \LessThan2~2 .output_mode = "comb_only"; -defparam \LessThan2~2 .register_cascade_mode = "off"; -defparam \LessThan2~2 .sum_lutc_input = "datac"; -defparam \LessThan2~2 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X2_Y7_N4 -maxii_lcell \LessThan2~4 ( -// Equation(s): -// \LessThan2~4_combout = (!fault_counter[3] & (!fault_counter[5] & (!fault_counter[2] & !fault_counter[4]))) - - .clk(gnd), - .dataa(fault_counter[3]), - .datab(fault_counter[5]), - .datac(fault_counter[2]), - .datad(fault_counter[4]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~4_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~4 .lut_mask = "0001"; -defparam \LessThan2~4 .operation_mode = "normal"; -defparam \LessThan2~4 .output_mode = "comb_only"; -defparam \LessThan2~4 .register_cascade_mode = "off"; -defparam \LessThan2~4 .sum_lutc_input = "datac"; -defparam \LessThan2~4 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y7_N1 -maxii_lcell \LessThan2~3 ( -// Equation(s): -// \LessThan2~3_combout = (!fault_counter[1] & (!fault_counter[0] & (!fault_counter[12] & !fault_counter[9]))) - - .clk(gnd), - .dataa(fault_counter[1]), - .datab(fault_counter[0]), - .datac(fault_counter[12]), - .datad(fault_counter[9]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~3_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~3 .lut_mask = "0001"; -defparam \LessThan2~3 .operation_mode = "normal"; -defparam \LessThan2~3 .output_mode = "comb_only"; -defparam \LessThan2~3 .register_cascade_mode = "off"; -defparam \LessThan2~3 .sum_lutc_input = "datac"; -defparam \LessThan2~3 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X2_Y7_N6 -maxii_lcell \LessThan2~5 ( -// Equation(s): -// \LessThan2~5_combout = (!fault_counter[6] & (!fault_counter[7] & (\LessThan2~4_combout & \LessThan2~3_combout ))) - - .clk(gnd), - .dataa(fault_counter[6]), - .datab(fault_counter[7]), - .datac(\LessThan2~4_combout ), - .datad(\LessThan2~3_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~5_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~5 .lut_mask = "1000"; -defparam \LessThan2~5 .operation_mode = "normal"; -defparam \LessThan2~5 .output_mode = "comb_only"; -defparam \LessThan2~5 .register_cascade_mode = "off"; -defparam \LessThan2~5 .sum_lutc_input = "datac"; -defparam \LessThan2~5 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y7_N3 -maxii_lcell \LessThan2~0 ( -// Equation(s): -// \LessThan2~0_combout = (((!fault_counter[15] & !fault_counter[14]))) - - .clk(gnd), - .dataa(vcc), - .datab(vcc), - .datac(fault_counter[15]), - .datad(fault_counter[14]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~0_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~0 .lut_mask = "000f"; -defparam \LessThan2~0 .operation_mode = "normal"; -defparam \LessThan2~0 .output_mode = "comb_only"; -defparam \LessThan2~0 .register_cascade_mode = "off"; -defparam \LessThan2~0 .sum_lutc_input = "datac"; -defparam \LessThan2~0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X2_Y7_N9 -maxii_lcell \LessThan2~1 ( -// Equation(s): -// \LessThan2~1_combout = (!fault_counter[22] & (!fault_counter[23] & (\LessThan2~0_combout & \fault_flag~7_combout ))) - - .clk(gnd), - .dataa(fault_counter[22]), - .datab(fault_counter[23]), - .datac(\LessThan2~0_combout ), - .datad(\fault_flag~7_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~1_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~1 .lut_mask = "1000"; -defparam \LessThan2~1 .operation_mode = "normal"; -defparam \LessThan2~1 .output_mode = "comb_only"; -defparam \LessThan2~1 .register_cascade_mode = "off"; -defparam \LessThan2~1 .sum_lutc_input = "datac"; -defparam \LessThan2~1 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X2_Y7_N7 -maxii_lcell \LessThan2~7 ( -// Equation(s): -// \LessThan2~7_combout = (\LessThan2~1_combout & ((\LessThan2~6_combout ) # ((\LessThan2~2_combout ) # (\LessThan2~5_combout )))) - - .clk(gnd), - .dataa(\LessThan2~6_combout ), - .datab(\LessThan2~2_combout ), - .datac(\LessThan2~5_combout ), - .datad(\LessThan2~1_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\LessThan2~7_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \LessThan2~7 .lut_mask = "fe00"; -defparam \LessThan2~7 .operation_mode = "normal"; -defparam \LessThan2~7 .output_mode = "comb_only"; -defparam \LessThan2~7 .register_cascade_mode = "off"; -defparam \LessThan2~7 .sum_lutc_input = "datac"; -defparam \LessThan2~7 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X2_Y7_N8 -maxii_lcell \fault_counter[26]~68 ( -// Equation(s): -// \fault_counter[26]~68_combout = (\fault_counter[26]~67_combout & (((\LessThan2~9_combout ) # (\LessThan2~7_combout )) # (!fault_counter[24]))) - - .clk(gnd), - .dataa(fault_counter[24]), - .datab(\fault_counter[26]~67_combout ), - .datac(\LessThan2~9_combout ), - .datad(\LessThan2~7_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_counter[26]~68_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[26]~68 .lut_mask = "ccc4"; -defparam \fault_counter[26]~68 .operation_mode = "normal"; -defparam \fault_counter[26]~68 .output_mode = "comb_only"; -defparam \fault_counter[26]~68 .register_cascade_mode = "off"; -defparam \fault_counter[26]~68 .sum_lutc_input = "datac"; -defparam \fault_counter[26]~68 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X2_Y7_N5 -maxii_lcell \fault_counter[26]~69 ( -// Equation(s): -// \fault_counter[26]~69_combout = (\fault_counter[26]~68_combout ) # ((\Equal0~0 & (cache_line_sclk[0] & \line_sclk~combout ))) - - .clk(gnd), - .dataa(\Equal0~0 ), - .datab(cache_line_sclk[0]), - .datac(\line_sclk~combout ), - .datad(\fault_counter[26]~68_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_counter[26]~69_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_counter[26]~69 .lut_mask = "ff80"; -defparam \fault_counter[26]~69 .operation_mode = "normal"; -defparam \fault_counter[26]~69 .output_mode = "comb_only"; -defparam \fault_counter[26]~69 .register_cascade_mode = "off"; -defparam \fault_counter[26]~69 .sum_lutc_input = "datac"; -defparam \fault_counter[26]~69 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y8_N6 -maxii_lcell \fault_flag~10 ( -// Equation(s): -// \fault_flag~10_combout = ((fault_counter[24] & ((fault_counter[23]) # (fault_counter[22])))) - - .clk(gnd), - .dataa(vcc), - .datab(fault_counter[23]), - .datac(fault_counter[22]), - .datad(fault_counter[24]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~10_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~10 .lut_mask = "fc00"; -defparam \fault_flag~10 .operation_mode = "normal"; -defparam \fault_flag~10 .output_mode = "comb_only"; -defparam \fault_flag~10 .register_cascade_mode = "off"; -defparam \fault_flag~10 .sum_lutc_input = "datac"; -defparam \fault_flag~10 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y8_N7 -maxii_lcell \fault_flag~6 ( -// Equation(s): -// \fault_flag~6_combout = (fault_counter[13] & (fault_counter[10] & (fault_counter[11] & fault_counter[16]))) - - .clk(gnd), - .dataa(fault_counter[13]), - .datab(fault_counter[10]), - .datac(fault_counter[11]), - .datad(fault_counter[16]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~6_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~6 .lut_mask = "8000"; -defparam \fault_flag~6 .operation_mode = "normal"; -defparam \fault_flag~6 .output_mode = "comb_only"; -defparam \fault_flag~6 .register_cascade_mode = "off"; -defparam \fault_flag~6 .sum_lutc_input = "datac"; -defparam \fault_flag~6 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y8_N0 -maxii_lcell \fault_flag~2 ( -// Equation(s): -// \fault_flag~2_combout = (fault_counter[16] & (((fault_counter[12] & fault_counter[13])) # (!\LessThan2~0_combout ))) - - .clk(gnd), - .dataa(\LessThan2~0_combout ), - .datab(fault_counter[12]), - .datac(fault_counter[13]), - .datad(fault_counter[16]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~2_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~2 .lut_mask = "d500"; -defparam \fault_flag~2 .operation_mode = "normal"; -defparam \fault_flag~2 .output_mode = "comb_only"; -defparam \fault_flag~2 .register_cascade_mode = "off"; -defparam \fault_flag~2 .sum_lutc_input = "datac"; -defparam \fault_flag~2 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y7_N0 -maxii_lcell \fault_flag~3 ( -// Equation(s): -// \fault_flag~3_combout = (fault_counter[1] & (fault_counter[3] & (fault_counter[2] & fault_counter[0]))) - - .clk(gnd), - .dataa(fault_counter[1]), - .datab(fault_counter[3]), - .datac(fault_counter[2]), - .datad(fault_counter[0]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~3_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~3 .lut_mask = "8000"; -defparam \fault_flag~3 .operation_mode = "normal"; -defparam \fault_flag~3 .output_mode = "comb_only"; -defparam \fault_flag~3 .register_cascade_mode = "off"; -defparam \fault_flag~3 .sum_lutc_input = "datac"; -defparam \fault_flag~3 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y8_N8 -maxii_lcell \fault_flag~4 ( -// Equation(s): -// \fault_flag~4_combout = (fault_counter[7] & (fault_counter[6] & (fault_counter[4] & fault_counter[5]))) - - .clk(gnd), - .dataa(fault_counter[7]), - .datab(fault_counter[6]), - .datac(fault_counter[4]), - .datad(fault_counter[5]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~4_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~4 .lut_mask = "8000"; -defparam \fault_flag~4 .operation_mode = "normal"; -defparam \fault_flag~4 .output_mode = "comb_only"; -defparam \fault_flag~4 .register_cascade_mode = "off"; -defparam \fault_flag~4 .sum_lutc_input = "datac"; -defparam \fault_flag~4 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y8_N1 -maxii_lcell \fault_flag~5 ( -// Equation(s): -// \fault_flag~5_combout = (fault_counter[8]) # ((fault_counter[9]) # ((\fault_flag~3_combout & \fault_flag~4_combout ))) - - .clk(gnd), - .dataa(\fault_flag~3_combout ), - .datab(fault_counter[8]), - .datac(fault_counter[9]), - .datad(\fault_flag~4_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~5_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~5 .lut_mask = "fefc"; -defparam \fault_flag~5 .operation_mode = "normal"; -defparam \fault_flag~5 .output_mode = "comb_only"; -defparam \fault_flag~5 .register_cascade_mode = "off"; -defparam \fault_flag~5 .sum_lutc_input = "datac"; -defparam \fault_flag~5 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y8_N2 -maxii_lcell \fault_flag~8 ( -// Equation(s): -// \fault_flag~8_combout = ((\fault_flag~2_combout ) # ((\fault_flag~6_combout & \fault_flag~5_combout ))) # (!\fault_flag~7_combout ) - - .clk(gnd), - .dataa(\fault_flag~7_combout ), - .datab(\fault_flag~6_combout ), - .datac(\fault_flag~2_combout ), - .datad(\fault_flag~5_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~8_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~8 .lut_mask = "fdf5"; -defparam \fault_flag~8 .operation_mode = "normal"; -defparam \fault_flag~8 .output_mode = "comb_only"; -defparam \fault_flag~8 .register_cascade_mode = "off"; -defparam \fault_flag~8 .sum_lutc_input = "datac"; -defparam \fault_flag~8 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y8_N3 -maxii_lcell \fault_flag~9 ( -// Equation(s): -// \fault_flag~9_combout = (fault_counter[24] & (fault_counter[21] & (fault_counter[20] & \fault_flag~8_combout ))) - - .clk(gnd), - .dataa(fault_counter[24]), - .datab(fault_counter[21]), - .datac(fault_counter[20]), - .datad(\fault_flag~8_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~9_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~9 .lut_mask = "8000"; -defparam \fault_flag~9 .operation_mode = "normal"; -defparam \fault_flag~9 .output_mode = "comb_only"; -defparam \fault_flag~9 .register_cascade_mode = "off"; -defparam \fault_flag~9 .sum_lutc_input = "datac"; -defparam \fault_flag~9 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X3_Y8_N4 -maxii_lcell \fault_flag[1][0] ( -// Equation(s): -// \fault_flag[1][0]~regout = DFFEAS((!\Equal0~1 & ((\fault_flag~10_combout ) # ((\fault_flag~9_combout ) # (!\fault_counter[26]~68_combout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag~10_combout ), - .datab(\Equal0~1 ), - .datac(\fault_counter[26]~68_combout ), - .datad(\fault_flag~9_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\fault_flag[1][0]~regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag[1][0] .lut_mask = "3323"; -defparam \fault_flag[1][0] .operation_mode = "normal"; -defparam \fault_flag[1][0] .output_mode = "reg_only"; -defparam \fault_flag[1][0] .register_cascade_mode = "off"; -defparam \fault_flag[1][0] .sum_lutc_input = "datac"; -defparam \fault_flag[1][0] .synch_mode = "off"; -// synopsys translate_on - -// Location: PIN_39, I/O Standard: 3.3-V LVTTL, Current Strength: Default -maxii_io \line_sen~I ( - .datain(gnd), - .oe(gnd), - .combout(\line_sen~combout ), - .padio(line_sen)); -// synopsys translate_off -defparam \line_sen~I .operation_mode = "input"; -// synopsys translate_on - -// Location: LC_X7_Y7_N2 -maxii_lcell \cache_line_sen[0] ( -// Equation(s): -// \Equal1~1 = ((\line_sen~combout & (cache_line_sen[0] & \Equal1~0 ))) -// cache_line_sen[0] = DFFEAS(\Equal1~1 , GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , \line_sen~combout , , , VCC) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\line_sen~combout ), - .datac(\line_sen~combout ), - .datad(\Equal1~0 ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal1~1 ), - .regout(cache_line_sen[0]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sen[0] .lut_mask = "c000"; -defparam \cache_line_sen[0] .operation_mode = "normal"; -defparam \cache_line_sen[0] .output_mode = "reg_and_comb"; -defparam \cache_line_sen[0] .register_cascade_mode = "off"; -defparam \cache_line_sen[0] .sum_lutc_input = "qfbk"; -defparam \cache_line_sen[0] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y7_N8 -maxii_lcell \cache_line_sen[1] ( -// Equation(s): -// cache_line_sen[1] = DFFEAS((((cache_line_sen[0]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(cache_line_sen[0]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sen[1]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sen[1] .lut_mask = "ff00"; -defparam \cache_line_sen[1] .operation_mode = "normal"; -defparam \cache_line_sen[1] .output_mode = "reg_only"; -defparam \cache_line_sen[1] .register_cascade_mode = "off"; -defparam \cache_line_sen[1] .sum_lutc_input = "datac"; -defparam \cache_line_sen[1] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y7_N3 -maxii_lcell \cache_line_sen[2] ( -// Equation(s): -// cache_line_sen[2] = DFFEAS((((cache_line_sen[1]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(cache_line_sen[1]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sen[2]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sen[2] .lut_mask = "ff00"; -defparam \cache_line_sen[2] .operation_mode = "normal"; -defparam \cache_line_sen[2] .output_mode = "reg_only"; -defparam \cache_line_sen[2] .register_cascade_mode = "off"; -defparam \cache_line_sen[2] .sum_lutc_input = "datac"; -defparam \cache_line_sen[2] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y7_N1 -maxii_lcell \cache_line_sen[3] ( -// Equation(s): -// \Equal1~0 = (cache_line_sen[1] & (!cache_line_sen[4] & (cache_line_sen[3] & cache_line_sen[2]))) -// cache_line_sen[3] = DFFEAS(\Equal1~0 , GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , cache_line_sen[2], , , VCC) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sen[1]), - .datab(cache_line_sen[4]), - .datac(cache_line_sen[2]), - .datad(cache_line_sen[2]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal1~0 ), - .regout(cache_line_sen[3]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sen[3] .lut_mask = "2000"; -defparam \cache_line_sen[3] .operation_mode = "normal"; -defparam \cache_line_sen[3] .output_mode = "reg_and_comb"; -defparam \cache_line_sen[3] .register_cascade_mode = "off"; -defparam \cache_line_sen[3] .sum_lutc_input = "qfbk"; -defparam \cache_line_sen[3] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y7_N0 -maxii_lcell \cache_line_sen[4] ( -// Equation(s): -// \Equal2~0 = (!cache_line_sen[1] & (!cache_line_sen[3] & (cache_line_sen[4] & !cache_line_sen[2]))) -// cache_line_sen[4] = DFFEAS(\Equal2~0 , GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , cache_line_sen[3], , , VCC) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sen[1]), - .datab(cache_line_sen[3]), - .datac(cache_line_sen[3]), - .datad(cache_line_sen[2]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal2~0 ), - .regout(cache_line_sen[4]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sen[4] .lut_mask = "0010"; -defparam \cache_line_sen[4] .operation_mode = "normal"; -defparam \cache_line_sen[4] .output_mode = "reg_and_comb"; -defparam \cache_line_sen[4] .register_cascade_mode = "off"; -defparam \cache_line_sen[4] .sum_lutc_input = "qfbk"; -defparam \cache_line_sen[4] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y7_N6 -maxii_lcell negedge_line_sen( -// Equation(s): -// \Equal2~1 = ((!cache_line_sen[0] & (\Equal2~0 & !\line_sen~combout ))) -// \negedge_line_sen~regout = DFFEAS(\Equal2~1 , GLOBAL(\sys_clk~combout ), VCC, , \rst_n~combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache_line_sen[0]), - .datac(\Equal2~0 ), - .datad(\line_sen~combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\rst_n~combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal2~1 ), - .regout(\negedge_line_sen~regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam negedge_line_sen.lut_mask = "0030"; -defparam negedge_line_sen.operation_mode = "normal"; -defparam negedge_line_sen.output_mode = "reg_and_comb"; -defparam negedge_line_sen.register_cascade_mode = "off"; -defparam negedge_line_sen.sum_lutc_input = "datac"; -defparam negedge_line_sen.synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y7_N4 -maxii_lcell filter_line_sen( -// Equation(s): -// \filter_line_sen~regout = DFFEAS(((\Equal1~1 ) # ((\filter_line_sen~regout & !\Equal2~1 ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\filter_line_sen~regout ), - .datab(vcc), - .datac(\Equal1~1 ), - .datad(\Equal2~1 ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\filter_line_sen~regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam filter_line_sen.lut_mask = "f0fa"; -defparam filter_line_sen.operation_mode = "normal"; -defparam filter_line_sen.output_mode = "reg_only"; -defparam filter_line_sen.register_cascade_mode = "off"; -defparam filter_line_sen.sum_lutc_input = "datac"; -defparam filter_line_sen.synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y7_N7 -maxii_lcell \i[26]~69 ( -// Equation(s): -// \i[26]~69_combout = (\negedge_line_sen~regout ) # ((\cnt_for_high_voltage_time~128_combout ) # ((\posedge_line_sclk~regout & \filter_line_sen~regout ))) - - .clk(gnd), - .dataa(\posedge_line_sclk~regout ), - .datab(\filter_line_sen~regout ), - .datac(\negedge_line_sen~regout ), - .datad(\cnt_for_high_voltage_time~128_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\i[26]~69_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[26]~69 .lut_mask = "fff8"; -defparam \i[26]~69 .operation_mode = "normal"; -defparam \i[26]~69 .output_mode = "comb_only"; -defparam \i[26]~69 .register_cascade_mode = "off"; -defparam \i[26]~69 .sum_lutc_input = "datac"; -defparam \i[26]~69 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y10_N4 -maxii_lcell \i[0] ( -// Equation(s): -// i[0] = DFFEAS((!i[0]), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[0]~9 = CARRY((i[0])) - - .clk(\sys_clk~combout ), - .dataa(i[0]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[0]), - .cout(\i[0]~9 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[0] .lut_mask = "55aa"; -defparam \i[0] .operation_mode = "arithmetic"; -defparam \i[0] .output_mode = "reg_only"; -defparam \i[0] .register_cascade_mode = "off"; -defparam \i[0] .sum_lutc_input = "datac"; -defparam \i[0] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y10_N5 -maxii_lcell \i[1] ( -// Equation(s): -// i[1] = DFFEAS(i[1] $ ((((\i[0]~9 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[1]~11 = CARRY(((!\i[0]~9 )) # (!i[1])) -// \i[1]~11COUT1_71 = CARRY(((!\i[0]~9 )) # (!i[1])) - - .clk(\sys_clk~combout ), - .dataa(i[1]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[0]~9 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[1]), - .cout(), - .cout0(\i[1]~11 ), - .cout1(\i[1]~11COUT1_71 )); -// synopsys translate_off -defparam \i[1] .cin_used = "true"; -defparam \i[1] .lut_mask = "5a5f"; -defparam \i[1] .operation_mode = "arithmetic"; -defparam \i[1] .output_mode = "reg_only"; -defparam \i[1] .register_cascade_mode = "off"; -defparam \i[1] .sum_lutc_input = "cin"; -defparam \i[1] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y10_N6 -maxii_lcell \i[2] ( -// Equation(s): -// i[2] = DFFEAS(i[2] $ ((((!(!\i[0]~9 & \i[1]~11 ) # (\i[0]~9 & \i[1]~11COUT1_71 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[2]~13 = CARRY((i[2] & ((!\i[1]~11 )))) -// \i[2]~13COUT1_72 = CARRY((i[2] & ((!\i[1]~11COUT1_71 )))) - - .clk(\sys_clk~combout ), - .dataa(i[2]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[0]~9 ), - .cin0(\i[1]~11 ), - .cin1(\i[1]~11COUT1_71 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[2]), - .cout(), - .cout0(\i[2]~13 ), - .cout1(\i[2]~13COUT1_72 )); -// synopsys translate_off -defparam \i[2] .cin0_used = "true"; -defparam \i[2] .cin1_used = "true"; -defparam \i[2] .cin_used = "true"; -defparam \i[2] .lut_mask = "a50a"; -defparam \i[2] .operation_mode = "arithmetic"; -defparam \i[2] .output_mode = "reg_only"; -defparam \i[2] .register_cascade_mode = "off"; -defparam \i[2] .sum_lutc_input = "cin"; -defparam \i[2] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y10_N7 -maxii_lcell \i[3] ( -// Equation(s): -// i[3] = DFFEAS((i[3] $ (((!\i[0]~9 & \i[2]~13 ) # (\i[0]~9 & \i[2]~13COUT1_72 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[3]~15 = CARRY(((!\i[2]~13 ) # (!i[3]))) -// \i[3]~15COUT1_73 = CARRY(((!\i[2]~13COUT1_72 ) # (!i[3]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[3]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[0]~9 ), - .cin0(\i[2]~13 ), - .cin1(\i[2]~13COUT1_72 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[3]), - .cout(), - .cout0(\i[3]~15 ), - .cout1(\i[3]~15COUT1_73 )); -// synopsys translate_off -defparam \i[3] .cin0_used = "true"; -defparam \i[3] .cin1_used = "true"; -defparam \i[3] .cin_used = "true"; -defparam \i[3] .lut_mask = "3c3f"; -defparam \i[3] .operation_mode = "arithmetic"; -defparam \i[3] .output_mode = "reg_only"; -defparam \i[3] .register_cascade_mode = "off"; -defparam \i[3] .sum_lutc_input = "cin"; -defparam \i[3] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X5_Y10_N8 -maxii_lcell \i[4] ( -// Equation(s): -// i[4] = DFFEAS(i[4] $ ((((!(!\i[0]~9 & \i[3]~15 ) # (\i[0]~9 & \i[3]~15COUT1_73 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[4]~5 = CARRY((i[4] & ((!\i[3]~15 )))) -// \i[4]~5COUT1_74 = CARRY((i[4] & ((!\i[3]~15COUT1_73 )))) - - .clk(\sys_clk~combout ), - .dataa(i[4]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[0]~9 ), - .cin0(\i[3]~15 ), - .cin1(\i[3]~15COUT1_73 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[4]), - .cout(), - .cout0(\i[4]~5 ), - .cout1(\i[4]~5COUT1_74 )); -// synopsys translate_off -defparam \i[4] .cin0_used = "true"; -defparam \i[4] .cin1_used = "true"; -defparam \i[4] .cin_used = "true"; -defparam \i[4] .lut_mask = "a50a"; -defparam \i[4] .operation_mode = "arithmetic"; -defparam \i[4] .output_mode = "reg_only"; -defparam \i[4] .register_cascade_mode = "off"; -defparam \i[4] .sum_lutc_input = "cin"; -defparam \i[4] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X9_Y10_N3 -maxii_lcell posedge_line_sclk( -// Equation(s): -// \Decoder0~65 = (\filter_line_sen~regout & (!i[4] & (posedge_line_sclk & \recv_complete~9_combout ))) -// \posedge_line_sclk~regout = DFFEAS(\Decoder0~65 , GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , \Equal0~1 , , , VCC) - - .clk(\sys_clk~combout ), - .dataa(\filter_line_sen~regout ), - .datab(i[4]), - .datac(\Equal0~1 ), - .datad(\recv_complete~9_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~65 ), - .regout(\posedge_line_sclk~regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam posedge_line_sclk.lut_mask = "2000"; -defparam posedge_line_sclk.operation_mode = "normal"; -defparam posedge_line_sclk.output_mode = "reg_and_comb"; -defparam posedge_line_sclk.register_cascade_mode = "off"; -defparam posedge_line_sclk.sum_lutc_input = "qfbk"; -defparam posedge_line_sclk.synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y7_N9 -maxii_lcell \i[26]~68 ( -// Equation(s): -// \i[26]~68_combout = (\fault_flag[0][0]~regout ) # ((\fault_flag[1][0]~regout ) # ((!\filter_line_sen~regout ) # (!\posedge_line_sclk~regout ))) - - .clk(gnd), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(\posedge_line_sclk~regout ), - .datad(\filter_line_sen~regout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\i[26]~68_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[26]~68 .lut_mask = "efff"; -defparam \i[26]~68 .operation_mode = "normal"; -defparam \i[26]~68 .output_mode = "comb_only"; -defparam \i[26]~68 .register_cascade_mode = "off"; -defparam \i[26]~68 .sum_lutc_input = "datac"; -defparam \i[26]~68 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y10_N9 -maxii_lcell \i[5] ( -// Equation(s): -// i[5] = DFFEAS((i[5] $ (((!\i[0]~9 & \i[4]~5 ) # (\i[0]~9 & \i[4]~5COUT1_74 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[5]~7 = CARRY(((!\i[4]~5COUT1_74 ) # (!i[5]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[5]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[0]~9 ), - .cin0(\i[4]~5 ), - .cin1(\i[4]~5COUT1_74 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[5]), - .cout(\i[5]~7 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[5] .cin0_used = "true"; -defparam \i[5] .cin1_used = "true"; -defparam \i[5] .cin_used = "true"; -defparam \i[5] .lut_mask = "3c3f"; -defparam \i[5] .operation_mode = "arithmetic"; -defparam \i[5] .output_mode = "reg_only"; -defparam \i[5] .register_cascade_mode = "off"; -defparam \i[5] .sum_lutc_input = "cin"; -defparam \i[5] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N0 -maxii_lcell \i[6] ( -// Equation(s): -// i[6] = DFFEAS((i[6] $ ((!\i[5]~7 ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[6]~17 = CARRY(((i[6] & !\i[5]~7 ))) -// \i[6]~17COUT1_75 = CARRY(((i[6] & !\i[5]~7 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[6]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[5]~7 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[6]), - .cout(), - .cout0(\i[6]~17 ), - .cout1(\i[6]~17COUT1_75 )); -// synopsys translate_off -defparam \i[6] .cin_used = "true"; -defparam \i[6] .lut_mask = "c30c"; -defparam \i[6] .operation_mode = "arithmetic"; -defparam \i[6] .output_mode = "reg_only"; -defparam \i[6] .register_cascade_mode = "off"; -defparam \i[6] .sum_lutc_input = "cin"; -defparam \i[6] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N1 -maxii_lcell \i[7] ( -// Equation(s): -// i[7] = DFFEAS((i[7] $ (((!\i[5]~7 & \i[6]~17 ) # (\i[5]~7 & \i[6]~17COUT1_75 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[7]~19 = CARRY(((!\i[6]~17 ) # (!i[7]))) -// \i[7]~19COUT1_76 = CARRY(((!\i[6]~17COUT1_75 ) # (!i[7]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[7]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[5]~7 ), - .cin0(\i[6]~17 ), - .cin1(\i[6]~17COUT1_75 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[7]), - .cout(), - .cout0(\i[7]~19 ), - .cout1(\i[7]~19COUT1_76 )); -// synopsys translate_off -defparam \i[7] .cin0_used = "true"; -defparam \i[7] .cin1_used = "true"; -defparam \i[7] .cin_used = "true"; -defparam \i[7] .lut_mask = "3c3f"; -defparam \i[7] .operation_mode = "arithmetic"; -defparam \i[7] .output_mode = "reg_only"; -defparam \i[7] .register_cascade_mode = "off"; -defparam \i[7] .sum_lutc_input = "cin"; -defparam \i[7] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N2 -maxii_lcell \i[8] ( -// Equation(s): -// i[8] = DFFEAS((i[8] $ ((!(!\i[5]~7 & \i[7]~19 ) # (\i[5]~7 & \i[7]~19COUT1_76 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[8]~29 = CARRY(((i[8] & !\i[7]~19 ))) -// \i[8]~29COUT1_77 = CARRY(((i[8] & !\i[7]~19COUT1_76 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[8]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[5]~7 ), - .cin0(\i[7]~19 ), - .cin1(\i[7]~19COUT1_76 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[8]), - .cout(), - .cout0(\i[8]~29 ), - .cout1(\i[8]~29COUT1_77 )); -// synopsys translate_off -defparam \i[8] .cin0_used = "true"; -defparam \i[8] .cin1_used = "true"; -defparam \i[8] .cin_used = "true"; -defparam \i[8] .lut_mask = "c30c"; -defparam \i[8] .operation_mode = "arithmetic"; -defparam \i[8] .output_mode = "reg_only"; -defparam \i[8] .register_cascade_mode = "off"; -defparam \i[8] .sum_lutc_input = "cin"; -defparam \i[8] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N3 -maxii_lcell \i[9] ( -// Equation(s): -// i[9] = DFFEAS(i[9] $ (((((!\i[5]~7 & \i[8]~29 ) # (\i[5]~7 & \i[8]~29COUT1_77 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[9]~31 = CARRY(((!\i[8]~29 )) # (!i[9])) -// \i[9]~31COUT1_78 = CARRY(((!\i[8]~29COUT1_77 )) # (!i[9])) - - .clk(\sys_clk~combout ), - .dataa(i[9]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[5]~7 ), - .cin0(\i[8]~29 ), - .cin1(\i[8]~29COUT1_77 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[9]), - .cout(), - .cout0(\i[9]~31 ), - .cout1(\i[9]~31COUT1_78 )); -// synopsys translate_off -defparam \i[9] .cin0_used = "true"; -defparam \i[9] .cin1_used = "true"; -defparam \i[9] .cin_used = "true"; -defparam \i[9] .lut_mask = "5a5f"; -defparam \i[9] .operation_mode = "arithmetic"; -defparam \i[9] .output_mode = "reg_only"; -defparam \i[9] .register_cascade_mode = "off"; -defparam \i[9] .sum_lutc_input = "cin"; -defparam \i[9] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N4 -maxii_lcell \i[10] ( -// Equation(s): -// i[10] = DFFEAS(i[10] $ ((((!(!\i[5]~7 & \i[9]~31 ) # (\i[5]~7 & \i[9]~31COUT1_78 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[10]~21 = CARRY((i[10] & ((!\i[9]~31COUT1_78 )))) - - .clk(\sys_clk~combout ), - .dataa(i[10]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[5]~7 ), - .cin0(\i[9]~31 ), - .cin1(\i[9]~31COUT1_78 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[10]), - .cout(\i[10]~21 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[10] .cin0_used = "true"; -defparam \i[10] .cin1_used = "true"; -defparam \i[10] .cin_used = "true"; -defparam \i[10] .lut_mask = "a50a"; -defparam \i[10] .operation_mode = "arithmetic"; -defparam \i[10] .output_mode = "reg_only"; -defparam \i[10] .register_cascade_mode = "off"; -defparam \i[10] .sum_lutc_input = "cin"; -defparam \i[10] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N5 -maxii_lcell \i[11] ( -// Equation(s): -// i[11] = DFFEAS(i[11] $ ((((\i[10]~21 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[11]~23 = CARRY(((!\i[10]~21 )) # (!i[11])) -// \i[11]~23COUT1_79 = CARRY(((!\i[10]~21 )) # (!i[11])) - - .clk(\sys_clk~combout ), - .dataa(i[11]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[10]~21 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[11]), - .cout(), - .cout0(\i[11]~23 ), - .cout1(\i[11]~23COUT1_79 )); -// synopsys translate_off -defparam \i[11] .cin_used = "true"; -defparam \i[11] .lut_mask = "5a5f"; -defparam \i[11] .operation_mode = "arithmetic"; -defparam \i[11] .output_mode = "reg_only"; -defparam \i[11] .register_cascade_mode = "off"; -defparam \i[11] .sum_lutc_input = "cin"; -defparam \i[11] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N6 -maxii_lcell \i[12] ( -// Equation(s): -// i[12] = DFFEAS(i[12] $ ((((!(!\i[10]~21 & \i[11]~23 ) # (\i[10]~21 & \i[11]~23COUT1_79 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[12]~25 = CARRY((i[12] & ((!\i[11]~23 )))) -// \i[12]~25COUT1_80 = CARRY((i[12] & ((!\i[11]~23COUT1_79 )))) - - .clk(\sys_clk~combout ), - .dataa(i[12]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[10]~21 ), - .cin0(\i[11]~23 ), - .cin1(\i[11]~23COUT1_79 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[12]), - .cout(), - .cout0(\i[12]~25 ), - .cout1(\i[12]~25COUT1_80 )); -// synopsys translate_off -defparam \i[12] .cin0_used = "true"; -defparam \i[12] .cin1_used = "true"; -defparam \i[12] .cin_used = "true"; -defparam \i[12] .lut_mask = "a50a"; -defparam \i[12] .operation_mode = "arithmetic"; -defparam \i[12] .output_mode = "reg_only"; -defparam \i[12] .register_cascade_mode = "off"; -defparam \i[12] .sum_lutc_input = "cin"; -defparam \i[12] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N7 -maxii_lcell \i[13] ( -// Equation(s): -// i[13] = DFFEAS((i[13] $ (((!\i[10]~21 & \i[12]~25 ) # (\i[10]~21 & \i[12]~25COUT1_80 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[13]~27 = CARRY(((!\i[12]~25 ) # (!i[13]))) -// \i[13]~27COUT1_81 = CARRY(((!\i[12]~25COUT1_80 ) # (!i[13]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[13]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[10]~21 ), - .cin0(\i[12]~25 ), - .cin1(\i[12]~25COUT1_80 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[13]), - .cout(), - .cout0(\i[13]~27 ), - .cout1(\i[13]~27COUT1_81 )); -// synopsys translate_off -defparam \i[13] .cin0_used = "true"; -defparam \i[13] .cin1_used = "true"; -defparam \i[13] .cin_used = "true"; -defparam \i[13] .lut_mask = "3c3f"; -defparam \i[13] .operation_mode = "arithmetic"; -defparam \i[13] .output_mode = "reg_only"; -defparam \i[13] .register_cascade_mode = "off"; -defparam \i[13] .sum_lutc_input = "cin"; -defparam \i[13] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N8 -maxii_lcell \i[14] ( -// Equation(s): -// i[14] = DFFEAS(i[14] $ ((((!(!\i[10]~21 & \i[13]~27 ) # (\i[10]~21 & \i[13]~27COUT1_81 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[14]~33 = CARRY((i[14] & ((!\i[13]~27 )))) -// \i[14]~33COUT1_82 = CARRY((i[14] & ((!\i[13]~27COUT1_81 )))) - - .clk(\sys_clk~combout ), - .dataa(i[14]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[10]~21 ), - .cin0(\i[13]~27 ), - .cin1(\i[13]~27COUT1_81 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[14]), - .cout(), - .cout0(\i[14]~33 ), - .cout1(\i[14]~33COUT1_82 )); -// synopsys translate_off -defparam \i[14] .cin0_used = "true"; -defparam \i[14] .cin1_used = "true"; -defparam \i[14] .cin_used = "true"; -defparam \i[14] .lut_mask = "a50a"; -defparam \i[14] .operation_mode = "arithmetic"; -defparam \i[14] .output_mode = "reg_only"; -defparam \i[14] .register_cascade_mode = "off"; -defparam \i[14] .sum_lutc_input = "cin"; -defparam \i[14] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y10_N9 -maxii_lcell \i[15] ( -// Equation(s): -// i[15] = DFFEAS((i[15] $ (((!\i[10]~21 & \i[14]~33 ) # (\i[10]~21 & \i[14]~33COUT1_82 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[15]~35 = CARRY(((!\i[14]~33COUT1_82 ) # (!i[15]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[15]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[10]~21 ), - .cin0(\i[14]~33 ), - .cin1(\i[14]~33COUT1_82 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[15]), - .cout(\i[15]~35 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[15] .cin0_used = "true"; -defparam \i[15] .cin1_used = "true"; -defparam \i[15] .cin_used = "true"; -defparam \i[15] .lut_mask = "3c3f"; -defparam \i[15] .operation_mode = "arithmetic"; -defparam \i[15] .output_mode = "reg_only"; -defparam \i[15] .register_cascade_mode = "off"; -defparam \i[15] .sum_lutc_input = "cin"; -defparam \i[15] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y10_N0 -maxii_lcell \i[16] ( -// Equation(s): -// i[16] = DFFEAS((i[16] $ ((!\i[15]~35 ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[16]~37 = CARRY(((i[16] & !\i[15]~35 ))) -// \i[16]~37COUT1_83 = CARRY(((i[16] & !\i[15]~35 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[16]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[15]~35 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[16]), - .cout(), - .cout0(\i[16]~37 ), - .cout1(\i[16]~37COUT1_83 )); -// synopsys translate_off -defparam \i[16] .cin_used = "true"; -defparam \i[16] .lut_mask = "c30c"; -defparam \i[16] .operation_mode = "arithmetic"; -defparam \i[16] .output_mode = "reg_only"; -defparam \i[16] .register_cascade_mode = "off"; -defparam \i[16] .sum_lutc_input = "cin"; -defparam \i[16] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y10_N1 -maxii_lcell \i[17] ( -// Equation(s): -// i[17] = DFFEAS((i[17] $ (((!\i[15]~35 & \i[16]~37 ) # (\i[15]~35 & \i[16]~37COUT1_83 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[17]~39 = CARRY(((!\i[16]~37 ) # (!i[17]))) -// \i[17]~39COUT1_84 = CARRY(((!\i[16]~37COUT1_83 ) # (!i[17]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[17]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[15]~35 ), - .cin0(\i[16]~37 ), - .cin1(\i[16]~37COUT1_83 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[17]), - .cout(), - .cout0(\i[17]~39 ), - .cout1(\i[17]~39COUT1_84 )); -// synopsys translate_off -defparam \i[17] .cin0_used = "true"; -defparam \i[17] .cin1_used = "true"; -defparam \i[17] .cin_used = "true"; -defparam \i[17] .lut_mask = "3c3f"; -defparam \i[17] .operation_mode = "arithmetic"; -defparam \i[17] .output_mode = "reg_only"; -defparam \i[17] .register_cascade_mode = "off"; -defparam \i[17] .sum_lutc_input = "cin"; -defparam \i[17] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X9_Y10_N6 -maxii_lcell \recv_complete~4 ( -// Equation(s): -// \recv_complete~4_combout = (!i[15] & (!i[17] & (!i[14] & !i[16]))) - - .clk(gnd), - .dataa(i[15]), - .datab(i[17]), - .datac(i[14]), - .datad(i[16]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~4_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~4 .lut_mask = "0001"; -defparam \recv_complete~4 .operation_mode = "normal"; -defparam \recv_complete~4 .output_mode = "comb_only"; -defparam \recv_complete~4 .register_cascade_mode = "off"; -defparam \recv_complete~4 .sum_lutc_input = "datac"; -defparam \recv_complete~4 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y10_N2 -maxii_lcell \i[18] ( -// Equation(s): -// i[18] = DFFEAS((i[18] $ ((!(!\i[15]~35 & \i[17]~39 ) # (\i[15]~35 & \i[17]~39COUT1_84 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[18]~41 = CARRY(((i[18] & !\i[17]~39 ))) -// \i[18]~41COUT1_85 = CARRY(((i[18] & !\i[17]~39COUT1_84 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[18]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[15]~35 ), - .cin0(\i[17]~39 ), - .cin1(\i[17]~39COUT1_84 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[18]), - .cout(), - .cout0(\i[18]~41 ), - .cout1(\i[18]~41COUT1_85 )); -// synopsys translate_off -defparam \i[18] .cin0_used = "true"; -defparam \i[18] .cin1_used = "true"; -defparam \i[18] .cin_used = "true"; -defparam \i[18] .lut_mask = "c30c"; -defparam \i[18] .operation_mode = "arithmetic"; -defparam \i[18] .output_mode = "reg_only"; -defparam \i[18] .register_cascade_mode = "off"; -defparam \i[18] .sum_lutc_input = "cin"; -defparam \i[18] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y10_N3 -maxii_lcell \i[19] ( -// Equation(s): -// i[19] = DFFEAS(i[19] $ (((((!\i[15]~35 & \i[18]~41 ) # (\i[15]~35 & \i[18]~41COUT1_85 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[19]~43 = CARRY(((!\i[18]~41 )) # (!i[19])) -// \i[19]~43COUT1_86 = CARRY(((!\i[18]~41COUT1_85 )) # (!i[19])) - - .clk(\sys_clk~combout ), - .dataa(i[19]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[15]~35 ), - .cin0(\i[18]~41 ), - .cin1(\i[18]~41COUT1_85 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[19]), - .cout(), - .cout0(\i[19]~43 ), - .cout1(\i[19]~43COUT1_86 )); -// synopsys translate_off -defparam \i[19] .cin0_used = "true"; -defparam \i[19] .cin1_used = "true"; -defparam \i[19] .cin_used = "true"; -defparam \i[19] .lut_mask = "5a5f"; -defparam \i[19] .operation_mode = "arithmetic"; -defparam \i[19] .output_mode = "reg_only"; -defparam \i[19] .register_cascade_mode = "off"; -defparam \i[19] .sum_lutc_input = "cin"; -defparam \i[19] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y10_N4 -maxii_lcell \i[20] ( -// Equation(s): -// i[20] = DFFEAS(i[20] $ ((((!(!\i[15]~35 & \i[19]~43 ) # (\i[15]~35 & \i[19]~43COUT1_86 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[20]~45 = CARRY((i[20] & ((!\i[19]~43COUT1_86 )))) - - .clk(\sys_clk~combout ), - .dataa(i[20]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[15]~35 ), - .cin0(\i[19]~43 ), - .cin1(\i[19]~43COUT1_86 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[20]), - .cout(\i[20]~45 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[20] .cin0_used = "true"; -defparam \i[20] .cin1_used = "true"; -defparam \i[20] .cin_used = "true"; -defparam \i[20] .lut_mask = "a50a"; -defparam \i[20] .operation_mode = "arithmetic"; -defparam \i[20] .output_mode = "reg_only"; -defparam \i[20] .register_cascade_mode = "off"; -defparam \i[20] .sum_lutc_input = "cin"; -defparam \i[20] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y10_N5 -maxii_lcell \i[21] ( -// Equation(s): -// i[21] = DFFEAS(i[21] $ ((((\i[20]~45 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[21]~47 = CARRY(((!\i[20]~45 )) # (!i[21])) -// \i[21]~47COUT1_87 = CARRY(((!\i[20]~45 )) # (!i[21])) - - .clk(\sys_clk~combout ), - .dataa(i[21]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[20]~45 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[21]), - .cout(), - .cout0(\i[21]~47 ), - .cout1(\i[21]~47COUT1_87 )); -// synopsys translate_off -defparam \i[21] .cin_used = "true"; -defparam \i[21] .lut_mask = "5a5f"; -defparam \i[21] .operation_mode = "arithmetic"; -defparam \i[21] .output_mode = "reg_only"; -defparam \i[21] .register_cascade_mode = "off"; -defparam \i[21] .sum_lutc_input = "cin"; -defparam \i[21] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X8_Y10_N6 -maxii_lcell \recv_complete~5 ( -// Equation(s): -// \recv_complete~5_combout = (!i[21] & (!i[20] & (!i[19] & !i[18]))) - - .clk(gnd), - .dataa(i[21]), - .datab(i[20]), - .datac(i[19]), - .datad(i[18]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~5_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~5 .lut_mask = "0001"; -defparam \recv_complete~5 .operation_mode = "normal"; -defparam \recv_complete~5 .output_mode = "comb_only"; -defparam \recv_complete~5 .register_cascade_mode = "off"; -defparam \recv_complete~5 .sum_lutc_input = "datac"; -defparam \recv_complete~5 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y10_N4 -maxii_lcell \recv_complete~1 ( -// Equation(s): -// \recv_complete~1_combout = (((!i[7] & !i[6]))) - - .clk(gnd), - .dataa(vcc), - .datab(vcc), - .datac(i[7]), - .datad(i[6]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~1_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~1 .lut_mask = "000f"; -defparam \recv_complete~1 .operation_mode = "normal"; -defparam \recv_complete~1 .output_mode = "comb_only"; -defparam \recv_complete~1 .register_cascade_mode = "off"; -defparam \recv_complete~1 .sum_lutc_input = "datac"; -defparam \recv_complete~1 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y10_N9 -maxii_lcell \recv_complete~2 ( -// Equation(s): -// \recv_complete~2_combout = (!i[10] & (!i[12] & (!i[13] & !i[11]))) - - .clk(gnd), - .dataa(i[10]), - .datab(i[12]), - .datac(i[13]), - .datad(i[11]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~2_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~2 .lut_mask = "0001"; -defparam \recv_complete~2 .operation_mode = "normal"; -defparam \recv_complete~2 .output_mode = "comb_only"; -defparam \recv_complete~2 .register_cascade_mode = "off"; -defparam \recv_complete~2 .sum_lutc_input = "datac"; -defparam \recv_complete~2 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y10_N5 -maxii_lcell \recv_complete~3 ( -// Equation(s): -// \recv_complete~3_combout = (!i[8] & (!i[9] & (\recv_complete~1_combout & \recv_complete~2_combout ))) - - .clk(gnd), - .dataa(i[8]), - .datab(i[9]), - .datac(\recv_complete~1_combout ), - .datad(\recv_complete~2_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~3_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~3 .lut_mask = "1000"; -defparam \recv_complete~3 .operation_mode = "normal"; -defparam \recv_complete~3 .output_mode = "comb_only"; -defparam \recv_complete~3 .register_cascade_mode = "off"; -defparam \recv_complete~3 .sum_lutc_input = "datac"; -defparam \recv_complete~3 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y10_N6 -maxii_lcell \i[22] ( -// Equation(s): -// i[22] = DFFEAS(i[22] $ ((((!(!\i[20]~45 & \i[21]~47 ) # (\i[20]~45 & \i[21]~47COUT1_87 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[22]~49 = CARRY((i[22] & ((!\i[21]~47 )))) -// \i[22]~49COUT1_88 = CARRY((i[22] & ((!\i[21]~47COUT1_87 )))) - - .clk(\sys_clk~combout ), - .dataa(i[22]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[20]~45 ), - .cin0(\i[21]~47 ), - .cin1(\i[21]~47COUT1_87 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[22]), - .cout(), - .cout0(\i[22]~49 ), - .cout1(\i[22]~49COUT1_88 )); -// synopsys translate_off -defparam \i[22] .cin0_used = "true"; -defparam \i[22] .cin1_used = "true"; -defparam \i[22] .cin_used = "true"; -defparam \i[22] .lut_mask = "a50a"; -defparam \i[22] .operation_mode = "arithmetic"; -defparam \i[22] .output_mode = "reg_only"; -defparam \i[22] .register_cascade_mode = "off"; -defparam \i[22] .sum_lutc_input = "cin"; -defparam \i[22] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y10_N7 -maxii_lcell \i[23] ( -// Equation(s): -// i[23] = DFFEAS((i[23] $ (((!\i[20]~45 & \i[22]~49 ) # (\i[20]~45 & \i[22]~49COUT1_88 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[23]~51 = CARRY(((!\i[22]~49 ) # (!i[23]))) -// \i[23]~51COUT1_89 = CARRY(((!\i[22]~49COUT1_88 ) # (!i[23]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[23]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[20]~45 ), - .cin0(\i[22]~49 ), - .cin1(\i[22]~49COUT1_88 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[23]), - .cout(), - .cout0(\i[23]~51 ), - .cout1(\i[23]~51COUT1_89 )); -// synopsys translate_off -defparam \i[23] .cin0_used = "true"; -defparam \i[23] .cin1_used = "true"; -defparam \i[23] .cin_used = "true"; -defparam \i[23] .lut_mask = "3c3f"; -defparam \i[23] .operation_mode = "arithmetic"; -defparam \i[23] .output_mode = "reg_only"; -defparam \i[23] .register_cascade_mode = "off"; -defparam \i[23] .sum_lutc_input = "cin"; -defparam \i[23] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y10_N8 -maxii_lcell \i[24] ( -// Equation(s): -// i[24] = DFFEAS(i[24] $ ((((!(!\i[20]~45 & \i[23]~51 ) # (\i[20]~45 & \i[23]~51COUT1_89 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[24]~53 = CARRY((i[24] & ((!\i[23]~51 )))) -// \i[24]~53COUT1_90 = CARRY((i[24] & ((!\i[23]~51COUT1_89 )))) - - .clk(\sys_clk~combout ), - .dataa(i[24]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[20]~45 ), - .cin0(\i[23]~51 ), - .cin1(\i[23]~51COUT1_89 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[24]), - .cout(), - .cout0(\i[24]~53 ), - .cout1(\i[24]~53COUT1_90 )); -// synopsys translate_off -defparam \i[24] .cin0_used = "true"; -defparam \i[24] .cin1_used = "true"; -defparam \i[24] .cin_used = "true"; -defparam \i[24] .lut_mask = "a50a"; -defparam \i[24] .operation_mode = "arithmetic"; -defparam \i[24] .output_mode = "reg_only"; -defparam \i[24] .register_cascade_mode = "off"; -defparam \i[24] .sum_lutc_input = "cin"; -defparam \i[24] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X7_Y10_N9 -maxii_lcell \i[25] ( -// Equation(s): -// i[25] = DFFEAS((i[25] $ (((!\i[20]~45 & \i[24]~53 ) # (\i[20]~45 & \i[24]~53COUT1_90 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[25]~55 = CARRY(((!\i[24]~53COUT1_90 ) # (!i[25]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[25]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[20]~45 ), - .cin0(\i[24]~53 ), - .cin1(\i[24]~53COUT1_90 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[25]), - .cout(\i[25]~55 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[25] .cin0_used = "true"; -defparam \i[25] .cin1_used = "true"; -defparam \i[25] .cin_used = "true"; -defparam \i[25] .lut_mask = "3c3f"; -defparam \i[25] .operation_mode = "arithmetic"; -defparam \i[25] .output_mode = "reg_only"; -defparam \i[25] .register_cascade_mode = "off"; -defparam \i[25] .sum_lutc_input = "cin"; -defparam \i[25] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X8_Y10_N0 -maxii_lcell \i[26] ( -// Equation(s): -// i[26] = DFFEAS((i[26] $ ((!\i[25]~55 ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[26]~57 = CARRY(((i[26] & !\i[25]~55 ))) -// \i[26]~57COUT1_91 = CARRY(((i[26] & !\i[25]~55 ))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[26]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[25]~55 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[26]), - .cout(), - .cout0(\i[26]~57 ), - .cout1(\i[26]~57COUT1_91 )); -// synopsys translate_off -defparam \i[26] .cin_used = "true"; -defparam \i[26] .lut_mask = "c30c"; -defparam \i[26] .operation_mode = "arithmetic"; -defparam \i[26] .output_mode = "reg_only"; -defparam \i[26] .register_cascade_mode = "off"; -defparam \i[26] .sum_lutc_input = "cin"; -defparam \i[26] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X8_Y10_N1 -maxii_lcell \i[27] ( -// Equation(s): -// i[27] = DFFEAS((i[27] $ (((!\i[25]~55 & \i[26]~57 ) # (\i[25]~55 & \i[26]~57COUT1_91 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[27]~59 = CARRY(((!\i[26]~57 ) # (!i[27]))) -// \i[27]~59COUT1_92 = CARRY(((!\i[26]~57COUT1_91 ) # (!i[27]))) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(i[27]), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[25]~55 ), - .cin0(\i[26]~57 ), - .cin1(\i[26]~57COUT1_91 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[27]), - .cout(), - .cout0(\i[27]~59 ), - .cout1(\i[27]~59COUT1_92 )); -// synopsys translate_off -defparam \i[27] .cin0_used = "true"; -defparam \i[27] .cin1_used = "true"; -defparam \i[27] .cin_used = "true"; -defparam \i[27] .lut_mask = "3c3f"; -defparam \i[27] .operation_mode = "arithmetic"; -defparam \i[27] .output_mode = "reg_only"; -defparam \i[27] .register_cascade_mode = "off"; -defparam \i[27] .sum_lutc_input = "cin"; -defparam \i[27] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X8_Y10_N2 -maxii_lcell \i[28] ( -// Equation(s): -// i[28] = DFFEAS(i[28] $ ((((!(!\i[25]~55 & \i[27]~59 ) # (\i[25]~55 & \i[27]~59COUT1_92 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[28]~61 = CARRY((i[28] & ((!\i[27]~59 )))) -// \i[28]~61COUT1_93 = CARRY((i[28] & ((!\i[27]~59COUT1_92 )))) - - .clk(\sys_clk~combout ), - .dataa(i[28]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[25]~55 ), - .cin0(\i[27]~59 ), - .cin1(\i[27]~59COUT1_92 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[28]), - .cout(), - .cout0(\i[28]~61 ), - .cout1(\i[28]~61COUT1_93 )); -// synopsys translate_off -defparam \i[28] .cin0_used = "true"; -defparam \i[28] .cin1_used = "true"; -defparam \i[28] .cin_used = "true"; -defparam \i[28] .lut_mask = "a50a"; -defparam \i[28] .operation_mode = "arithmetic"; -defparam \i[28] .output_mode = "reg_only"; -defparam \i[28] .register_cascade_mode = "off"; -defparam \i[28] .sum_lutc_input = "cin"; -defparam \i[28] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X8_Y10_N3 -maxii_lcell \i[29] ( -// Equation(s): -// i[29] = DFFEAS(i[29] $ (((((!\i[25]~55 & \i[28]~61 ) # (\i[25]~55 & \i[28]~61COUT1_93 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[29]~63 = CARRY(((!\i[28]~61 )) # (!i[29])) -// \i[29]~63COUT1_94 = CARRY(((!\i[28]~61COUT1_93 )) # (!i[29])) - - .clk(\sys_clk~combout ), - .dataa(i[29]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[25]~55 ), - .cin0(\i[28]~61 ), - .cin1(\i[28]~61COUT1_93 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[29]), - .cout(), - .cout0(\i[29]~63 ), - .cout1(\i[29]~63COUT1_94 )); -// synopsys translate_off -defparam \i[29] .cin0_used = "true"; -defparam \i[29] .cin1_used = "true"; -defparam \i[29] .cin_used = "true"; -defparam \i[29] .lut_mask = "5a5f"; -defparam \i[29] .operation_mode = "arithmetic"; -defparam \i[29] .output_mode = "reg_only"; -defparam \i[29] .register_cascade_mode = "off"; -defparam \i[29] .sum_lutc_input = "cin"; -defparam \i[29] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X8_Y10_N4 -maxii_lcell \i[30] ( -// Equation(s): -// i[30] = DFFEAS(i[30] $ ((((!(!\i[25]~55 & \i[29]~63 ) # (\i[25]~55 & \i[29]~63COUT1_94 ))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) -// \i[30]~65 = CARRY((i[30] & ((!\i[29]~63COUT1_94 )))) - - .clk(\sys_clk~combout ), - .dataa(i[30]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[25]~55 ), - .cin0(\i[29]~63 ), - .cin1(\i[29]~63COUT1_94 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[30]), - .cout(\i[30]~65 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[30] .cin0_used = "true"; -defparam \i[30] .cin1_used = "true"; -defparam \i[30] .cin_used = "true"; -defparam \i[30] .lut_mask = "a50a"; -defparam \i[30] .operation_mode = "arithmetic"; -defparam \i[30] .output_mode = "reg_only"; -defparam \i[30] .register_cascade_mode = "off"; -defparam \i[30] .sum_lutc_input = "cin"; -defparam \i[30] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X8_Y10_N5 -maxii_lcell \i[31] ( -// Equation(s): -// i[31] = DFFEAS(i[31] $ ((((\i[30]~65 )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \i[26]~69_combout , , , \i[26]~68_combout , ) - - .clk(\sys_clk~combout ), - .dataa(i[31]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\i[26]~68_combout ), - .sload(gnd), - .ena(\i[26]~69_combout ), - .cin(\i[30]~65 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(i[31]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \i[31] .cin_used = "true"; -defparam \i[31] .lut_mask = "5a5a"; -defparam \i[31] .operation_mode = "normal"; -defparam \i[31] .output_mode = "reg_only"; -defparam \i[31] .register_cascade_mode = "off"; -defparam \i[31] .sum_lutc_input = "cin"; -defparam \i[31] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X8_Y10_N8 -maxii_lcell \recv_complete~7 ( -// Equation(s): -// \recv_complete~7_combout = (!i[28] & (!i[27] & (!i[26] & !i[29]))) - - .clk(gnd), - .dataa(i[28]), - .datab(i[27]), - .datac(i[26]), - .datad(i[29]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~7_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~7 .lut_mask = "0001"; -defparam \recv_complete~7 .operation_mode = "normal"; -defparam \recv_complete~7 .output_mode = "comb_only"; -defparam \recv_complete~7 .register_cascade_mode = "off"; -defparam \recv_complete~7 .sum_lutc_input = "datac"; -defparam \recv_complete~7 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y10_N7 -maxii_lcell \recv_complete~6 ( -// Equation(s): -// \recv_complete~6_combout = (!i[25] & (!i[22] & (!i[24] & !i[23]))) - - .clk(gnd), - .dataa(i[25]), - .datab(i[22]), - .datac(i[24]), - .datad(i[23]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~6_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~6 .lut_mask = "0001"; -defparam \recv_complete~6 .operation_mode = "normal"; -defparam \recv_complete~6 .output_mode = "comb_only"; -defparam \recv_complete~6 .register_cascade_mode = "off"; -defparam \recv_complete~6 .sum_lutc_input = "datac"; -defparam \recv_complete~6 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y10_N7 -maxii_lcell \recv_complete~8 ( -// Equation(s): -// \recv_complete~8_combout = (!i[31] & (!i[30] & (\recv_complete~7_combout & \recv_complete~6_combout ))) - - .clk(gnd), - .dataa(i[31]), - .datab(i[30]), - .datac(\recv_complete~7_combout ), - .datad(\recv_complete~6_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~8_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~8 .lut_mask = "1000"; -defparam \recv_complete~8 .operation_mode = "normal"; -defparam \recv_complete~8 .output_mode = "comb_only"; -defparam \recv_complete~8 .register_cascade_mode = "off"; -defparam \recv_complete~8 .sum_lutc_input = "datac"; -defparam \recv_complete~8 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y10_N8 -maxii_lcell \recv_complete~9 ( -// Equation(s): -// \recv_complete~9_combout = (\recv_complete~4_combout & (\recv_complete~5_combout & (\recv_complete~3_combout & \recv_complete~8_combout ))) - - .clk(gnd), - .dataa(\recv_complete~4_combout ), - .datab(\recv_complete~5_combout ), - .datac(\recv_complete~3_combout ), - .datad(\recv_complete~8_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~9_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~9 .lut_mask = "8000"; -defparam \recv_complete~9 .operation_mode = "normal"; -defparam \recv_complete~9 .output_mode = "comb_only"; -defparam \recv_complete~9 .register_cascade_mode = "off"; -defparam \recv_complete~9 .sum_lutc_input = "datac"; -defparam \recv_complete~9 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y10_N0 -maxii_lcell \recv_complete~0 ( -// Equation(s): -// \recv_complete~0_combout = (!i[1] & (!i[3] & (!i[2]))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[3]), - .datac(i[2]), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~0_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~0 .lut_mask = "0101"; -defparam \recv_complete~0 .operation_mode = "normal"; -defparam \recv_complete~0 .output_mode = "comb_only"; -defparam \recv_complete~0 .register_cascade_mode = "off"; -defparam \recv_complete~0 .sum_lutc_input = "datac"; -defparam \recv_complete~0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y10_N2 -maxii_lcell \fault_flag~0 ( -// Equation(s): -// \fault_flag~0_combout = (i[5] & (i[4] & ((i[0]) # (!\recv_complete~0_combout )))) - - .clk(gnd), - .dataa(i[0]), - .datab(i[5]), - .datac(\recv_complete~0_combout ), - .datad(i[4]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\fault_flag~0_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag~0 .lut_mask = "8c00"; -defparam \fault_flag~0 .operation_mode = "normal"; -defparam \fault_flag~0 .output_mode = "comb_only"; -defparam \fault_flag~0 .register_cascade_mode = "off"; -defparam \fault_flag~0 .sum_lutc_input = "datac"; -defparam \fault_flag~0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N1 -maxii_lcell \fault_flag[0][0] ( -// Equation(s): -// \fault_flag[0][0]~regout = DFFEAS(((\fault_flag~0_combout ) # ((!\Equal1~1 & \fault_flag[0][0]~regout ))) # (!\recv_complete~9_combout ), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\Equal1~1 ), - .datab(\fault_flag[0][0]~regout ), - .datac(\recv_complete~9_combout ), - .datad(\fault_flag~0_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\fault_flag[0][0]~regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \fault_flag[0][0] .lut_mask = "ff4f"; -defparam \fault_flag[0][0] .operation_mode = "normal"; -defparam \fault_flag[0][0] .output_mode = "reg_only"; -defparam \fault_flag[0][0] .register_cascade_mode = "off"; -defparam \fault_flag[0][0] .sum_lutc_input = "datac"; -defparam \fault_flag[0][0] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N5 -maxii_lcell \cnt_for_high_voltage_time~128 ( -// Equation(s): -// \cnt_for_high_voltage_time~128_combout = ((\fault_flag[0][0]~regout ) # ((\fault_flag[1][0]~regout ))) - - .clk(gnd), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(vcc), - .datad(\fault_flag[1][0]~regout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\cnt_for_high_voltage_time~128_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time~128 .lut_mask = "ffcc"; -defparam \cnt_for_high_voltage_time~128 .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time~128 .output_mode = "comb_only"; -defparam \cnt_for_high_voltage_time~128 .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time~128 .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time~128 .synch_mode = "off"; -// synopsys translate_on - -// Location: PIN_41, I/O Standard: 3.3-V LVTTL, Current Strength: Default -maxii_io \line_sdata~I ( - .datain(gnd), - .oe(gnd), - .combout(\line_sdata~combout ), - .padio(line_sdata)); -// synopsys translate_off -defparam \line_sdata~I .operation_mode = "input"; -// synopsys translate_on - -// Location: LC_X6_Y5_N6 -maxii_lcell \tmp_cache_line_sdata[0] ( -// Equation(s): -// tmp_cache_line_sdata[0] = DFFEAS((((!\line_sdata~combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(\line_sdata~combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(tmp_cache_line_sdata[0]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \tmp_cache_line_sdata[0] .lut_mask = "00ff"; -defparam \tmp_cache_line_sdata[0] .operation_mode = "normal"; -defparam \tmp_cache_line_sdata[0] .output_mode = "reg_only"; -defparam \tmp_cache_line_sdata[0] .register_cascade_mode = "off"; -defparam \tmp_cache_line_sdata[0] .sum_lutc_input = "datac"; -defparam \tmp_cache_line_sdata[0] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y5_N4 -maxii_lcell \tmp_cache_line_sdata[1] ( -// Equation(s): -// tmp_cache_line_sdata[1] = DFFEAS(GND, GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , tmp_cache_line_sdata[0], , , VCC) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(tmp_cache_line_sdata[0]), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(tmp_cache_line_sdata[1]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \tmp_cache_line_sdata[1] .lut_mask = "0000"; -defparam \tmp_cache_line_sdata[1] .operation_mode = "normal"; -defparam \tmp_cache_line_sdata[1] .output_mode = "reg_only"; -defparam \tmp_cache_line_sdata[1] .register_cascade_mode = "off"; -defparam \tmp_cache_line_sdata[1] .sum_lutc_input = "datac"; -defparam \tmp_cache_line_sdata[1] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y5_N2 -maxii_lcell \tmp_cache_line_sdata[2] ( -// Equation(s): -// tmp_cache_line_sdata[2] = DFFEAS(GND, GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , tmp_cache_line_sdata[1], , , VCC) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(tmp_cache_line_sdata[1]), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(tmp_cache_line_sdata[2]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \tmp_cache_line_sdata[2] .lut_mask = "0000"; -defparam \tmp_cache_line_sdata[2] .operation_mode = "normal"; -defparam \tmp_cache_line_sdata[2] .output_mode = "reg_only"; -defparam \tmp_cache_line_sdata[2] .register_cascade_mode = "off"; -defparam \tmp_cache_line_sdata[2] .sum_lutc_input = "datac"; -defparam \tmp_cache_line_sdata[2] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X6_Y5_N8 -maxii_lcell \tmp_cache_line_sdata[3] ( -// Equation(s): -// tmp_cache_line_sdata[3] = DFFEAS((((tmp_cache_line_sdata[2]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(tmp_cache_line_sdata[2]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(tmp_cache_line_sdata[3]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \tmp_cache_line_sdata[3] .lut_mask = "ff00"; -defparam \tmp_cache_line_sdata[3] .operation_mode = "normal"; -defparam \tmp_cache_line_sdata[3] .output_mode = "reg_only"; -defparam \tmp_cache_line_sdata[3] .register_cascade_mode = "off"; -defparam \tmp_cache_line_sdata[3] .sum_lutc_input = "datac"; -defparam \tmp_cache_line_sdata[3] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y5_N5 -maxii_lcell \tmp_cache_line_sdata[4] ( -// Equation(s): -// tmp_cache_line_sdata[4] = DFFEAS((((tmp_cache_line_sdata[3]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(tmp_cache_line_sdata[3]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(tmp_cache_line_sdata[4]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \tmp_cache_line_sdata[4] .lut_mask = "ff00"; -defparam \tmp_cache_line_sdata[4] .operation_mode = "normal"; -defparam \tmp_cache_line_sdata[4] .output_mode = "reg_only"; -defparam \tmp_cache_line_sdata[4] .register_cascade_mode = "off"; -defparam \tmp_cache_line_sdata[4] .sum_lutc_input = "datac"; -defparam \tmp_cache_line_sdata[4] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y6_N3 -maxii_lcell fiter_line_sdata( -// Equation(s): -// \fiter_line_sdata~regout = DFFEAS((((!tmp_cache_line_sdata[4]))), GLOBAL(\sys_clk~combout ), VCC, , \rst_n~combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(tmp_cache_line_sdata[4]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\rst_n~combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\fiter_line_sdata~regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam fiter_line_sdata.lut_mask = "00ff"; -defparam fiter_line_sdata.operation_mode = "normal"; -defparam fiter_line_sdata.output_mode = "reg_only"; -defparam fiter_line_sdata.register_cascade_mode = "off"; -defparam fiter_line_sdata.sum_lutc_input = "datac"; -defparam fiter_line_sdata.synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N9 -maxii_lcell \Decoder0~101 ( -// Equation(s): -// \Decoder0~101_combout = (!i[5] & (\recv_complete~0_combout & (!i[0] & \Decoder0~65 ))) - - .clk(gnd), - .dataa(i[5]), - .datab(\recv_complete~0_combout ), - .datac(i[0]), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~101_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~101 .lut_mask = "0400"; -defparam \Decoder0~101 .operation_mode = "normal"; -defparam \Decoder0~101 .output_mode = "comb_only"; -defparam \Decoder0~101 .register_cascade_mode = "off"; -defparam \Decoder0~101 .sum_lutc_input = "datac"; -defparam \Decoder0~101 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N0 -maxii_lcell \cache_line_sdata[0] ( -// Equation(s): -// cache_line_sdata[0] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~101_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~101_combout & ((cache_line_sdata[0]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(\fiter_line_sdata~regout ), - .datac(cache_line_sdata[0]), - .datad(\Decoder0~101_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[0]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[0] .lut_mask = "1150"; -defparam \cache_line_sdata[0] .operation_mode = "normal"; -defparam \cache_line_sdata[0] .output_mode = "reg_only"; -defparam \cache_line_sdata[0] .register_cascade_mode = "off"; -defparam \cache_line_sdata[0] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[0] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N3 -maxii_lcell \recv_complete~10 ( -// Equation(s): -// \recv_complete~10_combout = ((!i[0] & ((i[5])))) - - .clk(gnd), - .dataa(vcc), - .datab(i[0]), - .datac(vcc), - .datad(i[5]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~10_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~10 .lut_mask = "3300"; -defparam \recv_complete~10 .operation_mode = "normal"; -defparam \recv_complete~10 .output_mode = "comb_only"; -defparam \recv_complete~10 .register_cascade_mode = "off"; -defparam \recv_complete~10 .sum_lutc_input = "datac"; -defparam \recv_complete~10 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N4 -maxii_lcell \recv_complete~11 ( -// Equation(s): -// \recv_complete~11_combout = (\negedge_line_sen~regout & (\recv_complete~0_combout & (i[4] & \recv_complete~10_combout ))) - - .clk(gnd), - .dataa(\negedge_line_sen~regout ), - .datab(\recv_complete~0_combout ), - .datac(i[4]), - .datad(\recv_complete~10_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\recv_complete~11_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \recv_complete~11 .lut_mask = "8000"; -defparam \recv_complete~11 .operation_mode = "normal"; -defparam \recv_complete~11 .output_mode = "comb_only"; -defparam \recv_complete~11 .register_cascade_mode = "off"; -defparam \recv_complete~11 .sum_lutc_input = "datac"; -defparam \recv_complete~11 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N7 -maxii_lcell \cache2_line_sdata[45]~50 ( -// Equation(s): -// \cache2_line_sdata[45]~50_combout = (\fault_flag[1][0]~regout ) # ((\fault_flag[0][0]~regout ) # ((\recv_complete~11_combout & \recv_complete~9_combout ))) - - .clk(gnd), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\recv_complete~11_combout ), - .datad(\recv_complete~9_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\cache2_line_sdata[45]~50_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[45]~50 .lut_mask = "feee"; -defparam \cache2_line_sdata[45]~50 .operation_mode = "normal"; -defparam \cache2_line_sdata[45]~50 .output_mode = "comb_only"; -defparam \cache2_line_sdata[45]~50 .register_cascade_mode = "off"; -defparam \cache2_line_sdata[45]~50 .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[45]~50 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N8 -maxii_lcell \cache2_line_sdata[0] ( -// Equation(s): -// cache2_line_sdata[0] = DFFEAS((cache_line_sdata[0] & (((!\fault_flag[1][0]~regout & !\fault_flag[0][0]~regout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[0]), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[0]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[0] .lut_mask = "000a"; -defparam \cache2_line_sdata[0] .operation_mode = "normal"; -defparam \cache2_line_sdata[0] .output_mode = "reg_only"; -defparam \cache2_line_sdata[0] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[0] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[0] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N6 -maxii_lcell enable_count_high_voltage_time( -// Equation(s): -// \enable_count_high_voltage_time~regout = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & (\recv_complete~9_combout & \recv_complete~11_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(\recv_complete~9_combout ), - .datad(\recv_complete~11_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\enable_count_high_voltage_time~regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam enable_count_high_voltage_time.lut_mask = "1000"; -defparam enable_count_high_voltage_time.operation_mode = "normal"; -defparam enable_count_high_voltage_time.output_mode = "reg_only"; -defparam enable_count_high_voltage_time.register_cascade_mode = "off"; -defparam enable_count_high_voltage_time.sum_lutc_input = "datac"; -defparam enable_count_high_voltage_time.synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y6_N8 -maxii_lcell \cache_enable_count_high_voltage_time[0] ( -// Equation(s): -// cache_enable_count_high_voltage_time[0] = DFFEAS((((\enable_count_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(\enable_count_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_enable_count_high_voltage_time[0]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_enable_count_high_voltage_time[0] .lut_mask = "ff00"; -defparam \cache_enable_count_high_voltage_time[0] .operation_mode = "normal"; -defparam \cache_enable_count_high_voltage_time[0] .output_mode = "reg_only"; -defparam \cache_enable_count_high_voltage_time[0] .register_cascade_mode = "off"; -defparam \cache_enable_count_high_voltage_time[0] .sum_lutc_input = "datac"; -defparam \cache_enable_count_high_voltage_time[0] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y6_N3 -maxii_lcell \cache_enable_count_high_voltage_time[1] ( -// Equation(s): -// posedge_enable_count_high_voltage_time = (((cache_enable_count_high_voltage_time[1]) # (!cache_enable_count_high_voltage_time[0]))) -// cache_enable_count_high_voltage_time[1] = DFFEAS(posedge_enable_count_high_voltage_time, GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , cache_enable_count_high_voltage_time[0], , , VCC) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(vcc), - .datac(cache_enable_count_high_voltage_time[0]), - .datad(cache_enable_count_high_voltage_time[0]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(posedge_enable_count_high_voltage_time), - .regout(cache_enable_count_high_voltage_time[1]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_enable_count_high_voltage_time[1] .lut_mask = "f0ff"; -defparam \cache_enable_count_high_voltage_time[1] .operation_mode = "normal"; -defparam \cache_enable_count_high_voltage_time[1] .output_mode = "reg_and_comb"; -defparam \cache_enable_count_high_voltage_time[1] .register_cascade_mode = "off"; -defparam \cache_enable_count_high_voltage_time[1] .sum_lutc_input = "qfbk"; -defparam \cache_enable_count_high_voltage_time[1] .synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X12_Y5_N4 -maxii_lcell \Add2~0 ( -// Equation(s): -// \Add2~0_combout = ((!cnt_for_high_voltage_time[0])) -// \Add2~2 = CARRY(((cnt_for_high_voltage_time[0]))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[0]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~0_combout ), - .regout(), - .cout(\Add2~2 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Add2~0 .lut_mask = "33cc"; -defparam \Add2~0 .operation_mode = "arithmetic"; -defparam \Add2~0 .output_mode = "comb_only"; -defparam \Add2~0 .register_cascade_mode = "off"; -defparam \Add2~0 .sum_lutc_input = "datac"; -defparam \Add2~0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N0 -maxii_lcell \cnt_for_high_voltage_time[18]~129 ( -// Equation(s): -// \cnt_for_high_voltage_time[18]~129_combout = ((cnt_for_high_voltage_time[0]) # ((\cnt_for_high_voltage_time~128_combout ) # (!\Equal4~9_combout ))) # (!posedge_enable_count_high_voltage_time) - - .clk(gnd), - .dataa(posedge_enable_count_high_voltage_time), - .datab(cnt_for_high_voltage_time[0]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Equal4~9_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\cnt_for_high_voltage_time[18]~129_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[18]~129 .lut_mask = "fdff"; -defparam \cnt_for_high_voltage_time[18]~129 .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[18]~129 .output_mode = "comb_only"; -defparam \cnt_for_high_voltage_time[18]~129 .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[18]~129 .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[18]~129 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y5_N1 -maxii_lcell \cnt_for_high_voltage_time[0] ( -// Equation(s): -// cnt_for_high_voltage_time[0] = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & ((\Add2~0_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\Add2~0_combout ), - .datad(posedge_enable_count_high_voltage_time), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[0]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[0] .lut_mask = "1011"; -defparam \cnt_for_high_voltage_time[0] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[0] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[0] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[0] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[0] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y5_N5 -maxii_lcell \Add2~155 ( -// Equation(s): -// \Add2~155_combout = cnt_for_high_voltage_time[1] $ ((((!\Add2~2 )))) -// \Add2~157 = CARRY((!cnt_for_high_voltage_time[1] & ((!\Add2~2 )))) -// \Add2~157COUT1_161 = CARRY((!cnt_for_high_voltage_time[1] & ((!\Add2~2 )))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[1]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~2 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~155_combout ), - .regout(), - .cout(), - .cout0(\Add2~157 ), - .cout1(\Add2~157COUT1_161 )); -// synopsys translate_off -defparam \Add2~155 .cin_used = "true"; -defparam \Add2~155 .lut_mask = "a505"; -defparam \Add2~155 .operation_mode = "arithmetic"; -defparam \Add2~155 .output_mode = "comb_only"; -defparam \Add2~155 .register_cascade_mode = "off"; -defparam \Add2~155 .sum_lutc_input = "cin"; -defparam \Add2~155 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y5_N3 -maxii_lcell \cnt_for_high_voltage_time[1] ( -// Equation(s): -// cnt_for_high_voltage_time[1] = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & ((\Add2~155_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\Add2~155_combout ), - .datad(posedge_enable_count_high_voltage_time), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[1]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[1] .lut_mask = "1011"; -defparam \cnt_for_high_voltage_time[1] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[1] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[1] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[1] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[1] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y5_N6 -maxii_lcell \Add2~150 ( -// Equation(s): -// \Add2~150_combout = cnt_for_high_voltage_time[2] $ (((((!\Add2~2 & \Add2~157 ) # (\Add2~2 & \Add2~157COUT1_161 ))))) -// \Add2~152 = CARRY((cnt_for_high_voltage_time[2]) # ((!\Add2~157 ))) -// \Add2~152COUT1_162 = CARRY((cnt_for_high_voltage_time[2]) # ((!\Add2~157COUT1_161 ))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[2]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~2 ), - .cin0(\Add2~157 ), - .cin1(\Add2~157COUT1_161 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~150_combout ), - .regout(), - .cout(), - .cout0(\Add2~152 ), - .cout1(\Add2~152COUT1_162 )); -// synopsys translate_off -defparam \Add2~150 .cin0_used = "true"; -defparam \Add2~150 .cin1_used = "true"; -defparam \Add2~150 .cin_used = "true"; -defparam \Add2~150 .lut_mask = "5aaf"; -defparam \Add2~150 .operation_mode = "arithmetic"; -defparam \Add2~150 .output_mode = "comb_only"; -defparam \Add2~150 .register_cascade_mode = "off"; -defparam \Add2~150 .sum_lutc_input = "cin"; -defparam \Add2~150 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N9 -maxii_lcell \cnt_for_high_voltage_time[2] ( -// Equation(s): -// cnt_for_high_voltage_time[2] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((\Add2~150_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\Add2~150_combout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(posedge_enable_count_high_voltage_time), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[2]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[2] .lut_mask = "0203"; -defparam \cnt_for_high_voltage_time[2] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[2] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[2] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[2] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[2] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y5_N7 -maxii_lcell \Add2~145 ( -// Equation(s): -// \Add2~145_combout = (cnt_for_high_voltage_time[3] $ ((!(!\Add2~2 & \Add2~152 ) # (\Add2~2 & \Add2~152COUT1_162 )))) -// \Add2~147 = CARRY(((!cnt_for_high_voltage_time[3] & !\Add2~152 ))) -// \Add2~147COUT1_163 = CARRY(((!cnt_for_high_voltage_time[3] & !\Add2~152COUT1_162 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[3]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~2 ), - .cin0(\Add2~152 ), - .cin1(\Add2~152COUT1_162 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~145_combout ), - .regout(), - .cout(), - .cout0(\Add2~147 ), - .cout1(\Add2~147COUT1_163 )); -// synopsys translate_off -defparam \Add2~145 .cin0_used = "true"; -defparam \Add2~145 .cin1_used = "true"; -defparam \Add2~145 .cin_used = "true"; -defparam \Add2~145 .lut_mask = "c303"; -defparam \Add2~145 .operation_mode = "arithmetic"; -defparam \Add2~145 .output_mode = "comb_only"; -defparam \Add2~145 .register_cascade_mode = "off"; -defparam \Add2~145 .sum_lutc_input = "cin"; -defparam \Add2~145 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N4 -maxii_lcell \cnt_for_high_voltage_time[3] ( -// Equation(s): -// cnt_for_high_voltage_time[3] = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & ((\Add2~145_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\Add2~145_combout ), - .datab(\fault_flag[1][0]~regout ), - .datac(posedge_enable_count_high_voltage_time), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[3]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[3] .lut_mask = "0023"; -defparam \cnt_for_high_voltage_time[3] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[3] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[3] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[3] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[3] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y5_N8 -maxii_lcell \Add2~140 ( -// Equation(s): -// \Add2~140_combout = (cnt_for_high_voltage_time[4] $ (((!\Add2~2 & \Add2~147 ) # (\Add2~2 & \Add2~147COUT1_163 )))) -// \Add2~142 = CARRY(((cnt_for_high_voltage_time[4]) # (!\Add2~147 ))) -// \Add2~142COUT1_164 = CARRY(((cnt_for_high_voltage_time[4]) # (!\Add2~147COUT1_163 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[4]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~2 ), - .cin0(\Add2~147 ), - .cin1(\Add2~147COUT1_163 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~140_combout ), - .regout(), - .cout(), - .cout0(\Add2~142 ), - .cout1(\Add2~142COUT1_164 )); -// synopsys translate_off -defparam \Add2~140 .cin0_used = "true"; -defparam \Add2~140 .cin1_used = "true"; -defparam \Add2~140 .cin_used = "true"; -defparam \Add2~140 .lut_mask = "3ccf"; -defparam \Add2~140 .operation_mode = "arithmetic"; -defparam \Add2~140 .output_mode = "comb_only"; -defparam \Add2~140 .register_cascade_mode = "off"; -defparam \Add2~140 .sum_lutc_input = "cin"; -defparam \Add2~140 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N7 -maxii_lcell \cnt_for_high_voltage_time[4] ( -// Equation(s): -// cnt_for_high_voltage_time[4] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((\Add2~140_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\Add2~140_combout ), - .datab(\fault_flag[0][0]~regout ), - .datac(posedge_enable_count_high_voltage_time), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[4]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[4] .lut_mask = "0023"; -defparam \cnt_for_high_voltage_time[4] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[4] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[4] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[4] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[4] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y5_N9 -maxii_lcell \Add2~135 ( -// Equation(s): -// \Add2~135_combout = (cnt_for_high_voltage_time[5] $ ((!(!\Add2~2 & \Add2~142 ) # (\Add2~2 & \Add2~142COUT1_164 )))) -// \Add2~137 = CARRY(((!cnt_for_high_voltage_time[5] & !\Add2~142COUT1_164 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[5]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~2 ), - .cin0(\Add2~142 ), - .cin1(\Add2~142COUT1_164 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~135_combout ), - .regout(), - .cout(\Add2~137 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Add2~135 .cin0_used = "true"; -defparam \Add2~135 .cin1_used = "true"; -defparam \Add2~135 .cin_used = "true"; -defparam \Add2~135 .lut_mask = "c303"; -defparam \Add2~135 .operation_mode = "arithmetic"; -defparam \Add2~135 .output_mode = "comb_only"; -defparam \Add2~135 .register_cascade_mode = "off"; -defparam \Add2~135 .sum_lutc_input = "cin"; -defparam \Add2~135 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N6 -maxii_lcell \cnt_for_high_voltage_time[5] ( -// Equation(s): -// cnt_for_high_voltage_time[5] = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & ((\Add2~135_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(posedge_enable_count_high_voltage_time), - .datad(\Add2~135_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[5]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[5] .lut_mask = "1101"; -defparam \cnt_for_high_voltage_time[5] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[5] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[5] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[5] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[5] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N0 -maxii_lcell \Add2~130 ( -// Equation(s): -// \Add2~130_combout = (cnt_for_high_voltage_time[6] $ ((\Add2~137 ))) -// \Add2~132 = CARRY(((cnt_for_high_voltage_time[6]) # (!\Add2~137 ))) -// \Add2~132COUT1_165 = CARRY(((cnt_for_high_voltage_time[6]) # (!\Add2~137 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[6]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~137 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~130_combout ), - .regout(), - .cout(), - .cout0(\Add2~132 ), - .cout1(\Add2~132COUT1_165 )); -// synopsys translate_off -defparam \Add2~130 .cin_used = "true"; -defparam \Add2~130 .lut_mask = "3ccf"; -defparam \Add2~130 .operation_mode = "arithmetic"; -defparam \Add2~130 .output_mode = "comb_only"; -defparam \Add2~130 .register_cascade_mode = "off"; -defparam \Add2~130 .sum_lutc_input = "cin"; -defparam \Add2~130 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y5_N2 -maxii_lcell \cnt_for_high_voltage_time[6] ( -// Equation(s): -// cnt_for_high_voltage_time[6] = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & (\Add2~130_combout & posedge_enable_count_high_voltage_time))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\Add2~130_combout ), - .datad(posedge_enable_count_high_voltage_time), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[6]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[6] .lut_mask = "1000"; -defparam \cnt_for_high_voltage_time[6] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[6] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[6] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[6] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[6] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N1 -maxii_lcell \Add2~125 ( -// Equation(s): -// \Add2~125_combout = cnt_for_high_voltage_time[7] $ ((((!(!\Add2~137 & \Add2~132 ) # (\Add2~137 & \Add2~132COUT1_165 ))))) -// \Add2~127 = CARRY((!cnt_for_high_voltage_time[7] & ((!\Add2~132 )))) -// \Add2~127COUT1_166 = CARRY((!cnt_for_high_voltage_time[7] & ((!\Add2~132COUT1_165 )))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[7]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~137 ), - .cin0(\Add2~132 ), - .cin1(\Add2~132COUT1_165 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~125_combout ), - .regout(), - .cout(), - .cout0(\Add2~127 ), - .cout1(\Add2~127COUT1_166 )); -// synopsys translate_off -defparam \Add2~125 .cin0_used = "true"; -defparam \Add2~125 .cin1_used = "true"; -defparam \Add2~125 .cin_used = "true"; -defparam \Add2~125 .lut_mask = "a505"; -defparam \Add2~125 .operation_mode = "arithmetic"; -defparam \Add2~125 .output_mode = "comb_only"; -defparam \Add2~125 .register_cascade_mode = "off"; -defparam \Add2~125 .sum_lutc_input = "cin"; -defparam \Add2~125 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y5_N0 -maxii_lcell \cnt_for_high_voltage_time[7] ( -// Equation(s): -// cnt_for_high_voltage_time[7] = DFFEAS((!\fault_flag[1][0]~regout & (posedge_enable_count_high_voltage_time & (!\fault_flag[0][0]~regout & \Add2~125_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(posedge_enable_count_high_voltage_time), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~125_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[7]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[7] .lut_mask = "0400"; -defparam \cnt_for_high_voltage_time[7] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[7] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[7] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[7] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[7] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N2 -maxii_lcell \Add2~120 ( -// Equation(s): -// \Add2~120_combout = (cnt_for_high_voltage_time[8] $ (((!\Add2~137 & \Add2~127 ) # (\Add2~137 & \Add2~127COUT1_166 )))) -// \Add2~122 = CARRY(((cnt_for_high_voltage_time[8]) # (!\Add2~127 ))) -// \Add2~122COUT1_167 = CARRY(((cnt_for_high_voltage_time[8]) # (!\Add2~127COUT1_166 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[8]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~137 ), - .cin0(\Add2~127 ), - .cin1(\Add2~127COUT1_166 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~120_combout ), - .regout(), - .cout(), - .cout0(\Add2~122 ), - .cout1(\Add2~122COUT1_167 )); -// synopsys translate_off -defparam \Add2~120 .cin0_used = "true"; -defparam \Add2~120 .cin1_used = "true"; -defparam \Add2~120 .cin_used = "true"; -defparam \Add2~120 .lut_mask = "3ccf"; -defparam \Add2~120 .operation_mode = "arithmetic"; -defparam \Add2~120 .output_mode = "comb_only"; -defparam \Add2~120 .register_cascade_mode = "off"; -defparam \Add2~120 .sum_lutc_input = "cin"; -defparam \Add2~120 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N6 -maxii_lcell \cnt_for_high_voltage_time[8] ( -// Equation(s): -// cnt_for_high_voltage_time[8] = DFFEAS((!\fault_flag[0][0]~regout & (posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & \Add2~120_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(posedge_enable_count_high_voltage_time), - .datac(\fault_flag[1][0]~regout ), - .datad(\Add2~120_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[8]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[8] .lut_mask = "0400"; -defparam \cnt_for_high_voltage_time[8] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[8] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[8] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[8] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[8] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N3 -maxii_lcell \Add2~115 ( -// Equation(s): -// \Add2~115_combout = (cnt_for_high_voltage_time[9] $ ((!(!\Add2~137 & \Add2~122 ) # (\Add2~137 & \Add2~122COUT1_167 )))) -// \Add2~117 = CARRY(((!cnt_for_high_voltage_time[9] & !\Add2~122 ))) -// \Add2~117COUT1_168 = CARRY(((!cnt_for_high_voltage_time[9] & !\Add2~122COUT1_167 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[9]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~137 ), - .cin0(\Add2~122 ), - .cin1(\Add2~122COUT1_167 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~115_combout ), - .regout(), - .cout(), - .cout0(\Add2~117 ), - .cout1(\Add2~117COUT1_168 )); -// synopsys translate_off -defparam \Add2~115 .cin0_used = "true"; -defparam \Add2~115 .cin1_used = "true"; -defparam \Add2~115 .cin_used = "true"; -defparam \Add2~115 .lut_mask = "c303"; -defparam \Add2~115 .operation_mode = "arithmetic"; -defparam \Add2~115 .output_mode = "comb_only"; -defparam \Add2~115 .register_cascade_mode = "off"; -defparam \Add2~115 .sum_lutc_input = "cin"; -defparam \Add2~115 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N2 -maxii_lcell \cnt_for_high_voltage_time[9] ( -// Equation(s): -// cnt_for_high_voltage_time[9] = DFFEAS((!\fault_flag[0][0]~regout & (posedge_enable_count_high_voltage_time & (\Add2~115_combout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(posedge_enable_count_high_voltage_time), - .datac(\Add2~115_combout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[9]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[9] .lut_mask = "0040"; -defparam \cnt_for_high_voltage_time[9] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[9] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[9] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[9] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[9] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N4 -maxii_lcell \Add2~110 ( -// Equation(s): -// \Add2~110_combout = (cnt_for_high_voltage_time[10] $ (((!\Add2~137 & \Add2~117 ) # (\Add2~137 & \Add2~117COUT1_168 )))) -// \Add2~112 = CARRY(((cnt_for_high_voltage_time[10]) # (!\Add2~117COUT1_168 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[10]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~137 ), - .cin0(\Add2~117 ), - .cin1(\Add2~117COUT1_168 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~110_combout ), - .regout(), - .cout(\Add2~112 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Add2~110 .cin0_used = "true"; -defparam \Add2~110 .cin1_used = "true"; -defparam \Add2~110 .cin_used = "true"; -defparam \Add2~110 .lut_mask = "3ccf"; -defparam \Add2~110 .operation_mode = "arithmetic"; -defparam \Add2~110 .output_mode = "comb_only"; -defparam \Add2~110 .register_cascade_mode = "off"; -defparam \Add2~110 .sum_lutc_input = "cin"; -defparam \Add2~110 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N8 -maxii_lcell \cnt_for_high_voltage_time[10] ( -// Equation(s): -// cnt_for_high_voltage_time[10] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((\Add2~110_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(posedge_enable_count_high_voltage_time), - .datac(\Add2~110_combout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[10]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[10] .lut_mask = "0051"; -defparam \cnt_for_high_voltage_time[10] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[10] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[10] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[10] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[10] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N5 -maxii_lcell \Add2~105 ( -// Equation(s): -// \Add2~105_combout = (cnt_for_high_voltage_time[11] $ ((!\Add2~112 ))) -// \Add2~107 = CARRY(((!cnt_for_high_voltage_time[11] & !\Add2~112 ))) -// \Add2~107COUT1_169 = CARRY(((!cnt_for_high_voltage_time[11] & !\Add2~112 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[11]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~112 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~105_combout ), - .regout(), - .cout(), - .cout0(\Add2~107 ), - .cout1(\Add2~107COUT1_169 )); -// synopsys translate_off -defparam \Add2~105 .cin_used = "true"; -defparam \Add2~105 .lut_mask = "c303"; -defparam \Add2~105 .operation_mode = "arithmetic"; -defparam \Add2~105 .output_mode = "comb_only"; -defparam \Add2~105 .register_cascade_mode = "off"; -defparam \Add2~105 .sum_lutc_input = "cin"; -defparam \Add2~105 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N7 -maxii_lcell \cnt_for_high_voltage_time[11] ( -// Equation(s): -// cnt_for_high_voltage_time[11] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((\Add2~105_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(posedge_enable_count_high_voltage_time), - .datac(\fault_flag[1][0]~regout ), - .datad(\Add2~105_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[11]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[11] .lut_mask = "0501"; -defparam \cnt_for_high_voltage_time[11] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[11] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[11] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[11] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[11] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N9 -maxii_lcell \Equal4~6 ( -// Equation(s): -// \Equal4~6_combout = (!cnt_for_high_voltage_time[10] & (!cnt_for_high_voltage_time[11] & (!cnt_for_high_voltage_time[8] & !cnt_for_high_voltage_time[9]))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[10]), - .datab(cnt_for_high_voltage_time[11]), - .datac(cnt_for_high_voltage_time[8]), - .datad(cnt_for_high_voltage_time[9]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~6_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~6 .lut_mask = "0001"; -defparam \Equal4~6 .operation_mode = "normal"; -defparam \Equal4~6 .output_mode = "comb_only"; -defparam \Equal4~6 .register_cascade_mode = "off"; -defparam \Equal4~6 .sum_lutc_input = "datac"; -defparam \Equal4~6 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N6 -maxii_lcell \Add2~100 ( -// Equation(s): -// \Add2~100_combout = (cnt_for_high_voltage_time[12] $ (((!\Add2~112 & \Add2~107 ) # (\Add2~112 & \Add2~107COUT1_169 )))) -// \Add2~102 = CARRY(((cnt_for_high_voltage_time[12]) # (!\Add2~107 ))) -// \Add2~102COUT1_170 = CARRY(((cnt_for_high_voltage_time[12]) # (!\Add2~107COUT1_169 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[12]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~112 ), - .cin0(\Add2~107 ), - .cin1(\Add2~107COUT1_169 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~100_combout ), - .regout(), - .cout(), - .cout0(\Add2~102 ), - .cout1(\Add2~102COUT1_170 )); -// synopsys translate_off -defparam \Add2~100 .cin0_used = "true"; -defparam \Add2~100 .cin1_used = "true"; -defparam \Add2~100 .cin_used = "true"; -defparam \Add2~100 .lut_mask = "3ccf"; -defparam \Add2~100 .operation_mode = "arithmetic"; -defparam \Add2~100 .output_mode = "comb_only"; -defparam \Add2~100 .register_cascade_mode = "off"; -defparam \Add2~100 .sum_lutc_input = "cin"; -defparam \Add2~100 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y6_N2 -maxii_lcell \cnt_for_high_voltage_time[12] ( -// Equation(s): -// cnt_for_high_voltage_time[12] = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & ((\Add2~100_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~100_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[12]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[12] .lut_mask = "0301"; -defparam \cnt_for_high_voltage_time[12] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[12] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[12] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[12] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[12] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N7 -maxii_lcell \Add2~95 ( -// Equation(s): -// \Add2~95_combout = cnt_for_high_voltage_time[13] $ ((((!(!\Add2~112 & \Add2~102 ) # (\Add2~112 & \Add2~102COUT1_170 ))))) -// \Add2~97 = CARRY((!cnt_for_high_voltage_time[13] & ((!\Add2~102 )))) -// \Add2~97COUT1_171 = CARRY((!cnt_for_high_voltage_time[13] & ((!\Add2~102COUT1_170 )))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[13]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~112 ), - .cin0(\Add2~102 ), - .cin1(\Add2~102COUT1_170 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~95_combout ), - .regout(), - .cout(), - .cout0(\Add2~97 ), - .cout1(\Add2~97COUT1_171 )); -// synopsys translate_off -defparam \Add2~95 .cin0_used = "true"; -defparam \Add2~95 .cin1_used = "true"; -defparam \Add2~95 .cin_used = "true"; -defparam \Add2~95 .lut_mask = "a505"; -defparam \Add2~95 .operation_mode = "arithmetic"; -defparam \Add2~95 .output_mode = "comb_only"; -defparam \Add2~95 .register_cascade_mode = "off"; -defparam \Add2~95 .sum_lutc_input = "cin"; -defparam \Add2~95 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y6_N1 -maxii_lcell \cnt_for_high_voltage_time[13] ( -// Equation(s): -// cnt_for_high_voltage_time[13] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & (\Add2~95_combout & posedge_enable_count_high_voltage_time))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(\Add2~95_combout ), - .datad(posedge_enable_count_high_voltage_time), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[13]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[13] .lut_mask = "1000"; -defparam \cnt_for_high_voltage_time[13] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[13] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[13] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[13] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[13] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N8 -maxii_lcell \Add2~90 ( -// Equation(s): -// \Add2~90_combout = cnt_for_high_voltage_time[14] $ (((((!\Add2~112 & \Add2~97 ) # (\Add2~112 & \Add2~97COUT1_171 ))))) -// \Add2~92 = CARRY((cnt_for_high_voltage_time[14]) # ((!\Add2~97 ))) -// \Add2~92COUT1_172 = CARRY((cnt_for_high_voltage_time[14]) # ((!\Add2~97COUT1_171 ))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[14]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~112 ), - .cin0(\Add2~97 ), - .cin1(\Add2~97COUT1_171 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~90_combout ), - .regout(), - .cout(), - .cout0(\Add2~92 ), - .cout1(\Add2~92COUT1_172 )); -// synopsys translate_off -defparam \Add2~90 .cin0_used = "true"; -defparam \Add2~90 .cin1_used = "true"; -defparam \Add2~90 .cin_used = "true"; -defparam \Add2~90 .lut_mask = "5aaf"; -defparam \Add2~90 .operation_mode = "arithmetic"; -defparam \Add2~90 .output_mode = "comb_only"; -defparam \Add2~90 .register_cascade_mode = "off"; -defparam \Add2~90 .sum_lutc_input = "cin"; -defparam \Add2~90 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y6_N7 -maxii_lcell \cnt_for_high_voltage_time[14] ( -// Equation(s): -// cnt_for_high_voltage_time[14] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & \Add2~90_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~90_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[14]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[14] .lut_mask = "0200"; -defparam \cnt_for_high_voltage_time[14] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[14] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[14] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[14] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[14] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y5_N9 -maxii_lcell \Add2~85 ( -// Equation(s): -// \Add2~85_combout = (cnt_for_high_voltage_time[15] $ ((!(!\Add2~112 & \Add2~92 ) # (\Add2~112 & \Add2~92COUT1_172 )))) -// \Add2~87 = CARRY(((!cnt_for_high_voltage_time[15] & !\Add2~92COUT1_172 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[15]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~112 ), - .cin0(\Add2~92 ), - .cin1(\Add2~92COUT1_172 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~85_combout ), - .regout(), - .cout(\Add2~87 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Add2~85 .cin0_used = "true"; -defparam \Add2~85 .cin1_used = "true"; -defparam \Add2~85 .cin_used = "true"; -defparam \Add2~85 .lut_mask = "c303"; -defparam \Add2~85 .operation_mode = "arithmetic"; -defparam \Add2~85 .output_mode = "comb_only"; -defparam \Add2~85 .register_cascade_mode = "off"; -defparam \Add2~85 .sum_lutc_input = "cin"; -defparam \Add2~85 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y6_N5 -maxii_lcell \cnt_for_high_voltage_time[15] ( -// Equation(s): -// cnt_for_high_voltage_time[15] = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & ((\Add2~85_combout ) # (!posedge_enable_count_high_voltage_time)))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~85_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[15]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[15] .lut_mask = "0301"; -defparam \cnt_for_high_voltage_time[15] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[15] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[15] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[15] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[15] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y6_N9 -maxii_lcell \Equal4~5 ( -// Equation(s): -// \Equal4~5_combout = (!cnt_for_high_voltage_time[15] & (!cnt_for_high_voltage_time[13] & (!cnt_for_high_voltage_time[14] & !cnt_for_high_voltage_time[12]))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[15]), - .datab(cnt_for_high_voltage_time[13]), - .datac(cnt_for_high_voltage_time[14]), - .datad(cnt_for_high_voltage_time[12]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~5_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~5 .lut_mask = "0001"; -defparam \Equal4~5 .operation_mode = "normal"; -defparam \Equal4~5 .output_mode = "comb_only"; -defparam \Equal4~5 .register_cascade_mode = "off"; -defparam \Equal4~5 .sum_lutc_input = "datac"; -defparam \Equal4~5 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N3 -maxii_lcell \Equal4~7 ( -// Equation(s): -// \Equal4~7_combout = (!cnt_for_high_voltage_time[7] & (!cnt_for_high_voltage_time[4] & (!cnt_for_high_voltage_time[6] & !cnt_for_high_voltage_time[5]))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[7]), - .datab(cnt_for_high_voltage_time[4]), - .datac(cnt_for_high_voltage_time[6]), - .datad(cnt_for_high_voltage_time[5]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~7_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~7 .lut_mask = "0001"; -defparam \Equal4~7 .operation_mode = "normal"; -defparam \Equal4~7 .output_mode = "comb_only"; -defparam \Equal4~7 .register_cascade_mode = "off"; -defparam \Equal4~7 .sum_lutc_input = "datac"; -defparam \Equal4~7 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N5 -maxii_lcell \Equal4~8 ( -// Equation(s): -// \Equal4~8_combout = (!cnt_for_high_voltage_time[3] & (!cnt_for_high_voltage_time[2] & (!cnt_for_high_voltage_time[1] & \Equal4~7_combout ))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[3]), - .datab(cnt_for_high_voltage_time[2]), - .datac(cnt_for_high_voltage_time[1]), - .datad(\Equal4~7_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~8_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~8 .lut_mask = "0100"; -defparam \Equal4~8 .operation_mode = "normal"; -defparam \Equal4~8 .output_mode = "comb_only"; -defparam \Equal4~8 .register_cascade_mode = "off"; -defparam \Equal4~8 .sum_lutc_input = "datac"; -defparam \Equal4~8 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N0 -maxii_lcell \Add2~80 ( -// Equation(s): -// \Add2~80_combout = (cnt_for_high_voltage_time[16] $ ((\Add2~87 ))) -// \Add2~82 = CARRY(((cnt_for_high_voltage_time[16]) # (!\Add2~87 ))) -// \Add2~82COUT1_173 = CARRY(((cnt_for_high_voltage_time[16]) # (!\Add2~87 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[16]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~87 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~80_combout ), - .regout(), - .cout(), - .cout0(\Add2~82 ), - .cout1(\Add2~82COUT1_173 )); -// synopsys translate_off -defparam \Add2~80 .cin_used = "true"; -defparam \Add2~80 .lut_mask = "3ccf"; -defparam \Add2~80 .operation_mode = "arithmetic"; -defparam \Add2~80 .output_mode = "comb_only"; -defparam \Add2~80 .register_cascade_mode = "off"; -defparam \Add2~80 .sum_lutc_input = "cin"; -defparam \Add2~80 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N5 -maxii_lcell \cnt_for_high_voltage_time[16] ( -// Equation(s): -// cnt_for_high_voltage_time[16] = DFFEAS((!\fault_flag[0][0]~regout & (posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & \Add2~80_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(posedge_enable_count_high_voltage_time), - .datac(\fault_flag[1][0]~regout ), - .datad(\Add2~80_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[16]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[16] .lut_mask = "0400"; -defparam \cnt_for_high_voltage_time[16] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[16] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[16] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[16] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[16] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N1 -maxii_lcell \Add2~75 ( -// Equation(s): -// \Add2~75_combout = (cnt_for_high_voltage_time[17] $ ((!(!\Add2~87 & \Add2~82 ) # (\Add2~87 & \Add2~82COUT1_173 )))) -// \Add2~77 = CARRY(((!cnt_for_high_voltage_time[17] & !\Add2~82 ))) -// \Add2~77COUT1_174 = CARRY(((!cnt_for_high_voltage_time[17] & !\Add2~82COUT1_173 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[17]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~87 ), - .cin0(\Add2~82 ), - .cin1(\Add2~82COUT1_173 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~75_combout ), - .regout(), - .cout(), - .cout0(\Add2~77 ), - .cout1(\Add2~77COUT1_174 )); -// synopsys translate_off -defparam \Add2~75 .cin0_used = "true"; -defparam \Add2~75 .cin1_used = "true"; -defparam \Add2~75 .cin_used = "true"; -defparam \Add2~75 .lut_mask = "c303"; -defparam \Add2~75 .operation_mode = "arithmetic"; -defparam \Add2~75 .output_mode = "comb_only"; -defparam \Add2~75 .register_cascade_mode = "off"; -defparam \Add2~75 .sum_lutc_input = "cin"; -defparam \Add2~75 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N4 -maxii_lcell \cnt_for_high_voltage_time[17] ( -// Equation(s): -// cnt_for_high_voltage_time[17] = DFFEAS((!\fault_flag[0][0]~regout & (posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & \Add2~75_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(posedge_enable_count_high_voltage_time), - .datac(\fault_flag[1][0]~regout ), - .datad(\Add2~75_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[17]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[17] .lut_mask = "0400"; -defparam \cnt_for_high_voltage_time[17] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[17] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[17] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[17] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[17] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N2 -maxii_lcell \Add2~70 ( -// Equation(s): -// \Add2~70_combout = (cnt_for_high_voltage_time[18] $ (((!\Add2~87 & \Add2~77 ) # (\Add2~87 & \Add2~77COUT1_174 )))) -// \Add2~72 = CARRY(((cnt_for_high_voltage_time[18]) # (!\Add2~77 ))) -// \Add2~72COUT1_175 = CARRY(((cnt_for_high_voltage_time[18]) # (!\Add2~77COUT1_174 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[18]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~87 ), - .cin0(\Add2~77 ), - .cin1(\Add2~77COUT1_174 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~70_combout ), - .regout(), - .cout(), - .cout0(\Add2~72 ), - .cout1(\Add2~72COUT1_175 )); -// synopsys translate_off -defparam \Add2~70 .cin0_used = "true"; -defparam \Add2~70 .cin1_used = "true"; -defparam \Add2~70 .cin_used = "true"; -defparam \Add2~70 .lut_mask = "3ccf"; -defparam \Add2~70 .operation_mode = "arithmetic"; -defparam \Add2~70 .output_mode = "comb_only"; -defparam \Add2~70 .register_cascade_mode = "off"; -defparam \Add2~70 .sum_lutc_input = "cin"; -defparam \Add2~70 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N3 -maxii_lcell \cnt_for_high_voltage_time[18] ( -// Equation(s): -// cnt_for_high_voltage_time[18] = DFFEAS((!\fault_flag[0][0]~regout & (posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & \Add2~70_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(posedge_enable_count_high_voltage_time), - .datac(\fault_flag[1][0]~regout ), - .datad(\Add2~70_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[18]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[18] .lut_mask = "0400"; -defparam \cnt_for_high_voltage_time[18] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[18] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[18] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[18] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[18] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N3 -maxii_lcell \Add2~65 ( -// Equation(s): -// \Add2~65_combout = cnt_for_high_voltage_time[19] $ ((((!(!\Add2~87 & \Add2~72 ) # (\Add2~87 & \Add2~72COUT1_175 ))))) -// \Add2~67 = CARRY((!cnt_for_high_voltage_time[19] & ((!\Add2~72 )))) -// \Add2~67COUT1_176 = CARRY((!cnt_for_high_voltage_time[19] & ((!\Add2~72COUT1_175 )))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[19]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~87 ), - .cin0(\Add2~72 ), - .cin1(\Add2~72COUT1_175 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~65_combout ), - .regout(), - .cout(), - .cout0(\Add2~67 ), - .cout1(\Add2~67COUT1_176 )); -// synopsys translate_off -defparam \Add2~65 .cin0_used = "true"; -defparam \Add2~65 .cin1_used = "true"; -defparam \Add2~65 .cin_used = "true"; -defparam \Add2~65 .lut_mask = "a505"; -defparam \Add2~65 .operation_mode = "arithmetic"; -defparam \Add2~65 .output_mode = "comb_only"; -defparam \Add2~65 .register_cascade_mode = "off"; -defparam \Add2~65 .sum_lutc_input = "cin"; -defparam \Add2~65 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N1 -maxii_lcell \cnt_for_high_voltage_time[19] ( -// Equation(s): -// cnt_for_high_voltage_time[19] = DFFEAS((!\fault_flag[0][0]~regout & (posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & \Add2~65_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(posedge_enable_count_high_voltage_time), - .datac(\fault_flag[1][0]~regout ), - .datad(\Add2~65_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[19]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[19] .lut_mask = "0400"; -defparam \cnt_for_high_voltage_time[19] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[19] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[19] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[19] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[19] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y5_N0 -maxii_lcell \Equal4~3 ( -// Equation(s): -// \Equal4~3_combout = (!cnt_for_high_voltage_time[16] & (!cnt_for_high_voltage_time[19] & (!cnt_for_high_voltage_time[17] & !cnt_for_high_voltage_time[18]))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[16]), - .datab(cnt_for_high_voltage_time[19]), - .datac(cnt_for_high_voltage_time[17]), - .datad(cnt_for_high_voltage_time[18]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~3_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~3 .lut_mask = "0001"; -defparam \Equal4~3 .operation_mode = "normal"; -defparam \Equal4~3 .output_mode = "comb_only"; -defparam \Equal4~3 .register_cascade_mode = "off"; -defparam \Equal4~3 .sum_lutc_input = "datac"; -defparam \Equal4~3 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N4 -maxii_lcell \Add2~60 ( -// Equation(s): -// \Add2~60_combout = (cnt_for_high_voltage_time[20] $ (((!\Add2~87 & \Add2~67 ) # (\Add2~87 & \Add2~67COUT1_176 )))) -// \Add2~62 = CARRY(((cnt_for_high_voltage_time[20]) # (!\Add2~67COUT1_176 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[20]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~87 ), - .cin0(\Add2~67 ), - .cin1(\Add2~67COUT1_176 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~60_combout ), - .regout(), - .cout(\Add2~62 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Add2~60 .cin0_used = "true"; -defparam \Add2~60 .cin1_used = "true"; -defparam \Add2~60 .cin_used = "true"; -defparam \Add2~60 .lut_mask = "3ccf"; -defparam \Add2~60 .operation_mode = "arithmetic"; -defparam \Add2~60 .output_mode = "comb_only"; -defparam \Add2~60 .register_cascade_mode = "off"; -defparam \Add2~60 .sum_lutc_input = "cin"; -defparam \Add2~60 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N9 -maxii_lcell \cnt_for_high_voltage_time[20] ( -// Equation(s): -// cnt_for_high_voltage_time[20] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & \Add2~60_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~60_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[20]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[20] .lut_mask = "0200"; -defparam \cnt_for_high_voltage_time[20] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[20] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[20] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[20] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[20] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N5 -maxii_lcell \Add2~55 ( -// Equation(s): -// \Add2~55_combout = cnt_for_high_voltage_time[21] $ ((((!\Add2~62 )))) -// \Add2~57 = CARRY((!cnt_for_high_voltage_time[21] & ((!\Add2~62 )))) -// \Add2~57COUT1_177 = CARRY((!cnt_for_high_voltage_time[21] & ((!\Add2~62 )))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[21]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~62 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~55_combout ), - .regout(), - .cout(), - .cout0(\Add2~57 ), - .cout1(\Add2~57COUT1_177 )); -// synopsys translate_off -defparam \Add2~55 .cin_used = "true"; -defparam \Add2~55 .lut_mask = "a505"; -defparam \Add2~55 .operation_mode = "arithmetic"; -defparam \Add2~55 .output_mode = "comb_only"; -defparam \Add2~55 .register_cascade_mode = "off"; -defparam \Add2~55 .sum_lutc_input = "cin"; -defparam \Add2~55 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N0 -maxii_lcell \cnt_for_high_voltage_time[21] ( -// Equation(s): -// cnt_for_high_voltage_time[21] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & \Add2~55_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~55_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[21]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[21] .lut_mask = "0200"; -defparam \cnt_for_high_voltage_time[21] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[21] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[21] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[21] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[21] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N6 -maxii_lcell \Add2~50 ( -// Equation(s): -// \Add2~50_combout = (cnt_for_high_voltage_time[22] $ (((!\Add2~62 & \Add2~57 ) # (\Add2~62 & \Add2~57COUT1_177 )))) -// \Add2~52 = CARRY(((cnt_for_high_voltage_time[22]) # (!\Add2~57 ))) -// \Add2~52COUT1_178 = CARRY(((cnt_for_high_voltage_time[22]) # (!\Add2~57COUT1_177 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[22]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~62 ), - .cin0(\Add2~57 ), - .cin1(\Add2~57COUT1_177 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~50_combout ), - .regout(), - .cout(), - .cout0(\Add2~52 ), - .cout1(\Add2~52COUT1_178 )); -// synopsys translate_off -defparam \Add2~50 .cin0_used = "true"; -defparam \Add2~50 .cin1_used = "true"; -defparam \Add2~50 .cin_used = "true"; -defparam \Add2~50 .lut_mask = "3ccf"; -defparam \Add2~50 .operation_mode = "arithmetic"; -defparam \Add2~50 .output_mode = "comb_only"; -defparam \Add2~50 .register_cascade_mode = "off"; -defparam \Add2~50 .sum_lutc_input = "cin"; -defparam \Add2~50 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N3 -maxii_lcell \cnt_for_high_voltage_time[22] ( -// Equation(s): -// cnt_for_high_voltage_time[22] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & \Add2~50_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~50_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[22]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[22] .lut_mask = "0200"; -defparam \cnt_for_high_voltage_time[22] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[22] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[22] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[22] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[22] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N7 -maxii_lcell \Add2~45 ( -// Equation(s): -// \Add2~45_combout = (cnt_for_high_voltage_time[23] $ ((!(!\Add2~62 & \Add2~52 ) # (\Add2~62 & \Add2~52COUT1_178 )))) -// \Add2~47 = CARRY(((!cnt_for_high_voltage_time[23] & !\Add2~52 ))) -// \Add2~47COUT1_179 = CARRY(((!cnt_for_high_voltage_time[23] & !\Add2~52COUT1_178 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[23]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~62 ), - .cin0(\Add2~52 ), - .cin1(\Add2~52COUT1_178 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~45_combout ), - .regout(), - .cout(), - .cout0(\Add2~47 ), - .cout1(\Add2~47COUT1_179 )); -// synopsys translate_off -defparam \Add2~45 .cin0_used = "true"; -defparam \Add2~45 .cin1_used = "true"; -defparam \Add2~45 .cin_used = "true"; -defparam \Add2~45 .lut_mask = "c303"; -defparam \Add2~45 .operation_mode = "arithmetic"; -defparam \Add2~45 .output_mode = "comb_only"; -defparam \Add2~45 .register_cascade_mode = "off"; -defparam \Add2~45 .sum_lutc_input = "cin"; -defparam \Add2~45 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N5 -maxii_lcell \cnt_for_high_voltage_time[23] ( -// Equation(s): -// cnt_for_high_voltage_time[23] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (\Add2~45_combout & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\Add2~45_combout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[23]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[23] .lut_mask = "0020"; -defparam \cnt_for_high_voltage_time[23] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[23] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[23] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[23] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[23] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N8 -maxii_lcell \Add2~40 ( -// Equation(s): -// \Add2~40_combout = (cnt_for_high_voltage_time[24] $ (((!\Add2~62 & \Add2~47 ) # (\Add2~62 & \Add2~47COUT1_179 )))) -// \Add2~42 = CARRY(((cnt_for_high_voltage_time[24]) # (!\Add2~47 ))) -// \Add2~42COUT1_180 = CARRY(((cnt_for_high_voltage_time[24]) # (!\Add2~47COUT1_179 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[24]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~62 ), - .cin0(\Add2~47 ), - .cin1(\Add2~47COUT1_179 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~40_combout ), - .regout(), - .cout(), - .cout0(\Add2~42 ), - .cout1(\Add2~42COUT1_180 )); -// synopsys translate_off -defparam \Add2~40 .cin0_used = "true"; -defparam \Add2~40 .cin1_used = "true"; -defparam \Add2~40 .cin_used = "true"; -defparam \Add2~40 .lut_mask = "3ccf"; -defparam \Add2~40 .operation_mode = "arithmetic"; -defparam \Add2~40 .output_mode = "comb_only"; -defparam \Add2~40 .register_cascade_mode = "off"; -defparam \Add2~40 .sum_lutc_input = "cin"; -defparam \Add2~40 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N8 -maxii_lcell \cnt_for_high_voltage_time[24] ( -// Equation(s): -// cnt_for_high_voltage_time[24] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & \Add2~40_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~40_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[24]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[24] .lut_mask = "0200"; -defparam \cnt_for_high_voltage_time[24] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[24] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[24] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[24] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[24] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X14_Y5_N9 -maxii_lcell \Add2~35 ( -// Equation(s): -// \Add2~35_combout = (cnt_for_high_voltage_time[25] $ ((!(!\Add2~62 & \Add2~42 ) # (\Add2~62 & \Add2~42COUT1_180 )))) -// \Add2~37 = CARRY(((!cnt_for_high_voltage_time[25] & !\Add2~42COUT1_180 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[25]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~62 ), - .cin0(\Add2~42 ), - .cin1(\Add2~42COUT1_180 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~35_combout ), - .regout(), - .cout(\Add2~37 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Add2~35 .cin0_used = "true"; -defparam \Add2~35 .cin1_used = "true"; -defparam \Add2~35 .cin_used = "true"; -defparam \Add2~35 .lut_mask = "c303"; -defparam \Add2~35 .operation_mode = "arithmetic"; -defparam \Add2~35 .output_mode = "comb_only"; -defparam \Add2~35 .register_cascade_mode = "off"; -defparam \Add2~35 .sum_lutc_input = "cin"; -defparam \Add2~35 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N1 -maxii_lcell \cnt_for_high_voltage_time[25] ( -// Equation(s): -// cnt_for_high_voltage_time[25] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & \Add2~35_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~35_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[25]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[25] .lut_mask = "0200"; -defparam \cnt_for_high_voltage_time[25] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[25] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[25] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[25] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[25] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N0 -maxii_lcell \Add2~30 ( -// Equation(s): -// \Add2~30_combout = cnt_for_high_voltage_time[26] $ ((((\Add2~37 )))) -// \Add2~32 = CARRY((cnt_for_high_voltage_time[26]) # ((!\Add2~37 ))) -// \Add2~32COUT1_181 = CARRY((cnt_for_high_voltage_time[26]) # ((!\Add2~37 ))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[26]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~37 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~30_combout ), - .regout(), - .cout(), - .cout0(\Add2~32 ), - .cout1(\Add2~32COUT1_181 )); -// synopsys translate_off -defparam \Add2~30 .cin_used = "true"; -defparam \Add2~30 .lut_mask = "5aaf"; -defparam \Add2~30 .operation_mode = "arithmetic"; -defparam \Add2~30 .output_mode = "comb_only"; -defparam \Add2~30 .register_cascade_mode = "off"; -defparam \Add2~30 .sum_lutc_input = "cin"; -defparam \Add2~30 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N4 -maxii_lcell \cnt_for_high_voltage_time[26] ( -// Equation(s): -// cnt_for_high_voltage_time[26] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & \Add2~30_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~30_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[26]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[26] .lut_mask = "0200"; -defparam \cnt_for_high_voltage_time[26] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[26] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[26] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[26] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[26] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N1 -maxii_lcell \Add2~25 ( -// Equation(s): -// \Add2~25_combout = cnt_for_high_voltage_time[27] $ ((((!(!\Add2~37 & \Add2~32 ) # (\Add2~37 & \Add2~32COUT1_181 ))))) -// \Add2~27 = CARRY((!cnt_for_high_voltage_time[27] & ((!\Add2~32 )))) -// \Add2~27COUT1_182 = CARRY((!cnt_for_high_voltage_time[27] & ((!\Add2~32COUT1_181 )))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[27]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~37 ), - .cin0(\Add2~32 ), - .cin1(\Add2~32COUT1_181 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~25_combout ), - .regout(), - .cout(), - .cout0(\Add2~27 ), - .cout1(\Add2~27COUT1_182 )); -// synopsys translate_off -defparam \Add2~25 .cin0_used = "true"; -defparam \Add2~25 .cin1_used = "true"; -defparam \Add2~25 .cin_used = "true"; -defparam \Add2~25 .lut_mask = "a505"; -defparam \Add2~25 .operation_mode = "arithmetic"; -defparam \Add2~25 .output_mode = "comb_only"; -defparam \Add2~25 .register_cascade_mode = "off"; -defparam \Add2~25 .sum_lutc_input = "cin"; -defparam \Add2~25 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N7 -maxii_lcell \cnt_for_high_voltage_time[27] ( -// Equation(s): -// cnt_for_high_voltage_time[27] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (\Add2~25_combout & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\Add2~25_combout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[27]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[27] .lut_mask = "0020"; -defparam \cnt_for_high_voltage_time[27] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[27] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[27] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[27] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[27] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N6 -maxii_lcell \Equal4~1 ( -// Equation(s): -// \Equal4~1_combout = (!cnt_for_high_voltage_time[26] & (!cnt_for_high_voltage_time[25] & (!cnt_for_high_voltage_time[27] & !cnt_for_high_voltage_time[24]))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[26]), - .datab(cnt_for_high_voltage_time[25]), - .datac(cnt_for_high_voltage_time[27]), - .datad(cnt_for_high_voltage_time[24]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~1_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~1 .lut_mask = "0001"; -defparam \Equal4~1 .operation_mode = "normal"; -defparam \Equal4~1 .output_mode = "comb_only"; -defparam \Equal4~1 .register_cascade_mode = "off"; -defparam \Equal4~1 .sum_lutc_input = "datac"; -defparam \Equal4~1 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X16_Y5_N2 -maxii_lcell \Equal4~2 ( -// Equation(s): -// \Equal4~2_combout = (!cnt_for_high_voltage_time[23] & (!cnt_for_high_voltage_time[20] & (!cnt_for_high_voltage_time[21] & !cnt_for_high_voltage_time[22]))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[23]), - .datab(cnt_for_high_voltage_time[20]), - .datac(cnt_for_high_voltage_time[21]), - .datad(cnt_for_high_voltage_time[22]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~2_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~2 .lut_mask = "0001"; -defparam \Equal4~2 .operation_mode = "normal"; -defparam \Equal4~2 .output_mode = "comb_only"; -defparam \Equal4~2 .register_cascade_mode = "off"; -defparam \Equal4~2 .sum_lutc_input = "datac"; -defparam \Equal4~2 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N2 -maxii_lcell \Add2~20 ( -// Equation(s): -// \Add2~20_combout = cnt_for_high_voltage_time[28] $ (((((!\Add2~37 & \Add2~27 ) # (\Add2~37 & \Add2~27COUT1_182 ))))) -// \Add2~22 = CARRY((cnt_for_high_voltage_time[28]) # ((!\Add2~27 ))) -// \Add2~22COUT1_183 = CARRY((cnt_for_high_voltage_time[28]) # ((!\Add2~27COUT1_182 ))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[28]), - .datab(vcc), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~37 ), - .cin0(\Add2~27 ), - .cin1(\Add2~27COUT1_182 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~20_combout ), - .regout(), - .cout(), - .cout0(\Add2~22 ), - .cout1(\Add2~22COUT1_183 )); -// synopsys translate_off -defparam \Add2~20 .cin0_used = "true"; -defparam \Add2~20 .cin1_used = "true"; -defparam \Add2~20 .cin_used = "true"; -defparam \Add2~20 .lut_mask = "5aaf"; -defparam \Add2~20 .operation_mode = "arithmetic"; -defparam \Add2~20 .output_mode = "comb_only"; -defparam \Add2~20 .register_cascade_mode = "off"; -defparam \Add2~20 .sum_lutc_input = "cin"; -defparam \Add2~20 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N6 -maxii_lcell \cnt_for_high_voltage_time[28] ( -// Equation(s): -// cnt_for_high_voltage_time[28] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & \Add2~20_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\Add2~20_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[28]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[28] .lut_mask = "0200"; -defparam \cnt_for_high_voltage_time[28] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[28] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[28] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[28] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[28] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N3 -maxii_lcell \Add2~15 ( -// Equation(s): -// \Add2~15_combout = (cnt_for_high_voltage_time[29] $ ((!(!\Add2~37 & \Add2~22 ) # (\Add2~37 & \Add2~22COUT1_183 )))) -// \Add2~17 = CARRY(((!cnt_for_high_voltage_time[29] & !\Add2~22 ))) -// \Add2~17COUT1_184 = CARRY(((!cnt_for_high_voltage_time[29] & !\Add2~22COUT1_183 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[29]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~37 ), - .cin0(\Add2~22 ), - .cin1(\Add2~22COUT1_183 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~15_combout ), - .regout(), - .cout(), - .cout0(\Add2~17 ), - .cout1(\Add2~17COUT1_184 )); -// synopsys translate_off -defparam \Add2~15 .cin0_used = "true"; -defparam \Add2~15 .cin1_used = "true"; -defparam \Add2~15 .cin_used = "true"; -defparam \Add2~15 .lut_mask = "c303"; -defparam \Add2~15 .operation_mode = "arithmetic"; -defparam \Add2~15 .output_mode = "comb_only"; -defparam \Add2~15 .register_cascade_mode = "off"; -defparam \Add2~15 .sum_lutc_input = "cin"; -defparam \Add2~15 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N7 -maxii_lcell \cnt_for_high_voltage_time[29] ( -// Equation(s): -// cnt_for_high_voltage_time[29] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & (posedge_enable_count_high_voltage_time & \Add2~15_combout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(posedge_enable_count_high_voltage_time), - .datad(\Add2~15_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[29]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[29] .lut_mask = "1000"; -defparam \cnt_for_high_voltage_time[29] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[29] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[29] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[29] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[29] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N4 -maxii_lcell \Add2~10 ( -// Equation(s): -// \Add2~10_combout = (cnt_for_high_voltage_time[30] $ (((!\Add2~37 & \Add2~17 ) # (\Add2~37 & \Add2~17COUT1_184 )))) -// \Add2~12 = CARRY(((cnt_for_high_voltage_time[30]) # (!\Add2~17COUT1_184 ))) - - .clk(gnd), - .dataa(vcc), - .datab(cnt_for_high_voltage_time[30]), - .datac(vcc), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~37 ), - .cin0(\Add2~17 ), - .cin1(\Add2~17COUT1_184 ), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~10_combout ), - .regout(), - .cout(\Add2~12 ), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Add2~10 .cin0_used = "true"; -defparam \Add2~10 .cin1_used = "true"; -defparam \Add2~10 .cin_used = "true"; -defparam \Add2~10 .lut_mask = "3ccf"; -defparam \Add2~10 .operation_mode = "arithmetic"; -defparam \Add2~10 .output_mode = "comb_only"; -defparam \Add2~10 .register_cascade_mode = "off"; -defparam \Add2~10 .sum_lutc_input = "cin"; -defparam \Add2~10 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N9 -maxii_lcell \cnt_for_high_voltage_time[30] ( -// Equation(s): -// cnt_for_high_voltage_time[30] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[0][0]~regout & (\Add2~10_combout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[0][0]~regout ), - .datac(\Add2~10_combout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[30]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[30] .lut_mask = "0020"; -defparam \cnt_for_high_voltage_time[30] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[30] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[30] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[30] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[30] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N5 -maxii_lcell \Add2~5 ( -// Equation(s): -// \Add2~5_combout = ((\Add2~12 $ (!cnt_for_high_voltage_time[31]))) - - .clk(gnd), - .dataa(vcc), - .datab(vcc), - .datac(vcc), - .datad(cnt_for_high_voltage_time[31]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(\Add2~12 ), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Add2~5_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Add2~5 .cin_used = "true"; -defparam \Add2~5 .lut_mask = "f00f"; -defparam \Add2~5 .operation_mode = "normal"; -defparam \Add2~5 .output_mode = "comb_only"; -defparam \Add2~5 .register_cascade_mode = "off"; -defparam \Add2~5 .sum_lutc_input = "cin"; -defparam \Add2~5 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X15_Y5_N8 -maxii_lcell \cnt_for_high_voltage_time[31] ( -// Equation(s): -// cnt_for_high_voltage_time[31] = DFFEAS((posedge_enable_count_high_voltage_time & (!\fault_flag[0][0]~regout & (\Add2~5_combout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , -// \cnt_for_high_voltage_time[18]~129_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(posedge_enable_count_high_voltage_time), - .datab(\fault_flag[0][0]~regout ), - .datac(\Add2~5_combout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cnt_for_high_voltage_time[18]~129_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cnt_for_high_voltage_time[31]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cnt_for_high_voltage_time[31] .lut_mask = "0020"; -defparam \cnt_for_high_voltage_time[31] .operation_mode = "normal"; -defparam \cnt_for_high_voltage_time[31] .output_mode = "reg_only"; -defparam \cnt_for_high_voltage_time[31] .register_cascade_mode = "off"; -defparam \cnt_for_high_voltage_time[31] .sum_lutc_input = "datac"; -defparam \cnt_for_high_voltage_time[31] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N8 -maxii_lcell \Equal4~0 ( -// Equation(s): -// \Equal4~0_combout = (!cnt_for_high_voltage_time[31] & (!cnt_for_high_voltage_time[28] & (!cnt_for_high_voltage_time[29] & !cnt_for_high_voltage_time[30]))) - - .clk(gnd), - .dataa(cnt_for_high_voltage_time[31]), - .datab(cnt_for_high_voltage_time[28]), - .datac(cnt_for_high_voltage_time[29]), - .datad(cnt_for_high_voltage_time[30]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~0_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~0 .lut_mask = "0001"; -defparam \Equal4~0 .operation_mode = "normal"; -defparam \Equal4~0 .output_mode = "comb_only"; -defparam \Equal4~0 .register_cascade_mode = "off"; -defparam \Equal4~0 .sum_lutc_input = "datac"; -defparam \Equal4~0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N1 -maxii_lcell \Equal4~4 ( -// Equation(s): -// \Equal4~4_combout = (\Equal4~3_combout & (\Equal4~1_combout & (\Equal4~2_combout & \Equal4~0_combout ))) - - .clk(gnd), - .dataa(\Equal4~3_combout ), - .datab(\Equal4~1_combout ), - .datac(\Equal4~2_combout ), - .datad(\Equal4~0_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~4_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~4 .lut_mask = "8000"; -defparam \Equal4~4 .operation_mode = "normal"; -defparam \Equal4~4 .output_mode = "comb_only"; -defparam \Equal4~4 .register_cascade_mode = "off"; -defparam \Equal4~4 .sum_lutc_input = "datac"; -defparam \Equal4~4 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y5_N2 -maxii_lcell \Equal4~9 ( -// Equation(s): -// \Equal4~9_combout = (\Equal4~6_combout & (\Equal4~5_combout & (\Equal4~8_combout & \Equal4~4_combout ))) - - .clk(gnd), - .dataa(\Equal4~6_combout ), - .datab(\Equal4~5_combout ), - .datac(\Equal4~8_combout ), - .datad(\Equal4~4_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~9_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~9 .lut_mask = "8000"; -defparam \Equal4~9 .operation_mode = "normal"; -defparam \Equal4~9 .output_mode = "comb_only"; -defparam \Equal4~9 .register_cascade_mode = "off"; -defparam \Equal4~9 .sum_lutc_input = "datac"; -defparam \Equal4~9 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y4_N1 -maxii_lcell \Equal4~10 ( -// Equation(s): -// \Equal4~10_combout = (((cnt_for_high_voltage_time[0] & \Equal4~9_combout ))) - - .clk(gnd), - .dataa(vcc), - .datab(vcc), - .datac(cnt_for_high_voltage_time[0]), - .datad(\Equal4~9_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Equal4~10_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Equal4~10 .lut_mask = "f000"; -defparam \Equal4~10 .operation_mode = "normal"; -defparam \Equal4~10 .output_mode = "comb_only"; -defparam \Equal4~10 .register_cascade_mode = "off"; -defparam \Equal4~10 .sum_lutc_input = "datac"; -defparam \Equal4~10 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y4_N2 -maxii_lcell is_high_voltage_time( -// Equation(s): -// \is_high_voltage_time~regout = DFFEAS(((\Equal4~10_combout ) # ((!cache_enable_count_high_voltage_time[1] & cache_enable_count_high_voltage_time[0]))) # (!\Equal4~9_combout ), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , -// \cnt_for_high_voltage_time~128_combout , ) - - .clk(\sys_clk~combout ), - .dataa(cache_enable_count_high_voltage_time[1]), - .datab(\Equal4~9_combout ), - .datac(cache_enable_count_high_voltage_time[0]), - .datad(\Equal4~10_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(\cnt_for_high_voltage_time~128_combout ), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\is_high_voltage_time~regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam is_high_voltage_time.lut_mask = "ff73"; -defparam is_high_voltage_time.operation_mode = "normal"; -defparam is_high_voltage_time.output_mode = "reg_only"; -defparam is_high_voltage_time.register_cascade_mode = "off"; -defparam is_high_voltage_time.sum_lutc_input = "datac"; -defparam is_high_voltage_time.synch_mode = "on"; -// synopsys translate_on - -// Location: LC_X8_Y5_N7 -maxii_lcell \signal_high_voltage[0]~reg0 ( -// Equation(s): -// \signal_high_voltage[0]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[0] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[0]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[0]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[0]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[0]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[0]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[0]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[0]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[0]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N2 -maxii_lcell \Decoder0~66 ( -// Equation(s): -// \Decoder0~66_combout = (\recv_complete~0_combout & (i[0] & (\Decoder0~65 & !i[5]))) - - .clk(gnd), - .dataa(\recv_complete~0_combout ), - .datab(i[0]), - .datac(\Decoder0~65 ), - .datad(i[5]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~66_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~66 .lut_mask = "0080"; -defparam \Decoder0~66 .operation_mode = "normal"; -defparam \Decoder0~66 .output_mode = "comb_only"; -defparam \Decoder0~66 .register_cascade_mode = "off"; -defparam \Decoder0~66 .sum_lutc_input = "datac"; -defparam \Decoder0~66 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N1 -maxii_lcell \cache_line_sdata[1] ( -// Equation(s): -// cache_line_sdata[1] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~66_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~66_combout & ((cache_line_sdata[1]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[1]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~66_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[1]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[1] .lut_mask = "050c"; -defparam \cache_line_sdata[1] .operation_mode = "normal"; -defparam \cache_line_sdata[1] .output_mode = "reg_only"; -defparam \cache_line_sdata[1] .register_cascade_mode = "off"; -defparam \cache_line_sdata[1] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[1] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N9 -maxii_lcell \cache2_line_sdata[1] ( -// Equation(s): -// cache2_line_sdata[1] = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache_line_sdata[1]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[1]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[1]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[1] .lut_mask = "0300"; -defparam \cache2_line_sdata[1] .operation_mode = "normal"; -defparam \cache2_line_sdata[1] .output_mode = "reg_only"; -defparam \cache2_line_sdata[1] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[1] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[1] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y6_N7 -maxii_lcell \signal_high_voltage[1]~reg0 ( -// Equation(s): -// \signal_high_voltage[1]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[1] & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[1]), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[1]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[1]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[1]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[1]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[1]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[1]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[1]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y7_N8 -maxii_lcell \Decoder0~64 ( -// Equation(s): -// \Decoder0~64_combout = (((!i[5] & !i[0]))) - - .clk(gnd), - .dataa(vcc), - .datab(vcc), - .datac(i[5]), - .datad(i[0]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~64_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~64 .lut_mask = "000f"; -defparam \Decoder0~64 .operation_mode = "normal"; -defparam \Decoder0~64 .output_mode = "comb_only"; -defparam \Decoder0~64 .register_cascade_mode = "off"; -defparam \Decoder0~64 .sum_lutc_input = "datac"; -defparam \Decoder0~64 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y7_N2 -maxii_lcell \always3~0 ( -// Equation(s): -// \always3~0_combout = (((\filter_line_sen~regout & \posedge_line_sclk~regout ))) - - .clk(gnd), - .dataa(vcc), - .datab(vcc), - .datac(\filter_line_sen~regout ), - .datad(\posedge_line_sclk~regout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\always3~0_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \always3~0 .lut_mask = "f000"; -defparam \always3~0 .operation_mode = "normal"; -defparam \always3~0 .output_mode = "comb_only"; -defparam \always3~0 .register_cascade_mode = "off"; -defparam \always3~0 .sum_lutc_input = "datac"; -defparam \always3~0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N5 -maxii_lcell \Decoder0~68 ( -// Equation(s): -// \Decoder0~68_combout = (!i[4] & (i[1] & (\always3~0_combout & \recv_complete~9_combout ))) - - .clk(gnd), - .dataa(i[4]), - .datab(i[1]), - .datac(\always3~0_combout ), - .datad(\recv_complete~9_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~68_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~68 .lut_mask = "4000"; -defparam \Decoder0~68 .operation_mode = "normal"; -defparam \Decoder0~68 .output_mode = "comb_only"; -defparam \Decoder0~68 .register_cascade_mode = "off"; -defparam \Decoder0~68 .sum_lutc_input = "datac"; -defparam \Decoder0~68 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y7_N4 -maxii_lcell \Decoder0~102 ( -// Equation(s): -// \Decoder0~102_combout = (!i[3] & (!i[2] & (\Decoder0~64_combout & \Decoder0~68_combout ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[2]), - .datac(\Decoder0~64_combout ), - .datad(\Decoder0~68_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~102_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~102 .lut_mask = "1000"; -defparam \Decoder0~102 .operation_mode = "normal"; -defparam \Decoder0~102 .output_mode = "comb_only"; -defparam \Decoder0~102 .register_cascade_mode = "off"; -defparam \Decoder0~102 .sum_lutc_input = "datac"; -defparam \Decoder0~102 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y7_N5 -maxii_lcell \cache_line_sdata[2] ( -// Equation(s): -// cache_line_sdata[2] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~102_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~102_combout & (cache_line_sdata[2])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[2]), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~102_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[2]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[2] .lut_mask = "0322"; -defparam \cache_line_sdata[2] .operation_mode = "normal"; -defparam \cache_line_sdata[2] .output_mode = "reg_only"; -defparam \cache_line_sdata[2] .register_cascade_mode = "off"; -defparam \cache_line_sdata[2] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[2] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N0 -maxii_lcell \cache2_line_sdata[2] ( -// Equation(s): -// cache2_line_sdata[2] = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache_line_sdata[2])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[2]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[2]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[2] .lut_mask = "0500"; -defparam \cache2_line_sdata[2] .operation_mode = "normal"; -defparam \cache2_line_sdata[2] .output_mode = "reg_only"; -defparam \cache2_line_sdata[2] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[2] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[2] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y6_N9 -maxii_lcell \signal_high_voltage[2]~reg0 ( -// Equation(s): -// \signal_high_voltage[2]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[2] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[2]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[2]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[2]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[2]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[2]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[2]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[2]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[2]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y10_N2 -maxii_lcell \Decoder0~69 ( -// Equation(s): -// \Decoder0~69_combout = ((i[0] & (i[1] & \Decoder0~65 ))) - - .clk(gnd), - .dataa(vcc), - .datab(i[0]), - .datac(i[1]), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~69_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~69 .lut_mask = "c000"; -defparam \Decoder0~69 .operation_mode = "normal"; -defparam \Decoder0~69 .output_mode = "comb_only"; -defparam \Decoder0~69 .register_cascade_mode = "off"; -defparam \Decoder0~69 .sum_lutc_input = "datac"; -defparam \Decoder0~69 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y7_N3 -maxii_lcell \Decoder0~103 ( -// Equation(s): -// \Decoder0~103_combout = (!i[2] & (!i[5] & (\Decoder0~69_combout & !i[3]))) - - .clk(gnd), - .dataa(i[2]), - .datab(i[5]), - .datac(\Decoder0~69_combout ), - .datad(i[3]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~103_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~103 .lut_mask = "0010"; -defparam \Decoder0~103 .operation_mode = "normal"; -defparam \Decoder0~103 .output_mode = "comb_only"; -defparam \Decoder0~103 .register_cascade_mode = "off"; -defparam \Decoder0~103 .sum_lutc_input = "datac"; -defparam \Decoder0~103 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y7_N7 -maxii_lcell \cache_line_sdata[3] ( -// Equation(s): -// cache_line_sdata[3] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~103_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~103_combout & (cache_line_sdata[3])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[3]), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~103_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[3]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[3] .lut_mask = "0322"; -defparam \cache_line_sdata[3] .operation_mode = "normal"; -defparam \cache_line_sdata[3] .output_mode = "reg_only"; -defparam \cache_line_sdata[3] .register_cascade_mode = "off"; -defparam \cache_line_sdata[3] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[3] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y6_N5 -maxii_lcell \cache2_line_sdata[3] ( -// Equation(s): -// cache2_line_sdata[3] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache_line_sdata[3])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache_line_sdata[3]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[3]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[3] .lut_mask = "1100"; -defparam \cache2_line_sdata[3] .operation_mode = "normal"; -defparam \cache2_line_sdata[3] .output_mode = "reg_only"; -defparam \cache2_line_sdata[3] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[3] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[3] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y5_N4 -maxii_lcell \signal_high_voltage[3]~reg0 ( -// Equation(s): -// \signal_high_voltage[3]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[3] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[3]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[3]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[3]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[3]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[3]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[3]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[3]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[3]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y6_N8 -maxii_lcell \Decoder0~70 ( -// Equation(s): -// \Decoder0~70_combout = ((!i[1] & (!i[5] & !i[0]))) - - .clk(gnd), - .dataa(vcc), - .datab(i[1]), - .datac(i[5]), - .datad(i[0]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~70_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~70 .lut_mask = "0003"; -defparam \Decoder0~70 .operation_mode = "normal"; -defparam \Decoder0~70 .output_mode = "comb_only"; -defparam \Decoder0~70 .register_cascade_mode = "off"; -defparam \Decoder0~70 .sum_lutc_input = "datac"; -defparam \Decoder0~70 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N3 -maxii_lcell \Decoder0~71 ( -// Equation(s): -// \Decoder0~71_combout = (i[2] & (\Decoder0~70_combout & (!i[3] & \Decoder0~65 ))) - - .clk(gnd), - .dataa(i[2]), - .datab(\Decoder0~70_combout ), - .datac(i[3]), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~71_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~71 .lut_mask = "0800"; -defparam \Decoder0~71 .operation_mode = "normal"; -defparam \Decoder0~71 .output_mode = "comb_only"; -defparam \Decoder0~71 .register_cascade_mode = "off"; -defparam \Decoder0~71 .sum_lutc_input = "datac"; -defparam \Decoder0~71 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N4 -maxii_lcell \cache_line_sdata[4] ( -// Equation(s): -// cache_line_sdata[4] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~71_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~71_combout & ((cache_line_sdata[4]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[4]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~71_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[4]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[4] .lut_mask = "050c"; -defparam \cache_line_sdata[4] .operation_mode = "normal"; -defparam \cache_line_sdata[4] .output_mode = "reg_only"; -defparam \cache_line_sdata[4] .register_cascade_mode = "off"; -defparam \cache_line_sdata[4] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[4] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y6_N2 -maxii_lcell \cache2_line_sdata[4] ( -// Equation(s): -// cache2_line_sdata[4] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache_line_sdata[4])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache_line_sdata[4]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[4]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[4] .lut_mask = "1100"; -defparam \cache2_line_sdata[4] .operation_mode = "normal"; -defparam \cache2_line_sdata[4] .output_mode = "reg_only"; -defparam \cache2_line_sdata[4] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[4] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[4] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y5_N2 -maxii_lcell \signal_high_voltage[4]~reg0 ( -// Equation(s): -// \signal_high_voltage[4]~reg0_regout = DFFEAS((cache2_line_sdata[4] & (\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache2_line_sdata[4]), - .datab(\is_high_voltage_time~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[4]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[4]~reg0 .lut_mask = "0008"; -defparam \signal_high_voltage[4]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[4]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[4]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[4]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[4]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y10_N0 -maxii_lcell \Decoder0~72 ( -// Equation(s): -// \Decoder0~72_combout = ((i[0] & (!i[1] & \Decoder0~65 ))) - - .clk(gnd), - .dataa(vcc), - .datab(i[0]), - .datac(i[1]), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~72_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~72 .lut_mask = "0c00"; -defparam \Decoder0~72 .operation_mode = "normal"; -defparam \Decoder0~72 .output_mode = "comb_only"; -defparam \Decoder0~72 .register_cascade_mode = "off"; -defparam \Decoder0~72 .sum_lutc_input = "datac"; -defparam \Decoder0~72 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N8 -maxii_lcell \Decoder0~104 ( -// Equation(s): -// \Decoder0~104_combout = (!i[5] & (i[2] & (!i[3] & \Decoder0~72_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[2]), - .datac(i[3]), - .datad(\Decoder0~72_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~104_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~104 .lut_mask = "0400"; -defparam \Decoder0~104 .operation_mode = "normal"; -defparam \Decoder0~104 .output_mode = "comb_only"; -defparam \Decoder0~104 .register_cascade_mode = "off"; -defparam \Decoder0~104 .sum_lutc_input = "datac"; -defparam \Decoder0~104 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N9 -maxii_lcell \cache_line_sdata[5] ( -// Equation(s): -// cache_line_sdata[5] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~104_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~104_combout & ((cache_line_sdata[5]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[5]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~104_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[5]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[5] .lut_mask = "050c"; -defparam \cache_line_sdata[5] .operation_mode = "normal"; -defparam \cache_line_sdata[5] .output_mode = "reg_only"; -defparam \cache_line_sdata[5] .register_cascade_mode = "off"; -defparam \cache_line_sdata[5] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[5] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N0 -maxii_lcell \cache2_line_sdata[5] ( -// Equation(s): -// cache2_line_sdata[5] = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache_line_sdata[5]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[5]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[5]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[5] .lut_mask = "0300"; -defparam \cache2_line_sdata[5] .operation_mode = "normal"; -defparam \cache2_line_sdata[5] .output_mode = "reg_only"; -defparam \cache2_line_sdata[5] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[5] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[5] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N8 -maxii_lcell \signal_high_voltage[5]~reg0 ( -// Equation(s): -// \signal_high_voltage[5]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[5] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[5]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[5]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[5]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[5]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[5]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[5]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[5]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[5]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N4 -maxii_lcell \Decoder0~73 ( -// Equation(s): -// \Decoder0~73_combout = (!i[3] & (((i[2])))) - - .clk(gnd), - .dataa(i[3]), - .datab(vcc), - .datac(i[2]), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~73_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~73 .lut_mask = "5050"; -defparam \Decoder0~73 .operation_mode = "normal"; -defparam \Decoder0~73 .output_mode = "comb_only"; -defparam \Decoder0~73 .register_cascade_mode = "off"; -defparam \Decoder0~73 .sum_lutc_input = "datac"; -defparam \Decoder0~73 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N9 -maxii_lcell \Decoder0~105 ( -// Equation(s): -// \Decoder0~105_combout = (!i[5] & (!i[0] & (\Decoder0~68_combout & \Decoder0~73_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[0]), - .datac(\Decoder0~68_combout ), - .datad(\Decoder0~73_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~105_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~105 .lut_mask = "1000"; -defparam \Decoder0~105 .operation_mode = "normal"; -defparam \Decoder0~105 .output_mode = "comb_only"; -defparam \Decoder0~105 .register_cascade_mode = "off"; -defparam \Decoder0~105 .sum_lutc_input = "datac"; -defparam \Decoder0~105 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N4 -maxii_lcell \cache_line_sdata[6] ( -// Equation(s): -// cache_line_sdata[6] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~105_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~105_combout & ((cache_line_sdata[6]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[6]), - .datad(\Decoder0~105_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[6]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[6] .lut_mask = "1130"; -defparam \cache_line_sdata[6] .operation_mode = "normal"; -defparam \cache_line_sdata[6] .output_mode = "reg_only"; -defparam \cache_line_sdata[6] .register_cascade_mode = "off"; -defparam \cache_line_sdata[6] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[6] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N1 -maxii_lcell \cache2_line_sdata[6] ( -// Equation(s): -// cache2_line_sdata[6] = DFFEAS((cache_line_sdata[6] & (((!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[6]), - .datab(vcc), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[6]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[6] .lut_mask = "000a"; -defparam \cache2_line_sdata[6] .operation_mode = "normal"; -defparam \cache2_line_sdata[6] .output_mode = "reg_only"; -defparam \cache2_line_sdata[6] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[6] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[6] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N7 -maxii_lcell \signal_high_voltage[6]~reg0 ( -// Equation(s): -// \signal_high_voltage[6]~reg0_regout = DFFEAS((\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & (cache2_line_sdata[6] & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\is_high_voltage_time~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(cache2_line_sdata[6]), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[6]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[6]~reg0 .lut_mask = "0020"; -defparam \signal_high_voltage[6]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[6]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[6]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[6]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[6]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y7_N9 -maxii_lcell \Decoder0~106 ( -// Equation(s): -// \Decoder0~106_combout = (i[2] & (!i[5] & (\Decoder0~69_combout & !i[3]))) - - .clk(gnd), - .dataa(i[2]), - .datab(i[5]), - .datac(\Decoder0~69_combout ), - .datad(i[3]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~106_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~106 .lut_mask = "0020"; -defparam \Decoder0~106 .operation_mode = "normal"; -defparam \Decoder0~106 .output_mode = "comb_only"; -defparam \Decoder0~106 .register_cascade_mode = "off"; -defparam \Decoder0~106 .sum_lutc_input = "datac"; -defparam \Decoder0~106 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y7_N1 -maxii_lcell \cache_line_sdata[7] ( -// Equation(s): -// cache_line_sdata[7] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~106_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~106_combout & ((cache_line_sdata[7]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[7]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~106_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[7]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[7] .lut_mask = "050c"; -defparam \cache_line_sdata[7] .operation_mode = "normal"; -defparam \cache_line_sdata[7] .output_mode = "reg_only"; -defparam \cache_line_sdata[7] .register_cascade_mode = "off"; -defparam \cache_line_sdata[7] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[7] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N0 -maxii_lcell \cache2_line_sdata[7] ( -// Equation(s): -// cache2_line_sdata[7] = DFFEAS((cache_line_sdata[7] & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[7]), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[7]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[7] .lut_mask = "0202"; -defparam \cache2_line_sdata[7] .operation_mode = "normal"; -defparam \cache2_line_sdata[7] .output_mode = "reg_only"; -defparam \cache2_line_sdata[7] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[7] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[7] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y4_N4 -maxii_lcell \signal_high_voltage[7]~reg0 ( -// Equation(s): -// \signal_high_voltage[7]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[7] & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[7]), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[7]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[7]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[7]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[7]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[7]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[7]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[7]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N6 -maxii_lcell \Decoder0~107 ( -// Equation(s): -// \Decoder0~107_combout = (!i[2] & (\Decoder0~70_combout & (i[3] & \Decoder0~65 ))) - - .clk(gnd), - .dataa(i[2]), - .datab(\Decoder0~70_combout ), - .datac(i[3]), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~107_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~107 .lut_mask = "4000"; -defparam \Decoder0~107 .operation_mode = "normal"; -defparam \Decoder0~107 .output_mode = "comb_only"; -defparam \Decoder0~107 .register_cascade_mode = "off"; -defparam \Decoder0~107 .sum_lutc_input = "datac"; -defparam \Decoder0~107 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N7 -maxii_lcell \cache_line_sdata[8] ( -// Equation(s): -// cache_line_sdata[8] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~107_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~107_combout & (cache_line_sdata[8])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[8]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~107_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[8]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[8] .lut_mask = "0544"; -defparam \cache_line_sdata[8] .operation_mode = "normal"; -defparam \cache_line_sdata[8] .output_mode = "reg_only"; -defparam \cache_line_sdata[8] .register_cascade_mode = "off"; -defparam \cache_line_sdata[8] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[8] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N3 -maxii_lcell \cache2_line_sdata[8] ( -// Equation(s): -// cache2_line_sdata[8] = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache_line_sdata[8])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[8]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[8]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[8] .lut_mask = "0500"; -defparam \cache2_line_sdata[8] .operation_mode = "normal"; -defparam \cache2_line_sdata[8] .output_mode = "reg_only"; -defparam \cache2_line_sdata[8] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[8] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[8] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y5_N3 -maxii_lcell \signal_high_voltage[8]~reg0 ( -// Equation(s): -// \signal_high_voltage[8]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[8] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[8]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[8]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[8]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[8]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[8]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[8]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[8]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[8]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N2 -maxii_lcell \Decoder0~108 ( -// Equation(s): -// \Decoder0~108_combout = (!i[5] & (!i[2] & (i[3] & \Decoder0~72_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[2]), - .datac(i[3]), - .datad(\Decoder0~72_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~108_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~108 .lut_mask = "1000"; -defparam \Decoder0~108 .operation_mode = "normal"; -defparam \Decoder0~108 .output_mode = "comb_only"; -defparam \Decoder0~108 .register_cascade_mode = "off"; -defparam \Decoder0~108 .sum_lutc_input = "datac"; -defparam \Decoder0~108 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N0 -maxii_lcell \cache_line_sdata[9] ( -// Equation(s): -// cache_line_sdata[9] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~108_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~108_combout & ((cache_line_sdata[9]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[9]), - .datad(\Decoder0~108_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[9]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[9] .lut_mask = "1130"; -defparam \cache_line_sdata[9] .operation_mode = "normal"; -defparam \cache_line_sdata[9] .output_mode = "reg_only"; -defparam \cache_line_sdata[9] .register_cascade_mode = "off"; -defparam \cache_line_sdata[9] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[9] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N6 -maxii_lcell \cache2_line_sdata[9] ( -// Equation(s): -// cache2_line_sdata[9] = DFFEAS((cache_line_sdata[9] & (((!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[9]), - .datab(vcc), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[9]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[9] .lut_mask = "000a"; -defparam \cache2_line_sdata[9] .operation_mode = "normal"; -defparam \cache2_line_sdata[9] .output_mode = "reg_only"; -defparam \cache2_line_sdata[9] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[9] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[9] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y4_N6 -maxii_lcell \signal_high_voltage[9]~reg0 ( -// Equation(s): -// \signal_high_voltage[9]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & (\is_high_voltage_time~regout & cache2_line_sdata[9]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\is_high_voltage_time~regout ), - .datad(cache2_line_sdata[9]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[9]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[9]~reg0 .lut_mask = "1000"; -defparam \signal_high_voltage[9]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[9]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[9]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[9]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[9]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y6_N1 -maxii_lcell \Decoder0~74 ( -// Equation(s): -// \Decoder0~74_combout = (((!i[2] & i[3]))) - - .clk(gnd), - .dataa(vcc), - .datab(vcc), - .datac(i[2]), - .datad(i[3]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~74_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~74 .lut_mask = "0f00"; -defparam \Decoder0~74 .operation_mode = "normal"; -defparam \Decoder0~74 .output_mode = "comb_only"; -defparam \Decoder0~74 .register_cascade_mode = "off"; -defparam \Decoder0~74 .sum_lutc_input = "datac"; -defparam \Decoder0~74 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N8 -maxii_lcell \Decoder0~109 ( -// Equation(s): -// \Decoder0~109_combout = (!i[0] & (!i[5] & (\Decoder0~74_combout & \Decoder0~68_combout ))) - - .clk(gnd), - .dataa(i[0]), - .datab(i[5]), - .datac(\Decoder0~74_combout ), - .datad(\Decoder0~68_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~109_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~109 .lut_mask = "1000"; -defparam \Decoder0~109 .operation_mode = "normal"; -defparam \Decoder0~109 .output_mode = "comb_only"; -defparam \Decoder0~109 .register_cascade_mode = "off"; -defparam \Decoder0~109 .sum_lutc_input = "datac"; -defparam \Decoder0~109 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N9 -maxii_lcell \cache_line_sdata[10] ( -// Equation(s): -// cache_line_sdata[10] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~109_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~109_combout & (cache_line_sdata[10])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[10]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~109_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[10]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[10] .lut_mask = "0544"; -defparam \cache_line_sdata[10] .operation_mode = "normal"; -defparam \cache_line_sdata[10] .output_mode = "reg_only"; -defparam \cache_line_sdata[10] .register_cascade_mode = "off"; -defparam \cache_line_sdata[10] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[10] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N0 -maxii_lcell \cache2_line_sdata[10] ( -// Equation(s): -// cache2_line_sdata[10] = DFFEAS(((cache_line_sdata[10] & (!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache_line_sdata[10]), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[10]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[10] .lut_mask = "000c"; -defparam \cache2_line_sdata[10] .operation_mode = "normal"; -defparam \cache2_line_sdata[10] .output_mode = "reg_only"; -defparam \cache2_line_sdata[10] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[10] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[10] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y7_N6 -maxii_lcell \signal_high_voltage[10]~reg0 ( -// Equation(s): -// \signal_high_voltage[10]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & cache2_line_sdata[10]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\is_high_voltage_time~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(cache2_line_sdata[10]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[10]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[10]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[10]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[10]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[10]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[10]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[10]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N8 -maxii_lcell \Decoder0~110 ( -// Equation(s): -// \Decoder0~110_combout = (!i[5] & (i[3] & (!i[2] & \Decoder0~69_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[3]), - .datac(i[2]), - .datad(\Decoder0~69_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~110_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~110 .lut_mask = "0400"; -defparam \Decoder0~110 .operation_mode = "normal"; -defparam \Decoder0~110 .output_mode = "comb_only"; -defparam \Decoder0~110 .register_cascade_mode = "off"; -defparam \Decoder0~110 .sum_lutc_input = "datac"; -defparam \Decoder0~110 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N9 -maxii_lcell \cache_line_sdata[11] ( -// Equation(s): -// cache_line_sdata[11] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~110_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~110_combout & ((cache_line_sdata[11]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[11]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~110_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[11]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[11] .lut_mask = "050c"; -defparam \cache_line_sdata[11] .operation_mode = "normal"; -defparam \cache_line_sdata[11] .output_mode = "reg_only"; -defparam \cache_line_sdata[11] .register_cascade_mode = "off"; -defparam \cache_line_sdata[11] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[11] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N6 -maxii_lcell \cache2_line_sdata[11] ( -// Equation(s): -// cache2_line_sdata[11] = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache_line_sdata[11])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[11]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[11]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[11] .lut_mask = "0500"; -defparam \cache2_line_sdata[11] .operation_mode = "normal"; -defparam \cache2_line_sdata[11] .output_mode = "reg_only"; -defparam \cache2_line_sdata[11] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[11] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[11] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y4_N1 -maxii_lcell \signal_high_voltage[11]~reg0 ( -// Equation(s): -// \signal_high_voltage[11]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & (\is_high_voltage_time~regout & cache2_line_sdata[11]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\is_high_voltage_time~regout ), - .datad(cache2_line_sdata[11]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[11]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[11]~reg0 .lut_mask = "1000"; -defparam \signal_high_voltage[11]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[11]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[11]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[11]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[11]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N2 -maxii_lcell \Decoder0~76 ( -// Equation(s): -// \Decoder0~76_combout = (i[2] & (\Decoder0~70_combout & (i[3] & \Decoder0~65 ))) - - .clk(gnd), - .dataa(i[2]), - .datab(\Decoder0~70_combout ), - .datac(i[3]), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~76_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~76 .lut_mask = "8000"; -defparam \Decoder0~76 .operation_mode = "normal"; -defparam \Decoder0~76 .output_mode = "comb_only"; -defparam \Decoder0~76 .register_cascade_mode = "off"; -defparam \Decoder0~76 .sum_lutc_input = "datac"; -defparam \Decoder0~76 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y8_N0 -maxii_lcell \cache_line_sdata[12] ( -// Equation(s): -// cache_line_sdata[12] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~76_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~76_combout & (cache_line_sdata[12])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[12]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~76_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[12]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[12] .lut_mask = "0544"; -defparam \cache_line_sdata[12] .operation_mode = "normal"; -defparam \cache_line_sdata[12] .output_mode = "reg_only"; -defparam \cache_line_sdata[12] .register_cascade_mode = "off"; -defparam \cache_line_sdata[12] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[12] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N2 -maxii_lcell \cache2_line_sdata[12] ( -// Equation(s): -// cache2_line_sdata[12] = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache_line_sdata[12])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[12]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[12]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[12] .lut_mask = "0500"; -defparam \cache2_line_sdata[12] .operation_mode = "normal"; -defparam \cache2_line_sdata[12] .output_mode = "reg_only"; -defparam \cache2_line_sdata[12] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[12] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[12] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y5_N8 -maxii_lcell \signal_high_voltage[12]~reg0 ( -// Equation(s): -// \signal_high_voltage[12]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[12] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[12]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[12]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[12]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[12]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[12]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[12]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[12]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[12]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N1 -maxii_lcell \Decoder0~111 ( -// Equation(s): -// \Decoder0~111_combout = (!i[5] & (i[2] & (i[3] & \Decoder0~72_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[2]), - .datac(i[3]), - .datad(\Decoder0~72_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~111_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~111 .lut_mask = "4000"; -defparam \Decoder0~111 .operation_mode = "normal"; -defparam \Decoder0~111 .output_mode = "comb_only"; -defparam \Decoder0~111 .register_cascade_mode = "off"; -defparam \Decoder0~111 .sum_lutc_input = "datac"; -defparam \Decoder0~111 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N5 -maxii_lcell \cache_line_sdata[13] ( -// Equation(s): -// cache_line_sdata[13] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~111_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~111_combout & ((cache_line_sdata[13]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[13]), - .datad(\Decoder0~111_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[13]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[13] .lut_mask = "1130"; -defparam \cache_line_sdata[13] .operation_mode = "normal"; -defparam \cache_line_sdata[13] .output_mode = "reg_only"; -defparam \cache_line_sdata[13] .register_cascade_mode = "off"; -defparam \cache_line_sdata[13] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[13] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N5 -maxii_lcell \cache2_line_sdata[13] ( -// Equation(s): -// cache2_line_sdata[13] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache_line_sdata[13])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache_line_sdata[13]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[13]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[13] .lut_mask = "1100"; -defparam \cache2_line_sdata[13] .operation_mode = "normal"; -defparam \cache2_line_sdata[13] .output_mode = "reg_only"; -defparam \cache2_line_sdata[13] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[13] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[13] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y4_N9 -maxii_lcell \signal_high_voltage[13]~reg0 ( -// Equation(s): -// \signal_high_voltage[13]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & (\is_high_voltage_time~regout & cache2_line_sdata[13]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\is_high_voltage_time~regout ), - .datad(cache2_line_sdata[13]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[13]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[13]~reg0 .lut_mask = "1000"; -defparam \signal_high_voltage[13]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[13]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[13]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[13]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[13]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N1 -maxii_lcell \Decoder0~77 ( -// Equation(s): -// \Decoder0~77_combout = (\Decoder0~64_combout & (i[3] & (i[2] & \Decoder0~68_combout ))) - - .clk(gnd), - .dataa(\Decoder0~64_combout ), - .datab(i[3]), - .datac(i[2]), - .datad(\Decoder0~68_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~77_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~77 .lut_mask = "8000"; -defparam \Decoder0~77 .operation_mode = "normal"; -defparam \Decoder0~77 .output_mode = "comb_only"; -defparam \Decoder0~77 .register_cascade_mode = "off"; -defparam \Decoder0~77 .sum_lutc_input = "datac"; -defparam \Decoder0~77 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N2 -maxii_lcell \cache_line_sdata[14] ( -// Equation(s): -// cache_line_sdata[14] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~77_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~77_combout & ((cache_line_sdata[14]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[14]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~77_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[14]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[14] .lut_mask = "050c"; -defparam \cache_line_sdata[14] .operation_mode = "normal"; -defparam \cache_line_sdata[14] .output_mode = "reg_only"; -defparam \cache_line_sdata[14] .register_cascade_mode = "off"; -defparam \cache_line_sdata[14] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[14] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N5 -maxii_lcell \cache2_line_sdata[14] ( -// Equation(s): -// cache2_line_sdata[14] = DFFEAS(((cache_line_sdata[14] & (!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache_line_sdata[14]), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[14]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[14] .lut_mask = "000c"; -defparam \cache2_line_sdata[14] .operation_mode = "normal"; -defparam \cache2_line_sdata[14] .output_mode = "reg_only"; -defparam \cache2_line_sdata[14] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[14] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[14] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y4_N6 -maxii_lcell \signal_high_voltage[14]~reg0 ( -// Equation(s): -// \signal_high_voltage[14]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (\is_high_voltage_time~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[14]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\is_high_voltage_time~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[14]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[14]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[14]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[14]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[14]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[14]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[14]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[14]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N4 -maxii_lcell \Decoder0~112 ( -// Equation(s): -// \Decoder0~112_combout = (!i[5] & (i[3] & (i[2] & \Decoder0~69_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[3]), - .datac(i[2]), - .datad(\Decoder0~69_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~112_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~112 .lut_mask = "4000"; -defparam \Decoder0~112 .operation_mode = "normal"; -defparam \Decoder0~112 .output_mode = "comb_only"; -defparam \Decoder0~112 .register_cascade_mode = "off"; -defparam \Decoder0~112 .sum_lutc_input = "datac"; -defparam \Decoder0~112 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N5 -maxii_lcell \cache_line_sdata[15] ( -// Equation(s): -// cache_line_sdata[15] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~112_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~112_combout & ((cache_line_sdata[15]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[15]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~112_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[15]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[15] .lut_mask = "050c"; -defparam \cache_line_sdata[15] .operation_mode = "normal"; -defparam \cache_line_sdata[15] .output_mode = "reg_only"; -defparam \cache_line_sdata[15] .register_cascade_mode = "off"; -defparam \cache_line_sdata[15] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[15] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N3 -maxii_lcell \cache2_line_sdata[15] ( -// Equation(s): -// cache2_line_sdata[15] = DFFEAS(((cache_line_sdata[15] & (!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache_line_sdata[15]), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[15]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[15] .lut_mask = "000c"; -defparam \cache2_line_sdata[15] .operation_mode = "normal"; -defparam \cache2_line_sdata[15] .output_mode = "reg_only"; -defparam \cache2_line_sdata[15] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[15] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[15] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N3 -maxii_lcell \signal_high_voltage[15]~reg0 ( -// Equation(s): -// \signal_high_voltage[15]~reg0_regout = DFFEAS((\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[15]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\is_high_voltage_time~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[15]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[15]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[15]~reg0 .lut_mask = "0200"; -defparam \signal_high_voltage[15]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[15]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[15]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[15]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[15]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N2 -maxii_lcell \Decoder0~78 ( -// Equation(s): -// \Decoder0~78_combout = (\Decoder0~64_combout & (i[4] & (\always3~0_combout & \recv_complete~9_combout ))) - - .clk(gnd), - .dataa(\Decoder0~64_combout ), - .datab(i[4]), - .datac(\always3~0_combout ), - .datad(\recv_complete~9_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~78_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~78 .lut_mask = "8000"; -defparam \Decoder0~78 .operation_mode = "normal"; -defparam \Decoder0~78 .output_mode = "comb_only"; -defparam \Decoder0~78 .register_cascade_mode = "off"; -defparam \Decoder0~78 .sum_lutc_input = "datac"; -defparam \Decoder0~78 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N4 -maxii_lcell \Decoder0~113 ( -// Equation(s): -// \Decoder0~113_combout = (!i[1] & (!i[2] & (!i[3] & \Decoder0~78_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[2]), - .datac(i[3]), - .datad(\Decoder0~78_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~113_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~113 .lut_mask = "0100"; -defparam \Decoder0~113 .operation_mode = "normal"; -defparam \Decoder0~113 .output_mode = "comb_only"; -defparam \Decoder0~113 .register_cascade_mode = "off"; -defparam \Decoder0~113 .sum_lutc_input = "datac"; -defparam \Decoder0~113 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N5 -maxii_lcell \cache_line_sdata[16] ( -// Equation(s): -// cache_line_sdata[16] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~113_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~113_combout & ((cache_line_sdata[16]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[16]), - .datad(\Decoder0~113_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[16]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[16] .lut_mask = "1130"; -defparam \cache_line_sdata[16] .operation_mode = "normal"; -defparam \cache_line_sdata[16] .output_mode = "reg_only"; -defparam \cache_line_sdata[16] .register_cascade_mode = "off"; -defparam \cache_line_sdata[16] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[16] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N7 -maxii_lcell \cache2_line_sdata[16] ( -// Equation(s): -// cache2_line_sdata[16] = DFFEAS((cache_line_sdata[16] & (((!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[16]), - .datab(vcc), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[16]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[16] .lut_mask = "000a"; -defparam \cache2_line_sdata[16] .operation_mode = "normal"; -defparam \cache2_line_sdata[16] .output_mode = "reg_only"; -defparam \cache2_line_sdata[16] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[16] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[16] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y7_N9 -maxii_lcell \signal_high_voltage[16]~reg0 ( -// Equation(s): -// \signal_high_voltage[16]~reg0_regout = DFFEAS((cache2_line_sdata[16] & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache2_line_sdata[16]), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[16]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[16]~reg0 .lut_mask = "0200"; -defparam \signal_high_voltage[16]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[16]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[16]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[16]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[16]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N7 -maxii_lcell \Decoder0~79 ( -// Equation(s): -// \Decoder0~79_combout = (i[4] & (\always3~0_combout & (\recv_complete~9_combout & i[0]))) - - .clk(gnd), - .dataa(i[4]), - .datab(\always3~0_combout ), - .datac(\recv_complete~9_combout ), - .datad(i[0]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~79_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~79 .lut_mask = "8000"; -defparam \Decoder0~79 .operation_mode = "normal"; -defparam \Decoder0~79 .output_mode = "comb_only"; -defparam \Decoder0~79 .register_cascade_mode = "off"; -defparam \Decoder0~79 .sum_lutc_input = "datac"; -defparam \Decoder0~79 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N0 -maxii_lcell \Decoder0~80 ( -// Equation(s): -// \Decoder0~80_combout = (!i[5] & (((\Decoder0~79_combout & \recv_complete~0_combout )))) - - .clk(gnd), - .dataa(i[5]), - .datab(vcc), - .datac(\Decoder0~79_combout ), - .datad(\recv_complete~0_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~80_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~80 .lut_mask = "5000"; -defparam \Decoder0~80 .operation_mode = "normal"; -defparam \Decoder0~80 .output_mode = "comb_only"; -defparam \Decoder0~80 .register_cascade_mode = "off"; -defparam \Decoder0~80 .sum_lutc_input = "datac"; -defparam \Decoder0~80 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N1 -maxii_lcell \cache_line_sdata[17] ( -// Equation(s): -// cache_line_sdata[17] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~80_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~80_combout & ((cache_line_sdata[17]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[17]), - .datad(\Decoder0~80_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[17]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[17] .lut_mask = "1130"; -defparam \cache_line_sdata[17] .operation_mode = "normal"; -defparam \cache_line_sdata[17] .output_mode = "reg_only"; -defparam \cache_line_sdata[17] .register_cascade_mode = "off"; -defparam \cache_line_sdata[17] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[17] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N6 -maxii_lcell \cache2_line_sdata[17] ( -// Equation(s): -// cache2_line_sdata[17] = DFFEAS((!\fault_flag[1][0]~regout & (((cache_line_sdata[17] & !\fault_flag[0][0]~regout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(vcc), - .datac(cache_line_sdata[17]), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[17]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[17] .lut_mask = "0050"; -defparam \cache2_line_sdata[17] .operation_mode = "normal"; -defparam \cache2_line_sdata[17] .output_mode = "reg_only"; -defparam \cache2_line_sdata[17] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[17] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[17] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N7 -maxii_lcell \signal_high_voltage[17]~reg0 ( -// Equation(s): -// \signal_high_voltage[17]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[17] & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[17]), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[17]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[17]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[17]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[17]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[17]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[17]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[17]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N8 -maxii_lcell \Decoder0~114 ( -// Equation(s): -// \Decoder0~114_combout = (i[1] & (!i[2] & (!i[3] & \Decoder0~78_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[2]), - .datac(i[3]), - .datad(\Decoder0~78_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~114_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~114 .lut_mask = "0200"; -defparam \Decoder0~114 .operation_mode = "normal"; -defparam \Decoder0~114 .output_mode = "comb_only"; -defparam \Decoder0~114 .register_cascade_mode = "off"; -defparam \Decoder0~114 .sum_lutc_input = "datac"; -defparam \Decoder0~114 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N9 -maxii_lcell \cache_line_sdata[18] ( -// Equation(s): -// cache_line_sdata[18] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~114_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~114_combout & ((cache_line_sdata[18]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[18]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~114_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[18]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[18] .lut_mask = "050c"; -defparam \cache_line_sdata[18] .operation_mode = "normal"; -defparam \cache_line_sdata[18] .output_mode = "reg_only"; -defparam \cache_line_sdata[18] .register_cascade_mode = "off"; -defparam \cache_line_sdata[18] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[18] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N4 -maxii_lcell \cache2_line_sdata[18] ( -// Equation(s): -// cache2_line_sdata[18] = DFFEAS(((!\fault_flag[0][0]~regout & (cache_line_sdata[18] & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(cache_line_sdata[18]), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[18]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[18] .lut_mask = "0030"; -defparam \cache2_line_sdata[18] .operation_mode = "normal"; -defparam \cache2_line_sdata[18] .output_mode = "reg_only"; -defparam \cache2_line_sdata[18] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[18] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[18] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N0 -maxii_lcell \signal_high_voltage[18]~reg0 ( -// Equation(s): -// \signal_high_voltage[18]~reg0_regout = DFFEAS((\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[18]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\is_high_voltage_time~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[18]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[18]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[18]~reg0 .lut_mask = "0200"; -defparam \signal_high_voltage[18]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[18]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[18]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[18]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[18]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y9_N7 -maxii_lcell \Decoder0~67 ( -// Equation(s): -// \Decoder0~67_combout = (((!i[2] & !i[3]))) - - .clk(gnd), - .dataa(vcc), - .datab(vcc), - .datac(i[2]), - .datad(i[3]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~67_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~67 .lut_mask = "000f"; -defparam \Decoder0~67 .operation_mode = "normal"; -defparam \Decoder0~67 .output_mode = "comb_only"; -defparam \Decoder0~67 .register_cascade_mode = "off"; -defparam \Decoder0~67 .sum_lutc_input = "datac"; -defparam \Decoder0~67 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y9_N4 -maxii_lcell \Decoder0~81 ( -// Equation(s): -// \Decoder0~81_combout = (i[1] & (!i[5] & (\Decoder0~67_combout & \Decoder0~79_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[5]), - .datac(\Decoder0~67_combout ), - .datad(\Decoder0~79_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~81_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~81 .lut_mask = "2000"; -defparam \Decoder0~81 .operation_mode = "normal"; -defparam \Decoder0~81 .output_mode = "comb_only"; -defparam \Decoder0~81 .register_cascade_mode = "off"; -defparam \Decoder0~81 .sum_lutc_input = "datac"; -defparam \Decoder0~81 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y9_N5 -maxii_lcell \cache_line_sdata[19] ( -// Equation(s): -// cache_line_sdata[19] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~81_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~81_combout & ((cache_line_sdata[19]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[19]), - .datad(\Decoder0~81_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[19]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[19] .lut_mask = "1130"; -defparam \cache_line_sdata[19] .operation_mode = "normal"; -defparam \cache_line_sdata[19] .output_mode = "reg_only"; -defparam \cache_line_sdata[19] .register_cascade_mode = "off"; -defparam \cache_line_sdata[19] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[19] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y6_N8 -maxii_lcell \cache2_line_sdata[19] ( -// Equation(s): -// cache2_line_sdata[19] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & (cache_line_sdata[19]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(cache_line_sdata[19]), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[19]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[19] .lut_mask = "1010"; -defparam \cache2_line_sdata[19] .operation_mode = "normal"; -defparam \cache2_line_sdata[19] .output_mode = "reg_only"; -defparam \cache2_line_sdata[19] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[19] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[19] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y5_N5 -maxii_lcell \signal_high_voltage[19]~reg0 ( -// Equation(s): -// \signal_high_voltage[19]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[19] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[19]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[19]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[19]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[19]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[19]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[19]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[19]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[19]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y6_N1 -maxii_lcell \Decoder0~82 ( -// Equation(s): -// \Decoder0~82_combout = (i[4] & (!i[0] & (!i[5] & !i[1]))) - - .clk(gnd), - .dataa(i[4]), - .datab(i[0]), - .datac(i[5]), - .datad(i[1]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~82_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~82 .lut_mask = "0002"; -defparam \Decoder0~82 .operation_mode = "normal"; -defparam \Decoder0~82 .output_mode = "comb_only"; -defparam \Decoder0~82 .register_cascade_mode = "off"; -defparam \Decoder0~82 .sum_lutc_input = "datac"; -defparam \Decoder0~82 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y6_N2 -maxii_lcell \Decoder0~115 ( -// Equation(s): -// \Decoder0~115_combout = (\filter_line_sen~regout & (i[2] & (\posedge_line_sclk~regout & \recv_complete~9_combout ))) - - .clk(gnd), - .dataa(\filter_line_sen~regout ), - .datab(i[2]), - .datac(\posedge_line_sclk~regout ), - .datad(\recv_complete~9_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~115_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~115 .lut_mask = "8000"; -defparam \Decoder0~115 .operation_mode = "normal"; -defparam \Decoder0~115 .output_mode = "comb_only"; -defparam \Decoder0~115 .register_cascade_mode = "off"; -defparam \Decoder0~115 .sum_lutc_input = "datac"; -defparam \Decoder0~115 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y6_N6 -maxii_lcell \Decoder0~83 ( -// Equation(s): -// \Decoder0~83_combout = ((!i[3] & (\Decoder0~82_combout & \Decoder0~115_combout ))) - - .clk(gnd), - .dataa(vcc), - .datab(i[3]), - .datac(\Decoder0~82_combout ), - .datad(\Decoder0~115_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~83_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~83 .lut_mask = "3000"; -defparam \Decoder0~83 .operation_mode = "normal"; -defparam \Decoder0~83 .output_mode = "comb_only"; -defparam \Decoder0~83 .register_cascade_mode = "off"; -defparam \Decoder0~83 .sum_lutc_input = "datac"; -defparam \Decoder0~83 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y6_N7 -maxii_lcell \cache_line_sdata[20] ( -// Equation(s): -// cache_line_sdata[20] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~83_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~83_combout & (cache_line_sdata[20])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[20]), - .datab(\fiter_line_sdata~regout ), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~83_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[20]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[20] .lut_mask = "030a"; -defparam \cache_line_sdata[20] .operation_mode = "normal"; -defparam \cache_line_sdata[20] .output_mode = "reg_only"; -defparam \cache_line_sdata[20] .register_cascade_mode = "off"; -defparam \cache_line_sdata[20] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[20] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N1 -maxii_lcell \cache2_line_sdata[20] ( -// Equation(s): -// cache2_line_sdata[20] = DFFEAS((!\fault_flag[1][0]~regout & (((cache_line_sdata[20] & !\fault_flag[0][0]~regout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(vcc), - .datac(cache_line_sdata[20]), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[20]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[20] .lut_mask = "0050"; -defparam \cache2_line_sdata[20] .operation_mode = "normal"; -defparam \cache2_line_sdata[20] .output_mode = "reg_only"; -defparam \cache2_line_sdata[20] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[20] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[20] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N3 -maxii_lcell \signal_high_voltage[20]~reg0 ( -// Equation(s): -// \signal_high_voltage[20]~reg0_regout = DFFEAS((\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[20]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\is_high_voltage_time~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[20]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[20]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[20]~reg0 .lut_mask = "0200"; -defparam \signal_high_voltage[20]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[20]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[20]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[20]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[20]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N2 -maxii_lcell \Decoder0~84 ( -// Equation(s): -// \Decoder0~84_combout = (!i[1] & (\Decoder0~73_combout & (\Decoder0~79_combout & !i[5]))) - - .clk(gnd), - .dataa(i[1]), - .datab(\Decoder0~73_combout ), - .datac(\Decoder0~79_combout ), - .datad(i[5]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~84_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~84 .lut_mask = "0040"; -defparam \Decoder0~84 .operation_mode = "normal"; -defparam \Decoder0~84 .output_mode = "comb_only"; -defparam \Decoder0~84 .register_cascade_mode = "off"; -defparam \Decoder0~84 .sum_lutc_input = "datac"; -defparam \Decoder0~84 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N3 -maxii_lcell \cache_line_sdata[21] ( -// Equation(s): -// cache_line_sdata[21] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~84_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~84_combout & ((cache_line_sdata[21]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[21]), - .datad(\Decoder0~84_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[21]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[21] .lut_mask = "1130"; -defparam \cache_line_sdata[21] .operation_mode = "normal"; -defparam \cache_line_sdata[21] .output_mode = "reg_only"; -defparam \cache_line_sdata[21] .register_cascade_mode = "off"; -defparam \cache_line_sdata[21] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[21] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y6_N6 -maxii_lcell \cache2_line_sdata[21] ( -// Equation(s): -// cache2_line_sdata[21] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & (cache_line_sdata[21]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(cache_line_sdata[21]), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[21]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[21] .lut_mask = "1010"; -defparam \cache2_line_sdata[21] .operation_mode = "normal"; -defparam \cache2_line_sdata[21] .output_mode = "reg_only"; -defparam \cache2_line_sdata[21] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[21] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[21] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y6_N4 -maxii_lcell \signal_high_voltage[21]~reg0 ( -// Equation(s): -// \signal_high_voltage[21]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & (cache2_line_sdata[21] & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(cache2_line_sdata[21]), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[21]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[21]~reg0 .lut_mask = "1000"; -defparam \signal_high_voltage[21]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[21]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[21]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[21]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[21]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N0 -maxii_lcell \Decoder0~116 ( -// Equation(s): -// \Decoder0~116_combout = (i[1] & (i[2] & (!i[3] & \Decoder0~78_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[2]), - .datac(i[3]), - .datad(\Decoder0~78_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~116_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~116 .lut_mask = "0800"; -defparam \Decoder0~116 .operation_mode = "normal"; -defparam \Decoder0~116 .output_mode = "comb_only"; -defparam \Decoder0~116 .register_cascade_mode = "off"; -defparam \Decoder0~116 .sum_lutc_input = "datac"; -defparam \Decoder0~116 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N1 -maxii_lcell \cache_line_sdata[22] ( -// Equation(s): -// cache_line_sdata[22] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~116_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~116_combout & ((cache_line_sdata[22]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[22]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~116_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[22]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[22] .lut_mask = "050c"; -defparam \cache_line_sdata[22] .operation_mode = "normal"; -defparam \cache_line_sdata[22] .output_mode = "reg_only"; -defparam \cache_line_sdata[22] .register_cascade_mode = "off"; -defparam \cache_line_sdata[22] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[22] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N9 -maxii_lcell \cache2_line_sdata[22] ( -// Equation(s): -// cache2_line_sdata[22] = DFFEAS((cache_line_sdata[22] & (((!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[22]), - .datab(vcc), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[22]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[22] .lut_mask = "000a"; -defparam \cache2_line_sdata[22] .operation_mode = "normal"; -defparam \cache2_line_sdata[22] .output_mode = "reg_only"; -defparam \cache2_line_sdata[22] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[22] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[22] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N1 -maxii_lcell \signal_high_voltage[22]~reg0 ( -// Equation(s): -// \signal_high_voltage[22]~reg0_regout = DFFEAS((\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[22]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\is_high_voltage_time~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[22]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[22]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[22]~reg0 .lut_mask = "0200"; -defparam \signal_high_voltage[22]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[22]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[22]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[22]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[22]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N8 -maxii_lcell \Decoder0~85 ( -// Equation(s): -// \Decoder0~85_combout = (i[1] & (\Decoder0~73_combout & (!i[5] & \Decoder0~79_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(\Decoder0~73_combout ), - .datac(i[5]), - .datad(\Decoder0~79_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~85_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~85 .lut_mask = "0800"; -defparam \Decoder0~85 .operation_mode = "normal"; -defparam \Decoder0~85 .output_mode = "comb_only"; -defparam \Decoder0~85 .register_cascade_mode = "off"; -defparam \Decoder0~85 .sum_lutc_input = "datac"; -defparam \Decoder0~85 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N9 -maxii_lcell \cache_line_sdata[23] ( -// Equation(s): -// cache_line_sdata[23] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~85_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~85_combout & ((cache_line_sdata[23]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[23]), - .datad(\Decoder0~85_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[23]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[23] .lut_mask = "1130"; -defparam \cache_line_sdata[23] .operation_mode = "normal"; -defparam \cache_line_sdata[23] .output_mode = "reg_only"; -defparam \cache_line_sdata[23] .register_cascade_mode = "off"; -defparam \cache_line_sdata[23] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[23] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N3 -maxii_lcell \cache2_line_sdata[23] ( -// Equation(s): -// cache2_line_sdata[23] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache_line_sdata[23])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache_line_sdata[23]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[23]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[23] .lut_mask = "1100"; -defparam \cache2_line_sdata[23] .operation_mode = "normal"; -defparam \cache2_line_sdata[23] .output_mode = "reg_only"; -defparam \cache2_line_sdata[23] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[23] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[23] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y9_N9 -maxii_lcell \signal_high_voltage[23]~reg0 ( -// Equation(s): -// \signal_high_voltage[23]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[23] & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[23]), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[23]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[23]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[23]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[23]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[23]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[23]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[23]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y6_N3 -maxii_lcell \Decoder0~86 ( -// Equation(s): -// \Decoder0~86_combout = (\Decoder0~82_combout & (\always3~0_combout & (\Decoder0~74_combout & \recv_complete~9_combout ))) - - .clk(gnd), - .dataa(\Decoder0~82_combout ), - .datab(\always3~0_combout ), - .datac(\Decoder0~74_combout ), - .datad(\recv_complete~9_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~86_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~86 .lut_mask = "8000"; -defparam \Decoder0~86 .operation_mode = "normal"; -defparam \Decoder0~86 .output_mode = "comb_only"; -defparam \Decoder0~86 .register_cascade_mode = "off"; -defparam \Decoder0~86 .sum_lutc_input = "datac"; -defparam \Decoder0~86 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y6_N9 -maxii_lcell \cache_line_sdata[24] ( -// Equation(s): -// cache_line_sdata[24] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~86_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~86_combout & (cache_line_sdata[24])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[24]), - .datab(\fiter_line_sdata~regout ), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~86_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[24]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[24] .lut_mask = "030a"; -defparam \cache_line_sdata[24] .operation_mode = "normal"; -defparam \cache_line_sdata[24] .output_mode = "reg_only"; -defparam \cache_line_sdata[24] .register_cascade_mode = "off"; -defparam \cache_line_sdata[24] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[24] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N0 -maxii_lcell \cache2_line_sdata[24] ( -// Equation(s): -// cache2_line_sdata[24] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache_line_sdata[24])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache_line_sdata[24]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[24]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[24] .lut_mask = "1100"; -defparam \cache2_line_sdata[24] .operation_mode = "normal"; -defparam \cache2_line_sdata[24] .output_mode = "reg_only"; -defparam \cache2_line_sdata[24] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[24] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[24] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y9_N5 -maxii_lcell \signal_high_voltage[24]~reg0 ( -// Equation(s): -// \signal_high_voltage[24]~reg0_regout = DFFEAS((cache2_line_sdata[24] & (\is_high_voltage_time~regout & (!\fault_flag[1][0]~regout & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache2_line_sdata[24]), - .datab(\is_high_voltage_time~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[24]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[24]~reg0 .lut_mask = "0008"; -defparam \signal_high_voltage[24]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[24]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[24]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[24]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[24]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N7 -maxii_lcell \Decoder0~75 ( -// Equation(s): -// \Decoder0~75_combout = (((i[3] & !i[5]))) - - .clk(gnd), - .dataa(vcc), - .datab(vcc), - .datac(i[3]), - .datad(i[5]), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~75_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~75 .lut_mask = "00f0"; -defparam \Decoder0~75 .operation_mode = "normal"; -defparam \Decoder0~75 .output_mode = "comb_only"; -defparam \Decoder0~75 .register_cascade_mode = "off"; -defparam \Decoder0~75 .sum_lutc_input = "datac"; -defparam \Decoder0~75 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N8 -maxii_lcell \Decoder0~87 ( -// Equation(s): -// \Decoder0~87_combout = (!i[1] & (!i[2] & (\Decoder0~75_combout & \Decoder0~79_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[2]), - .datac(\Decoder0~75_combout ), - .datad(\Decoder0~79_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~87_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~87 .lut_mask = "1000"; -defparam \Decoder0~87 .operation_mode = "normal"; -defparam \Decoder0~87 .output_mode = "comb_only"; -defparam \Decoder0~87 .register_cascade_mode = "off"; -defparam \Decoder0~87 .sum_lutc_input = "datac"; -defparam \Decoder0~87 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N9 -maxii_lcell \cache_line_sdata[25] ( -// Equation(s): -// cache_line_sdata[25] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~87_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~87_combout & (cache_line_sdata[25])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[25]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~87_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[25]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[25] .lut_mask = "0544"; -defparam \cache_line_sdata[25] .operation_mode = "normal"; -defparam \cache_line_sdata[25] .output_mode = "reg_only"; -defparam \cache_line_sdata[25] .register_cascade_mode = "off"; -defparam \cache_line_sdata[25] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[25] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N5 -maxii_lcell \cache2_line_sdata[25] ( -// Equation(s): -// cache2_line_sdata[25] = DFFEAS(((!\fault_flag[0][0]~regout & (cache_line_sdata[25] & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(cache_line_sdata[25]), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[25]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[25] .lut_mask = "0030"; -defparam \cache2_line_sdata[25] .operation_mode = "normal"; -defparam \cache2_line_sdata[25] .output_mode = "reg_only"; -defparam \cache2_line_sdata[25] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[25] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[25] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N9 -maxii_lcell \signal_high_voltage[25]~reg0 ( -// Equation(s): -// \signal_high_voltage[25]~reg0_regout = DFFEAS((\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & (cache2_line_sdata[25] & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\is_high_voltage_time~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(cache2_line_sdata[25]), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[25]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[25]~reg0 .lut_mask = "0020"; -defparam \signal_high_voltage[25]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[25]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[25]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[25]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[25]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N3 -maxii_lcell \Decoder0~117 ( -// Equation(s): -// \Decoder0~117_combout = (i[3] & (!i[2] & (i[1] & \Decoder0~78_combout ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[2]), - .datac(i[1]), - .datad(\Decoder0~78_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~117_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~117 .lut_mask = "2000"; -defparam \Decoder0~117 .operation_mode = "normal"; -defparam \Decoder0~117 .output_mode = "comb_only"; -defparam \Decoder0~117 .register_cascade_mode = "off"; -defparam \Decoder0~117 .sum_lutc_input = "datac"; -defparam \Decoder0~117 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y7_N2 -maxii_lcell \cache_line_sdata[26] ( -// Equation(s): -// cache_line_sdata[26] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~117_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~117_combout & ((cache_line_sdata[26]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[26]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~117_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[26]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[26] .lut_mask = "050c"; -defparam \cache_line_sdata[26] .operation_mode = "normal"; -defparam \cache_line_sdata[26] .output_mode = "reg_only"; -defparam \cache_line_sdata[26] .register_cascade_mode = "off"; -defparam \cache_line_sdata[26] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[26] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N2 -maxii_lcell \cache2_line_sdata[26] ( -// Equation(s): -// cache2_line_sdata[26] = DFFEAS(((!\fault_flag[0][0]~regout & (cache_line_sdata[26] & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(cache_line_sdata[26]), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[26]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[26] .lut_mask = "0030"; -defparam \cache2_line_sdata[26] .operation_mode = "normal"; -defparam \cache2_line_sdata[26] .output_mode = "reg_only"; -defparam \cache2_line_sdata[26] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[26] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[26] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N8 -maxii_lcell \signal_high_voltage[26]~reg0 ( -// Equation(s): -// \signal_high_voltage[26]~reg0_regout = DFFEAS((\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[26]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\is_high_voltage_time~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[26]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[26]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[26]~reg0 .lut_mask = "0200"; -defparam \signal_high_voltage[26]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[26]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[26]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[26]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[26]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N4 -maxii_lcell \Decoder0~88 ( -// Equation(s): -// \Decoder0~88_combout = (i[1] & (!i[2] & (\Decoder0~75_combout & \Decoder0~79_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[2]), - .datac(\Decoder0~75_combout ), - .datad(\Decoder0~79_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~88_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~88 .lut_mask = "2000"; -defparam \Decoder0~88 .operation_mode = "normal"; -defparam \Decoder0~88 .output_mode = "comb_only"; -defparam \Decoder0~88 .register_cascade_mode = "off"; -defparam \Decoder0~88 .sum_lutc_input = "datac"; -defparam \Decoder0~88 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N5 -maxii_lcell \cache_line_sdata[27] ( -// Equation(s): -// cache_line_sdata[27] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~88_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~88_combout & ((cache_line_sdata[27]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[27]), - .datad(\Decoder0~88_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[27]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[27] .lut_mask = "1130"; -defparam \cache_line_sdata[27] .operation_mode = "normal"; -defparam \cache_line_sdata[27] .output_mode = "reg_only"; -defparam \cache_line_sdata[27] .register_cascade_mode = "off"; -defparam \cache_line_sdata[27] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[27] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N4 -maxii_lcell \cache2_line_sdata[27] ( -// Equation(s): -// cache2_line_sdata[27] = DFFEAS((cache_line_sdata[27] & (!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[27]), - .datab(\fault_flag[1][0]~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[27]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[27] .lut_mask = "0202"; -defparam \cache2_line_sdata[27] .operation_mode = "normal"; -defparam \cache2_line_sdata[27] .output_mode = "reg_only"; -defparam \cache2_line_sdata[27] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[27] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[27] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N4 -maxii_lcell \signal_high_voltage[27]~reg0 ( -// Equation(s): -// \signal_high_voltage[27]~reg0_regout = DFFEAS((cache2_line_sdata[27] & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache2_line_sdata[27]), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[27]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[27]~reg0 .lut_mask = "0200"; -defparam \signal_high_voltage[27]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[27]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[27]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[27]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[27]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y6_N8 -maxii_lcell \Decoder0~89 ( -// Equation(s): -// \Decoder0~89_combout = (i[4] & (i[3] & (\Decoder0~70_combout & \Decoder0~115_combout ))) - - .clk(gnd), - .dataa(i[4]), - .datab(i[3]), - .datac(\Decoder0~70_combout ), - .datad(\Decoder0~115_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~89_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~89 .lut_mask = "8000"; -defparam \Decoder0~89 .operation_mode = "normal"; -defparam \Decoder0~89 .output_mode = "comb_only"; -defparam \Decoder0~89 .register_cascade_mode = "off"; -defparam \Decoder0~89 .sum_lutc_input = "datac"; -defparam \Decoder0~89 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y6_N5 -maxii_lcell \cache_line_sdata[28] ( -// Equation(s): -// cache_line_sdata[28] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~89_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~89_combout & ((cache_line_sdata[28]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(\fiter_line_sdata~regout ), - .datac(cache_line_sdata[28]), - .datad(\Decoder0~89_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[28]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[28] .lut_mask = "1150"; -defparam \cache_line_sdata[28] .operation_mode = "normal"; -defparam \cache_line_sdata[28] .output_mode = "reg_only"; -defparam \cache_line_sdata[28] .register_cascade_mode = "off"; -defparam \cache_line_sdata[28] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[28] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y6_N0 -maxii_lcell \cache2_line_sdata[28] ( -// Equation(s): -// cache2_line_sdata[28] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache_line_sdata[28])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache_line_sdata[28]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[28]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[28] .lut_mask = "1100"; -defparam \cache2_line_sdata[28] .operation_mode = "normal"; -defparam \cache2_line_sdata[28] .output_mode = "reg_only"; -defparam \cache2_line_sdata[28] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[28] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[28] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y7_N5 -maxii_lcell \signal_high_voltage[28]~reg0 ( -// Equation(s): -// \signal_high_voltage[28]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[28] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[28]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[28]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[28]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[28]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[28]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[28]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[28]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[28]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N0 -maxii_lcell \Decoder0~90 ( -// Equation(s): -// \Decoder0~90_combout = (!i[1] & (i[2] & (\Decoder0~75_combout & \Decoder0~79_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[2]), - .datac(\Decoder0~75_combout ), - .datad(\Decoder0~79_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~90_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~90 .lut_mask = "4000"; -defparam \Decoder0~90 .operation_mode = "normal"; -defparam \Decoder0~90 .output_mode = "comb_only"; -defparam \Decoder0~90 .register_cascade_mode = "off"; -defparam \Decoder0~90 .sum_lutc_input = "datac"; -defparam \Decoder0~90 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N1 -maxii_lcell \cache_line_sdata[29] ( -// Equation(s): -// cache_line_sdata[29] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~90_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~90_combout & (cache_line_sdata[29])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[29]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~90_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[29]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[29] .lut_mask = "0544"; -defparam \cache_line_sdata[29] .operation_mode = "normal"; -defparam \cache_line_sdata[29] .output_mode = "reg_only"; -defparam \cache_line_sdata[29] .register_cascade_mode = "off"; -defparam \cache_line_sdata[29] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[29] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N9 -maxii_lcell \cache2_line_sdata[29] ( -// Equation(s): -// cache2_line_sdata[29] = DFFEAS((cache_line_sdata[29] & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[29]), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[29]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[29] .lut_mask = "0202"; -defparam \cache2_line_sdata[29] .operation_mode = "normal"; -defparam \cache2_line_sdata[29] .output_mode = "reg_only"; -defparam \cache2_line_sdata[29] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[29] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[29] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N1 -maxii_lcell \signal_high_voltage[29]~reg0 ( -// Equation(s): -// \signal_high_voltage[29]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[29] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[29]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[29]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[29]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[29]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[29]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[29]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[29]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[29]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N6 -maxii_lcell \Decoder0~91 ( -// Equation(s): -// \Decoder0~91_combout = (i[1] & (i[2] & (i[3] & \Decoder0~78_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[2]), - .datac(i[3]), - .datad(\Decoder0~78_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~91_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~91 .lut_mask = "8000"; -defparam \Decoder0~91 .operation_mode = "normal"; -defparam \Decoder0~91 .output_mode = "comb_only"; -defparam \Decoder0~91 .register_cascade_mode = "off"; -defparam \Decoder0~91 .sum_lutc_input = "datac"; -defparam \Decoder0~91 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y7_N7 -maxii_lcell \cache_line_sdata[30] ( -// Equation(s): -// cache_line_sdata[30] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~91_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~91_combout & ((cache_line_sdata[30]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[30]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~91_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[30]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[30] .lut_mask = "050c"; -defparam \cache_line_sdata[30] .operation_mode = "normal"; -defparam \cache_line_sdata[30] .output_mode = "reg_only"; -defparam \cache_line_sdata[30] .register_cascade_mode = "off"; -defparam \cache_line_sdata[30] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[30] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y8_N8 -maxii_lcell \cache2_line_sdata[30] ( -// Equation(s): -// cache2_line_sdata[30] = DFFEAS(((cache_line_sdata[30] & (!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache_line_sdata[30]), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[30]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[30] .lut_mask = "000c"; -defparam \cache2_line_sdata[30] .operation_mode = "normal"; -defparam \cache2_line_sdata[30] .output_mode = "reg_only"; -defparam \cache2_line_sdata[30] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[30] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[30] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y9_N4 -maxii_lcell \signal_high_voltage[30]~reg0 ( -// Equation(s): -// \signal_high_voltage[30]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (\is_high_voltage_time~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[30]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\is_high_voltage_time~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[30]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[30]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[30]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[30]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[30]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[30]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[30]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[30]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N2 -maxii_lcell \Decoder0~92 ( -// Equation(s): -// \Decoder0~92_combout = (i[1] & (i[2] & (\Decoder0~75_combout & \Decoder0~79_combout ))) - - .clk(gnd), - .dataa(i[1]), - .datab(i[2]), - .datac(\Decoder0~75_combout ), - .datad(\Decoder0~79_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~92_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~92 .lut_mask = "8000"; -defparam \Decoder0~92 .operation_mode = "normal"; -defparam \Decoder0~92 .output_mode = "comb_only"; -defparam \Decoder0~92 .register_cascade_mode = "off"; -defparam \Decoder0~92 .sum_lutc_input = "datac"; -defparam \Decoder0~92 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y9_N3 -maxii_lcell \cache_line_sdata[31] ( -// Equation(s): -// cache_line_sdata[31] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~92_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~92_combout & (cache_line_sdata[31])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[31]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~92_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[31]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[31] .lut_mask = "0544"; -defparam \cache_line_sdata[31] .operation_mode = "normal"; -defparam \cache_line_sdata[31] .output_mode = "reg_only"; -defparam \cache_line_sdata[31] .register_cascade_mode = "off"; -defparam \cache_line_sdata[31] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[31] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N0 -maxii_lcell \cache2_line_sdata[31] ( -// Equation(s): -// cache2_line_sdata[31] = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache_line_sdata[31]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[31]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[31]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[31] .lut_mask = "0300"; -defparam \cache2_line_sdata[31] .operation_mode = "normal"; -defparam \cache2_line_sdata[31] .output_mode = "reg_only"; -defparam \cache2_line_sdata[31] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[31] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[31] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y9_N5 -maxii_lcell \signal_high_voltage[31]~reg0 ( -// Equation(s): -// \signal_high_voltage[31]~reg0_regout = DFFEAS((cache2_line_sdata[31] & (\is_high_voltage_time~regout & (!\fault_flag[1][0]~regout & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache2_line_sdata[31]), - .datab(\is_high_voltage_time~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[31]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[31]~reg0 .lut_mask = "0008"; -defparam \signal_high_voltage[31]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[31]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[31]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[31]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[31]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y10_N2 -maxii_lcell \Decoder0~118 ( -// Equation(s): -// \Decoder0~118_combout = (!i[0] & (i[5] & (\recv_complete~0_combout & \Decoder0~65 ))) - - .clk(gnd), - .dataa(i[0]), - .datab(i[5]), - .datac(\recv_complete~0_combout ), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~118_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~118 .lut_mask = "4000"; -defparam \Decoder0~118 .operation_mode = "normal"; -defparam \Decoder0~118 .output_mode = "comb_only"; -defparam \Decoder0~118 .register_cascade_mode = "off"; -defparam \Decoder0~118 .sum_lutc_input = "datac"; -defparam \Decoder0~118 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y10_N3 -maxii_lcell \cache_line_sdata[32] ( -// Equation(s): -// cache_line_sdata[32] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~118_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~118_combout & (cache_line_sdata[32])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[32]), - .datab(\fiter_line_sdata~regout ), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~118_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[32]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[32] .lut_mask = "030a"; -defparam \cache_line_sdata[32] .operation_mode = "normal"; -defparam \cache_line_sdata[32] .output_mode = "reg_only"; -defparam \cache_line_sdata[32] .register_cascade_mode = "off"; -defparam \cache_line_sdata[32] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[32] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N7 -maxii_lcell \cache2_line_sdata[32] ( -// Equation(s): -// cache2_line_sdata[32] = DFFEAS((cache_line_sdata[32] & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[32]), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[32]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[32] .lut_mask = "0202"; -defparam \cache2_line_sdata[32] .operation_mode = "normal"; -defparam \cache2_line_sdata[32] .output_mode = "reg_only"; -defparam \cache2_line_sdata[32] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[32] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[32] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N1 -maxii_lcell \signal_high_voltage[32]~reg0 ( -// Equation(s): -// \signal_high_voltage[32]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & (\is_high_voltage_time~regout & cache2_line_sdata[32]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(\is_high_voltage_time~regout ), - .datad(cache2_line_sdata[32]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[32]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[32]~reg0 .lut_mask = "1000"; -defparam \signal_high_voltage[32]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[32]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[32]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[32]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[32]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y10_N8 -maxii_lcell \Decoder0~93 ( -// Equation(s): -// \Decoder0~93_combout = (i[0] & (i[5] & (\recv_complete~0_combout & \Decoder0~65 ))) - - .clk(gnd), - .dataa(i[0]), - .datab(i[5]), - .datac(\recv_complete~0_combout ), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~93_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~93 .lut_mask = "8000"; -defparam \Decoder0~93 .operation_mode = "normal"; -defparam \Decoder0~93 .output_mode = "comb_only"; -defparam \Decoder0~93 .register_cascade_mode = "off"; -defparam \Decoder0~93 .sum_lutc_input = "datac"; -defparam \Decoder0~93 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y10_N9 -maxii_lcell \cache_line_sdata[33] ( -// Equation(s): -// cache_line_sdata[33] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~93_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~93_combout & (cache_line_sdata[33])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[33]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~93_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[33]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[33] .lut_mask = "0544"; -defparam \cache_line_sdata[33] .operation_mode = "normal"; -defparam \cache_line_sdata[33] .output_mode = "reg_only"; -defparam \cache_line_sdata[33] .register_cascade_mode = "off"; -defparam \cache_line_sdata[33] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[33] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N2 -maxii_lcell \cache2_line_sdata[33] ( -// Equation(s): -// cache2_line_sdata[33] = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache_line_sdata[33])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[33]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[33]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[33] .lut_mask = "0500"; -defparam \cache2_line_sdata[33] .operation_mode = "normal"; -defparam \cache2_line_sdata[33] .output_mode = "reg_only"; -defparam \cache2_line_sdata[33] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[33] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[33] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N6 -maxii_lcell \signal_high_voltage[33]~reg0 ( -// Equation(s): -// \signal_high_voltage[33]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[33] & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[33]), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[33]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[33]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[33]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[33]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[33]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[33]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[33]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N6 -maxii_lcell \Decoder0~119 ( -// Equation(s): -// \Decoder0~119_combout = (!i[3] & (!i[2] & (\recv_complete~10_combout & \Decoder0~68_combout ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[2]), - .datac(\recv_complete~10_combout ), - .datad(\Decoder0~68_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~119_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~119 .lut_mask = "1000"; -defparam \Decoder0~119 .operation_mode = "normal"; -defparam \Decoder0~119 .output_mode = "comb_only"; -defparam \Decoder0~119 .register_cascade_mode = "off"; -defparam \Decoder0~119 .sum_lutc_input = "datac"; -defparam \Decoder0~119 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N7 -maxii_lcell \cache_line_sdata[34] ( -// Equation(s): -// cache_line_sdata[34] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~119_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~119_combout & (cache_line_sdata[34])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[34]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~119_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[34]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[34] .lut_mask = "0544"; -defparam \cache_line_sdata[34] .operation_mode = "normal"; -defparam \cache_line_sdata[34] .output_mode = "reg_only"; -defparam \cache_line_sdata[34] .register_cascade_mode = "off"; -defparam \cache_line_sdata[34] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[34] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y8_N5 -maxii_lcell \cache2_line_sdata[34] ( -// Equation(s): -// cache2_line_sdata[34] = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache_line_sdata[34]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[34]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[34]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[34] .lut_mask = "0300"; -defparam \cache2_line_sdata[34] .operation_mode = "normal"; -defparam \cache2_line_sdata[34] .output_mode = "reg_only"; -defparam \cache2_line_sdata[34] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[34] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[34] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y7_N3 -maxii_lcell \signal_high_voltage[34]~reg0 ( -// Equation(s): -// \signal_high_voltage[34]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (\is_high_voltage_time~regout & (!\fault_flag[0][0]~regout & cache2_line_sdata[34]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\is_high_voltage_time~regout ), - .datac(\fault_flag[0][0]~regout ), - .datad(cache2_line_sdata[34]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[34]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[34]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[34]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[34]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[34]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[34]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[34]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N1 -maxii_lcell \Decoder0~120 ( -// Equation(s): -// \Decoder0~120_combout = (i[5] & (!i[3] & (!i[2] & \Decoder0~69_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[3]), - .datac(i[2]), - .datad(\Decoder0~69_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~120_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~120 .lut_mask = "0200"; -defparam \Decoder0~120 .operation_mode = "normal"; -defparam \Decoder0~120 .output_mode = "comb_only"; -defparam \Decoder0~120 .register_cascade_mode = "off"; -defparam \Decoder0~120 .sum_lutc_input = "datac"; -defparam \Decoder0~120 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N0 -maxii_lcell \cache_line_sdata[35] ( -// Equation(s): -// cache_line_sdata[35] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~120_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~120_combout & ((cache_line_sdata[35]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[35]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~120_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[35]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[35] .lut_mask = "050c"; -defparam \cache_line_sdata[35] .operation_mode = "normal"; -defparam \cache_line_sdata[35] .output_mode = "reg_only"; -defparam \cache_line_sdata[35] .register_cascade_mode = "off"; -defparam \cache_line_sdata[35] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[35] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N2 -maxii_lcell \cache2_line_sdata[35] ( -// Equation(s): -// cache2_line_sdata[35] = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache_line_sdata[35]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[35]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[35]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[35] .lut_mask = "0300"; -defparam \cache2_line_sdata[35] .operation_mode = "normal"; -defparam \cache2_line_sdata[35] .output_mode = "reg_only"; -defparam \cache2_line_sdata[35] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[35] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[35] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N3 -maxii_lcell \signal_high_voltage[35]~reg0 ( -// Equation(s): -// \signal_high_voltage[35]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[35] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[35]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[35]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[35]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[35]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[35]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[35]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[35]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[35]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N3 -maxii_lcell \Decoder0~94 ( -// Equation(s): -// \Decoder0~94_combout = (i[5] & (!i[0] & (!i[1]))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[0]), - .datac(i[1]), - .datad(vcc), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~94_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~94 .lut_mask = "0202"; -defparam \Decoder0~94 .operation_mode = "normal"; -defparam \Decoder0~94 .output_mode = "comb_only"; -defparam \Decoder0~94 .register_cascade_mode = "off"; -defparam \Decoder0~94 .sum_lutc_input = "datac"; -defparam \Decoder0~94 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N8 -maxii_lcell \Decoder0~95 ( -// Equation(s): -// \Decoder0~95_combout = (!i[3] & (i[2] & (\Decoder0~94_combout & \Decoder0~65 ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[2]), - .datac(\Decoder0~94_combout ), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~95_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~95 .lut_mask = "4000"; -defparam \Decoder0~95 .operation_mode = "normal"; -defparam \Decoder0~95 .output_mode = "comb_only"; -defparam \Decoder0~95 .register_cascade_mode = "off"; -defparam \Decoder0~95 .sum_lutc_input = "datac"; -defparam \Decoder0~95 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N9 -maxii_lcell \cache_line_sdata[36] ( -// Equation(s): -// cache_line_sdata[36] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~95_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~95_combout & ((cache_line_sdata[36]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[36]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~95_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[36]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[36] .lut_mask = "050c"; -defparam \cache_line_sdata[36] .operation_mode = "normal"; -defparam \cache_line_sdata[36] .output_mode = "reg_only"; -defparam \cache_line_sdata[36] .register_cascade_mode = "off"; -defparam \cache_line_sdata[36] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[36] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N6 -maxii_lcell \cache2_line_sdata[36] ( -// Equation(s): -// cache2_line_sdata[36] = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache_line_sdata[36]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[36]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[36]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[36] .lut_mask = "0300"; -defparam \cache2_line_sdata[36] .operation_mode = "normal"; -defparam \cache2_line_sdata[36] .output_mode = "reg_only"; -defparam \cache2_line_sdata[36] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[36] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[36] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y5_N0 -maxii_lcell \signal_high_voltage[36]~reg0 ( -// Equation(s): -// \signal_high_voltage[36]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[36] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[36]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[36]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[36]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[36]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[36]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[36]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[36]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[36]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N2 -maxii_lcell \Decoder0~121 ( -// Equation(s): -// \Decoder0~121_combout = (!i[3] & (i[2] & (i[5] & \Decoder0~72_combout ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[2]), - .datac(i[5]), - .datad(\Decoder0~72_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~121_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~121 .lut_mask = "4000"; -defparam \Decoder0~121 .operation_mode = "normal"; -defparam \Decoder0~121 .output_mode = "comb_only"; -defparam \Decoder0~121 .register_cascade_mode = "off"; -defparam \Decoder0~121 .sum_lutc_input = "datac"; -defparam \Decoder0~121 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N3 -maxii_lcell \cache_line_sdata[37] ( -// Equation(s): -// cache_line_sdata[37] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~121_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~121_combout & (cache_line_sdata[37])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[37]), - .datab(\fiter_line_sdata~regout ), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~121_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[37]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[37] .lut_mask = "030a"; -defparam \cache_line_sdata[37] .operation_mode = "normal"; -defparam \cache_line_sdata[37] .output_mode = "reg_only"; -defparam \cache_line_sdata[37] .register_cascade_mode = "off"; -defparam \cache_line_sdata[37] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[37] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N4 -maxii_lcell \cache2_line_sdata[37] ( -// Equation(s): -// cache2_line_sdata[37] = DFFEAS((cache_line_sdata[37] & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[37]), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[37]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[37] .lut_mask = "0202"; -defparam \cache2_line_sdata[37] .operation_mode = "normal"; -defparam \cache2_line_sdata[37] .output_mode = "reg_only"; -defparam \cache2_line_sdata[37] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[37] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[37] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N5 -maxii_lcell \signal_high_voltage[37]~reg0 ( -// Equation(s): -// \signal_high_voltage[37]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (\is_high_voltage_time~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[37]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\is_high_voltage_time~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[37]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[37]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[37]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[37]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[37]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[37]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[37]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[37]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N5 -maxii_lcell \Decoder0~122 ( -// Equation(s): -// \Decoder0~122_combout = (!i[0] & (\Decoder0~73_combout & (i[5] & \Decoder0~68_combout ))) - - .clk(gnd), - .dataa(i[0]), - .datab(\Decoder0~73_combout ), - .datac(i[5]), - .datad(\Decoder0~68_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~122_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~122 .lut_mask = "4000"; -defparam \Decoder0~122 .operation_mode = "normal"; -defparam \Decoder0~122 .output_mode = "comb_only"; -defparam \Decoder0~122 .register_cascade_mode = "off"; -defparam \Decoder0~122 .sum_lutc_input = "datac"; -defparam \Decoder0~122 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y9_N6 -maxii_lcell \cache_line_sdata[38] ( -// Equation(s): -// cache_line_sdata[38] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~122_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~122_combout & (cache_line_sdata[38])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[38]), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~122_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[38]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[38] .lut_mask = "0322"; -defparam \cache_line_sdata[38] .operation_mode = "normal"; -defparam \cache_line_sdata[38] .output_mode = "reg_only"; -defparam \cache_line_sdata[38] .register_cascade_mode = "off"; -defparam \cache_line_sdata[38] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[38] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N8 -maxii_lcell \cache2_line_sdata[38] ( -// Equation(s): -// cache2_line_sdata[38] = DFFEAS(((cache_line_sdata[38] & (!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache_line_sdata[38]), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[38]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[38] .lut_mask = "000c"; -defparam \cache2_line_sdata[38] .operation_mode = "normal"; -defparam \cache2_line_sdata[38] .output_mode = "reg_only"; -defparam \cache2_line_sdata[38] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[38] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[38] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y9_N4 -maxii_lcell \signal_high_voltage[38]~reg0 ( -// Equation(s): -// \signal_high_voltage[38]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & (cache2_line_sdata[38] & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(cache2_line_sdata[38]), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[38]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[38]~reg0 .lut_mask = "1000"; -defparam \signal_high_voltage[38]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[38]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[38]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[38]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[38]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y10_N6 -maxii_lcell \Decoder0~123 ( -// Equation(s): -// \Decoder0~123_combout = (!i[3] & (i[5] & (i[2] & \Decoder0~69_combout ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[5]), - .datac(i[2]), - .datad(\Decoder0~69_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~123_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~123 .lut_mask = "4000"; -defparam \Decoder0~123 .operation_mode = "normal"; -defparam \Decoder0~123 .output_mode = "comb_only"; -defparam \Decoder0~123 .register_cascade_mode = "off"; -defparam \Decoder0~123 .sum_lutc_input = "datac"; -defparam \Decoder0~123 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y10_N7 -maxii_lcell \cache_line_sdata[39] ( -// Equation(s): -// cache_line_sdata[39] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~123_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~123_combout & ((cache_line_sdata[39]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(\fiter_line_sdata~regout ), - .datac(cache_line_sdata[39]), - .datad(\Decoder0~123_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[39]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[39] .lut_mask = "1150"; -defparam \cache_line_sdata[39] .operation_mode = "normal"; -defparam \cache_line_sdata[39] .output_mode = "reg_only"; -defparam \cache_line_sdata[39] .register_cascade_mode = "off"; -defparam \cache_line_sdata[39] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[39] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N2 -maxii_lcell \cache2_line_sdata[39] ( -// Equation(s): -// cache2_line_sdata[39] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache_line_sdata[39])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache_line_sdata[39]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[39]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[39] .lut_mask = "1100"; -defparam \cache2_line_sdata[39] .operation_mode = "normal"; -defparam \cache2_line_sdata[39] .output_mode = "reg_only"; -defparam \cache2_line_sdata[39] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[39] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[39] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N9 -maxii_lcell \signal_high_voltage[39]~reg0 ( -// Equation(s): -// \signal_high_voltage[39]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & (\is_high_voltage_time~regout & cache2_line_sdata[39]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(\is_high_voltage_time~regout ), - .datad(cache2_line_sdata[39]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[39]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[39]~reg0 .lut_mask = "1000"; -defparam \signal_high_voltage[39]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[39]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[39]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[39]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[39]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N1 -maxii_lcell \Decoder0~96 ( -// Equation(s): -// \Decoder0~96_combout = (i[3] & (!i[2] & (\Decoder0~94_combout & \Decoder0~65 ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[2]), - .datac(\Decoder0~94_combout ), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~96_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~96 .lut_mask = "2000"; -defparam \Decoder0~96 .operation_mode = "normal"; -defparam \Decoder0~96 .output_mode = "comb_only"; -defparam \Decoder0~96 .register_cascade_mode = "off"; -defparam \Decoder0~96 .sum_lutc_input = "datac"; -defparam \Decoder0~96 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N2 -maxii_lcell \cache_line_sdata[40] ( -// Equation(s): -// cache_line_sdata[40] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~96_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~96_combout & ((cache_line_sdata[40]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(cache_line_sdata[40]), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~96_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[40]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[40] .lut_mask = "050c"; -defparam \cache_line_sdata[40] .operation_mode = "normal"; -defparam \cache_line_sdata[40] .output_mode = "reg_only"; -defparam \cache_line_sdata[40] .register_cascade_mode = "off"; -defparam \cache_line_sdata[40] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[40] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N7 -maxii_lcell \cache2_line_sdata[40] ( -// Equation(s): -// cache2_line_sdata[40] = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache_line_sdata[40]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[40]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[40]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[40] .lut_mask = "0300"; -defparam \cache2_line_sdata[40] .operation_mode = "normal"; -defparam \cache2_line_sdata[40] .output_mode = "reg_only"; -defparam \cache2_line_sdata[40] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[40] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[40] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y6_N6 -maxii_lcell \signal_high_voltage[40]~reg0 ( -// Equation(s): -// \signal_high_voltage[40]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[40] & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[40]), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[40]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[40]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[40]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[40]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[40]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[40]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[40]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N5 -maxii_lcell \Decoder0~124 ( -// Equation(s): -// \Decoder0~124_combout = (i[3] & (!i[2] & (i[5] & \Decoder0~72_combout ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[2]), - .datac(i[5]), - .datad(\Decoder0~72_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~124_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~124 .lut_mask = "2000"; -defparam \Decoder0~124 .operation_mode = "normal"; -defparam \Decoder0~124 .output_mode = "comb_only"; -defparam \Decoder0~124 .register_cascade_mode = "off"; -defparam \Decoder0~124 .sum_lutc_input = "datac"; -defparam \Decoder0~124 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N6 -maxii_lcell \cache_line_sdata[41] ( -// Equation(s): -// cache_line_sdata[41] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~124_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~124_combout & (cache_line_sdata[41])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache_line_sdata[41]), - .datab(\fiter_line_sdata~regout ), - .datac(\cnt_for_high_voltage_time~128_combout ), - .datad(\Decoder0~124_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[41]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[41] .lut_mask = "030a"; -defparam \cache_line_sdata[41] .operation_mode = "normal"; -defparam \cache_line_sdata[41] .output_mode = "reg_only"; -defparam \cache_line_sdata[41] .register_cascade_mode = "off"; -defparam \cache_line_sdata[41] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[41] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y8_N8 -maxii_lcell \cache2_line_sdata[41] ( -// Equation(s): -// cache2_line_sdata[41] = DFFEAS((!\fault_flag[1][0]~regout & (((cache_line_sdata[41] & !\fault_flag[0][0]~regout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(vcc), - .datac(cache_line_sdata[41]), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[41]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[41] .lut_mask = "0050"; -defparam \cache2_line_sdata[41] .operation_mode = "normal"; -defparam \cache2_line_sdata[41] .output_mode = "reg_only"; -defparam \cache2_line_sdata[41] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[41] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[41] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N1 -maxii_lcell \signal_high_voltage[41]~reg0 ( -// Equation(s): -// \signal_high_voltage[41]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[41] & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[41]), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[41]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[41]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[41]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[41]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[41]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[41]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[41]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y7_N5 -maxii_lcell \Decoder0~125 ( -// Equation(s): -// \Decoder0~125_combout = (i[5] & (!i[0] & (\Decoder0~74_combout & \Decoder0~68_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[0]), - .datac(\Decoder0~74_combout ), - .datad(\Decoder0~68_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~125_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~125 .lut_mask = "2000"; -defparam \Decoder0~125 .operation_mode = "normal"; -defparam \Decoder0~125 .output_mode = "comb_only"; -defparam \Decoder0~125 .register_cascade_mode = "off"; -defparam \Decoder0~125 .sum_lutc_input = "datac"; -defparam \Decoder0~125 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y7_N6 -maxii_lcell \cache_line_sdata[42] ( -// Equation(s): -// cache_line_sdata[42] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~125_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~125_combout & ((cache_line_sdata[42]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[42]), - .datad(\Decoder0~125_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[42]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[42] .lut_mask = "1130"; -defparam \cache_line_sdata[42] .operation_mode = "normal"; -defparam \cache_line_sdata[42] .output_mode = "reg_only"; -defparam \cache_line_sdata[42] .register_cascade_mode = "off"; -defparam \cache_line_sdata[42] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[42] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y6_N9 -maxii_lcell \cache2_line_sdata[42] ( -// Equation(s): -// cache2_line_sdata[42] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache_line_sdata[42])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache_line_sdata[42]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[42]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[42] .lut_mask = "1100"; -defparam \cache2_line_sdata[42] .operation_mode = "normal"; -defparam \cache2_line_sdata[42] .output_mode = "reg_only"; -defparam \cache2_line_sdata[42] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[42] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[42] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y6_N4 -maxii_lcell \signal_high_voltage[42]~reg0 ( -// Equation(s): -// \signal_high_voltage[42]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[42] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[42]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[42]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[42]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[42]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[42]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[42]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[42]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[42]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N6 -maxii_lcell \Decoder0~126 ( -// Equation(s): -// \Decoder0~126_combout = (i[5] & (!i[2] & (i[3] & \Decoder0~69_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[2]), - .datac(i[3]), - .datad(\Decoder0~69_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~126_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~126 .lut_mask = "2000"; -defparam \Decoder0~126 .operation_mode = "normal"; -defparam \Decoder0~126 .output_mode = "comb_only"; -defparam \Decoder0~126 .register_cascade_mode = "off"; -defparam \Decoder0~126 .sum_lutc_input = "datac"; -defparam \Decoder0~126 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N7 -maxii_lcell \cache_line_sdata[43] ( -// Equation(s): -// cache_line_sdata[43] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~126_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~126_combout & ((cache_line_sdata[43]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[43]), - .datad(\Decoder0~126_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[43]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[43] .lut_mask = "1130"; -defparam \cache_line_sdata[43] .operation_mode = "normal"; -defparam \cache_line_sdata[43] .output_mode = "reg_only"; -defparam \cache_line_sdata[43] .register_cascade_mode = "off"; -defparam \cache_line_sdata[43] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[43] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N4 -maxii_lcell \cache2_line_sdata[43] ( -// Equation(s): -// cache2_line_sdata[43] = DFFEAS(((!\fault_flag[1][0]~regout & (cache_line_sdata[43] & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[1][0]~regout ), - .datac(cache_line_sdata[43]), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[43]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[43] .lut_mask = "0030"; -defparam \cache2_line_sdata[43] .operation_mode = "normal"; -defparam \cache2_line_sdata[43] .output_mode = "reg_only"; -defparam \cache2_line_sdata[43] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[43] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[43] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N6 -maxii_lcell \signal_high_voltage[43]~reg0 ( -// Equation(s): -// \signal_high_voltage[43]~reg0_regout = DFFEAS((cache2_line_sdata[43] & (!\fault_flag[1][0]~regout & (\is_high_voltage_time~regout & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache2_line_sdata[43]), - .datab(\fault_flag[1][0]~regout ), - .datac(\is_high_voltage_time~regout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[43]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[43]~reg0 .lut_mask = "0020"; -defparam \signal_high_voltage[43]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[43]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[43]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[43]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[43]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N4 -maxii_lcell \Decoder0~97 ( -// Equation(s): -// \Decoder0~97_combout = (i[3] & (i[2] & (\Decoder0~94_combout & \Decoder0~65 ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[2]), - .datac(\Decoder0~94_combout ), - .datad(\Decoder0~65 ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~97_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~97 .lut_mask = "8000"; -defparam \Decoder0~97 .operation_mode = "normal"; -defparam \Decoder0~97 .output_mode = "comb_only"; -defparam \Decoder0~97 .register_cascade_mode = "off"; -defparam \Decoder0~97 .sum_lutc_input = "datac"; -defparam \Decoder0~97 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y6_N5 -maxii_lcell \cache_line_sdata[44] ( -// Equation(s): -// cache_line_sdata[44] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~97_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~97_combout & ((cache_line_sdata[44]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[44]), - .datad(\Decoder0~97_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[44]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[44] .lut_mask = "1130"; -defparam \cache_line_sdata[44] .operation_mode = "normal"; -defparam \cache_line_sdata[44] .output_mode = "reg_only"; -defparam \cache_line_sdata[44] .register_cascade_mode = "off"; -defparam \cache_line_sdata[44] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[44] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y6_N4 -maxii_lcell \cache2_line_sdata[44] ( -// Equation(s): -// cache2_line_sdata[44] = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache_line_sdata[44])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache_line_sdata[44]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[44]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[44] .lut_mask = "1100"; -defparam \cache2_line_sdata[44] .operation_mode = "normal"; -defparam \cache2_line_sdata[44] .output_mode = "reg_only"; -defparam \cache2_line_sdata[44] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[44] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[44] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y6_N3 -maxii_lcell \signal_high_voltage[44]~reg0 ( -// Equation(s): -// \signal_high_voltage[44]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[44] & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[44]), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[44]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[44]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[44]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[44]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[44]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[44]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[44]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N3 -maxii_lcell \Decoder0~98 ( -// Equation(s): -// \Decoder0~98_combout = (i[5] & (i[2] & (i[3] & \Decoder0~72_combout ))) - - .clk(gnd), - .dataa(i[5]), - .datab(i[2]), - .datac(i[3]), - .datad(\Decoder0~72_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~98_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~98 .lut_mask = "8000"; -defparam \Decoder0~98 .operation_mode = "normal"; -defparam \Decoder0~98 .output_mode = "comb_only"; -defparam \Decoder0~98 .register_cascade_mode = "off"; -defparam \Decoder0~98 .sum_lutc_input = "datac"; -defparam \Decoder0~98 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y10_N4 -maxii_lcell \cache_line_sdata[45] ( -// Equation(s): -// cache_line_sdata[45] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~98_combout & (!\fiter_line_sdata~regout )) # (!\Decoder0~98_combout & ((cache_line_sdata[45]))))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fiter_line_sdata~regout ), - .datab(\cnt_for_high_voltage_time~128_combout ), - .datac(cache_line_sdata[45]), - .datad(\Decoder0~98_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[45]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[45] .lut_mask = "1130"; -defparam \cache_line_sdata[45] .operation_mode = "normal"; -defparam \cache_line_sdata[45] .output_mode = "reg_only"; -defparam \cache_line_sdata[45] .register_cascade_mode = "off"; -defparam \cache_line_sdata[45] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[45] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N7 -maxii_lcell \cache2_line_sdata[45] ( -// Equation(s): -// cache2_line_sdata[45] = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache_line_sdata[45])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[45]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[45]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[45] .lut_mask = "0500"; -defparam \cache2_line_sdata[45] .operation_mode = "normal"; -defparam \cache2_line_sdata[45] .output_mode = "reg_only"; -defparam \cache2_line_sdata[45] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[45] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[45] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N9 -maxii_lcell \signal_high_voltage[45]~reg0 ( -// Equation(s): -// \signal_high_voltage[45]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[45] & (!\fault_flag[0][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[45]), - .datac(\fault_flag[0][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[45]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[45]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[45]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[45]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[45]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[45]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[45]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N3 -maxii_lcell \Decoder0~99 ( -// Equation(s): -// \Decoder0~99_combout = (i[3] & (i[2] & (\Decoder0~68_combout & \recv_complete~10_combout ))) - - .clk(gnd), - .dataa(i[3]), - .datab(i[2]), - .datac(\Decoder0~68_combout ), - .datad(\recv_complete~10_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~99_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~99 .lut_mask = "8000"; -defparam \Decoder0~99 .operation_mode = "normal"; -defparam \Decoder0~99 .output_mode = "comb_only"; -defparam \Decoder0~99 .register_cascade_mode = "off"; -defparam \Decoder0~99 .sum_lutc_input = "datac"; -defparam \Decoder0~99 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N2 -maxii_lcell \cache_line_sdata[46] ( -// Equation(s): -// cache_line_sdata[46] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~99_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~99_combout & (cache_line_sdata[46])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[46]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~99_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[46]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[46] .lut_mask = "0544"; -defparam \cache_line_sdata[46] .operation_mode = "normal"; -defparam \cache_line_sdata[46] .output_mode = "reg_only"; -defparam \cache_line_sdata[46] .register_cascade_mode = "off"; -defparam \cache_line_sdata[46] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[46] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y8_N0 -maxii_lcell \cache2_line_sdata[46] ( -// Equation(s): -// cache2_line_sdata[46] = DFFEAS(((cache_line_sdata[46] & (!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache_line_sdata[46]), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[46]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[46] .lut_mask = "000c"; -defparam \cache2_line_sdata[46] .operation_mode = "normal"; -defparam \cache2_line_sdata[46] .output_mode = "reg_only"; -defparam \cache2_line_sdata[46] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[46] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[46] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y6_N7 -maxii_lcell \signal_high_voltage[46]~reg0 ( -// Equation(s): -// \signal_high_voltage[46]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (\is_high_voltage_time~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[46]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\is_high_voltage_time~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[46]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[46]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[46]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[46]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[46]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[46]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[46]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[46]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y10_N1 -maxii_lcell \Decoder0~100 ( -// Equation(s): -// \Decoder0~100_combout = (i[2] & (i[5] & (i[3] & \Decoder0~69_combout ))) - - .clk(gnd), - .dataa(i[2]), - .datab(i[5]), - .datac(i[3]), - .datad(\Decoder0~69_combout ), - .aclr(gnd), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(\Decoder0~100_combout ), - .regout(), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \Decoder0~100 .lut_mask = "8000"; -defparam \Decoder0~100 .operation_mode = "normal"; -defparam \Decoder0~100 .output_mode = "comb_only"; -defparam \Decoder0~100 .register_cascade_mode = "off"; -defparam \Decoder0~100 .sum_lutc_input = "datac"; -defparam \Decoder0~100 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y10_N9 -maxii_lcell \cache_line_sdata[47] ( -// Equation(s): -// cache_line_sdata[47] = DFFEAS((!\cnt_for_high_voltage_time~128_combout & ((\Decoder0~100_combout & ((!\fiter_line_sdata~regout ))) # (!\Decoder0~100_combout & (cache_line_sdata[47])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\cnt_for_high_voltage_time~128_combout ), - .datab(cache_line_sdata[47]), - .datac(\fiter_line_sdata~regout ), - .datad(\Decoder0~100_combout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache_line_sdata[47]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache_line_sdata[47] .lut_mask = "0544"; -defparam \cache_line_sdata[47] .operation_mode = "normal"; -defparam \cache_line_sdata[47] .output_mode = "reg_only"; -defparam \cache_line_sdata[47] .register_cascade_mode = "off"; -defparam \cache_line_sdata[47] .sum_lutc_input = "datac"; -defparam \cache_line_sdata[47] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y7_N7 -maxii_lcell \cache2_line_sdata[47] ( -// Equation(s): -// cache2_line_sdata[47] = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache_line_sdata[47])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , \cache2_line_sdata[45]~50_combout , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache_line_sdata[47]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\cache2_line_sdata[45]~50_combout ), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(cache2_line_sdata[47]), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \cache2_line_sdata[47] .lut_mask = "0500"; -defparam \cache2_line_sdata[47] .operation_mode = "normal"; -defparam \cache2_line_sdata[47] .output_mode = "reg_only"; -defparam \cache2_line_sdata[47] .register_cascade_mode = "off"; -defparam \cache2_line_sdata[47] .sum_lutc_input = "datac"; -defparam \cache2_line_sdata[47] .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y6_N9 -maxii_lcell \signal_high_voltage[47]~reg0 ( -// Equation(s): -// \signal_high_voltage[47]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[47] & (!\fault_flag[1][0]~regout & \is_high_voltage_time~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[47]), - .datac(\fault_flag[1][0]~regout ), - .datad(\is_high_voltage_time~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_high_voltage[47]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_high_voltage[47]~reg0 .lut_mask = "0400"; -defparam \signal_high_voltage[47]~reg0 .operation_mode = "normal"; -defparam \signal_high_voltage[47]~reg0 .output_mode = "reg_only"; -defparam \signal_high_voltage[47]~reg0 .register_cascade_mode = "off"; -defparam \signal_high_voltage[47]~reg0 .sum_lutc_input = "datac"; -defparam \signal_high_voltage[47]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y5_N6 -maxii_lcell \signal_low_voltage[0]~reg0 ( -// Equation(s): -// \signal_low_voltage[0]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (((!\fault_flag[0][0]~regout & cache2_line_sdata[0])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(vcc), - .datac(\fault_flag[0][0]~regout ), - .datad(cache2_line_sdata[0]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[0]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[0]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[0]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[0]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[0]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[0]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[0]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y6_N6 -maxii_lcell \signal_low_voltage[1]~reg0 ( -// Equation(s): -// \signal_low_voltage[1]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[1]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[1]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[1]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[1]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[1]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[1]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[1]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[1]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[1]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y6_N5 -maxii_lcell \signal_low_voltage[2]~reg0 ( -// Equation(s): -// \signal_low_voltage[2]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[2] & (!\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[2]), - .datac(\fault_flag[0][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[2]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[2]~reg0 .lut_mask = "0404"; -defparam \signal_low_voltage[2]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[2]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[2]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[2]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[2]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y5_N6 -maxii_lcell \signal_low_voltage[3]~reg0 ( -// Equation(s): -// \signal_low_voltage[3]~reg0_regout = DFFEAS(((cache2_line_sdata[3] & (!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache2_line_sdata[3]), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[3]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[3]~reg0 .lut_mask = "000c"; -defparam \signal_low_voltage[3]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[3]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[3]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[3]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[3]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y5_N9 -maxii_lcell \signal_low_voltage[4]~reg0 ( -// Equation(s): -// \signal_low_voltage[4]~reg0_regout = DFFEAS((cache2_line_sdata[4] & (((!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout )))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache2_line_sdata[4]), - .datab(vcc), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[4]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[4]~reg0 .lut_mask = "000a"; -defparam \signal_low_voltage[4]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[4]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[4]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[4]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[4]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N6 -maxii_lcell \signal_low_voltage[5]~reg0 ( -// Equation(s): -// \signal_low_voltage[5]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[5] & (!\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[5]), - .datac(\fault_flag[0][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[5]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[5]~reg0 .lut_mask = "0404"; -defparam \signal_low_voltage[5]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[5]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[5]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[5]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[5]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N1 -maxii_lcell \signal_low_voltage[6]~reg0 ( -// Equation(s): -// \signal_low_voltage[6]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (cache2_line_sdata[6] & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(cache2_line_sdata[6]), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[6]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[6]~reg0 .lut_mask = "0030"; -defparam \signal_low_voltage[6]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[6]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[6]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[6]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[6]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y4_N9 -maxii_lcell \signal_low_voltage[7]~reg0 ( -// Equation(s): -// \signal_low_voltage[7]~reg0_regout = DFFEAS(((cache2_line_sdata[7] & (!\fault_flag[1][0]~regout & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache2_line_sdata[7]), - .datac(\fault_flag[1][0]~regout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[7]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[7]~reg0 .lut_mask = "000c"; -defparam \signal_low_voltage[7]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[7]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[7]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[7]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[7]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y5_N5 -maxii_lcell \signal_low_voltage[8]~reg0 ( -// Equation(s): -// \signal_low_voltage[8]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (((!\fault_flag[0][0]~regout & cache2_line_sdata[8])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(vcc), - .datac(\fault_flag[0][0]~regout ), - .datad(cache2_line_sdata[8]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[8]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[8]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[8]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[8]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[8]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[8]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[8]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y4_N5 -maxii_lcell \signal_low_voltage[9]~reg0 ( -// Equation(s): -// \signal_low_voltage[9]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[9]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[9]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[9]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[9]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[9]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[9]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[9]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[9]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[9]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y7_N7 -maxii_lcell \signal_low_voltage[10]~reg0 ( -// Equation(s): -// \signal_low_voltage[10]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[10]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[10]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[10]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[10]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[10]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[10]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[10]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[10]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[10]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y4_N8 -maxii_lcell \signal_low_voltage[11]~reg0 ( -// Equation(s): -// \signal_low_voltage[11]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[11]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[11]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[11]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[11]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[11]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[11]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[11]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[11]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[11]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y5_N9 -maxii_lcell \signal_low_voltage[12]~reg0 ( -// Equation(s): -// \signal_low_voltage[12]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (((!\fault_flag[0][0]~regout & cache2_line_sdata[12])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(vcc), - .datac(\fault_flag[0][0]~regout ), - .datad(cache2_line_sdata[12]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[12]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[12]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[12]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[12]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[12]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[12]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[12]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y4_N4 -maxii_lcell \signal_low_voltage[13]~reg0 ( -// Equation(s): -// \signal_low_voltage[13]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[13]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[13]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[13]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[13]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[13]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[13]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[13]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[13]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[13]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y4_N8 -maxii_lcell \signal_low_voltage[14]~reg0 ( -// Equation(s): -// \signal_low_voltage[14]~reg0_regout = DFFEAS(((cache2_line_sdata[14] & (!\fault_flag[1][0]~regout & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache2_line_sdata[14]), - .datac(\fault_flag[1][0]~regout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[14]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[14]~reg0 .lut_mask = "000c"; -defparam \signal_low_voltage[14]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[14]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[14]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[14]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[14]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N5 -maxii_lcell \signal_low_voltage[15]~reg0 ( -// Equation(s): -// \signal_low_voltage[15]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[15]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[15]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[15]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[15]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[15]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[15]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[15]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[15]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[15]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y7_N8 -maxii_lcell \signal_low_voltage[16]~reg0 ( -// Equation(s): -// \signal_low_voltage[16]~reg0_regout = DFFEAS((cache2_line_sdata[16] & (!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(cache2_line_sdata[16]), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[16]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[16]~reg0 .lut_mask = "0202"; -defparam \signal_low_voltage[16]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[16]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[16]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[16]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[16]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N8 -maxii_lcell \signal_low_voltage[17]~reg0 ( -// Equation(s): -// \signal_low_voltage[17]~reg0_regout = DFFEAS(((cache2_line_sdata[17] & (!\fault_flag[1][0]~regout & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache2_line_sdata[17]), - .datac(\fault_flag[1][0]~regout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[17]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[17]~reg0 .lut_mask = "000c"; -defparam \signal_low_voltage[17]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[17]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[17]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[17]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[17]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N9 -maxii_lcell \signal_low_voltage[18]~reg0 ( -// Equation(s): -// \signal_low_voltage[18]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[18]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[18]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[18]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[18]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[18]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[18]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[18]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[18]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[18]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X9_Y5_N0 -maxii_lcell \signal_low_voltage[19]~reg0 ( -// Equation(s): -// \signal_low_voltage[19]~reg0_regout = DFFEAS(((cache2_line_sdata[19] & (!\fault_flag[0][0]~regout & !\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache2_line_sdata[19]), - .datac(\fault_flag[0][0]~regout ), - .datad(\fault_flag[1][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[19]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[19]~reg0 .lut_mask = "000c"; -defparam \signal_low_voltage[19]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[19]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[19]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[19]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[19]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N6 -maxii_lcell \signal_low_voltage[20]~reg0 ( -// Equation(s): -// \signal_low_voltage[20]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & ((cache2_line_sdata[20])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(vcc), - .datad(cache2_line_sdata[20]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[20]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[20]~reg0 .lut_mask = "1100"; -defparam \signal_low_voltage[20]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[20]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[20]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[20]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[20]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y6_N3 -maxii_lcell \signal_low_voltage[21]~reg0 ( -// Equation(s): -// \signal_low_voltage[21]~reg0_regout = DFFEAS(((cache2_line_sdata[21] & (!\fault_flag[1][0]~regout & !\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(cache2_line_sdata[21]), - .datac(\fault_flag[1][0]~regout ), - .datad(\fault_flag[0][0]~regout ), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[21]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[21]~reg0 .lut_mask = "000c"; -defparam \signal_low_voltage[21]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[21]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[21]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[21]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[21]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N6 -maxii_lcell \signal_low_voltage[22]~reg0 ( -// Equation(s): -// \signal_low_voltage[22]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[22]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[22]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[22]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[22]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[22]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[22]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[22]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[22]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[22]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y9_N6 -maxii_lcell \signal_low_voltage[23]~reg0 ( -// Equation(s): -// \signal_low_voltage[23]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache2_line_sdata[23])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[23]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[23]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[23]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[23]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[23]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[23]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[23]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[23]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y9_N4 -maxii_lcell \signal_low_voltage[24]~reg0 ( -// Equation(s): -// \signal_low_voltage[24]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache2_line_sdata[24])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[24]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[24]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[24]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[24]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[24]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[24]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[24]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[24]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y9_N8 -maxii_lcell \signal_low_voltage[25]~reg0 ( -// Equation(s): -// \signal_low_voltage[25]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache2_line_sdata[25])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[25]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[25]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[25]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[25]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[25]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[25]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[25]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[25]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y8_N0 -maxii_lcell \signal_low_voltage[26]~reg0 ( -// Equation(s): -// \signal_low_voltage[26]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (!\fault_flag[0][0]~regout & ((cache2_line_sdata[26])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(\fault_flag[0][0]~regout ), - .datac(vcc), - .datad(cache2_line_sdata[26]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[26]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[26]~reg0 .lut_mask = "1100"; -defparam \signal_low_voltage[26]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[26]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[26]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[26]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[26]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X13_Y8_N2 -maxii_lcell \signal_low_voltage[27]~reg0 ( -// Equation(s): -// \signal_low_voltage[27]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[27]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[27]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[27]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[27]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[27]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[27]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[27]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[27]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[27]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y7_N4 -maxii_lcell \signal_low_voltage[28]~reg0 ( -// Equation(s): -// \signal_low_voltage[28]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[28] & (!\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[28]), - .datac(\fault_flag[0][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[28]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[28]~reg0 .lut_mask = "0404"; -defparam \signal_low_voltage[28]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[28]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[28]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[28]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[28]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N5 -maxii_lcell \signal_low_voltage[29]~reg0 ( -// Equation(s): -// \signal_low_voltage[29]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[29] & (!\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[29]), - .datac(\fault_flag[0][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[29]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[29]~reg0 .lut_mask = "0404"; -defparam \signal_low_voltage[29]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[29]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[29]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[29]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[29]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y9_N2 -maxii_lcell \signal_low_voltage[30]~reg0 ( -// Equation(s): -// \signal_low_voltage[30]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[30]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[30]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[30]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[30]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[30]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[30]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[30]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[30]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[30]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X11_Y9_N6 -maxii_lcell \signal_low_voltage[31]~reg0 ( -// Equation(s): -// \signal_low_voltage[31]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[31]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[31]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[31]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[31]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[31]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[31]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[31]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[31]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[31]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N7 -maxii_lcell \signal_low_voltage[32]~reg0 ( -// Equation(s): -// \signal_low_voltage[32]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache2_line_sdata[32])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache2_line_sdata[32]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[32]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[32]~reg0 .lut_mask = "1100"; -defparam \signal_low_voltage[32]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[32]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[32]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[32]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[32]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N3 -maxii_lcell \signal_low_voltage[33]~reg0 ( -// Equation(s): -// \signal_low_voltage[33]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (cache2_line_sdata[33] & (!\fault_flag[1][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(cache2_line_sdata[33]), - .datac(\fault_flag[1][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[33]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[33]~reg0 .lut_mask = "0404"; -defparam \signal_low_voltage[33]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[33]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[33]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[33]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[33]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X12_Y7_N2 -maxii_lcell \signal_low_voltage[34]~reg0 ( -// Equation(s): -// \signal_low_voltage[34]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[34]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[34]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[34]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[34]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[34]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[34]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[34]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[34]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[34]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N4 -maxii_lcell \signal_low_voltage[35]~reg0 ( -// Equation(s): -// \signal_low_voltage[35]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (cache2_line_sdata[35] & (!\fault_flag[0][0]~regout ))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(cache2_line_sdata[35]), - .datac(\fault_flag[0][0]~regout ), - .datad(vcc), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[35]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[35]~reg0 .lut_mask = "0404"; -defparam \signal_low_voltage[35]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[35]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[35]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[35]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[35]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X8_Y5_N2 -maxii_lcell \signal_low_voltage[36]~reg0 ( -// Equation(s): -// \signal_low_voltage[36]~reg0_regout = DFFEAS((!\fault_flag[1][0]~regout & (((!\fault_flag[0][0]~regout & cache2_line_sdata[36])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[1][0]~regout ), - .datab(vcc), - .datac(\fault_flag[0][0]~regout ), - .datad(cache2_line_sdata[36]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[36]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[36]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[36]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[36]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[36]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[36]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[36]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N4 -maxii_lcell \signal_low_voltage[37]~reg0 ( -// Equation(s): -// \signal_low_voltage[37]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache2_line_sdata[37])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[37]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[37]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[37]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[37]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[37]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[37]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[37]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[37]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y9_N2 -maxii_lcell \signal_low_voltage[38]~reg0 ( -// Equation(s): -// \signal_low_voltage[38]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[38]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[38]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[38]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[38]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[38]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[38]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[38]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[38]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[38]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X10_Y9_N8 -maxii_lcell \signal_low_voltage[39]~reg0 ( -// Equation(s): -// \signal_low_voltage[39]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache2_line_sdata[39])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache2_line_sdata[39]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[39]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[39]~reg0 .lut_mask = "1100"; -defparam \signal_low_voltage[39]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[39]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[39]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[39]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[39]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y6_N4 -maxii_lcell \signal_low_voltage[40]~reg0 ( -// Equation(s): -// \signal_low_voltage[40]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache2_line_sdata[40])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[40]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[40]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[40]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[40]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[40]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[40]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[40]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[40]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y8_N8 -maxii_lcell \signal_low_voltage[41]~reg0 ( -// Equation(s): -// \signal_low_voltage[41]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache2_line_sdata[41])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[41]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[41]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[41]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[41]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[41]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[41]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[41]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[41]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X7_Y6_N2 -maxii_lcell \signal_low_voltage[42]~reg0 ( -// Equation(s): -// \signal_low_voltage[42]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[42]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[42]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[42]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[42]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[42]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[42]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[42]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[42]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[42]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X5_Y8_N7 -maxii_lcell \signal_low_voltage[43]~reg0 ( -// Equation(s): -// \signal_low_voltage[43]~reg0_regout = DFFEAS(((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & cache2_line_sdata[43]))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(vcc), - .datab(\fault_flag[0][0]~regout ), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[43]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[43]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[43]~reg0 .lut_mask = "0300"; -defparam \signal_low_voltage[43]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[43]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[43]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[43]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[43]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y6_N1 -maxii_lcell \signal_low_voltage[44]~reg0 ( -// Equation(s): -// \signal_low_voltage[44]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache2_line_sdata[44])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[44]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[44]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[44]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[44]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[44]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[44]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[44]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[44]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y6_N2 -maxii_lcell \signal_low_voltage[45]~reg0 ( -// Equation(s): -// \signal_low_voltage[45]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (!\fault_flag[1][0]~regout & ((cache2_line_sdata[45])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(\fault_flag[1][0]~regout ), - .datac(vcc), - .datad(cache2_line_sdata[45]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[45]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[45]~reg0 .lut_mask = "1100"; -defparam \signal_low_voltage[45]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[45]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[45]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[45]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[45]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y6_N5 -maxii_lcell \signal_low_voltage[46]~reg0 ( -// Equation(s): -// \signal_low_voltage[46]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache2_line_sdata[46])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[46]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[46]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[46]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[46]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[46]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[46]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[46]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[46]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: LC_X6_Y6_N8 -maxii_lcell \signal_low_voltage[47]~reg0 ( -// Equation(s): -// \signal_low_voltage[47]~reg0_regout = DFFEAS((!\fault_flag[0][0]~regout & (((!\fault_flag[1][0]~regout & cache2_line_sdata[47])))), GLOBAL(\sys_clk~combout ), GLOBAL(\rst_n~combout ), , , , , , ) - - .clk(\sys_clk~combout ), - .dataa(\fault_flag[0][0]~regout ), - .datab(vcc), - .datac(\fault_flag[1][0]~regout ), - .datad(cache2_line_sdata[47]), - .aclr(!\rst_n~combout ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .cin(gnd), - .cin0(gnd), - .cin1(vcc), - .inverta(gnd), - .regcascin(gnd), - .devclrn(devclrn), - .devpor(devpor), - .combout(), - .regout(\signal_low_voltage[47]~reg0_regout ), - .cout(), - .cout0(), - .cout1()); -// synopsys translate_off -defparam \signal_low_voltage[47]~reg0 .lut_mask = "0500"; -defparam \signal_low_voltage[47]~reg0 .operation_mode = "normal"; -defparam \signal_low_voltage[47]~reg0 .output_mode = "reg_only"; -defparam \signal_low_voltage[47]~reg0 .register_cascade_mode = "off"; -defparam \signal_low_voltage[47]~reg0 .sum_lutc_input = "datac"; -defparam \signal_low_voltage[47]~reg0 .synch_mode = "off"; -// synopsys translate_on - -// Location: PIN_43, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[0]~I ( - .datain(!\signal_high_voltage[0]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[0])); -// synopsys translate_off -defparam \signal_high_voltage[0]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_44, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[1]~I ( - .datain(!\signal_high_voltage[1]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[1])); -// synopsys translate_off -defparam \signal_high_voltage[1]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_45, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[2]~I ( - .datain(!\signal_high_voltage[2]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[2])); -// synopsys translate_off -defparam \signal_high_voltage[2]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_48, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[3]~I ( - .datain(!\signal_high_voltage[3]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[3])); -// synopsys translate_off -defparam \signal_high_voltage[3]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_53, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[4]~I ( - .datain(!\signal_high_voltage[4]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[4])); -// synopsys translate_off -defparam \signal_high_voltage[4]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_55, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[5]~I ( - .datain(!\signal_high_voltage[5]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[5])); -// synopsys translate_off -defparam \signal_high_voltage[5]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_57, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[6]~I ( - .datain(!\signal_high_voltage[6]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[6])); -// synopsys translate_off -defparam \signal_high_voltage[6]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_58, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[7]~I ( - .datain(!\signal_high_voltage[7]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[7])); -// synopsys translate_off -defparam \signal_high_voltage[7]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_63, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[8]~I ( - .datain(!\signal_high_voltage[8]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[8])); -// synopsys translate_off -defparam \signal_high_voltage[8]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_66, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[9]~I ( - .datain(!\signal_high_voltage[9]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[9])); -// synopsys translate_off -defparam \signal_high_voltage[9]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_67, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[10]~I ( - .datain(!\signal_high_voltage[10]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[10])); -// synopsys translate_off -defparam \signal_high_voltage[10]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_68, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[11]~I ( - .datain(!\signal_high_voltage[11]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[11])); -// synopsys translate_off -defparam \signal_high_voltage[11]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_73, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[12]~I ( - .datain(!\signal_high_voltage[12]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[12])); -// synopsys translate_off -defparam \signal_high_voltage[12]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_74, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[13]~I ( - .datain(!\signal_high_voltage[13]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[13])); -// synopsys translate_off -defparam \signal_high_voltage[13]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_75, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[14]~I ( - .datain(!\signal_high_voltage[14]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[14])); -// synopsys translate_off -defparam \signal_high_voltage[14]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_76, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[15]~I ( - .datain(!\signal_high_voltage[15]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[15])); -// synopsys translate_off -defparam \signal_high_voltage[15]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_81, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[16]~I ( - .datain(!\signal_high_voltage[16]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[16])); -// synopsys translate_off -defparam \signal_high_voltage[16]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_84, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[17]~I ( - .datain(!\signal_high_voltage[17]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[17])); -// synopsys translate_off -defparam \signal_high_voltage[17]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_85, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[18]~I ( - .datain(!\signal_high_voltage[18]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[18])); -// synopsys translate_off -defparam \signal_high_voltage[18]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_86, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[19]~I ( - .datain(!\signal_high_voltage[19]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[19])); -// synopsys translate_off -defparam \signal_high_voltage[19]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_93, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[20]~I ( - .datain(!\signal_high_voltage[20]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[20])); -// synopsys translate_off -defparam \signal_high_voltage[20]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_94, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[21]~I ( - .datain(!\signal_high_voltage[21]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[21])); -// synopsys translate_off -defparam \signal_high_voltage[21]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_95, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[22]~I ( - .datain(!\signal_high_voltage[22]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[22])); -// synopsys translate_off -defparam \signal_high_voltage[22]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_96, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[23]~I ( - .datain(!\signal_high_voltage[23]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[23])); -// synopsys translate_off -defparam \signal_high_voltage[23]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_103, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[24]~I ( - .datain(!\signal_high_voltage[24]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[24])); -// synopsys translate_off -defparam \signal_high_voltage[24]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_104, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[25]~I ( - .datain(!\signal_high_voltage[25]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[25])); -// synopsys translate_off -defparam \signal_high_voltage[25]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_105, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[26]~I ( - .datain(!\signal_high_voltage[26]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[26])); -// synopsys translate_off -defparam \signal_high_voltage[26]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_106, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[27]~I ( - .datain(!\signal_high_voltage[27]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[27])); -// synopsys translate_off -defparam \signal_high_voltage[27]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_113, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[28]~I ( - .datain(!\signal_high_voltage[28]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[28])); -// synopsys translate_off -defparam \signal_high_voltage[28]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_114, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[29]~I ( - .datain(!\signal_high_voltage[29]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[29])); -// synopsys translate_off -defparam \signal_high_voltage[29]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_117, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[30]~I ( - .datain(!\signal_high_voltage[30]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[30])); -// synopsys translate_off -defparam \signal_high_voltage[30]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_118, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[31]~I ( - .datain(!\signal_high_voltage[31]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[31])); -// synopsys translate_off -defparam \signal_high_voltage[31]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_123, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[32]~I ( - .datain(!\signal_high_voltage[32]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[32])); -// synopsys translate_off -defparam \signal_high_voltage[32]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_124, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[33]~I ( - .datain(!\signal_high_voltage[33]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[33])); -// synopsys translate_off -defparam \signal_high_voltage[33]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_125, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[34]~I ( - .datain(!\signal_high_voltage[34]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[34])); -// synopsys translate_off -defparam \signal_high_voltage[34]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_127, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[35]~I ( - .datain(!\signal_high_voltage[35]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[35])); -// synopsys translate_off -defparam \signal_high_voltage[35]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_133, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[36]~I ( - .datain(!\signal_high_voltage[36]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[36])); -// synopsys translate_off -defparam \signal_high_voltage[36]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_134, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[37]~I ( - .datain(!\signal_high_voltage[37]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[37])); -// synopsys translate_off -defparam \signal_high_voltage[37]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_137, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[38]~I ( - .datain(!\signal_high_voltage[38]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[38])); -// synopsys translate_off -defparam \signal_high_voltage[38]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_138, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[39]~I ( - .datain(!\signal_high_voltage[39]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[39])); -// synopsys translate_off -defparam \signal_high_voltage[39]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_1, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[40]~I ( - .datain(!\signal_high_voltage[40]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[40])); -// synopsys translate_off -defparam \signal_high_voltage[40]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_2, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[41]~I ( - .datain(!\signal_high_voltage[41]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[41])); -// synopsys translate_off -defparam \signal_high_voltage[41]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_3, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[42]~I ( - .datain(!\signal_high_voltage[42]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[42])); -// synopsys translate_off -defparam \signal_high_voltage[42]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_4, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[43]~I ( - .datain(!\signal_high_voltage[43]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[43])); -// synopsys translate_off -defparam \signal_high_voltage[43]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_12, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[44]~I ( - .datain(!\signal_high_voltage[44]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[44])); -// synopsys translate_off -defparam \signal_high_voltage[44]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_13, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[45]~I ( - .datain(!\signal_high_voltage[45]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[45])); -// synopsys translate_off -defparam \signal_high_voltage[45]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_14, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[46]~I ( - .datain(!\signal_high_voltage[46]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[46])); -// synopsys translate_off -defparam \signal_high_voltage[46]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_high_voltage[47]~I ( - .datain(!\signal_high_voltage[47]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_high_voltage[47])); -// synopsys translate_off -defparam \signal_high_voltage[47]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_49, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[0]~I ( - .datain(!\signal_low_voltage[0]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[0])); -// synopsys translate_off -defparam \signal_low_voltage[0]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_50, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[1]~I ( - .datain(!\signal_low_voltage[1]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[1])); -// synopsys translate_off -defparam \signal_low_voltage[1]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_51, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[2]~I ( - .datain(!\signal_low_voltage[2]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[2])); -// synopsys translate_off -defparam \signal_low_voltage[2]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_52, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[3]~I ( - .datain(!\signal_low_voltage[3]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[3])); -// synopsys translate_off -defparam \signal_low_voltage[3]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_59, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[4]~I ( - .datain(!\signal_low_voltage[4]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[4])); -// synopsys translate_off -defparam \signal_low_voltage[4]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_60, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[5]~I ( - .datain(!\signal_low_voltage[5]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[5])); -// synopsys translate_off -defparam \signal_low_voltage[5]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_61, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[6]~I ( - .datain(!\signal_low_voltage[6]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[6])); -// synopsys translate_off -defparam \signal_low_voltage[6]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_62, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[7]~I ( - .datain(!\signal_low_voltage[7]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[7])); -// synopsys translate_off -defparam \signal_low_voltage[7]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_69, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[8]~I ( - .datain(!\signal_low_voltage[8]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[8])); -// synopsys translate_off -defparam \signal_low_voltage[8]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_70, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[9]~I ( - .datain(!\signal_low_voltage[9]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[9])); -// synopsys translate_off -defparam \signal_low_voltage[9]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_71, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[10]~I ( - .datain(!\signal_low_voltage[10]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[10])); -// synopsys translate_off -defparam \signal_low_voltage[10]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_72, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[11]~I ( - .datain(!\signal_low_voltage[11]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[11])); -// synopsys translate_off -defparam \signal_low_voltage[11]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_77, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[12]~I ( - .datain(!\signal_low_voltage[12]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[12])); -// synopsys translate_off -defparam \signal_low_voltage[12]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_78, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[13]~I ( - .datain(!\signal_low_voltage[13]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[13])); -// synopsys translate_off -defparam \signal_low_voltage[13]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_79, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[14]~I ( - .datain(!\signal_low_voltage[14]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[14])); -// synopsys translate_off -defparam \signal_low_voltage[14]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_80, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[15]~I ( - .datain(!\signal_low_voltage[15]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[15])); -// synopsys translate_off -defparam \signal_low_voltage[15]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_87, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[16]~I ( - .datain(!\signal_low_voltage[16]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[16])); -// synopsys translate_off -defparam \signal_low_voltage[16]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_88, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[17]~I ( - .datain(!\signal_low_voltage[17]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[17])); -// synopsys translate_off -defparam \signal_low_voltage[17]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_89, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[18]~I ( - .datain(!\signal_low_voltage[18]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[18])); -// synopsys translate_off -defparam \signal_low_voltage[18]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_91, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[19]~I ( - .datain(!\signal_low_voltage[19]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[19])); -// synopsys translate_off -defparam \signal_low_voltage[19]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_97, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[20]~I ( - .datain(!\signal_low_voltage[20]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[20])); -// synopsys translate_off -defparam \signal_low_voltage[20]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_98, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[21]~I ( - .datain(!\signal_low_voltage[21]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[21])); -// synopsys translate_off -defparam \signal_low_voltage[21]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_101, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[22]~I ( - .datain(!\signal_low_voltage[22]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[22])); -// synopsys translate_off -defparam \signal_low_voltage[22]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_102, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[23]~I ( - .datain(!\signal_low_voltage[23]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[23])); -// synopsys translate_off -defparam \signal_low_voltage[23]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_109, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[24]~I ( - .datain(!\signal_low_voltage[24]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[24])); -// synopsys translate_off -defparam \signal_low_voltage[24]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_110, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[25]~I ( - .datain(!\signal_low_voltage[25]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[25])); -// synopsys translate_off -defparam \signal_low_voltage[25]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_111, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[26]~I ( - .datain(!\signal_low_voltage[26]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[26])); -// synopsys translate_off -defparam \signal_low_voltage[26]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_112, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[27]~I ( - .datain(!\signal_low_voltage[27]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[27])); -// synopsys translate_off -defparam \signal_low_voltage[27]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_119, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[28]~I ( - .datain(!\signal_low_voltage[28]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[28])); -// synopsys translate_off -defparam \signal_low_voltage[28]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_120, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[29]~I ( - .datain(!\signal_low_voltage[29]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[29])); -// synopsys translate_off -defparam \signal_low_voltage[29]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_121, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[30]~I ( - .datain(!\signal_low_voltage[30]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[30])); -// synopsys translate_off -defparam \signal_low_voltage[30]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_122, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[31]~I ( - .datain(!\signal_low_voltage[31]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[31])); -// synopsys translate_off -defparam \signal_low_voltage[31]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_129, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[32]~I ( - .datain(!\signal_low_voltage[32]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[32])); -// synopsys translate_off -defparam \signal_low_voltage[32]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_130, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[33]~I ( - .datain(!\signal_low_voltage[33]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[33])); -// synopsys translate_off -defparam \signal_low_voltage[33]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_131, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[34]~I ( - .datain(!\signal_low_voltage[34]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[34])); -// synopsys translate_off -defparam \signal_low_voltage[34]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_132, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[35]~I ( - .datain(!\signal_low_voltage[35]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[35])); -// synopsys translate_off -defparam \signal_low_voltage[35]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_139, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[36]~I ( - .datain(!\signal_low_voltage[36]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[36])); -// synopsys translate_off -defparam \signal_low_voltage[36]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_140, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[37]~I ( - .datain(!\signal_low_voltage[37]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[37])); -// synopsys translate_off -defparam \signal_low_voltage[37]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_141, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[38]~I ( - .datain(!\signal_low_voltage[38]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[38])); -// synopsys translate_off -defparam \signal_low_voltage[38]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_142, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[39]~I ( - .datain(!\signal_low_voltage[39]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[39])); -// synopsys translate_off -defparam \signal_low_voltage[39]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_5, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[40]~I ( - .datain(!\signal_low_voltage[40]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[40])); -// synopsys translate_off -defparam \signal_low_voltage[40]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[41]~I ( - .datain(!\signal_low_voltage[41]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[41])); -// synopsys translate_off -defparam \signal_low_voltage[41]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[42]~I ( - .datain(!\signal_low_voltage[42]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[42])); -// synopsys translate_off -defparam \signal_low_voltage[42]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[43]~I ( - .datain(!\signal_low_voltage[43]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[43])); -// synopsys translate_off -defparam \signal_low_voltage[43]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_21, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[44]~I ( - .datain(!\signal_low_voltage[44]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[44])); -// synopsys translate_off -defparam \signal_low_voltage[44]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_22, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[45]~I ( - .datain(!\signal_low_voltage[45]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[45])); -// synopsys translate_off -defparam \signal_low_voltage[45]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_23, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[46]~I ( - .datain(!\signal_low_voltage[46]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[46])); -// synopsys translate_off -defparam \signal_low_voltage[46]~I .operation_mode = "output"; -// synopsys translate_on - -// Location: PIN_24, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA -maxii_io \signal_low_voltage[47]~I ( - .datain(!\signal_low_voltage[47]~reg0_regout ), - .oe(vcc), - .combout(), - .padio(signal_low_voltage[47])); -// synopsys translate_off -defparam \signal_low_voltage[47]~I .operation_mode = "output"; -// synopsys translate_on - -endmodule diff --git a/firmware/simulation/modelsim/PF1.vt b/firmware/simulation/modelsim/PF1.vt deleted file mode 100644 index 9e060f6..0000000 --- a/firmware/simulation/modelsim/PF1.vt +++ /dev/null @@ -1,112 +0,0 @@ -// Copyright (C) 1991-2011 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - -// ***************************************************************************** -// This file contains a Verilog test bench template that is freely editable to -// suit user's needs .Comments are provided in each section to help the user -// fill out necessary details. -// ***************************************************************************** -// Generated on "12/11/2013 17:08:40" - -// Verilog Test Bench template for design : PF1 -// -// Simulation tool : ModelSim-Altera (Verilog) -// - -`timescale 1 ns/ 1 ns -module PF1_vlg_tst(); -// constants -// general purpose registers -reg eachvec; -// test vector input registers -reg SCLK; -reg SDATA; -reg SEN; -reg clk; -reg rst_n; -// wires -wire [47:0] S_PF; -parameter PERIOD=20;//ʱڣλNS - -// assign statements (if any) -PF1 i1 ( -// port map - connection between master ports and signals/registers - .SCLK(SCLK), - .SDATA(SDATA), - .SEN(SEN), - .S_PF(S_PF), - .clk(clk), - .rst_n(rst_n) -); -initial begin - clk=0; - forever - #(PERIOD/2)clk = ~clk; -end - - - - -initial begin - SCLK=1; -end - -initial begin - rst_n=1; - -end - -initial begin - SEN=1; - end - - - - - - -initial begin - - -SDATA=0; -#20 -SDATA=0; -#20 -SDATA=0; - -#20 -SDATA=0; - -#20 -SDATA=0; - -#20 -SDATA=0; - -#20 -SDATA=0; - -#20 -SDATA=0; - -#20 -SDATA=0; - - -#1000 $stop; - -end - -endmodule - diff --git a/firmware/simulation/modelsim/PF1.vt.bak b/firmware/simulation/modelsim/PF1.vt.bak deleted file mode 100644 index 463b665..0000000 --- a/firmware/simulation/modelsim/PF1.vt.bak +++ /dev/null @@ -1,70 +0,0 @@ -// Copyright (C) 1991-2011 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - -// ***************************************************************************** -// This file contains a Verilog test bench template that is freely editable to -// suit user's needs .Comments are provided in each section to help the user -// fill out necessary details. -// ***************************************************************************** -// Generated on "12/11/2013 17:08:40" - -// Verilog Test Bench template for design : PF1 -// -// Simulation tool : ModelSim-Altera (Verilog) -// - -`timescale 1 ns/ 1 ps -module PF1_vlg_tst(); -// constants -// general purpose registers -reg eachvec; -// test vector input registers -reg SCLK; -reg SDATA; -reg SEN; -reg clk; -reg rst_n; -// wires -wire [47:0] S_PF; - -// assign statements (if any) -PF1 i1 ( -// port map - connection between master ports and signals/registers - .SCLK(SCLK), - .SDATA(SDATA), - .SEN(SEN), - .S_PF(S_PF), - .clk(clk), - .rst_n(rst_n) -); -initial -begin -// code that executes only once -// insert code here --> begin - -// --> end -$display("Running testbench"); -end -always -// optional sensitivity list -// @(event1 or event2 or .... eventn) -begin -// code executes for every event on sensitivity list -// insert code here --> begin - -@eachvec; -// --> end -end -endmodule - diff --git a/firmware/simulation/modelsim/PF1_modelsim.xrf b/firmware/simulation/modelsim/PF1_modelsim.xrf deleted file mode 100644 index 4224cdf..0000000 --- a/firmware/simulation/modelsim/PF1_modelsim.xrf +++ /dev/null @@ -1,560 +0,0 @@ -vendor_name = ModelSim -source_file = 1, C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v -source_file = 1, C:/Users/miaow/Desktop/valve_board_kun/PF1.v -source_file = 1, C:/Users/miaow/Desktop/valve_board_kun/db/PF1.cbx.xml -design_name = PF1 -instance = comp, \sys_clk~I , sys_clk, PF1, 1 -instance = comp, \rst_n~I , rst_n, PF1, 1 -instance = comp, \line_sclk~I , line_sclk, PF1, 1 -instance = comp, \cache_line_sclk[0] , cache_line_sclk[0], PF1, 1 -instance = comp, \cache_line_sclk[1] , cache_line_sclk[1], PF1, 1 -instance = comp, \cache_line_sclk[2] , cache_line_sclk[2], PF1, 1 -instance = comp, \cache_line_sclk[3] , cache_line_sclk[3], PF1, 1 -instance = comp, \cache_line_sclk[4] , cache_line_sclk[4], PF1, 1 -instance = comp, \fault_counter[0] , fault_counter[0], PF1, 1 -instance = comp, \fault_counter[1] , fault_counter[1], PF1, 1 -instance = comp, \fault_counter[2] , fault_counter[2], PF1, 1 -instance = comp, \fault_counter[3] , fault_counter[3], PF1, 1 -instance = comp, \fault_counter[4] , fault_counter[4], PF1, 1 -instance = comp, \fault_counter[5] , fault_counter[5], PF1, 1 -instance = comp, \fault_counter[6] , fault_counter[6], PF1, 1 -instance = comp, \fault_counter[7] , fault_counter[7], PF1, 1 -instance = comp, \fault_counter[8] , fault_counter[8], PF1, 1 -instance = comp, \fault_counter[9] , fault_counter[9], PF1, 1 -instance = comp, \fault_counter[10] , fault_counter[10], PF1, 1 -instance = comp, \fault_counter[11] , fault_counter[11], PF1, 1 -instance = comp, \fault_counter[12] , fault_counter[12], PF1, 1 -instance = comp, \fault_counter[13] , fault_counter[13], PF1, 1 -instance = comp, \fault_counter[14] , fault_counter[14], PF1, 1 -instance = comp, \fault_counter[15] , fault_counter[15], PF1, 1 -instance = comp, \fault_counter[16] , fault_counter[16], PF1, 1 -instance = comp, \fault_counter[17] , fault_counter[17], PF1, 1 -instance = comp, \fault_counter[18] , fault_counter[18], PF1, 1 -instance = comp, \fault_counter[19] , fault_counter[19], PF1, 1 -instance = comp, \fault_counter[20] , fault_counter[20], PF1, 1 -instance = comp, \fault_counter[21] , fault_counter[21], PF1, 1 -instance = comp, \fault_counter[22] , fault_counter[22], PF1, 1 -instance = comp, \fault_counter[23] , fault_counter[23], PF1, 1 -instance = comp, \fault_counter[24] , fault_counter[24], PF1, 1 -instance = comp, \fault_counter[25] , fault_counter[25], PF1, 1 -instance = comp, \fault_counter[26] , fault_counter[26], PF1, 1 -instance = comp, \fault_counter[27] , fault_counter[27], PF1, 1 -instance = comp, \fault_counter[28] , fault_counter[28], PF1, 1 -instance = comp, \fault_counter[29] , fault_counter[29], PF1, 1 -instance = comp, \fault_counter[30] , fault_counter[30], PF1, 1 -instance = comp, \fault_counter[31] , fault_counter[31], PF1, 1 -instance = comp, \fault_counter[26]~60 , fault_counter[26]~60, PF1, 1 -instance = comp, \fault_counter[26]~67 , fault_counter[26]~67, PF1, 1 -instance = comp, \fault_flag~7 , fault_flag~7, PF1, 1 -instance = comp, \LessThan2~8 , LessThan2~8, PF1, 1 -instance = comp, \LessThan2~9 , LessThan2~9, PF1, 1 -instance = comp, \LessThan2~6 , LessThan2~6, PF1, 1 -instance = comp, \LessThan2~2 , LessThan2~2, PF1, 1 -instance = comp, \LessThan2~4 , LessThan2~4, PF1, 1 -instance = comp, \LessThan2~3 , LessThan2~3, PF1, 1 -instance = comp, \LessThan2~5 , LessThan2~5, PF1, 1 -instance = comp, \LessThan2~0 , LessThan2~0, PF1, 1 -instance = comp, \LessThan2~1 , LessThan2~1, PF1, 1 -instance = comp, \LessThan2~7 , LessThan2~7, PF1, 1 -instance = comp, \fault_counter[26]~68 , fault_counter[26]~68, PF1, 1 -instance = comp, \fault_counter[26]~69 , fault_counter[26]~69, PF1, 1 -instance = comp, \fault_flag~10 , fault_flag~10, PF1, 1 -instance = comp, \fault_flag~6 , fault_flag~6, PF1, 1 -instance = comp, \fault_flag~2 , fault_flag~2, PF1, 1 -instance = comp, \fault_flag~3 , fault_flag~3, PF1, 1 -instance = comp, \fault_flag~4 , fault_flag~4, PF1, 1 -instance = comp, \fault_flag~5 , fault_flag~5, PF1, 1 -instance = comp, \fault_flag~8 , fault_flag~8, PF1, 1 -instance = comp, \fault_flag~9 , fault_flag~9, PF1, 1 -instance = comp, \fault_flag[1][0] , fault_flag[1][0], PF1, 1 -instance = comp, \line_sen~I , line_sen, PF1, 1 -instance = comp, \cache_line_sen[0] , cache_line_sen[0], PF1, 1 -instance = comp, \cache_line_sen[1] , cache_line_sen[1], PF1, 1 -instance = comp, \cache_line_sen[2] , cache_line_sen[2], PF1, 1 -instance = comp, \cache_line_sen[3] , cache_line_sen[3], PF1, 1 -instance = comp, \cache_line_sen[4] , cache_line_sen[4], PF1, 1 -instance = comp, \i[26]~69 , i[26]~69, PF1, 1 -instance = comp, \i[0] , i[0], PF1, 1 -instance = comp, \i[1] , i[1], PF1, 1 -instance = comp, \i[2] , i[2], PF1, 1 -instance = comp, \i[3] , i[3], PF1, 1 -instance = comp, \i[4] , i[4], PF1, 1 -instance = comp, \i[26]~68 , i[26]~68, PF1, 1 -instance = comp, \i[5] , i[5], PF1, 1 -instance = comp, \i[6] , i[6], PF1, 1 -instance = comp, \i[7] , i[7], PF1, 1 -instance = comp, \i[8] , i[8], PF1, 1 -instance = comp, \i[9] , i[9], PF1, 1 -instance = comp, \i[10] , i[10], PF1, 1 -instance = comp, \i[11] , i[11], PF1, 1 -instance = comp, \i[12] , i[12], PF1, 1 -instance = comp, \i[13] , i[13], PF1, 1 -instance = comp, \i[14] , i[14], PF1, 1 -instance = comp, \i[15] , i[15], PF1, 1 -instance = comp, \i[16] , i[16], PF1, 1 -instance = comp, \i[17] , i[17], PF1, 1 -instance = comp, \recv_complete~4 , recv_complete~4, PF1, 1 -instance = comp, \i[18] , i[18], PF1, 1 -instance = comp, \i[19] , i[19], PF1, 1 -instance = comp, \i[20] , i[20], PF1, 1 -instance = comp, \i[21] , i[21], PF1, 1 -instance = comp, \recv_complete~5 , recv_complete~5, PF1, 1 -instance = comp, \recv_complete~1 , recv_complete~1, PF1, 1 -instance = comp, \recv_complete~2 , recv_complete~2, PF1, 1 -instance = comp, \recv_complete~3 , recv_complete~3, PF1, 1 -instance = comp, \i[22] , i[22], PF1, 1 -instance = comp, \i[23] , i[23], PF1, 1 -instance = comp, \i[24] , i[24], PF1, 1 -instance = comp, \i[25] , i[25], PF1, 1 -instance = comp, \i[26] , i[26], PF1, 1 -instance = comp, \i[27] , i[27], PF1, 1 -instance = comp, \i[28] , i[28], PF1, 1 -instance = comp, \i[29] , i[29], PF1, 1 -instance = comp, \i[30] , i[30], PF1, 1 -instance = comp, \i[31] , i[31], PF1, 1 -instance = comp, \recv_complete~7 , recv_complete~7, PF1, 1 -instance = comp, \recv_complete~6 , recv_complete~6, PF1, 1 -instance = comp, \recv_complete~8 , recv_complete~8, PF1, 1 -instance = comp, \recv_complete~9 , recv_complete~9, PF1, 1 -instance = comp, \recv_complete~0 , recv_complete~0, PF1, 1 -instance = comp, \fault_flag~0 , fault_flag~0, PF1, 1 -instance = comp, \fault_flag[0][0] , fault_flag[0][0], PF1, 1 -instance = comp, \cnt_for_high_voltage_time~128 , cnt_for_high_voltage_time~128, PF1, 1 -instance = comp, \line_sdata~I , line_sdata, PF1, 1 -instance = comp, \tmp_cache_line_sdata[0] , tmp_cache_line_sdata[0], PF1, 1 -instance = comp, \tmp_cache_line_sdata[1] , tmp_cache_line_sdata[1], PF1, 1 -instance = comp, \tmp_cache_line_sdata[2] , tmp_cache_line_sdata[2], PF1, 1 -instance = comp, \tmp_cache_line_sdata[3] , tmp_cache_line_sdata[3], PF1, 1 -instance = comp, \tmp_cache_line_sdata[4] , tmp_cache_line_sdata[4], PF1, 1 -instance = comp, \Decoder0~101 , Decoder0~101, PF1, 1 -instance = comp, \cache_line_sdata[0] , cache_line_sdata[0], PF1, 1 -instance = comp, \recv_complete~10 , recv_complete~10, PF1, 1 -instance = comp, \recv_complete~11 , recv_complete~11, PF1, 1 -instance = comp, \cache2_line_sdata[45]~50 , cache2_line_sdata[45]~50, PF1, 1 -instance = comp, \cache2_line_sdata[0] , cache2_line_sdata[0], PF1, 1 -instance = comp, \cache_enable_count_high_voltage_time[0] , cache_enable_count_high_voltage_time[0], PF1, 1 -instance = comp, \cache_enable_count_high_voltage_time[1] , cache_enable_count_high_voltage_time[1], PF1, 1 -instance = comp, \Add2~0 , Add2~0, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[18]~129 , cnt_for_high_voltage_time[18]~129, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[0] , cnt_for_high_voltage_time[0], PF1, 1 -instance = comp, \Add2~155 , Add2~155, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[1] , cnt_for_high_voltage_time[1], PF1, 1 -instance = comp, \Add2~150 , Add2~150, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[2] , cnt_for_high_voltage_time[2], PF1, 1 -instance = comp, \Add2~145 , Add2~145, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[3] , cnt_for_high_voltage_time[3], PF1, 1 -instance = comp, \Add2~140 , Add2~140, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[4] , cnt_for_high_voltage_time[4], PF1, 1 -instance = comp, \Add2~135 , Add2~135, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[5] , cnt_for_high_voltage_time[5], PF1, 1 -instance = comp, \Add2~130 , Add2~130, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[6] , cnt_for_high_voltage_time[6], PF1, 1 -instance = comp, \Add2~125 , Add2~125, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[7] , cnt_for_high_voltage_time[7], PF1, 1 -instance = comp, \Add2~120 , Add2~120, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[8] , cnt_for_high_voltage_time[8], PF1, 1 -instance = comp, \Add2~115 , Add2~115, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[9] , cnt_for_high_voltage_time[9], PF1, 1 -instance = comp, \Add2~110 , Add2~110, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[10] , cnt_for_high_voltage_time[10], PF1, 1 -instance = comp, \Add2~105 , Add2~105, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[11] , cnt_for_high_voltage_time[11], PF1, 1 -instance = comp, \Equal4~6 , Equal4~6, PF1, 1 -instance = comp, \Add2~100 , Add2~100, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[12] , cnt_for_high_voltage_time[12], PF1, 1 -instance = comp, \Add2~95 , Add2~95, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[13] , cnt_for_high_voltage_time[13], PF1, 1 -instance = comp, \Add2~90 , Add2~90, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[14] , cnt_for_high_voltage_time[14], PF1, 1 -instance = comp, \Add2~85 , Add2~85, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[15] , cnt_for_high_voltage_time[15], PF1, 1 -instance = comp, \Equal4~5 , Equal4~5, PF1, 1 -instance = comp, \Equal4~7 , Equal4~7, PF1, 1 -instance = comp, \Equal4~8 , Equal4~8, PF1, 1 -instance = comp, \Add2~80 , Add2~80, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[16] , cnt_for_high_voltage_time[16], PF1, 1 -instance = comp, \Add2~75 , Add2~75, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[17] , cnt_for_high_voltage_time[17], PF1, 1 -instance = comp, \Add2~70 , Add2~70, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[18] , cnt_for_high_voltage_time[18], PF1, 1 -instance = comp, \Add2~65 , Add2~65, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[19] , cnt_for_high_voltage_time[19], PF1, 1 -instance = comp, \Equal4~3 , Equal4~3, PF1, 1 -instance = comp, \Add2~60 , Add2~60, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[20] , cnt_for_high_voltage_time[20], PF1, 1 -instance = comp, \Add2~55 , Add2~55, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[21] , cnt_for_high_voltage_time[21], PF1, 1 -instance = comp, \Add2~50 , Add2~50, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[22] , cnt_for_high_voltage_time[22], PF1, 1 -instance = comp, \Add2~45 , Add2~45, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[23] , cnt_for_high_voltage_time[23], PF1, 1 -instance = comp, \Add2~40 , Add2~40, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[24] , cnt_for_high_voltage_time[24], PF1, 1 -instance = comp, \Add2~35 , Add2~35, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[25] , cnt_for_high_voltage_time[25], PF1, 1 -instance = comp, \Add2~30 , Add2~30, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[26] , cnt_for_high_voltage_time[26], PF1, 1 -instance = comp, \Add2~25 , Add2~25, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[27] , cnt_for_high_voltage_time[27], PF1, 1 -instance = comp, \Equal4~1 , Equal4~1, PF1, 1 -instance = comp, \Equal4~2 , Equal4~2, PF1, 1 -instance = comp, \Add2~20 , Add2~20, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[28] , cnt_for_high_voltage_time[28], PF1, 1 -instance = comp, \Add2~15 , Add2~15, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[29] , cnt_for_high_voltage_time[29], PF1, 1 -instance = comp, \Add2~10 , Add2~10, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[30] , cnt_for_high_voltage_time[30], PF1, 1 -instance = comp, \Add2~5 , Add2~5, PF1, 1 -instance = comp, \cnt_for_high_voltage_time[31] , cnt_for_high_voltage_time[31], PF1, 1 -instance = comp, \Equal4~0 , Equal4~0, PF1, 1 -instance = comp, \Equal4~4 , Equal4~4, PF1, 1 -instance = comp, \Equal4~9 , Equal4~9, PF1, 1 -instance = comp, \Equal4~10 , Equal4~10, PF1, 1 -instance = comp, \signal_high_voltage[0]~reg0 , signal_high_voltage[0]~reg0, PF1, 1 -instance = comp, \Decoder0~66 , Decoder0~66, PF1, 1 -instance = comp, \cache_line_sdata[1] , cache_line_sdata[1], PF1, 1 -instance = comp, \cache2_line_sdata[1] , cache2_line_sdata[1], PF1, 1 -instance = comp, \signal_high_voltage[1]~reg0 , signal_high_voltage[1]~reg0, PF1, 1 -instance = comp, \Decoder0~64 , Decoder0~64, PF1, 1 -instance = comp, \always3~0 , always3~0, PF1, 1 -instance = comp, \Decoder0~68 , Decoder0~68, PF1, 1 -instance = comp, \Decoder0~102 , Decoder0~102, PF1, 1 -instance = comp, \cache_line_sdata[2] , cache_line_sdata[2], PF1, 1 -instance = comp, \cache2_line_sdata[2] , cache2_line_sdata[2], PF1, 1 -instance = comp, \signal_high_voltage[2]~reg0 , signal_high_voltage[2]~reg0, PF1, 1 -instance = comp, \Decoder0~69 , Decoder0~69, PF1, 1 -instance = comp, \Decoder0~103 , Decoder0~103, PF1, 1 -instance = comp, \cache_line_sdata[3] , cache_line_sdata[3], PF1, 1 -instance = comp, \cache2_line_sdata[3] , cache2_line_sdata[3], PF1, 1 -instance = comp, \signal_high_voltage[3]~reg0 , signal_high_voltage[3]~reg0, PF1, 1 -instance = comp, \Decoder0~70 , Decoder0~70, PF1, 1 -instance = comp, \Decoder0~71 , Decoder0~71, PF1, 1 -instance = comp, \cache_line_sdata[4] , cache_line_sdata[4], PF1, 1 -instance = comp, \cache2_line_sdata[4] , cache2_line_sdata[4], PF1, 1 -instance = comp, \signal_high_voltage[4]~reg0 , signal_high_voltage[4]~reg0, PF1, 1 -instance = comp, \Decoder0~72 , Decoder0~72, PF1, 1 -instance = comp, \Decoder0~104 , Decoder0~104, PF1, 1 -instance = comp, \cache_line_sdata[5] , cache_line_sdata[5], PF1, 1 -instance = comp, \cache2_line_sdata[5] , cache2_line_sdata[5], PF1, 1 -instance = comp, \signal_high_voltage[5]~reg0 , signal_high_voltage[5]~reg0, PF1, 1 -instance = comp, \Decoder0~73 , Decoder0~73, PF1, 1 -instance = comp, \Decoder0~105 , Decoder0~105, PF1, 1 -instance = comp, \cache_line_sdata[6] , cache_line_sdata[6], PF1, 1 -instance = comp, \cache2_line_sdata[6] , cache2_line_sdata[6], PF1, 1 -instance = comp, \signal_high_voltage[6]~reg0 , signal_high_voltage[6]~reg0, PF1, 1 -instance = comp, \Decoder0~106 , Decoder0~106, PF1, 1 -instance = comp, \cache_line_sdata[7] , cache_line_sdata[7], PF1, 1 -instance = comp, \cache2_line_sdata[7] , cache2_line_sdata[7], PF1, 1 -instance = comp, \signal_high_voltage[7]~reg0 , signal_high_voltage[7]~reg0, PF1, 1 -instance = comp, \Decoder0~107 , Decoder0~107, PF1, 1 -instance = comp, \cache_line_sdata[8] , cache_line_sdata[8], PF1, 1 -instance = comp, \cache2_line_sdata[8] , cache2_line_sdata[8], PF1, 1 -instance = comp, \signal_high_voltage[8]~reg0 , signal_high_voltage[8]~reg0, PF1, 1 -instance = comp, \Decoder0~108 , Decoder0~108, PF1, 1 -instance = comp, \cache_line_sdata[9] , cache_line_sdata[9], PF1, 1 -instance = comp, \cache2_line_sdata[9] , cache2_line_sdata[9], PF1, 1 -instance = comp, \signal_high_voltage[9]~reg0 , signal_high_voltage[9]~reg0, PF1, 1 -instance = comp, \Decoder0~74 , Decoder0~74, PF1, 1 -instance = comp, \Decoder0~109 , Decoder0~109, PF1, 1 -instance = comp, \cache_line_sdata[10] , cache_line_sdata[10], PF1, 1 -instance = comp, \cache2_line_sdata[10] , cache2_line_sdata[10], PF1, 1 -instance = comp, \signal_high_voltage[10]~reg0 , signal_high_voltage[10]~reg0, PF1, 1 -instance = comp, \Decoder0~110 , Decoder0~110, PF1, 1 -instance = comp, \cache_line_sdata[11] , cache_line_sdata[11], PF1, 1 -instance = comp, \cache2_line_sdata[11] , cache2_line_sdata[11], PF1, 1 -instance = comp, \signal_high_voltage[11]~reg0 , signal_high_voltage[11]~reg0, PF1, 1 -instance = comp, \Decoder0~76 , Decoder0~76, PF1, 1 -instance = comp, \cache_line_sdata[12] , cache_line_sdata[12], PF1, 1 -instance = comp, \cache2_line_sdata[12] , cache2_line_sdata[12], PF1, 1 -instance = comp, \signal_high_voltage[12]~reg0 , signal_high_voltage[12]~reg0, PF1, 1 -instance = comp, \Decoder0~111 , Decoder0~111, PF1, 1 -instance = comp, \cache_line_sdata[13] , cache_line_sdata[13], PF1, 1 -instance = comp, \cache2_line_sdata[13] , cache2_line_sdata[13], PF1, 1 -instance = comp, \signal_high_voltage[13]~reg0 , signal_high_voltage[13]~reg0, PF1, 1 -instance = comp, \Decoder0~77 , Decoder0~77, PF1, 1 -instance = comp, \cache_line_sdata[14] , cache_line_sdata[14], PF1, 1 -instance = comp, \cache2_line_sdata[14] , cache2_line_sdata[14], PF1, 1 -instance = comp, \signal_high_voltage[14]~reg0 , signal_high_voltage[14]~reg0, PF1, 1 -instance = comp, \Decoder0~112 , Decoder0~112, PF1, 1 -instance = comp, \cache_line_sdata[15] , cache_line_sdata[15], PF1, 1 -instance = comp, \cache2_line_sdata[15] , cache2_line_sdata[15], PF1, 1 -instance = comp, \signal_high_voltage[15]~reg0 , signal_high_voltage[15]~reg0, PF1, 1 -instance = comp, \Decoder0~78 , Decoder0~78, PF1, 1 -instance = comp, \Decoder0~113 , Decoder0~113, PF1, 1 -instance = comp, \cache_line_sdata[16] , cache_line_sdata[16], PF1, 1 -instance = comp, \cache2_line_sdata[16] , cache2_line_sdata[16], PF1, 1 -instance = comp, \signal_high_voltage[16]~reg0 , signal_high_voltage[16]~reg0, PF1, 1 -instance = comp, \Decoder0~79 , Decoder0~79, PF1, 1 -instance = comp, \Decoder0~80 , Decoder0~80, PF1, 1 -instance = comp, \cache_line_sdata[17] , cache_line_sdata[17], PF1, 1 -instance = comp, \cache2_line_sdata[17] , cache2_line_sdata[17], PF1, 1 -instance = comp, \signal_high_voltage[17]~reg0 , signal_high_voltage[17]~reg0, PF1, 1 -instance = comp, \Decoder0~114 , Decoder0~114, PF1, 1 -instance = comp, \cache_line_sdata[18] , cache_line_sdata[18], PF1, 1 -instance = comp, \cache2_line_sdata[18] , cache2_line_sdata[18], PF1, 1 -instance = comp, \signal_high_voltage[18]~reg0 , signal_high_voltage[18]~reg0, PF1, 1 -instance = comp, \Decoder0~67 , Decoder0~67, PF1, 1 -instance = comp, \Decoder0~81 , Decoder0~81, PF1, 1 -instance = comp, \cache_line_sdata[19] , cache_line_sdata[19], PF1, 1 -instance = comp, \cache2_line_sdata[19] , cache2_line_sdata[19], PF1, 1 -instance = comp, \signal_high_voltage[19]~reg0 , signal_high_voltage[19]~reg0, PF1, 1 -instance = comp, \Decoder0~82 , Decoder0~82, PF1, 1 -instance = comp, \Decoder0~115 , Decoder0~115, PF1, 1 -instance = comp, \Decoder0~83 , Decoder0~83, PF1, 1 -instance = comp, \cache_line_sdata[20] , cache_line_sdata[20], PF1, 1 -instance = comp, \cache2_line_sdata[20] , cache2_line_sdata[20], PF1, 1 -instance = comp, \signal_high_voltage[20]~reg0 , signal_high_voltage[20]~reg0, PF1, 1 -instance = comp, \Decoder0~84 , Decoder0~84, PF1, 1 -instance = comp, \cache_line_sdata[21] , cache_line_sdata[21], PF1, 1 -instance = comp, \cache2_line_sdata[21] , cache2_line_sdata[21], PF1, 1 -instance = comp, \signal_high_voltage[21]~reg0 , signal_high_voltage[21]~reg0, PF1, 1 -instance = comp, \Decoder0~116 , Decoder0~116, PF1, 1 -instance = comp, \cache_line_sdata[22] , cache_line_sdata[22], PF1, 1 -instance = comp, \cache2_line_sdata[22] , cache2_line_sdata[22], PF1, 1 -instance = comp, \signal_high_voltage[22]~reg0 , signal_high_voltage[22]~reg0, PF1, 1 -instance = comp, \Decoder0~85 , Decoder0~85, PF1, 1 -instance = comp, \cache_line_sdata[23] , cache_line_sdata[23], PF1, 1 -instance = comp, \cache2_line_sdata[23] , cache2_line_sdata[23], PF1, 1 -instance = comp, \signal_high_voltage[23]~reg0 , signal_high_voltage[23]~reg0, PF1, 1 -instance = comp, \Decoder0~86 , Decoder0~86, PF1, 1 -instance = comp, \cache_line_sdata[24] , cache_line_sdata[24], PF1, 1 -instance = comp, \cache2_line_sdata[24] , cache2_line_sdata[24], PF1, 1 -instance = comp, \signal_high_voltage[24]~reg0 , signal_high_voltage[24]~reg0, PF1, 1 -instance = comp, \Decoder0~75 , Decoder0~75, PF1, 1 -instance = comp, \Decoder0~87 , Decoder0~87, PF1, 1 -instance = comp, \cache_line_sdata[25] , cache_line_sdata[25], PF1, 1 -instance = comp, \cache2_line_sdata[25] , cache2_line_sdata[25], PF1, 1 -instance = comp, \signal_high_voltage[25]~reg0 , signal_high_voltage[25]~reg0, PF1, 1 -instance = comp, \Decoder0~117 , Decoder0~117, PF1, 1 -instance = comp, \cache_line_sdata[26] , cache_line_sdata[26], PF1, 1 -instance = comp, \cache2_line_sdata[26] , cache2_line_sdata[26], PF1, 1 -instance = comp, \signal_high_voltage[26]~reg0 , signal_high_voltage[26]~reg0, PF1, 1 -instance = comp, \Decoder0~88 , Decoder0~88, PF1, 1 -instance = comp, \cache_line_sdata[27] , cache_line_sdata[27], PF1, 1 -instance = comp, \cache2_line_sdata[27] , cache2_line_sdata[27], PF1, 1 -instance = comp, \signal_high_voltage[27]~reg0 , signal_high_voltage[27]~reg0, PF1, 1 -instance = comp, \Decoder0~89 , Decoder0~89, PF1, 1 -instance = comp, \cache_line_sdata[28] , cache_line_sdata[28], PF1, 1 -instance = comp, \cache2_line_sdata[28] , cache2_line_sdata[28], PF1, 1 -instance = comp, \signal_high_voltage[28]~reg0 , signal_high_voltage[28]~reg0, PF1, 1 -instance = comp, \Decoder0~90 , Decoder0~90, PF1, 1 -instance = comp, \cache_line_sdata[29] , cache_line_sdata[29], PF1, 1 -instance = comp, \cache2_line_sdata[29] , cache2_line_sdata[29], PF1, 1 -instance = comp, \signal_high_voltage[29]~reg0 , signal_high_voltage[29]~reg0, PF1, 1 -instance = comp, \Decoder0~91 , Decoder0~91, PF1, 1 -instance = comp, \cache_line_sdata[30] , cache_line_sdata[30], PF1, 1 -instance = comp, \cache2_line_sdata[30] , cache2_line_sdata[30], PF1, 1 -instance = comp, \signal_high_voltage[30]~reg0 , signal_high_voltage[30]~reg0, PF1, 1 -instance = comp, \Decoder0~92 , Decoder0~92, PF1, 1 -instance = comp, \cache_line_sdata[31] , cache_line_sdata[31], PF1, 1 -instance = comp, \cache2_line_sdata[31] , cache2_line_sdata[31], PF1, 1 -instance = comp, \signal_high_voltage[31]~reg0 , signal_high_voltage[31]~reg0, PF1, 1 -instance = comp, \Decoder0~118 , Decoder0~118, PF1, 1 -instance = comp, \cache_line_sdata[32] , cache_line_sdata[32], PF1, 1 -instance = comp, \cache2_line_sdata[32] , cache2_line_sdata[32], PF1, 1 -instance = comp, \signal_high_voltage[32]~reg0 , signal_high_voltage[32]~reg0, PF1, 1 -instance = comp, \Decoder0~93 , Decoder0~93, PF1, 1 -instance = comp, \cache_line_sdata[33] , cache_line_sdata[33], PF1, 1 -instance = comp, \cache2_line_sdata[33] , cache2_line_sdata[33], PF1, 1 -instance = comp, \signal_high_voltage[33]~reg0 , signal_high_voltage[33]~reg0, PF1, 1 -instance = comp, \Decoder0~119 , Decoder0~119, PF1, 1 -instance = comp, \cache_line_sdata[34] , cache_line_sdata[34], PF1, 1 -instance = comp, \cache2_line_sdata[34] , cache2_line_sdata[34], PF1, 1 -instance = comp, \signal_high_voltage[34]~reg0 , signal_high_voltage[34]~reg0, PF1, 1 -instance = comp, \Decoder0~120 , Decoder0~120, PF1, 1 -instance = comp, \cache_line_sdata[35] , cache_line_sdata[35], PF1, 1 -instance = comp, \cache2_line_sdata[35] , cache2_line_sdata[35], PF1, 1 -instance = comp, \signal_high_voltage[35]~reg0 , signal_high_voltage[35]~reg0, PF1, 1 -instance = comp, \Decoder0~94 , Decoder0~94, PF1, 1 -instance = comp, \Decoder0~95 , Decoder0~95, PF1, 1 -instance = comp, \cache_line_sdata[36] , cache_line_sdata[36], PF1, 1 -instance = comp, \cache2_line_sdata[36] , cache2_line_sdata[36], PF1, 1 -instance = comp, \signal_high_voltage[36]~reg0 , signal_high_voltage[36]~reg0, PF1, 1 -instance = comp, \Decoder0~121 , Decoder0~121, PF1, 1 -instance = comp, \cache_line_sdata[37] , cache_line_sdata[37], PF1, 1 -instance = comp, \cache2_line_sdata[37] , cache2_line_sdata[37], PF1, 1 -instance = comp, \signal_high_voltage[37]~reg0 , signal_high_voltage[37]~reg0, PF1, 1 -instance = comp, \Decoder0~122 , Decoder0~122, PF1, 1 -instance = comp, \cache_line_sdata[38] , cache_line_sdata[38], PF1, 1 -instance = comp, \cache2_line_sdata[38] , cache2_line_sdata[38], PF1, 1 -instance = comp, \signal_high_voltage[38]~reg0 , signal_high_voltage[38]~reg0, PF1, 1 -instance = comp, \Decoder0~123 , Decoder0~123, PF1, 1 -instance = comp, \cache_line_sdata[39] , cache_line_sdata[39], PF1, 1 -instance = comp, \cache2_line_sdata[39] , cache2_line_sdata[39], PF1, 1 -instance = comp, \signal_high_voltage[39]~reg0 , signal_high_voltage[39]~reg0, PF1, 1 -instance = comp, \Decoder0~96 , Decoder0~96, PF1, 1 -instance = comp, \cache_line_sdata[40] , cache_line_sdata[40], PF1, 1 -instance = comp, \cache2_line_sdata[40] , cache2_line_sdata[40], PF1, 1 -instance = comp, \signal_high_voltage[40]~reg0 , signal_high_voltage[40]~reg0, PF1, 1 -instance = comp, \Decoder0~124 , Decoder0~124, PF1, 1 -instance = comp, \cache_line_sdata[41] , cache_line_sdata[41], PF1, 1 -instance = comp, \cache2_line_sdata[41] , cache2_line_sdata[41], PF1, 1 -instance = comp, \signal_high_voltage[41]~reg0 , signal_high_voltage[41]~reg0, PF1, 1 -instance = comp, \Decoder0~125 , Decoder0~125, PF1, 1 -instance = comp, \cache_line_sdata[42] , cache_line_sdata[42], PF1, 1 -instance = comp, \cache2_line_sdata[42] , cache2_line_sdata[42], PF1, 1 -instance = comp, \signal_high_voltage[42]~reg0 , signal_high_voltage[42]~reg0, PF1, 1 -instance = comp, \Decoder0~126 , Decoder0~126, PF1, 1 -instance = comp, \cache_line_sdata[43] , cache_line_sdata[43], PF1, 1 -instance = comp, \cache2_line_sdata[43] , cache2_line_sdata[43], PF1, 1 -instance = comp, \signal_high_voltage[43]~reg0 , signal_high_voltage[43]~reg0, PF1, 1 -instance = comp, \Decoder0~97 , Decoder0~97, PF1, 1 -instance = comp, \cache_line_sdata[44] , cache_line_sdata[44], PF1, 1 -instance = comp, \cache2_line_sdata[44] , cache2_line_sdata[44], PF1, 1 -instance = comp, \signal_high_voltage[44]~reg0 , signal_high_voltage[44]~reg0, PF1, 1 -instance = comp, \Decoder0~98 , Decoder0~98, PF1, 1 -instance = comp, \cache_line_sdata[45] , cache_line_sdata[45], PF1, 1 -instance = comp, \cache2_line_sdata[45] , cache2_line_sdata[45], PF1, 1 -instance = comp, \signal_high_voltage[45]~reg0 , signal_high_voltage[45]~reg0, PF1, 1 -instance = comp, \Decoder0~99 , Decoder0~99, PF1, 1 -instance = comp, \cache_line_sdata[46] , cache_line_sdata[46], PF1, 1 -instance = comp, \cache2_line_sdata[46] , cache2_line_sdata[46], PF1, 1 -instance = comp, \signal_high_voltage[46]~reg0 , signal_high_voltage[46]~reg0, PF1, 1 -instance = comp, \Decoder0~100 , Decoder0~100, PF1, 1 -instance = comp, \cache_line_sdata[47] , cache_line_sdata[47], PF1, 1 -instance = comp, \cache2_line_sdata[47] , cache2_line_sdata[47], PF1, 1 -instance = comp, \signal_high_voltage[47]~reg0 , signal_high_voltage[47]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[0]~reg0 , signal_low_voltage[0]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[1]~reg0 , signal_low_voltage[1]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[2]~reg0 , signal_low_voltage[2]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[3]~reg0 , signal_low_voltage[3]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[4]~reg0 , signal_low_voltage[4]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[5]~reg0 , signal_low_voltage[5]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[6]~reg0 , signal_low_voltage[6]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[7]~reg0 , signal_low_voltage[7]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[8]~reg0 , signal_low_voltage[8]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[9]~reg0 , signal_low_voltage[9]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[10]~reg0 , signal_low_voltage[10]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[11]~reg0 , signal_low_voltage[11]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[12]~reg0 , signal_low_voltage[12]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[13]~reg0 , signal_low_voltage[13]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[14]~reg0 , signal_low_voltage[14]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[15]~reg0 , signal_low_voltage[15]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[16]~reg0 , signal_low_voltage[16]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[17]~reg0 , signal_low_voltage[17]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[18]~reg0 , signal_low_voltage[18]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[19]~reg0 , signal_low_voltage[19]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[20]~reg0 , signal_low_voltage[20]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[21]~reg0 , signal_low_voltage[21]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[22]~reg0 , signal_low_voltage[22]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[23]~reg0 , signal_low_voltage[23]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[24]~reg0 , signal_low_voltage[24]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[25]~reg0 , signal_low_voltage[25]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[26]~reg0 , signal_low_voltage[26]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[27]~reg0 , signal_low_voltage[27]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[28]~reg0 , signal_low_voltage[28]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[29]~reg0 , signal_low_voltage[29]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[30]~reg0 , signal_low_voltage[30]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[31]~reg0 , signal_low_voltage[31]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[32]~reg0 , signal_low_voltage[32]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[33]~reg0 , signal_low_voltage[33]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[34]~reg0 , signal_low_voltage[34]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[35]~reg0 , signal_low_voltage[35]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[36]~reg0 , signal_low_voltage[36]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[37]~reg0 , signal_low_voltage[37]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[38]~reg0 , signal_low_voltage[38]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[39]~reg0 , signal_low_voltage[39]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[40]~reg0 , signal_low_voltage[40]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[41]~reg0 , signal_low_voltage[41]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[42]~reg0 , signal_low_voltage[42]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[43]~reg0 , signal_low_voltage[43]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[44]~reg0 , signal_low_voltage[44]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[45]~reg0 , signal_low_voltage[45]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[46]~reg0 , signal_low_voltage[46]~reg0, PF1, 1 -instance = comp, \signal_low_voltage[47]~reg0 , signal_low_voltage[47]~reg0, PF1, 1 -instance = comp, \signal_high_voltage[0]~I , signal_high_voltage[0], PF1, 1 -instance = comp, \signal_high_voltage[1]~I , signal_high_voltage[1], PF1, 1 -instance = comp, \signal_high_voltage[2]~I , signal_high_voltage[2], PF1, 1 -instance = comp, \signal_high_voltage[3]~I , signal_high_voltage[3], PF1, 1 -instance = comp, \signal_high_voltage[4]~I , signal_high_voltage[4], PF1, 1 -instance = comp, \signal_high_voltage[5]~I , signal_high_voltage[5], PF1, 1 -instance = comp, \signal_high_voltage[6]~I , signal_high_voltage[6], PF1, 1 -instance = comp, \signal_high_voltage[7]~I , signal_high_voltage[7], PF1, 1 -instance = comp, \signal_high_voltage[8]~I , signal_high_voltage[8], PF1, 1 -instance = comp, \signal_high_voltage[9]~I , signal_high_voltage[9], PF1, 1 -instance = comp, \signal_high_voltage[10]~I , signal_high_voltage[10], PF1, 1 -instance = comp, \signal_high_voltage[11]~I , signal_high_voltage[11], PF1, 1 -instance = comp, \signal_high_voltage[12]~I , signal_high_voltage[12], PF1, 1 -instance = comp, \signal_high_voltage[13]~I , signal_high_voltage[13], PF1, 1 -instance = comp, \signal_high_voltage[14]~I , signal_high_voltage[14], PF1, 1 -instance = comp, \signal_high_voltage[15]~I , signal_high_voltage[15], PF1, 1 -instance = comp, \signal_high_voltage[16]~I , signal_high_voltage[16], PF1, 1 -instance = comp, \signal_high_voltage[17]~I , signal_high_voltage[17], PF1, 1 -instance = comp, \signal_high_voltage[18]~I , signal_high_voltage[18], PF1, 1 -instance = comp, \signal_high_voltage[19]~I , signal_high_voltage[19], PF1, 1 -instance = comp, \signal_high_voltage[20]~I , signal_high_voltage[20], PF1, 1 -instance = comp, \signal_high_voltage[21]~I , signal_high_voltage[21], PF1, 1 -instance = comp, \signal_high_voltage[22]~I , signal_high_voltage[22], PF1, 1 -instance = comp, \signal_high_voltage[23]~I , signal_high_voltage[23], PF1, 1 -instance = comp, \signal_high_voltage[24]~I , signal_high_voltage[24], PF1, 1 -instance = comp, \signal_high_voltage[25]~I , signal_high_voltage[25], PF1, 1 -instance = comp, \signal_high_voltage[26]~I , signal_high_voltage[26], PF1, 1 -instance = comp, \signal_high_voltage[27]~I , signal_high_voltage[27], PF1, 1 -instance = comp, \signal_high_voltage[28]~I , signal_high_voltage[28], PF1, 1 -instance = comp, \signal_high_voltage[29]~I , signal_high_voltage[29], PF1, 1 -instance = comp, \signal_high_voltage[30]~I , signal_high_voltage[30], PF1, 1 -instance = comp, \signal_high_voltage[31]~I , signal_high_voltage[31], PF1, 1 -instance = comp, \signal_high_voltage[32]~I , signal_high_voltage[32], PF1, 1 -instance = comp, \signal_high_voltage[33]~I , signal_high_voltage[33], PF1, 1 -instance = comp, \signal_high_voltage[34]~I , signal_high_voltage[34], PF1, 1 -instance = comp, \signal_high_voltage[35]~I , signal_high_voltage[35], PF1, 1 -instance = comp, \signal_high_voltage[36]~I , signal_high_voltage[36], PF1, 1 -instance = comp, \signal_high_voltage[37]~I , signal_high_voltage[37], PF1, 1 -instance = comp, \signal_high_voltage[38]~I , signal_high_voltage[38], PF1, 1 -instance = comp, \signal_high_voltage[39]~I , signal_high_voltage[39], PF1, 1 -instance = comp, \signal_high_voltage[40]~I , signal_high_voltage[40], PF1, 1 -instance = comp, \signal_high_voltage[41]~I , signal_high_voltage[41], PF1, 1 -instance = comp, \signal_high_voltage[42]~I , signal_high_voltage[42], PF1, 1 -instance = comp, \signal_high_voltage[43]~I , signal_high_voltage[43], PF1, 1 -instance = comp, \signal_high_voltage[44]~I , signal_high_voltage[44], PF1, 1 -instance = comp, \signal_high_voltage[45]~I , signal_high_voltage[45], PF1, 1 -instance = comp, \signal_high_voltage[46]~I , signal_high_voltage[46], PF1, 1 -instance = comp, \signal_high_voltage[47]~I , signal_high_voltage[47], PF1, 1 -instance = comp, \signal_low_voltage[0]~I , signal_low_voltage[0], PF1, 1 -instance = comp, \signal_low_voltage[1]~I , signal_low_voltage[1], PF1, 1 -instance = comp, \signal_low_voltage[2]~I , signal_low_voltage[2], PF1, 1 -instance = comp, \signal_low_voltage[3]~I , signal_low_voltage[3], PF1, 1 -instance = comp, \signal_low_voltage[4]~I , signal_low_voltage[4], PF1, 1 -instance = comp, \signal_low_voltage[5]~I , signal_low_voltage[5], PF1, 1 -instance = comp, \signal_low_voltage[6]~I , signal_low_voltage[6], PF1, 1 -instance = comp, \signal_low_voltage[7]~I , signal_low_voltage[7], PF1, 1 -instance = comp, \signal_low_voltage[8]~I , signal_low_voltage[8], PF1, 1 -instance = comp, \signal_low_voltage[9]~I , signal_low_voltage[9], PF1, 1 -instance = comp, \signal_low_voltage[10]~I , signal_low_voltage[10], PF1, 1 -instance = comp, \signal_low_voltage[11]~I , signal_low_voltage[11], PF1, 1 -instance = comp, \signal_low_voltage[12]~I , signal_low_voltage[12], PF1, 1 -instance = comp, \signal_low_voltage[13]~I , signal_low_voltage[13], PF1, 1 -instance = comp, \signal_low_voltage[14]~I , signal_low_voltage[14], PF1, 1 -instance = comp, \signal_low_voltage[15]~I , signal_low_voltage[15], PF1, 1 -instance = comp, \signal_low_voltage[16]~I , signal_low_voltage[16], PF1, 1 -instance = comp, \signal_low_voltage[17]~I , signal_low_voltage[17], PF1, 1 -instance = comp, \signal_low_voltage[18]~I , signal_low_voltage[18], PF1, 1 -instance = comp, \signal_low_voltage[19]~I , signal_low_voltage[19], PF1, 1 -instance = comp, \signal_low_voltage[20]~I , signal_low_voltage[20], PF1, 1 -instance = comp, \signal_low_voltage[21]~I , signal_low_voltage[21], PF1, 1 -instance = comp, \signal_low_voltage[22]~I , signal_low_voltage[22], PF1, 1 -instance = comp, \signal_low_voltage[23]~I , signal_low_voltage[23], PF1, 1 -instance = comp, \signal_low_voltage[24]~I , signal_low_voltage[24], PF1, 1 -instance = comp, \signal_low_voltage[25]~I , signal_low_voltage[25], PF1, 1 -instance = comp, \signal_low_voltage[26]~I , signal_low_voltage[26], PF1, 1 -instance = comp, \signal_low_voltage[27]~I , signal_low_voltage[27], PF1, 1 -instance = comp, \signal_low_voltage[28]~I , signal_low_voltage[28], PF1, 1 -instance = comp, \signal_low_voltage[29]~I , signal_low_voltage[29], PF1, 1 -instance = comp, \signal_low_voltage[30]~I , signal_low_voltage[30], PF1, 1 -instance = comp, \signal_low_voltage[31]~I , signal_low_voltage[31], PF1, 1 -instance = comp, \signal_low_voltage[32]~I , signal_low_voltage[32], PF1, 1 -instance = comp, \signal_low_voltage[33]~I , signal_low_voltage[33], PF1, 1 -instance = comp, \signal_low_voltage[34]~I , signal_low_voltage[34], PF1, 1 -instance = comp, \signal_low_voltage[35]~I , signal_low_voltage[35], PF1, 1 -instance = comp, \signal_low_voltage[36]~I , signal_low_voltage[36], PF1, 1 -instance = comp, \signal_low_voltage[37]~I , signal_low_voltage[37], PF1, 1 -instance = comp, \signal_low_voltage[38]~I , signal_low_voltage[38], PF1, 1 -instance = comp, \signal_low_voltage[39]~I , signal_low_voltage[39], PF1, 1 -instance = comp, \signal_low_voltage[40]~I , signal_low_voltage[40], PF1, 1 -instance = comp, \signal_low_voltage[41]~I , signal_low_voltage[41], PF1, 1 -instance = comp, \signal_low_voltage[42]~I , signal_low_voltage[42], PF1, 1 -instance = comp, \signal_low_voltage[43]~I , signal_low_voltage[43], PF1, 1 -instance = comp, \signal_low_voltage[44]~I , signal_low_voltage[44], PF1, 1 -instance = comp, \signal_low_voltage[45]~I , signal_low_voltage[45], PF1, 1 -instance = comp, \signal_low_voltage[46]~I , signal_low_voltage[46], PF1, 1 -instance = comp, \signal_low_voltage[47]~I , signal_low_voltage[47], PF1, 1 diff --git a/firmware/simulation/modelsim/PF1_run_msim_gate_verilog.do b/firmware/simulation/modelsim/PF1_run_msim_gate_verilog.do deleted file mode 100644 index ea82fd6..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_gate_verilog.do +++ /dev/null @@ -1,17 +0,0 @@ -transcript on -if {[file exists gate_work]} { - vdel -lib gate_work -all -} -vlib gate_work -vmap work gate_work - -vlog -vlog01compat -work work +incdir+. {PF1.vo} - -vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v} - -vsim -t 1ps +transport_int_delays +transport_path_delays -L maxii_ver -L gate_work -L work -voptargs="+acc" tb_PF1 - -add wave * -view structure -view signals -run 5 ms diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do deleted file mode 100644 index 291b877..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do +++ /dev/null @@ -1,17 +0,0 @@ -transcript on -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/PF1.v} - -vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v} - -vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_PF1 - -add wave * -view structure -view signals -run 5 ms diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak deleted file mode 100644 index 0444f4f..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak +++ /dev/null @@ -1,9 +0,0 @@ -transcript on -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+D:/quartusworkplace/PF_DS0401/PF_DS {D:/quartusworkplace/PF_DS0401/PF_DS/PF1.v} - diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak1 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak1 deleted file mode 100644 index 0444f4f..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak1 +++ /dev/null @@ -1,9 +0,0 @@ -transcript on -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+D:/quartusworkplace/PF_DS0401/PF_DS {D:/quartusworkplace/PF_DS0401/PF_DS/PF1.v} - diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak10 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak10 deleted file mode 100644 index 8615eaa..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak10 +++ /dev/null @@ -1,45 +0,0 @@ -transcript on -if ![file isdirectory verilog_libs] { - file mkdir verilog_libs -} - -vlib verilog_libs/altera_ver -vmap altera_ver ./verilog_libs/altera_ver -vlog -vlog01compat -work altera_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_primitives.v} - -vlib verilog_libs/lpm_ver -vmap lpm_ver ./verilog_libs/lpm_ver -vlog -vlog01compat -work lpm_ver {d:/altera/11.0/quartus/eda/sim_lib/220model.v} - -vlib verilog_libs/sgate_ver -vmap sgate_ver ./verilog_libs/sgate_ver -vlog -vlog01compat -work sgate_ver {d:/altera/11.0/quartus/eda/sim_lib/sgate.v} - -vlib verilog_libs/altera_mf_ver -vmap altera_mf_ver ./verilog_libs/altera_mf_ver -vlog -vlog01compat -work altera_mf_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v} - -vlib verilog_libs/altera_lnsim_ver -vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver -vlog -sv -work altera_lnsim_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv} - -vlib verilog_libs/maxii_ver -vmap maxii_ver ./verilog_libs/maxii_ver -vlog -vlog01compat -work maxii_ver {d:/altera/11.0/quartus/eda/sim_lib/maxii_atoms.v} - -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/PF1.v} - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS/simulation/modelsim {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/simulation/modelsim/PF1.vt} - -vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" PF1_vlg_tst - -add wave * -view structure -view signals -run -all diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak11 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak11 deleted file mode 100644 index 291b877..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak11 +++ /dev/null @@ -1,17 +0,0 @@ -transcript on -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/PF1.v} - -vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v} - -vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_PF1 - -add wave * -view structure -view signals -run 5 ms diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak2 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak2 deleted file mode 100644 index 0444f4f..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak2 +++ /dev/null @@ -1,9 +0,0 @@ -transcript on -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+D:/quartusworkplace/PF_DS0401/PF_DS {D:/quartusworkplace/PF_DS0401/PF_DS/PF1.v} - diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak3 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak3 deleted file mode 100644 index 0444f4f..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak3 +++ /dev/null @@ -1,9 +0,0 @@ -transcript on -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+D:/quartusworkplace/PF_DS0401/PF_DS {D:/quartusworkplace/PF_DS0401/PF_DS/PF1.v} - diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak4 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak4 deleted file mode 100644 index e0f8621..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak4 +++ /dev/null @@ -1,37 +0,0 @@ -transcript on -if ![file isdirectory verilog_libs] { - file mkdir verilog_libs -} - -vlib verilog_libs/altera_ver -vmap altera_ver ./verilog_libs/altera_ver -vlog -vlog01compat -work altera_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_primitives.v} - -vlib verilog_libs/lpm_ver -vmap lpm_ver ./verilog_libs/lpm_ver -vlog -vlog01compat -work lpm_ver {d:/altera/11.0/quartus/eda/sim_lib/220model.v} - -vlib verilog_libs/sgate_ver -vmap sgate_ver ./verilog_libs/sgate_ver -vlog -vlog01compat -work sgate_ver {d:/altera/11.0/quartus/eda/sim_lib/sgate.v} - -vlib verilog_libs/altera_mf_ver -vmap altera_mf_ver ./verilog_libs/altera_mf_ver -vlog -vlog01compat -work altera_mf_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v} - -vlib verilog_libs/altera_lnsim_ver -vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver -vlog -sv -work altera_lnsim_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv} - -vlib verilog_libs/maxii_ver -vmap maxii_ver ./verilog_libs/maxii_ver -vlog -vlog01compat -work maxii_ver {d:/altera/11.0/quartus/eda/sim_lib/maxii_atoms.v} - -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/PF1.v} - diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak5 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak5 deleted file mode 100644 index e0f8621..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak5 +++ /dev/null @@ -1,37 +0,0 @@ -transcript on -if ![file isdirectory verilog_libs] { - file mkdir verilog_libs -} - -vlib verilog_libs/altera_ver -vmap altera_ver ./verilog_libs/altera_ver -vlog -vlog01compat -work altera_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_primitives.v} - -vlib verilog_libs/lpm_ver -vmap lpm_ver ./verilog_libs/lpm_ver -vlog -vlog01compat -work lpm_ver {d:/altera/11.0/quartus/eda/sim_lib/220model.v} - -vlib verilog_libs/sgate_ver -vmap sgate_ver ./verilog_libs/sgate_ver -vlog -vlog01compat -work sgate_ver {d:/altera/11.0/quartus/eda/sim_lib/sgate.v} - -vlib verilog_libs/altera_mf_ver -vmap altera_mf_ver ./verilog_libs/altera_mf_ver -vlog -vlog01compat -work altera_mf_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v} - -vlib verilog_libs/altera_lnsim_ver -vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver -vlog -sv -work altera_lnsim_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv} - -vlib verilog_libs/maxii_ver -vmap maxii_ver ./verilog_libs/maxii_ver -vlog -vlog01compat -work maxii_ver {d:/altera/11.0/quartus/eda/sim_lib/maxii_atoms.v} - -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/PF1.v} - diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak6 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak6 deleted file mode 100644 index 8615eaa..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak6 +++ /dev/null @@ -1,45 +0,0 @@ -transcript on -if ![file isdirectory verilog_libs] { - file mkdir verilog_libs -} - -vlib verilog_libs/altera_ver -vmap altera_ver ./verilog_libs/altera_ver -vlog -vlog01compat -work altera_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_primitives.v} - -vlib verilog_libs/lpm_ver -vmap lpm_ver ./verilog_libs/lpm_ver -vlog -vlog01compat -work lpm_ver {d:/altera/11.0/quartus/eda/sim_lib/220model.v} - -vlib verilog_libs/sgate_ver -vmap sgate_ver ./verilog_libs/sgate_ver -vlog -vlog01compat -work sgate_ver {d:/altera/11.0/quartus/eda/sim_lib/sgate.v} - -vlib verilog_libs/altera_mf_ver -vmap altera_mf_ver ./verilog_libs/altera_mf_ver -vlog -vlog01compat -work altera_mf_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v} - -vlib verilog_libs/altera_lnsim_ver -vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver -vlog -sv -work altera_lnsim_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv} - -vlib verilog_libs/maxii_ver -vmap maxii_ver ./verilog_libs/maxii_ver -vlog -vlog01compat -work maxii_ver {d:/altera/11.0/quartus/eda/sim_lib/maxii_atoms.v} - -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/PF1.v} - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS/simulation/modelsim {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/simulation/modelsim/PF1.vt} - -vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" PF1_vlg_tst - -add wave * -view structure -view signals -run -all diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak7 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak7 deleted file mode 100644 index 8615eaa..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak7 +++ /dev/null @@ -1,45 +0,0 @@ -transcript on -if ![file isdirectory verilog_libs] { - file mkdir verilog_libs -} - -vlib verilog_libs/altera_ver -vmap altera_ver ./verilog_libs/altera_ver -vlog -vlog01compat -work altera_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_primitives.v} - -vlib verilog_libs/lpm_ver -vmap lpm_ver ./verilog_libs/lpm_ver -vlog -vlog01compat -work lpm_ver {d:/altera/11.0/quartus/eda/sim_lib/220model.v} - -vlib verilog_libs/sgate_ver -vmap sgate_ver ./verilog_libs/sgate_ver -vlog -vlog01compat -work sgate_ver {d:/altera/11.0/quartus/eda/sim_lib/sgate.v} - -vlib verilog_libs/altera_mf_ver -vmap altera_mf_ver ./verilog_libs/altera_mf_ver -vlog -vlog01compat -work altera_mf_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v} - -vlib verilog_libs/altera_lnsim_ver -vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver -vlog -sv -work altera_lnsim_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv} - -vlib verilog_libs/maxii_ver -vmap maxii_ver ./verilog_libs/maxii_ver -vlog -vlog01compat -work maxii_ver {d:/altera/11.0/quartus/eda/sim_lib/maxii_atoms.v} - -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/PF1.v} - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS/simulation/modelsim {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/simulation/modelsim/PF1.vt} - -vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" PF1_vlg_tst - -add wave * -view structure -view signals -run -all diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak8 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak8 deleted file mode 100644 index 8615eaa..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak8 +++ /dev/null @@ -1,45 +0,0 @@ -transcript on -if ![file isdirectory verilog_libs] { - file mkdir verilog_libs -} - -vlib verilog_libs/altera_ver -vmap altera_ver ./verilog_libs/altera_ver -vlog -vlog01compat -work altera_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_primitives.v} - -vlib verilog_libs/lpm_ver -vmap lpm_ver ./verilog_libs/lpm_ver -vlog -vlog01compat -work lpm_ver {d:/altera/11.0/quartus/eda/sim_lib/220model.v} - -vlib verilog_libs/sgate_ver -vmap sgate_ver ./verilog_libs/sgate_ver -vlog -vlog01compat -work sgate_ver {d:/altera/11.0/quartus/eda/sim_lib/sgate.v} - -vlib verilog_libs/altera_mf_ver -vmap altera_mf_ver ./verilog_libs/altera_mf_ver -vlog -vlog01compat -work altera_mf_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v} - -vlib verilog_libs/altera_lnsim_ver -vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver -vlog -sv -work altera_lnsim_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv} - -vlib verilog_libs/maxii_ver -vmap maxii_ver ./verilog_libs/maxii_ver -vlog -vlog01compat -work maxii_ver {d:/altera/11.0/quartus/eda/sim_lib/maxii_atoms.v} - -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/PF1.v} - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS/simulation/modelsim {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/simulation/modelsim/PF1.vt} - -vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" PF1_vlg_tst - -add wave * -view structure -view signals -run -all diff --git a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak9 b/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak9 deleted file mode 100644 index 8615eaa..0000000 --- a/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak9 +++ /dev/null @@ -1,45 +0,0 @@ -transcript on -if ![file isdirectory verilog_libs] { - file mkdir verilog_libs -} - -vlib verilog_libs/altera_ver -vmap altera_ver ./verilog_libs/altera_ver -vlog -vlog01compat -work altera_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_primitives.v} - -vlib verilog_libs/lpm_ver -vmap lpm_ver ./verilog_libs/lpm_ver -vlog -vlog01compat -work lpm_ver {d:/altera/11.0/quartus/eda/sim_lib/220model.v} - -vlib verilog_libs/sgate_ver -vmap sgate_ver ./verilog_libs/sgate_ver -vlog -vlog01compat -work sgate_ver {d:/altera/11.0/quartus/eda/sim_lib/sgate.v} - -vlib verilog_libs/altera_mf_ver -vmap altera_mf_ver ./verilog_libs/altera_mf_ver -vlog -vlog01compat -work altera_mf_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v} - -vlib verilog_libs/altera_lnsim_ver -vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver -vlog -sv -work altera_lnsim_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv} - -vlib verilog_libs/maxii_ver -vmap maxii_ver ./verilog_libs/maxii_ver -vlog -vlog01compat -work maxii_ver {d:/altera/11.0/quartus/eda/sim_lib/maxii_atoms.v} - -if {[file exists rtl_work]} { - vdel -lib rtl_work -all -} -vlib rtl_work -vmap work rtl_work - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/PF1.v} - -vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS/simulation/modelsim {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/simulation/modelsim/PF1.vt} - -vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" PF1_vlg_tst - -add wave * -view structure -view signals -run -all diff --git a/firmware/simulation/modelsim/PF1_v.sdo b/firmware/simulation/modelsim/PF1_v.sdo deleted file mode 100644 index 02c2e91..0000000 --- a/firmware/simulation/modelsim/PF1_v.sdo +++ /dev/null @@ -1,13729 +0,0 @@ -// Copyright (C) 2020 Intel Corporation. All rights reserved. -// Your use of Intel Corporation's design tools, logic functions -// and other software and tools, and any partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Intel Program License -// Subscription Agreement, the Intel Quartus Prime License Agreement, -// the Intel FPGA IP License Agreement, or other applicable license -// agreement, including, without limitation, that your use is for -// the sole purpose of programming logic devices manufactured by -// Intel and sold by Intel or its authorized distributors. Please -// refer to the applicable agreement for further details, at -// https://fpgasoftware.intel.com/eula. - - -// -// Device: Altera EPM1270T144C5 Package TQFP144 -// - -// -// This SDF file should be used for ModelSim-Altera (Verilog) only -// - -(DELAYFILE - (SDFVERSION "2.1") - (DESIGN "PF1") - (DATE "11/11/2021 17:04:11") - (VENDOR "Altera") - (PROGRAM "Quartus Prime") - (VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition") - (DIVIDER .) - (TIMESCALE 1 ps) - - (CELL - (CELLTYPE "maxii_io") - (INSTANCE sys_clk\~I) - (DELAY - (ABSOLUTE - (IOPATH padio combout (1163:1163:1163) (1163:1163:1163)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE rst_n\~I) - (DELAY - (ABSOLUTE - (IOPATH padio combout (1132:1132:1132) (1132:1132:1132)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE line_sclk\~I) - (DELAY - (ABSOLUTE - (IOPATH padio combout (1132:1132:1132) (1132:1132:1132)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sclk\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4542:4542:4542) (4542:4542:4542)) - (PORT datac (4612:4612:4612) (4612:4612:4612)) - (PORT datad (1181:1181:1181) (1181:1181:1181)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datad combout (200:200:200) (200:200:200)) - (IOPATH qfbkin combout (595:595:595) (595:595:595)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sclk\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT datac (4892:4892:4892) (4892:4892:4892)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - (IOPATH (posedge clk) qfbkout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) qfbkout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sclk\[1\].lecomb) - (DELAY - (ABSOLUTE - (PORT datad (1291:1291:1291) (1291:1291:1291)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sclk\[1\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sclk\[2\].lecomb) - (DELAY - (ABSOLUTE - (PORT datac (969:969:969) (969:969:969)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sclk\[2\].lereg) - (DELAY - (ABSOLUTE - (PORT datac (1249:1249:1249) (1249:1249:1249)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sclk\[3\].lecomb) - (DELAY - (ABSOLUTE - (PORT datad (915:915:915) (915:915:915)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sclk\[3\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sclk\[4\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (904:904:904)) - (PORT datab (929:929:929) (929:929:929)) - (PORT datac (971:971:971) (971:971:971)) - (PORT datad (920:920:920) (920:920:920)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datad combout (200:200:200) (200:200:200)) - (IOPATH qfbkin combout (595:595:595) (595:595:595)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sclk\[4\].lereg) - (DELAY - (ABSOLUTE - (PORT datac (1251:1251:1251) (1251:1251:1251)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) qfbkout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) qfbkout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1332:1332:1332) (1332:1332:1332)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datab cout (954:954:954) (954:954:954)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (2845:2845:2845) (2845:2845:2845)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2353:2353:2353) (2353:2353:2353)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[1\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (936:936:936)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[1\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (2845:2845:2845) (2845:2845:2845)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2353:2353:2353) (2353:2353:2353)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[2\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (921:921:921) (921:921:921)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[2\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (2845:2845:2845) (2845:2845:2845)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2353:2353:2353) (2353:2353:2353)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[3\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[3\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (2845:2845:2845) (2845:2845:2845)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2353:2353:2353) (2353:2353:2353)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[4\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (884:884:884)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[4\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (2845:2845:2845) (2845:2845:2845)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2353:2353:2353) (2353:2353:2353)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[5\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (891:891:891) (891:891:891)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout (1099:1099:1099) (1099:1099:1099)) - (IOPATH cin cout (349:349:349) (349:349:349)) - (IOPATH cin0 cout (399:399:399) (399:399:399)) - (IOPATH cin1 cout (387:387:387) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[5\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (2845:2845:2845) (2845:2845:2845)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2353:2353:2353) (2353:2353:2353)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[6\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (900:900:900) (900:900:900)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[6\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[7\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[7\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[8\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[8\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[9\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[9\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[10\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (893:893:893)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout (1077:1077:1077) (1077:1077:1077)) - (IOPATH cin cout (246:246:246) (246:246:246)) - (IOPATH cin0 cout (261:261:261) (261:261:261)) - (IOPATH cin1 cout (252:252:252) (252:252:252)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[10\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[11\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (892:892:892)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[11\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[12\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (893:893:893)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[12\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[13\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (901:901:901) (901:901:901)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[13\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[14\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[14\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[15\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout (1099:1099:1099) (1099:1099:1099)) - (IOPATH cin cout (349:349:349) (349:349:349)) - (IOPATH cin0 cout (399:399:399) (399:399:399)) - (IOPATH cin1 cout (387:387:387) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[15\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3458:3458:3458) (3458:3458:3458)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3067:3067:3067) (3067:3067:3067)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[16\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (909:909:909) (909:909:909)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[16\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[17\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[17\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[18\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[18\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[19\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[19\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[20\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (893:893:893)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout (1077:1077:1077) (1077:1077:1077)) - (IOPATH cin cout (246:246:246) (246:246:246)) - (IOPATH cin0 cout (261:261:261) (261:261:261)) - (IOPATH cin1 cout (252:252:252) (252:252:252)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[20\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[21\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (892:892:892)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[21\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[22\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (893:893:893)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[22\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[23\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (911:911:911) (911:911:911)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[23\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[24\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[24\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[25\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout (1099:1099:1099) (1099:1099:1099)) - (IOPATH cin cout (349:349:349) (349:349:349)) - (IOPATH cin0 cout (399:399:399) (399:399:399)) - (IOPATH cin1 cout (387:387:387) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[25\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3469:3469:3469) (3469:3469:3469)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3113:3113:3113) (3113:3113:3113)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[26\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (918:918:918)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[26\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3477:3477:3477) (3477:3477:3477)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3117:3117:3117) (3117:3117:3117)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[27\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (928:928:928) (928:928:928)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[27\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3477:3477:3477) (3477:3477:3477)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3117:3117:3117) (3117:3117:3117)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[28\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (927:927:927) (927:927:927)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[28\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3477:3477:3477) (3477:3477:3477)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3117:3117:3117) (3117:3117:3117)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[29\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (895:895:895) (895:895:895)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[29\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3477:3477:3477) (3477:3477:3477)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3117:3117:3117) (3117:3117:3117)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[30\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (893:893:893)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout (1077:1077:1077) (1077:1077:1077)) - (IOPATH cin cout (246:246:246) (246:246:246)) - (IOPATH cin0 cout (261:261:261) (261:261:261)) - (IOPATH cin1 cout (252:252:252) (252:252:252)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[30\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3477:3477:3477) (3477:3477:3477)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3117:3117:3117) (3117:3117:3117)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[31\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (901:901:901) (901:901:901)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_counter\[31\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (3477:3477:3477) (3477:3477:3477)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3117:3117:3117) (3117:3117:3117)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[26\]\~60.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1244:1244:1244) (1244:1244:1244)) - (PORT datab (935:935:935) (935:935:935)) - (PORT datac (977:977:977) (977:977:977)) - (PORT datad (938:938:938) (938:938:938)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[26\]\~67.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (899:899:899) (899:899:899)) - (PORT datab (1262:1262:1262) (1262:1262:1262)) - (PORT datac (975:975:975) (975:975:975)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~7.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2005:2005:2005) (2005:2005:2005)) - (PORT datac (2007:2007:2007) (2007:2007:2007)) - (PORT datad (1992:1992:1992) (1992:1992:1992)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~8.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2070:2070:2070) (2070:2070:2070)) - (PORT datac (2105:2105:2105) (2105:2105:2105)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~9.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1939:1939:1939) (1939:1939:1939)) - (PORT datab (1986:1986:1986) (1986:1986:1986)) - (PORT datac (2643:2643:2643) (2643:2643:2643)) - (PORT datad (729:729:729) (729:729:729)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~6.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1826:1826:1826) (1826:1826:1826)) - (PORT datab (1948:1948:1948) (1948:1948:1948)) - (PORT datac (1961:1961:1961) (1961:1961:1961)) - (PORT datad (1858:1858:1858) (1858:1858:1858)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~2.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1337:1337:1337) (1337:1337:1337)) - (PORT datac (1412:1412:1412) (1412:1412:1412)) - (PORT datad (1322:1322:1322) (1322:1322:1322)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~4.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1317:1317:1317) (1317:1317:1317)) - (PORT datab (1330:1330:1330) (1330:1330:1330)) - (PORT datac (1403:1403:1403) (1403:1403:1403)) - (PORT datad (1321:1321:1321) (1321:1321:1321)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~3.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (949:949:949) (949:949:949)) - (PORT datab (1335:1335:1335) (1335:1335:1335)) - (PORT datac (1412:1412:1412) (1412:1412:1412)) - (PORT datad (1919:1919:1919) (1919:1919:1919)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~5.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2043:2043:2043) (2043:2043:2043)) - (PORT datab (1902:1902:1902) (1902:1902:1902)) - (PORT datac (769:769:769) (769:769:769)) - (PORT datad (1173:1173:1173) (1173:1173:1173)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~0.lecomb) - (DELAY - (ABSOLUTE - (PORT datac (1332:1332:1332) (1332:1332:1332)) - (PORT datad (1305:1305:1305) (1305:1305:1305)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~1.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2569:2569:2569) (2569:2569:2569)) - (PORT datab (1979:1979:1979) (1979:1979:1979)) - (PORT datac (1200:1200:1200) (1200:1200:1200)) - (PORT datad (732:732:732) (732:732:732)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE LessThan2\~7.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1125:1125:1125) (1125:1125:1125)) - (PORT datab (1153:1153:1153) (1153:1153:1153)) - (PORT datac (765:765:765) (765:765:765)) - (PORT datad (730:730:730) (730:730:730)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[26\]\~68.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2016:2016:2016) (2016:2016:2016)) - (PORT datab (1810:1810:1810) (1810:1810:1810)) - (PORT datac (761:761:761) (761:761:761)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_counter\[26\]\~69.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1172:1172:1172) (1172:1172:1172)) - (PORT datab (918:918:918) (918:918:918)) - (PORT datac (4619:4619:4619) (4619:4619:4619)) - (PORT datad (729:729:729) (729:729:729)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~10.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3322:3322:3322) (3322:3322:3322)) - (PORT datac (2743:2743:2743) (2743:2743:2743)) - (PORT datad (2699:2699:2699) (2699:2699:2699)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~6.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2039:2039:2039) (2039:2039:2039)) - (PORT datab (3512:3512:3512) (3512:3512:3512)) - (PORT datac (2909:2909:2909) (2909:2909:2909)) - (PORT datad (2703:2703:2703) (2703:2703:2703)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~2.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1923:1923:1923) (1923:1923:1923)) - (PORT datab (2130:2130:2130) (2130:2130:2130)) - (PORT datac (2114:2114:2114) (2114:2114:2114)) - (PORT datad (2702:2702:2702) (2702:2702:2702)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~3.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (950:950:950) (950:950:950)) - (PORT datab (918:918:918) (918:918:918)) - (PORT datac (998:998:998) (998:998:998)) - (PORT datad (1335:1335:1335) (1335:1335:1335)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~4.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1985:1985:1985) (1985:1985:1985)) - (PORT datab (2668:2668:2668) (2668:2668:2668)) - (PORT datac (2016:2016:2016) (2016:2016:2016)) - (PORT datad (3667:3667:3667) (3667:3667:3667)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~5.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1839:1839:1839) (1839:1839:1839)) - (PORT datab (2124:2124:2124) (2124:2124:2124)) - (PORT datac (2650:2650:2650) (2650:2650:2650)) - (PORT datad (724:724:724) (724:724:724)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~8.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1824:1824:1824) (1824:1824:1824)) - (PORT datab (732:732:732) (732:732:732)) - (PORT datac (776:776:776) (776:776:776)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~9.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2684:2684:2684) (2684:2684:2684)) - (PORT datab (2730:2730:2730) (2730:2730:2730)) - (PORT datac (2678:2678:2678) (2678:2678:2678)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\[1\]\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (694:694:694) (694:694:694)) - (PORT datab (3058:3058:3058) (3058:3058:3058)) - (PORT datac (2898:2898:2898) (2898:2898:2898)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_flag\[1\]\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE line_sen\~I) - (DELAY - (ABSOLUTE - (IOPATH padio combout (1132:1132:1132) (1132:1132:1132)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sen\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (5251:5251:5251) (5251:5251:5251)) - (PORT datac (5298:5298:5298) (5298:5298:5298)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datad combout (200:200:200) (200:200:200)) - (IOPATH qfbkin combout (595:595:595) (595:595:595)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sen\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT datac (5578:5578:5578) (5578:5578:5578)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - (IOPATH (posedge clk) qfbkout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) qfbkout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sen\[1\].lecomb) - (DELAY - (ABSOLUTE - (PORT datad (928:928:928) (928:928:928)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sen\[1\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sen\[2\].lecomb) - (DELAY - (ABSOLUTE - (PORT datad (956:956:956) (956:956:956)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sen\[2\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sen\[3\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (947:947:947) (947:947:947)) - (PORT datab (1308:1308:1308) (1308:1308:1308)) - (PORT datac (1360:1360:1360) (1360:1360:1360)) - (PORT datad (943:943:943) (943:943:943)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datad combout (200:200:200) (200:200:200)) - (IOPATH qfbkin combout (595:595:595) (595:595:595)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sen\[3\].lereg) - (DELAY - (ABSOLUTE - (PORT datac (1640:1640:1640) (1640:1640:1640)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - (IOPATH (posedge clk) qfbkout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) qfbkout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sen\[4\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (948:948:948) (948:948:948)) - (PORT datab (910:910:910) (910:910:910)) - (PORT datac (2055:2055:2055) (2055:2055:2055)) - (PORT datad (944:944:944) (944:944:944)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datad combout (200:200:200) (200:200:200)) - (IOPATH qfbkin combout (595:595:595) (595:595:595)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sen\[4\].lereg) - (DELAY - (ABSOLUTE - (PORT datac (2335:2335:2335) (2335:2335:2335)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - (IOPATH (posedge clk) qfbkout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) qfbkout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE negedge_line_sen.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (928:928:928) (928:928:928)) - (PORT datac (762:762:762) (762:762:762)) - (PORT datad (5222:5222:5222) (5222:5222:5222)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE negedge_line_sen.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (1372:1372:1372) (1372:1372:1372)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (6366:6366:6366) (6366:6366:6366)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE filter_line_sen.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (904:904:904) (904:904:904)) - (PORT datac (2381:2381:2381) (2381:2381:2381)) - (PORT datad (1887:1887:1887) (1887:1887:1887)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE filter_line_sen.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[26\]\~69.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3402:3402:3402) (3402:3402:3402)) - (PORT datab (2085:2085:2085) (2085:2085:2085)) - (PORT datac (951:951:951) (951:951:951)) - (PORT datad (2063:2063:2063) (2063:2063:2063)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (936:936:936) (936:936:936)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH dataa cout (1077:1077:1077) (1077:1077:1077)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4107:4107:4107) (4107:4107:4107)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3763:3763:3763) (3763:3763:3763)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[1\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (932:932:932) (932:932:932)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[1\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4107:4107:4107) (4107:4107:4107)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3763:3763:3763) (3763:3763:3763)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[2\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (934:934:934) (934:934:934)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[2\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4107:4107:4107) (4107:4107:4107)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3763:3763:3763) (3763:3763:3763)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[3\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (918:918:918)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[3\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4107:4107:4107) (4107:4107:4107)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3763:3763:3763) (3763:3763:3763)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[4\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (894:894:894)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[4\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4107:4107:4107) (4107:4107:4107)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3763:3763:3763) (3763:3763:3763)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE posedge_line_sclk.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3306:3306:3306) (3306:3306:3306)) - (PORT datab (2621:2621:2621) (2621:2621:2621)) - (PORT datac (3666:3666:3666) (3666:3666:3666)) - (PORT datad (741:741:741) (741:741:741)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datad combout (200:200:200) (200:200:200)) - (IOPATH qfbkin combout (595:595:595) (595:595:595)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE posedge_line_sclk.lereg) - (DELAY - (ABSOLUTE - (PORT datac (3946:3946:3946) (3946:3946:3946)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - (IOPATH (posedge clk) qfbkout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) qfbkout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[26\]\~68.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2264:2264:2264) (2264:2264:2264)) - (PORT datab (2760:2760:2760) (2760:2760:2760)) - (PORT datac (3469:3469:3469) (3469:3469:3469)) - (PORT datad (2082:2082:2082) (2082:2082:2082)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[5\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (911:911:911) (911:911:911)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout (1099:1099:1099) (1099:1099:1099)) - (IOPATH cin cout (349:349:349) (349:349:349)) - (IOPATH cin0 cout (399:399:399) (399:399:399)) - (IOPATH cin1 cout (387:387:387) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[5\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4107:4107:4107) (4107:4107:4107)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3763:3763:3763) (3763:3763:3763)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[6\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (900:900:900) (900:900:900)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[6\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[7\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[7\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[8\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[8\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[9\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[9\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[10\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (893:893:893)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout (1077:1077:1077) (1077:1077:1077)) - (IOPATH cin cout (246:246:246) (246:246:246)) - (IOPATH cin0 cout (261:261:261) (261:261:261)) - (IOPATH cin1 cout (252:252:252) (252:252:252)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[10\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[11\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (892:892:892)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[11\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[12\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (893:893:893)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[12\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[13\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (901:901:901) (901:901:901)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[13\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[14\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[14\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[15\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout (1099:1099:1099) (1099:1099:1099)) - (IOPATH cin cout (349:349:349) (349:349:349)) - (IOPATH cin0 cout (399:399:399) (399:399:399)) - (IOPATH cin1 cout (387:387:387) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[15\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4902:4902:4902) (4902:4902:4902)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3043:3043:3043) (3043:3043:3043)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[16\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (900:900:900) (900:900:900)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[16\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[17\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[17\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~4.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1859:1859:1859) (1859:1859:1859)) - (PORT datab (1839:1839:1839) (1839:1839:1839)) - (PORT datac (2078:2078:2078) (2078:2078:2078)) - (PORT datad (1922:1922:1922) (1922:1922:1922)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[18\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[18\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[19\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[19\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[20\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (893:893:893)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout (1077:1077:1077) (1077:1077:1077)) - (IOPATH cin cout (246:246:246) (246:246:246)) - (IOPATH cin0 cout (261:261:261) (261:261:261)) - (IOPATH cin1 cout (252:252:252) (252:252:252)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[20\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[21\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (892:892:892) (892:892:892)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[21\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~5.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1286:1286:1286)) - (PORT datab (1265:1265:1265) (1265:1265:1265)) - (PORT datac (1938:1938:1938) (1938:1938:1938)) - (PORT datad (1307:1307:1307) (1307:1307:1307)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~1.lecomb) - (DELAY - (ABSOLUTE - (PORT datac (1926:1926:1926) (1926:1926:1926)) - (PORT datad (1900:1900:1900) (1900:1900:1900)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~2.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1873:1873:1873) (1873:1873:1873)) - (PORT datab (1877:1877:1877) (1877:1877:1877)) - (PORT datac (2073:2073:2073) (2073:2073:2073)) - (PORT datad (1922:1922:1922) (1922:1922:1922)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~3.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1980:1980:1980) (1980:1980:1980)) - (PORT datab (2031:2031:2031) (2031:2031:2031)) - (PORT datac (779:779:779) (779:779:779)) - (PORT datad (721:721:721) (721:721:721)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[22\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (893:893:893) (893:893:893)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[22\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[23\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (901:901:901) (901:901:901)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[23\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[24\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[24\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[25\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (910:910:910) (910:910:910)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout (1099:1099:1099) (1099:1099:1099)) - (IOPATH cin cout (349:349:349) (349:349:349)) - (IOPATH cin0 cout (399:399:399) (399:399:399)) - (IOPATH cin1 cout (387:387:387) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[25\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4898:4898:4898) (4898:4898:4898)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3199:3199:3199) (3199:3199:3199)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[26\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (918:918:918)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[26\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4865:4865:4865) (4865:4865:4865)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3214:3214:3214) (3214:3214:3214)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[27\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (918:918:918) (918:918:918)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[27\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4865:4865:4865) (4865:4865:4865)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3214:3214:3214) (3214:3214:3214)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[28\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1335:1335:1335) (1335:1335:1335)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[28\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4865:4865:4865) (4865:4865:4865)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3214:3214:3214) (3214:3214:3214)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[29\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (902:902:902) (902:902:902)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[29\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4865:4865:4865) (4865:4865:4865)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3214:3214:3214) (3214:3214:3214)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[30\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (884:884:884)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1626:1626:1626) (1626:1626:1626)) - (IOPATH cin0 regin (1161:1161:1161) (1161:1161:1161)) - (IOPATH cin1 regin (1150:1150:1150) (1150:1150:1150)) - (IOPATH dataa cout (1077:1077:1077) (1077:1077:1077)) - (IOPATH cin cout (246:246:246) (246:246:246)) - (IOPATH cin0 cout (261:261:261) (261:261:261)) - (IOPATH cin1 cout (252:252:252) (252:252:252)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[30\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4865:4865:4865) (4865:4865:4865)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3214:3214:3214) (3214:3214:3214)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE i\[31\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH cin regin (1367:1367:1367) (1367:1367:1367)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE i\[31\].lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4865:4865:4865) (4865:4865:4865)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3214:3214:3214) (3214:3214:3214)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~7.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1343:1343:1343) (1343:1343:1343)) - (PORT datab (926:926:926) (926:926:926)) - (PORT datac (977:977:977) (977:977:977)) - (PORT datad (928:928:928) (928:928:928)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~6.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1260:1260:1260) (1260:1260:1260)) - (PORT datab (1317:1317:1317) (1317:1317:1317)) - (PORT datac (1999:1999:1999) (1999:1999:1999)) - (PORT datad (1286:1286:1286) (1286:1286:1286)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~8.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1302:1302:1302) (1302:1302:1302)) - (PORT datab (1297:1297:1297) (1297:1297:1297)) - (PORT datac (1188:1188:1188) (1188:1188:1188)) - (PORT datad (1141:1141:1141) (1141:1141:1141)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~9.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (710:710:710) (710:710:710)) - (PORT datab (1114:1114:1114) (1114:1114:1114)) - (PORT datac (777:777:777) (777:777:777)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (951:951:951) (951:951:951)) - (PORT datab (928:928:928) (928:928:928)) - (PORT datac (1007:1007:1007) (1007:1007:1007)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\~0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (938:938:938) (938:938:938)) - (PORT datab (915:915:915) (915:915:915)) - (PORT datac (776:776:776) (776:776:776)) - (PORT datad (920:920:920) (920:920:920)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fault_flag\[0\]\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1957:1957:1957) (1957:1957:1957)) - (PORT datab (927:927:927) (927:927:927)) - (PORT datac (2701:2701:2701) (2701:2701:2701)) - (PORT datad (3095:3095:3095) (3095:3095:3095)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fault_flag\[0\]\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\~128.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (937:937:937) (937:937:937)) - (PORT datad (1972:1972:1972) (1972:1972:1972)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE line_sdata\~I) - (DELAY - (ABSOLUTE - (IOPATH padio combout (1132:1132:1132) (1132:1132:1132)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE tmp_cache_line_sdata\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT datad (4474:4474:4474) (4474:4474:4474)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE tmp_cache_line_sdata\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE tmp_cache_line_sdata\[1\].lecomb) - (DELAY - (ABSOLUTE - (PORT datac (954:954:954) (954:954:954)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE tmp_cache_line_sdata\[1\].lereg) - (DELAY - (ABSOLUTE - (PORT datac (1234:1234:1234) (1234:1234:1234)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE tmp_cache_line_sdata\[2\].lecomb) - (DELAY - (ABSOLUTE - (PORT datac (951:951:951) (951:951:951)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE tmp_cache_line_sdata\[2\].lereg) - (DELAY - (ABSOLUTE - (PORT datac (1231:1231:1231) (1231:1231:1231)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE tmp_cache_line_sdata\[3\].lecomb) - (DELAY - (ABSOLUTE - (PORT datad (898:898:898) (898:898:898)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE tmp_cache_line_sdata\[3\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE tmp_cache_line_sdata\[4\].lecomb) - (DELAY - (ABSOLUTE - (PORT datad (895:895:895) (895:895:895)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE tmp_cache_line_sdata\[4\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE fiter_line_sdata.lecomb) - (DELAY - (ABSOLUTE - (PORT datad (1989:1989:1989) (1989:1989:1989)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE fiter_line_sdata.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (1372:1372:1372) (1372:1372:1372)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (7019:7019:7019) (7019:7019:7019)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~101.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4078:4078:4078) (4078:4078:4078)) - (PORT datab (3149:3149:3149) (3149:3149:3149)) - (PORT datac (3892:3892:3892) (3892:3892:3892)) - (PORT datad (3257:3257:3257) (3257:3257:3257)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1954:1954:1954) (1954:1954:1954)) - (PORT datab (3611:3611:3611) (3611:3611:3611)) - (PORT datac (958:958:958) (958:958:958)) - (PORT datad (714:714:714) (714:714:714)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~10.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3378:3378:3378) (3378:3378:3378)) - (PORT datad (3307:3307:3307) (3307:3307:3307)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE recv_complete\~11.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3262:3262:3262) (3262:3262:3262)) - (PORT datab (2530:2530:2530) (2530:2530:2530)) - (PORT datac (3561:3561:3561) (3561:3561:3561)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[45\]\~50.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2784:2784:2784) (2784:2784:2784)) - (PORT datab (2784:2784:2784) (2784:2784:2784)) - (PORT datac (758:758:758) (758:758:758)) - (PORT datad (2114:2114:2114) (2114:2114:2114)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1406:1406:1406) (1406:1406:1406)) - (PORT datac (2854:2854:2854) (2854:2854:2854)) - (PORT datad (2792:2792:2792) (2792:2792:2792)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (1906:1906:1906) (1906:1906:1906)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE enable_count_high_voltage_time.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3521:3521:3521) (3521:3521:3521)) - (PORT datab (3119:3119:3119) (3119:3119:3119)) - (PORT datac (1994:1994:1994) (1994:1994:1994)) - (PORT datad (2369:2369:2369) (2369:2369:2369)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE enable_count_high_voltage_time.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_enable_count_high_voltage_time\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT datad (2663:2663:2663) (2663:2663:2663)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_enable_count_high_voltage_time\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_enable_count_high_voltage_time\[1\].lecomb) - (DELAY - (ABSOLUTE - (PORT datac (2035:2035:2035) (2035:2035:2035)) - (PORT datad (897:897:897) (897:897:897)) - (IOPATH datad combout (200:200:200) (200:200:200)) - (IOPATH qfbkin combout (595:595:595) (595:595:595)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_enable_count_high_voltage_time\[1\].lereg) - (DELAY - (ABSOLUTE - (PORT datac (2315:2315:2315) (2315:2315:2315)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - (IOPATH (posedge clk) qfbkout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) qfbkout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datac (posedge clk) (333:333:333)) - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datac (posedge clk) (221:221:221)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (894:894:894) (894:894:894)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datab cout (954:954:954) (954:954:954)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[18\]\~129.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2700:2700:2700) (2700:2700:2700)) - (PORT datab (2046:2046:2046) (2046:2046:2046)) - (PORT datac (2641:2641:2641) (2641:2641:2641)) - (PORT datad (719:719:719) (719:719:719)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[0\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4219:4219:4219) (4219:4219:4219)) - (PORT datab (3581:3581:3581) (3581:3581:3581)) - (PORT datac (767:767:767) (767:767:767)) - (PORT datad (3880:3880:3880) (3880:3880:3880)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[0\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2377:2377:2377) (2377:2377:2377)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~155.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (879:879:879) (879:879:879)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[1\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4222:4222:4222) (4222:4222:4222)) - (PORT datab (3581:3581:3581) (3581:3581:3581)) - (PORT datac (771:771:771) (771:771:771)) - (PORT datad (3878:3878:3878) (3878:3878:3878)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[1\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2377:2377:2377) (2377:2377:2377)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~150.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1273:1273:1273) (1273:1273:1273)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[2\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1225:1225:1225) (1225:1225:1225)) - (PORT datab (3021:3021:3021) (3021:3021:3021)) - (PORT datac (4253:4253:4253) (4253:4253:4253)) - (PORT datad (3376:3376:3376) (3376:3376:3376)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[2\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (1927:1927:1927) (1927:1927:1927)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~145.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1292:1292:1292) (1292:1292:1292)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[3\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1159:1159:1159) (1159:1159:1159)) - (PORT datab (4017:4017:4017) (4017:4017:4017)) - (PORT datac (2770:2770:2770) (2770:2770:2770)) - (PORT datad (3017:3017:3017) (3017:3017:3017)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[3\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (1927:1927:1927) (1927:1927:1927)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~140.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1295:1295:1295) (1295:1295:1295)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[4\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2364:2364:2364) (2364:2364:2364)) - (PORT datab (3023:3023:3023) (3023:3023:3023)) - (PORT datac (2778:2778:2778) (2778:2778:2778)) - (PORT datad (4031:4031:4031) (4031:4031:4031)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[4\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (1927:1927:1927) (1927:1927:1927)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~135.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1302:1302:1302) (1302:1302:1302)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout (1099:1099:1099) (1099:1099:1099)) - (IOPATH cin cout (349:349:349) (349:349:349)) - (IOPATH cin0 cout (399:399:399) (399:399:399)) - (IOPATH cin1 cout (387:387:387) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[5\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4224:4224:4224) (4224:4224:4224)) - (PORT datab (3024:3024:3024) (3024:3024:3024)) - (PORT datac (2779:2779:2779) (2779:2779:2779)) - (PORT datad (1776:1776:1776) (1776:1776:1776)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[5\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (1927:1927:1927) (1927:1927:1927)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~130.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1309:1309:1309) (1309:1309:1309)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[6\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4220:4220:4220) (4220:4220:4220)) - (PORT datab (3580:3580:3580) (3580:3580:3580)) - (PORT datac (1244:1244:1244) (1244:1244:1244)) - (PORT datad (3879:3879:3879) (3879:3879:3879)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[6\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2377:2377:2377) (2377:2377:2377)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~125.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1282:1282:1282) (1282:1282:1282)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[7\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4219:4219:4219) (4219:4219:4219)) - (PORT datab (3869:3869:3869) (3869:3869:3869)) - (PORT datac (3611:3611:3611) (3611:3611:3611)) - (PORT datad (1133:1133:1133) (1133:1133:1133)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[7\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2377:2377:2377) (2377:2377:2377)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~120.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1830:1830:1830) (1830:1830:1830)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[8\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4533:4533:4533) (4533:4533:4533)) - (PORT datab (4019:4019:4019) (4019:4019:4019)) - (PORT datac (4302:4302:4302) (4302:4302:4302)) - (PORT datad (1760:1760:1760) (1760:1760:1760)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[8\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2526:2526:2526) (2526:2526:2526)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~115.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1982:1982:1982) (1982:1982:1982)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[9\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4521:4521:4521) (4521:4521:4521)) - (PORT datab (4000:4000:4000) (4000:4000:4000)) - (PORT datac (2051:2051:2051) (2051:2051:2051)) - (PORT datad (4011:4011:4011) (4011:4011:4011)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[9\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2526:2526:2526) (2526:2526:2526)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~110.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1919:1919:1919) (1919:1919:1919)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout (954:954:954) (954:954:954)) - (IOPATH cin cout (246:246:246) (246:246:246)) - (IOPATH cin0 cout (261:261:261) (261:261:261)) - (IOPATH cin1 cout (252:252:252) (252:252:252)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[10\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4531:4531:4531) (4531:4531:4531)) - (PORT datab (4016:4016:4016) (4016:4016:4016)) - (PORT datac (1956:1956:1956) (1956:1956:1956)) - (PORT datad (4016:4016:4016) (4016:4016:4016)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[10\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2526:2526:2526) (2526:2526:2526)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~105.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2023:2023:2023) (2023:2023:2023)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[11\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4532:4532:4532) (4532:4532:4532)) - (PORT datab (4018:4018:4018) (4018:4018:4018)) - (PORT datac (4301:4301:4301) (4301:4301:4301)) - (PORT datad (1855:1855:1855) (1855:1855:1855)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[11\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2526:2526:2526) (2526:2526:2526)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~6.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (884:884:884) (884:884:884)) - (PORT datab (894:894:894) (894:894:894)) - (PORT datac (961:961:961) (961:961:961)) - (PORT datad (908:908:908) (908:908:908)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~100.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2149:2149:2149) (2149:2149:2149)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[12\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1829:1829:1829) (1829:1829:1829)) - (PORT datab (4052:4052:4052) (4052:4052:4052)) - (PORT datac (3589:3589:3589) (3589:3589:3589)) - (PORT datad (2022:2022:2022) (2022:2022:2022)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[12\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3103:3103:3103) (3103:3103:3103)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~95.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2109:2109:2109) (2109:2109:2109)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[13\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3558:3558:3558) (3558:3558:3558)) - (PORT datab (4052:4052:4052) (4052:4052:4052)) - (PORT datac (1938:1938:1938) (1938:1938:1938)) - (PORT datad (2460:2460:2460) (2460:2460:2460)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[13\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3103:3103:3103) (3103:3103:3103)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~90.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1996:1996:1996) (1996:1996:1996)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[14\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1836:1836:1836) (1836:1836:1836)) - (PORT datab (4057:4057:4057) (4057:4057:4057)) - (PORT datac (3594:3594:3594) (3594:3594:3594)) - (PORT datad (1800:1800:1800) (1800:1800:1800)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[14\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3103:3103:3103) (3103:3103:3103)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~85.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2113:2113:2113) (2113:2113:2113)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout (1099:1099:1099) (1099:1099:1099)) - (IOPATH cin cout (349:349:349) (349:349:349)) - (IOPATH cin0 cout (399:399:399) (399:399:399)) - (IOPATH cin1 cout (387:387:387) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[15\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1837:1837:1837) (1837:1837:1837)) - (PORT datab (4058:4058:4058) (4058:4058:4058)) - (PORT datac (3595:3595:3595) (3595:3595:3595)) - (PORT datad (2581:2581:2581) (2581:2581:2581)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[15\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3103:3103:3103) (3103:3103:3103)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~5.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (878:878:878)) - (PORT datab (906:906:906) (906:906:906)) - (PORT datac (942:942:942) (942:942:942)) - (PORT datad (908:908:908) (908:908:908)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~7.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1322:1322:1322) (1322:1322:1322)) - (PORT datab (917:917:917) (917:917:917)) - (PORT datac (1401:1401:1401) (1401:1401:1401)) - (PORT datad (1349:1349:1349) (1349:1349:1349)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~8.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (889:889:889) (889:889:889)) - (PORT datab (903:903:903) (903:903:903)) - (PORT datac (2011:2011:2011) (2011:2011:2011)) - (PORT datad (733:733:733) (733:733:733)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~80.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1998:1998:1998) (1998:1998:1998)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[16\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4533:4533:4533) (4533:4533:4533)) - (PORT datab (4020:4020:4020) (4020:4020:4020)) - (PORT datac (4301:4301:4301) (4301:4301:4301)) - (PORT datad (1933:1933:1933) (1933:1933:1933)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[16\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2526:2526:2526) (2526:2526:2526)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~75.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1848:1848:1848) (1848:1848:1848)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[17\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4522:4522:4522) (4522:4522:4522)) - (PORT datab (4008:4008:4008) (4008:4008:4008)) - (PORT datac (4295:4295:4295) (4295:4295:4295)) - (PORT datad (1767:1767:1767) (1767:1767:1767)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[17\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2526:2526:2526) (2526:2526:2526)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~70.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1908:1908:1908) (1908:1908:1908)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[18\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4520:4520:4520) (4520:4520:4520)) - (PORT datab (4004:4004:4004) (4004:4004:4004)) - (PORT datac (4293:4293:4293) (4293:4293:4293)) - (PORT datad (1800:1800:1800) (1800:1800:1800)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[18\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2526:2526:2526) (2526:2526:2526)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~65.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1854:1854:1854) (1854:1854:1854)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[19\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4522:4522:4522) (4522:4522:4522)) - (PORT datab (3996:3996:3996) (3996:3996:3996)) - (PORT datac (4291:4291:4291) (4291:4291:4291)) - (PORT datad (1779:1779:1779) (1779:1779:1779)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[19\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2526:2526:2526) (2526:2526:2526)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~3.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (903:903:903) (903:903:903)) - (PORT datab (901:901:901) (901:901:901)) - (PORT datac (962:962:962) (962:962:962)) - (PORT datad (905:905:905) (905:905:905)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~60.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1926:1926:1926) (1926:1926:1926)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout (954:954:954) (954:954:954)) - (IOPATH cin cout (246:246:246) (246:246:246)) - (IOPATH cin0 cout (261:261:261) (261:261:261)) - (IOPATH cin1 cout (252:252:252) (252:252:252)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[20\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3299:3299:3299) (3299:3299:3299)) - (PORT datab (5301:5301:5301) (5301:5301:5301)) - (PORT datac (5120:5120:5120) (5120:5120:5120)) - (PORT datad (1627:1627:1627) (1627:1627:1627)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[20\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3671:3671:3671) (3671:3671:3671)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~55.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1992:1992:1992) (1992:1992:1992)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[21\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3273:3273:3273) (3273:3273:3273)) - (PORT datab (5292:5292:5292) (5292:5292:5292)) - (PORT datac (5116:5116:5116) (5116:5116:5116)) - (PORT datad (1761:1761:1761) (1761:1761:1761)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[21\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3671:3671:3671) (3671:3671:3671)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~50.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1900:1900:1900) (1900:1900:1900)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[22\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3288:3288:3288) (3288:3288:3288)) - (PORT datab (5294:5294:5294) (5294:5294:5294)) - (PORT datac (5112:5112:5112) (5112:5112:5112)) - (PORT datad (1638:1638:1638) (1638:1638:1638)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[22\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3671:3671:3671) (3671:3671:3671)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~45.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1997:1997:1997) (1997:1997:1997)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[23\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3303:3303:3303) (3303:3303:3303)) - (PORT datab (5305:5305:5305) (5305:5305:5305)) - (PORT datac (1791:1791:1791) (1791:1791:1791)) - (PORT datad (4087:4087:4087) (4087:4087:4087)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[23\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3671:3671:3671) (3671:3671:3671)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~40.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1881:1881:1881) (1881:1881:1881)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[24\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3301:3301:3301) (3301:3301:3301)) - (PORT datab (5303:5303:5303) (5303:5303:5303)) - (PORT datac (5121:5121:5121) (5121:5121:5121)) - (PORT datad (1818:1818:1818) (1818:1818:1818)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[24\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3671:3671:3671) (3671:3671:3671)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~35.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1898:1898:1898) (1898:1898:1898)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (975:975:975) (975:975:975)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout (1099:1099:1099) (1099:1099:1099)) - (IOPATH cin cout (349:349:349) (349:349:349)) - (IOPATH cin0 cout (399:399:399) (399:399:399)) - (IOPATH cin1 cout (387:387:387) (387:387:387)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[25\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3281:3281:3281) (3281:3281:3281)) - (PORT datab (5292:5292:5292) (5292:5292:5292)) - (PORT datac (5115:5115:5115) (5115:5115:5115)) - (PORT datad (1626:1626:1626) (1626:1626:1626)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[25\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3671:3671:3671) (3671:3671:3671)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~30.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2080:2080:2080) (2080:2080:2080)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[26\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3292:3292:3292) (3292:3292:3292)) - (PORT datab (5297:5297:5297) (5297:5297:5297)) - (PORT datac (5115:5115:5115) (5115:5115:5115)) - (PORT datad (1131:1131:1131) (1131:1131:1131)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[26\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3671:3671:3671) (3671:3671:3671)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~25.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1286:1286:1286) (1286:1286:1286)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[27\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3302:3302:3302) (3302:3302:3302)) - (PORT datab (5304:5304:5304) (5304:5304:5304)) - (PORT datac (1400:1400:1400) (1400:1400:1400)) - (PORT datad (4086:4086:4086) (4086:4086:4086)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[27\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3671:3671:3671) (3671:3671:3671)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~1.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (888:888:888) (888:888:888)) - (PORT datab (907:907:907) (907:907:907)) - (PORT datac (950:950:950) (950:950:950)) - (PORT datad (913:913:913) (913:913:913)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~2.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (891:891:891)) - (PORT datab (905:905:905) (905:905:905)) - (PORT datac (951:951:951) (951:951:951)) - (PORT datad (913:913:913) (913:913:913)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~20.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (900:900:900) (900:900:900)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH dataa cout0 (978:978:978) (978:978:978)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH dataa cout1 (973:973:973) (973:973:973)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[28\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4050:4050:4050) (4050:4050:4050)) - (PORT datab (4733:4733:4733) (4733:4733:4733)) - (PORT datac (3638:3638:3638) (3638:3638:3638)) - (PORT datad (725:725:725) (725:725:725)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[28\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3119:3119:3119) (3119:3119:3119)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~15.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (896:896:896) (896:896:896)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout0 (747:747:747) (747:747:747)) - (IOPATH cin0 cout0 (123:123:123) (123:123:123)) - (IOPATH datab cout1 (743:743:743) (743:743:743)) - (IOPATH cin1 cout1 (111:111:111) (111:111:111)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[29\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3604:3604:3604) (3604:3604:3604)) - (PORT datab (4733:4733:4733) (4733:4733:4733)) - (PORT datac (4082:4082:4082) (4082:4082:4082)) - (PORT datad (723:723:723) (723:723:723)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[29\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3119:3119:3119) (3119:3119:3119)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~10.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (904:904:904) (904:904:904)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH cin combout (1234:1234:1234) (1234:1234:1234)) - (IOPATH cin0 combout (815:815:815) (815:815:815)) - (IOPATH cin1 combout (804:804:804) (804:804:804)) - (IOPATH datab cout (954:954:954) (954:954:954)) - (IOPATH cin cout (246:246:246) (246:246:246)) - (IOPATH cin0 cout (261:261:261) (261:261:261)) - (IOPATH cin1 cout (252:252:252) (252:252:252)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[30\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4047:4047:4047) (4047:4047:4047)) - (PORT datab (3592:3592:3592) (3592:3592:3592)) - (PORT datac (777:777:777) (777:777:777)) - (PORT datad (4743:4743:4743) (4743:4743:4743)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[30\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3119:3119:3119) (3119:3119:3119)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Add2\~5.lecomb) - (DELAY - (ABSOLUTE - (PORT datad (905:905:905) (905:905:905)) - (IOPATH datad combout (200:200:200) (200:200:200)) - (IOPATH cin combout (975:975:975) (975:975:975)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cnt_for_high_voltage_time\[31\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4049:4049:4049) (4049:4049:4049)) - (PORT datab (3592:3592:3592) (3592:3592:3592)) - (PORT datac (776:776:776) (776:776:776)) - (PORT datad (4744:4744:4744) (4744:4744:4744)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cnt_for_high_voltage_time\[31\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3119:3119:3119) (3119:3119:3119)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1922:1922:1922) (1922:1922:1922)) - (PORT datab (1985:1985:1985) (1985:1985:1985)) - (PORT datac (1998:1998:1998) (1998:1998:1998)) - (PORT datad (1921:1921:1921) (1921:1921:1921)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~4.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1124:1124:1124) (1124:1124:1124)) - (PORT datab (1776:1776:1776) (1776:1776:1776)) - (PORT datac (1775:1775:1775) (1775:1775:1775)) - (PORT datad (733:733:733) (733:733:733)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~9.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1119:1119:1119) (1119:1119:1119)) - (PORT datab (1969:1969:1969) (1969:1969:1969)) - (PORT datac (772:772:772) (772:772:772)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Equal4\~10.lecomb) - (DELAY - (ABSOLUTE - (PORT datac (2305:2305:2305) (2305:2305:2305)) - (PORT datad (1783:1783:1783) (1783:1783:1783)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE is_high_voltage_time.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2916:2916:2916) (2916:2916:2916)) - (PORT datab (1782:1782:1782) (1782:1782:1782)) - (PORT datac (2161:2161:2161) (2161:2161:2161)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE is_high_voltage_time.lereg) - (DELAY - (ABSOLUTE - (PORT sclr (4345:4345:4345) (4345:4345:4345)) - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP sclr (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD sclr (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[0\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3734:3734:3734) (3734:3734:3734)) - (PORT datab (3371:3371:3371) (3371:3371:3371)) - (PORT datac (2781:2781:2781) (2781:2781:2781)) - (PORT datad (2998:2998:2998) (2998:2998:2998)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[0\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~66.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2491:2491:2491) (2491:2491:2491)) - (PORT datab (3379:3379:3379) (3379:3379:3379)) - (PORT datac (1941:1941:1941) (1941:1941:1941)) - (PORT datad (3308:3308:3308) (3308:3308:3308)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[1\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3544:3544:3544) (3544:3544:3544)) - (PORT datab (920:920:920) (920:920:920)) - (PORT datac (1931:1931:1931) (1931:1931:1931)) - (PORT datad (728:728:728) (728:728:728)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[1\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[1\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2781:2781:2781) (2781:2781:2781)) - (PORT datac (2851:2851:2851) (2851:2851:2851)) - (PORT datad (927:927:927) (927:927:927)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[1\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (1906:1906:1906) (1906:1906:1906)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[1\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3406:3406:3406) (3406:3406:3406)) - (PORT datab (3842:3842:3842) (3842:3842:3842)) - (PORT datac (3042:3042:3042) (3042:3042:3042)) - (PORT datad (2942:2942:2942) (2942:2942:2942)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[1\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~64.lecomb) - (DELAY - (ABSOLUTE - (PORT datac (3388:3388:3388) (3388:3388:3388)) - (PORT datad (3412:3412:3412) (3412:3412:3412)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE always3\~0.lecomb) - (DELAY - (ABSOLUTE - (PORT datac (972:972:972) (972:972:972)) - (PORT datad (2806:2806:2806) (2806:2806:2806)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~68.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3422:3422:3422) (3422:3422:3422)) - (PORT datab (2850:2850:2850) (2850:2850:2850)) - (PORT datac (2656:2656:2656) (2656:2656:2656)) - (PORT datad (2081:2081:2081) (2081:2081:2081)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~102.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3437:3437:3437) (3437:3437:3437)) - (PORT datab (2711:2711:2711) (2711:2711:2711)) - (PORT datac (1901:1901:1901) (1901:1901:1901)) - (PORT datad (2577:2577:2577) (2577:2577:2577)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[2\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (PORT datab (2060:2060:2060) (2060:2060:2060)) - (PORT datac (2268:2268:2268) (2268:2268:2268)) - (PORT datad (534:534:534) (534:534:534)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[2\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[2\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2360:2360:2360) (2360:2360:2360)) - (PORT datac (2325:2325:2325) (2325:2325:2325)) - (PORT datad (2162:2162:2162) (2162:2162:2162)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[2\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2985:2985:2985) (2985:2985:2985)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[2\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2979:2979:2979) (2979:2979:2979)) - (PORT datab (2096:2096:2096) (2096:2096:2096)) - (PORT datac (2534:2534:2534) (2534:2534:2534)) - (PORT datad (2941:2941:2941) (2941:2941:2941)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[2\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~69.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3166:3166:3166) (3166:3166:3166)) - (PORT datac (4537:4537:4537) (4537:4537:4537)) - (PORT datad (748:748:748) (748:748:748)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~103.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3388:3388:3388) (3388:3388:3388)) - (PORT datab (3324:3324:3324) (3324:3324:3324)) - (PORT datac (2011:2011:2011) (2011:2011:2011)) - (PORT datad (4211:4211:4211) (4211:4211:4211)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[3\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2569:2569:2569) (2569:2569:2569)) - (PORT datab (3269:3269:3269) (3269:3269:3269)) - (PORT datac (2895:2895:2895) (2895:2895:2895)) - (PORT datad (723:723:723) (723:723:723)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[3\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[3\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3014:3014:3014) (3014:3014:3014)) - (PORT datab (3552:3552:3552) (3552:3552:3552)) - (PORT datad (2142:2142:2142) (2142:2142:2142)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[3\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3148:3148:3148) (3148:3148:3148)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[3\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4228:4228:4228) (4228:4228:4228)) - (PORT datab (1943:1943:1943) (1943:1943:1943)) - (PORT datac (3012:3012:3012) (3012:3012:3012)) - (PORT datad (2919:2919:2919) (2919:2919:2919)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[3\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~70.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2646:2646:2646) (2646:2646:2646)) - (PORT datac (2840:2840:2840) (2840:2840:2840)) - (PORT datad (2915:2915:2915) (2915:2915:2915)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~71.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4055:4055:4055) (4055:4055:4055)) - (PORT datab (1892:1892:1892) (1892:1892:1892)) - (PORT datac (2971:2971:2971) (2971:2971:2971)) - (PORT datad (2581:2581:2581) (2581:2581:2581)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[4\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2297:2297:2297) (2297:2297:2297)) - (PORT datab (1276:1276:1276) (1276:1276:1276)) - (PORT datac (824:824:824) (824:824:824)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[4\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[4\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3003:3003:3003) (3003:3003:3003)) - (PORT datab (3546:3546:3546) (3546:3546:3546)) - (PORT datad (2830:2830:2830) (2830:2830:2830)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[4\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3148:3148:3148) (3148:3148:3148)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[4\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1927:1927:1927) (1927:1927:1927)) - (PORT datab (2921:2921:2921) (2921:2921:2921)) - (PORT datac (3008:3008:3008) (3008:3008:3008)) - (PORT datad (4238:4238:4238) (4238:4238:4238)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[4\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~72.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3166:3166:3166) (3166:3166:3166)) - (PORT datac (4539:4539:4539) (4539:4539:4539)) - (PORT datad (749:749:749) (749:749:749)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~104.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2672:2672:2672) (2672:2672:2672)) - (PORT datab (2712:2712:2712) (2712:2712:2712)) - (PORT datac (4429:4429:4429) (4429:4429:4429)) - (PORT datad (1347:1347:1347) (1347:1347:1347)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[5\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3574:3574:3574) (3574:3574:3574)) - (PORT datab (910:910:910) (910:910:910)) - (PORT datac (4153:4153:4153) (4153:4153:4153)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[5\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[5\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2383:2383:2383) (2383:2383:2383)) - (PORT datac (2320:2320:2320) (2320:2320:2320)) - (PORT datad (4498:4498:4498) (4498:4498:4498)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[5\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3159:3159:3159) (3159:3159:3159)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[5\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2260:2260:2260) (2260:2260:2260)) - (PORT datab (919:919:919) (919:919:919)) - (PORT datac (2451:2451:2451) (2451:2451:2451)) - (PORT datad (4312:4312:4312) (4312:4312:4312)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[5\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~73.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3276:3276:3276) (3276:3276:3276)) - (PORT datac (2717:2717:2717) (2717:2717:2717)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datac combout (511:511:511) (511:511:511)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~105.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (5422:5422:5422) (5422:5422:5422)) - (PORT datab (2610:2610:2610) (2610:2610:2610)) - (PORT datac (796:796:796) (796:796:796)) - (PORT datad (3148:3148:3148) (3148:3148:3148)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[6\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4173:4173:4173) (4173:4173:4173)) - (PORT datab (4027:4027:4027) (4027:4027:4027)) - (PORT datac (979:979:979) (979:979:979)) - (PORT datad (731:731:731) (731:731:731)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[6\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[6\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (915:915:915)) - (PORT datac (1485:1485:1485) (1485:1485:1485)) - (PORT datad (2686:2686:2686) (2686:2686:2686)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[6\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3096:3096:3096) (3096:3096:3096)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[6\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3184:3184:3184) (3184:3184:3184)) - (PORT datab (2908:2908:2908) (2908:2908:2908)) - (PORT datac (1982:1982:1982) (1982:1982:1982)) - (PORT datad (4086:4086:4086) (4086:4086:4086)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[6\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~106.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3385:3385:3385) (3385:3385:3385)) - (PORT datab (3320:3320:3320) (3320:3320:3320)) - (PORT datac (2015:2015:2015) (2015:2015:2015)) - (PORT datad (4207:4207:4207) (4207:4207:4207)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[7\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2859:2859:2859) (2859:2859:2859)) - (PORT datab (901:901:901) (901:901:901)) - (PORT datac (2639:2639:2639) (2639:2639:2639)) - (PORT datad (723:723:723) (723:723:723)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[7\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[7\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2138:2138:2138) (2138:2138:2138)) - (PORT datab (2868:2868:2868) (2868:2868:2868)) - (PORT datac (4279:4279:4279) (4279:4279:4279)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[7\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3165:3165:3165) (3165:3165:3165)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[7\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2950:2950:2950) (2950:2950:2950)) - (PORT datab (2020:2020:2020) (2020:2020:2020)) - (PORT datac (4083:4083:4083) (4083:4083:4083)) - (PORT datad (915:915:915) (915:915:915)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[7\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~107.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4049:4049:4049) (4049:4049:4049)) - (PORT datab (1887:1887:1887) (1887:1887:1887)) - (PORT datac (2958:2958:2958) (2958:2958:2958)) - (PORT datad (2588:2588:2588) (2588:2588:2588)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[8\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (756:756:756) (756:756:756)) - (PORT datab (901:901:901) (901:901:901)) - (PORT datac (2373:2373:2373) (2373:2373:2373)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[8\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[8\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2421:2421:2421) (2421:2421:2421)) - (PORT datac (3504:3504:3504) (3504:3504:3504)) - (PORT datad (1997:1997:1997) (1997:1997:1997)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[8\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3290:3290:3290) (3290:3290:3290)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[8\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3718:3718:3718) (3718:3718:3718)) - (PORT datab (2021:2021:2021) (2021:2021:2021)) - (PORT datac (2763:2763:2763) (2763:2763:2763)) - (PORT datad (2992:2992:2992) (2992:2992:2992)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[8\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~108.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2685:2685:2685) (2685:2685:2685)) - (PORT datab (2722:2722:2722) (2722:2722:2722)) - (PORT datac (4443:4443:4443) (4443:4443:4443)) - (PORT datad (1335:1335:1335) (1335:1335:1335)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[9\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3560:3560:3560) (3560:3560:3560)) - (PORT datab (2605:2605:2605) (2605:2605:2605)) - (PORT datac (948:948:948) (948:948:948)) - (PORT datad (728:728:728) (728:728:728)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[9\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[9\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1990:1990:1990) (1990:1990:1990)) - (PORT datac (2351:2351:2351) (2351:2351:2351)) - (PORT datad (3429:3429:3429) (3429:3429:3429)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[9\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3086:3086:3086) (3086:3086:3086)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[9\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3551:3551:3551) (3551:3551:3551)) - (PORT datab (3069:3069:3069) (3069:3069:3069)) - (PORT datac (1461:1461:1461) (1461:1461:1461)) - (PORT datad (2120:2120:2120) (2120:2120:2120)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[9\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~74.lecomb) - (DELAY - (ABSOLUTE - (PORT datac (3471:3471:3471) (3471:3471:3471)) - (PORT datad (2842:2842:2842) (2842:2842:2842)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~109.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2811:2811:2811) (2811:2811:2811)) - (PORT datab (2710:2710:2710) (2710:2710:2710)) - (PORT datac (1963:1963:1963) (1963:1963:1963)) - (PORT datad (1262:1262:1262) (1262:1262:1262)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[10\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (760:760:760) (760:760:760)) - (PORT datab (919:919:919) (919:919:919)) - (PORT datac (2371:2371:2371) (2371:2371:2371)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[10\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[10\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1861:1861:1861) (1861:1861:1861)) - (PORT datac (2337:2337:2337) (2337:2337:2337)) - (PORT datad (3420:3420:3420) (3420:3420:3420)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[10\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3086:3086:3086) (3086:3086:3086)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[10\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (5217:5217:5217) (5217:5217:5217)) - (PORT datab (3627:3627:3627) (3627:3627:3627)) - (PORT datac (3673:3673:3673) (3673:3673:3673)) - (PORT datad (2210:2210:2210) (2210:2210:2210)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[10\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~110.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3363:3363:3363) (3363:3363:3363)) - (PORT datab (4185:4185:4185) (4185:4185:4185)) - (PORT datac (2811:2811:2811) (2811:2811:2811)) - (PORT datad (2076:2076:2076) (2076:2076:2076)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[11\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2937:2937:2937) (2937:2937:2937)) - (PORT datab (921:921:921) (921:921:921)) - (PORT datac (2173:2173:2173) (2173:2173:2173)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[11\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[11\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2432:2432:2432) (2432:2432:2432)) - (PORT datac (3515:3515:3515) (3515:3515:3515)) - (PORT datad (924:924:924) (924:924:924)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[11\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3290:3290:3290) (3290:3290:3290)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[11\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3538:3538:3538) (3538:3538:3538)) - (PORT datab (3062:3062:3062) (3062:3062:3062)) - (PORT datac (1452:1452:1452) (1452:1452:1452)) - (PORT datad (2612:2612:2612) (2612:2612:2612)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[11\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~76.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4056:4056:4056) (4056:4056:4056)) - (PORT datab (1893:1893:1893) (1893:1893:1893)) - (PORT datac (2972:2972:2972) (2972:2972:2972)) - (PORT datad (2581:2581:2581) (2581:2581:2581)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[12\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (765:765:765) (765:765:765)) - (PORT datab (900:900:900) (900:900:900)) - (PORT datac (2367:2367:2367) (2367:2367:2367)) - (PORT datad (738:738:738) (738:738:738)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[12\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[12\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2418:2418:2418) (2418:2418:2418)) - (PORT datac (3505:3505:3505) (3505:3505:3505)) - (PORT datad (1985:1985:1985) (1985:1985:1985)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[12\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3290:3290:3290) (3290:3290:3290)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[12\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3731:3731:3731) (3731:3731:3731)) - (PORT datab (2137:2137:2137) (2137:2137:2137)) - (PORT datac (2779:2779:2779) (2779:2779:2779)) - (PORT datad (2997:2997:2997) (2997:2997:2997)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[12\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~111.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2686:2686:2686) (2686:2686:2686)) - (PORT datab (2723:2723:2723) (2723:2723:2723)) - (PORT datac (4444:4444:4444) (4444:4444:4444)) - (PORT datad (1332:1332:1332) (1332:1332:1332)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[13\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3580:3580:3580) (3580:3580:3580)) - (PORT datab (2593:2593:2593) (2593:2593:2593)) - (PORT datac (948:948:948) (948:948:948)) - (PORT datad (736:736:736) (736:736:736)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[13\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[13\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3832:3832:3832) (3832:3832:3832)) - (PORT datab (4499:4499:4499) (4499:4499:4499)) - (PORT datad (2008:2008:2008) (2008:2008:2008)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[13\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3090:3090:3090) (3090:3090:3090)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[13\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3547:3547:3547) (3547:3547:3547)) - (PORT datab (3065:3065:3065) (3065:3065:3065)) - (PORT datac (1458:1458:1458) (1458:1458:1458)) - (PORT datad (2658:2658:2658) (2658:2658:2658)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[13\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~77.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2475:2475:2475) (2475:2475:2475)) - (PORT datab (3430:3430:3430) (3430:3430:3430)) - (PORT datac (3996:3996:3996) (3996:3996:3996)) - (PORT datad (1800:1800:1800) (1800:1800:1800)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[14\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3533:3533:3533) (3533:3533:3533)) - (PORT datab (910:910:910) (910:910:910)) - (PORT datac (2485:2485:2485) (2485:2485:2485)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[14\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[14\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (917:917:917) (917:917:917)) - (PORT datac (2352:2352:2352) (2352:2352:2352)) - (PORT datad (3430:3430:3430) (3430:3430:3430)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[14\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3086:3086:3086) (3086:3086:3086)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[14\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2954:2954:2954) (2954:2954:2954)) - (PORT datab (919:919:919) (919:919:919)) - (PORT datac (4088:4088:4088) (4088:4088:4088)) - (PORT datad (2338:2338:2338) (2338:2338:2338)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[14\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~112.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3368:3368:3368) (3368:3368:3368)) - (PORT datab (4190:4190:4190) (4190:4190:4190)) - (PORT datac (2813:2813:2813) (2813:2813:2813)) - (PORT datad (2072:2072:2072) (2072:2072:2072)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[15\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2939:2939:2939) (2939:2939:2939)) - (PORT datab (2166:2166:2166) (2166:2166:2166)) - (PORT datac (2164:2164:2164) (2164:2164:2164)) - (PORT datad (534:534:534) (534:534:534)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[15\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[15\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2832:2832:2832) (2832:2832:2832)) - (PORT datac (2335:2335:2335) (2335:2335:2335)) - (PORT datad (3417:3417:3417) (3417:3417:3417)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[15\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3086:3086:3086) (3086:3086:3086)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[15\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3116:3116:3116) (3116:3116:3116)) - (PORT datab (3530:3530:3530) (3530:3530:3530)) - (PORT datac (5305:5305:5305) (5305:5305:5305)) - (PORT datad (2041:2041:2041) (2041:2041:2041)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[15\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~78.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1218:1218:1218) (1218:1218:1218)) - (PORT datab (3404:3404:3404) (3404:3404:3404)) - (PORT datac (2486:2486:2486) (2486:2486:2486)) - (PORT datad (2561:2561:2561) (2561:2561:2561)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~113.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3599:3599:3599) (3599:3599:3599)) - (PORT datab (3342:3342:3342) (3342:3342:3342)) - (PORT datac (4303:4303:4303) (4303:4303:4303)) - (PORT datad (784:784:784) (784:784:784)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[16\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2936:2936:2936) (2936:2936:2936)) - (PORT datab (2657:2657:2657) (2657:2657:2657)) - (PORT datac (939:939:939) (939:939:939)) - (PORT datad (534:534:534) (534:534:534)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[16\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[16\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1934:1934:1934) (1934:1934:1934)) - (PORT datac (2350:2350:2350) (2350:2350:2350)) - (PORT datad (3428:3428:3428) (3428:3428:3428)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[16\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3086:3086:3086) (3086:3086:3086)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[16\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2142:2142:2142) (2142:2142:2142)) - (PORT datab (3639:3639:3639) (3639:3639:3639)) - (PORT datac (5246:5246:5246) (5246:5246:5246)) - (PORT datad (3636:3636:3636) (3636:3636:3636)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[16\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~79.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2670:2670:2670) (2670:2670:2670)) - (PORT datab (2604:2604:2604) (2604:2604:2604)) - (PORT datac (2159:2159:2159) (2159:2159:2159)) - (PORT datad (2564:2564:2564) (2564:2564:2564)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~80.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3286:3286:3286) (3286:3286:3286)) - (PORT datac (784:784:784) (784:784:784)) - (PORT datad (3786:3786:3786) (3786:3786:3786)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[17\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2928:2928:2928) (2928:2928:2928)) - (PORT datab (1988:1988:1988) (1988:1988:1988)) - (PORT datac (1347:1347:1347) (1347:1347:1347)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[17\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[17\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2785:2785:2785) (2785:2785:2785)) - (PORT datac (2261:2261:2261) (2261:2261:2261)) - (PORT datad (2794:2794:2794) (2794:2794:2794)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[17\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (1906:1906:1906) (1906:1906:1906)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[17\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3261:3261:3261) (3261:3261:3261)) - (PORT datab (1914:1914:1914) (1914:1914:1914)) - (PORT datac (5316:5316:5316) (5316:5316:5316)) - (PORT datad (3142:3142:3142) (3142:3142:3142)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[17\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~114.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3603:3603:3603) (3603:3603:3603)) - (PORT datab (3335:3335:3335) (3335:3335:3335)) - (PORT datac (4295:4295:4295) (4295:4295:4295)) - (PORT datad (790:790:790) (790:790:790)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[18\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2932:2932:2932) (2932:2932:2932)) - (PORT datab (936:936:936) (936:936:936)) - (PORT datac (2702:2702:2702) (2702:2702:2702)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[18\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[18\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2898:2898:2898) (2898:2898:2898)) - (PORT datac (2597:2597:2597) (2597:2597:2597)) - (PORT datad (4076:4076:4076) (4076:4076:4076)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[18\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3080:3080:3080) (3080:3080:3080)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[18\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3108:3108:3108) (3108:3108:3108)) - (PORT datab (3528:3528:3528) (3528:3528:3528)) - (PORT datac (5296:5296:5296) (5296:5296:5296)) - (PORT datad (1374:1374:1374) (1374:1374:1374)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[18\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~67.lecomb) - (DELAY - (ABSOLUTE - (PORT datac (2637:2637:2637) (2637:2637:2637)) - (PORT datad (3217:3217:3217) (3217:3217:3217)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~81.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2096:2096:2096) (2096:2096:2096)) - (PORT datab (2624:2624:2624) (2624:2624:2624)) - (PORT datac (759:759:759) (759:759:759)) - (PORT datad (1136:1136:1136) (1136:1136:1136)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[19\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2201:2201:2201) (2201:2201:2201)) - (PORT datab (1880:1880:1880) (1880:1880:1880)) - (PORT datac (939:939:939) (939:939:939)) - (PORT datad (534:534:534) (534:534:534)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[19\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[19\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3011:3011:3011) (3011:3011:3011)) - (PORT datab (3550:3550:3550) (3550:3550:3550)) - (PORT datac (2617:2617:2617) (2617:2617:2617)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[19\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3148:3148:3148) (3148:3148:3148)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[19\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4234:4234:4234) (4234:4234:4234)) - (PORT datab (2034:2034:2034) (2034:2034:2034)) - (PORT datac (3019:3019:3019) (3019:3019:3019)) - (PORT datad (2924:2924:2924) (2924:2924:2924)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[19\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~82.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2848:2848:2848) (2848:2848:2848)) - (PORT datab (2907:2907:2907) (2907:2907:2907)) - (PORT datac (2845:2845:2845) (2845:2845:2845)) - (PORT datad (2663:2663:2663) (2663:2663:2663)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~115.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3353:3353:3353) (3353:3353:3353)) - (PORT datab (3442:3442:3442) (3442:3442:3442)) - (PORT datac (2900:2900:2900) (2900:2900:2900)) - (PORT datad (2138:2138:2138) (2138:2138:2138)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~83.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2838:2838:2838) (2838:2838:2838)) - (PORT datac (1221:1221:1221) (1221:1221:1221)) - (PORT datad (737:737:737) (737:737:737)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[20\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1348:1348:1348) (1348:1348:1348)) - (PORT datab (1416:1416:1416) (1416:1416:1416)) - (PORT datac (2191:2191:2191) (2191:2191:2191)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[20\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[20\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3277:3277:3277) (3277:3277:3277)) - (PORT datac (3223:3223:3223) (3223:3223:3223)) - (PORT datad (2121:2121:2121) (2121:2121:2121)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[20\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2370:2370:2370) (2370:2370:2370)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[20\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3173:3173:3173) (3173:3173:3173)) - (PORT datab (2895:2895:2895) (2895:2895:2895)) - (PORT datac (3869:3869:3869) (3869:3869:3869)) - (PORT datad (1863:1863:1863) (1863:1863:1863)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[20\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~84.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2135:2135:2135) (2135:2135:2135)) - (PORT datab (1212:1212:1212) (1212:1212:1212)) - (PORT datac (782:782:782) (782:782:782)) - (PORT datad (3819:3819:3819) (3819:3819:3819)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[21\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2930:2930:2930) (2930:2930:2930)) - (PORT datab (1987:1987:1987) (1987:1987:1987)) - (PORT datac (3212:3212:3212) (3212:3212:3212)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[21\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[21\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3013:3013:3013) (3013:3013:3013)) - (PORT datab (3552:3552:3552) (3552:3552:3552)) - (PORT datac (2737:2737:2737) (2737:2737:2737)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[21\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3148:3148:3148) (3148:3148:3148)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[21\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3956:3956:3956) (3956:3956:3956)) - (PORT datab (3501:3501:3501) (3501:3501:3501)) - (PORT datac (1928:1928:1928) (1928:1928:1928)) - (PORT datad (2885:2885:2885) (2885:2885:2885)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[21\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~116.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3592:3592:3592) (3592:3592:3592)) - (PORT datab (3346:3346:3346) (3346:3346:3346)) - (PORT datac (4307:4307:4307) (4307:4307:4307)) - (PORT datad (781:781:781) (781:781:781)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[22\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2921:2921:2921) (2921:2921:2921)) - (PORT datab (935:935:935) (935:935:935)) - (PORT datac (2707:2707:2707) (2707:2707:2707)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[22\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[22\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2234:2234:2234) (2234:2234:2234)) - (PORT datac (2346:2346:2346) (2346:2346:2346)) - (PORT datad (3424:3424:3424) (3424:3424:3424)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[22\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3086:3086:3086) (3086:3086:3086)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[22\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3112:3112:3112) (3112:3112:3112)) - (PORT datab (3527:3527:3527) (3527:3527:3527)) - (PORT datac (5296:5296:5296) (5296:5296:5296)) - (PORT datad (1926:1926:1926) (1926:1926:1926)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[22\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~85.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2141:2141:2141) (2141:2141:2141)) - (PORT datab (1216:1216:1216) (1216:1216:1216)) - (PORT datac (3334:3334:3334) (3334:3334:3334)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[23\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2937:2937:2937) (2937:2937:2937)) - (PORT datab (1984:1984:1984) (1984:1984:1984)) - (PORT datac (1343:1343:1343) (1343:1343:1343)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[23\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[23\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3817:3817:3817) (3817:3817:3817)) - (PORT datab (4491:4491:4491) (4491:4491:4491)) - (PORT datad (1892:1892:1892) (1892:1892:1892)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[23\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3090:3090:3090) (3090:3090:3090)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[23\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3532:3532:3532) (3532:3532:3532)) - (PORT datab (2099:2099:2099) (2099:2099:2099)) - (PORT datac (5162:5162:5162) (5162:5162:5162)) - (PORT datad (3702:3702:3702) (3702:3702:3702)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[23\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~86.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1147:1147:1147) (1147:1147:1147)) - (PORT datab (2564:2564:2564) (2564:2564:2564)) - (PORT datac (1232:1232:1232) (1232:1232:1232)) - (PORT datad (2138:2138:2138) (2138:2138:2138)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[24\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2009:2009:2009) (2009:2009:2009)) - (PORT datab (1413:1413:1413) (1413:1413:1413)) - (PORT datac (2194:2194:2194) (2194:2194:2194)) - (PORT datad (731:731:731) (731:731:731)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[24\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[24\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3810:3810:3810) (3810:3810:3810)) - (PORT datab (4496:4496:4496) (4496:4496:4496)) - (PORT datad (2733:2733:2733) (2733:2733:2733)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[24\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3090:3090:3090) (3090:3090:3090)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[24\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2011:2011:2011) (2011:2011:2011)) - (PORT datab (3692:3692:3692) (3692:3692:3692)) - (PORT datac (5167:5167:5167) (5167:5167:5167)) - (PORT datad (3551:3551:3551) (3551:3551:3551)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[24\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~75.lecomb) - (DELAY - (ABSOLUTE - (PORT datac (4210:4210:4210) (4210:4210:4210)) - (PORT datad (4012:4012:4012) (4012:4012:4012)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~87.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2836:2836:2836) (2836:2836:2836)) - (PORT datab (4042:4042:4042) (4042:4042:4042)) - (PORT datac (811:811:811) (811:811:811)) - (PORT datad (1290:1290:1290) (1290:1290:1290)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[25\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2551:2551:2551) (2551:2551:2551)) - (PORT datab (901:901:901) (901:901:901)) - (PORT datac (2989:2989:2989) (2989:2989:2989)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[25\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[25\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2909:2909:2909) (2909:2909:2909)) - (PORT datac (2707:2707:2707) (2707:2707:2707)) - (PORT datad (4087:4087:4087) (4087:4087:4087)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[25\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3080:3080:3080) (3080:3080:3080)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[25\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3180:3180:3180) (3180:3180:3180)) - (PORT datab (2904:2904:2904) (2904:2904:2904)) - (PORT datac (943:943:943) (943:943:943)) - (PORT datad (4082:4082:4082) (4082:4082:4082)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[25\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~117.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4241:4241:4241) (4241:4241:4241)) - (PORT datab (3343:3343:3343) (3343:3343:3343)) - (PORT datac (3665:3665:3665) (3665:3665:3665)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[26\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2823:2823:2823) (2823:2823:2823)) - (PORT datab (891:891:891) (891:891:891)) - (PORT datac (2606:2606:2606) (2606:2606:2606)) - (PORT datad (1111:1111:1111) (1111:1111:1111)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[26\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[26\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2896:2896:2896) (2896:2896:2896)) - (PORT datac (2146:2146:2146) (2146:2146:2146)) - (PORT datad (4070:4070:4070) (4070:4070:4070)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[26\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3080:3080:3080) (3080:3080:3080)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[26\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3182:3182:3182) (3182:3182:3182)) - (PORT datab (2906:2906:2906) (2906:2906:2906)) - (PORT datac (3875:3875:3875) (3875:3875:3875)) - (PORT datad (920:920:920) (920:920:920)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[26\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~88.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2831:2831:2831) (2831:2831:2831)) - (PORT datab (4051:4051:4051) (4051:4051:4051)) - (PORT datac (819:819:819) (819:819:819)) - (PORT datad (1299:1299:1299) (1299:1299:1299)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[27\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2921:2921:2921) (2921:2921:2921)) - (PORT datab (2451:2451:2451) (2451:2451:2451)) - (PORT datac (939:939:939) (939:939:939)) - (PORT datad (534:534:534) (534:534:534)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[27\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[27\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2168:2168:2168) (2168:2168:2168)) - (PORT datab (3418:3418:3418) (3418:3418:3418)) - (PORT datac (2339:2339:2339) (2339:2339:2339)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[27\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3086:3086:3086) (3086:3086:3086)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[27\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1974:1974:1974) (1974:1974:1974)) - (PORT datab (3533:3533:3533) (3533:3533:3533)) - (PORT datac (5307:5307:5307) (5307:5307:5307)) - (PORT datad (3138:3138:3138) (3138:3138:3138)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[27\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~89.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2766:2766:2766) (2766:2766:2766)) - (PORT datab (2836:2836:2836) (2836:2836:2836)) - (PORT datac (1221:1221:1221) (1221:1221:1221)) - (PORT datad (735:735:735) (735:735:735)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[28\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2112:2112:2112) (2112:2112:2112)) - (PORT datab (1417:1417:1417) (1417:1417:1417)) - (PORT datac (939:939:939) (939:939:939)) - (PORT datad (729:729:729) (729:729:729)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[28\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[28\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3005:3005:3005) (3005:3005:3005)) - (PORT datab (3547:3547:3547) (3547:3547:3547)) - (PORT datad (1283:1283:1283) (1283:1283:1283)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[28\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3148:3148:3148) (3148:3148:3148)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[28\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (5218:5218:5218) (5218:5218:5218)) - (PORT datab (2061:2061:2061) (2061:2061:2061)) - (PORT datac (3674:3674:3674) (3674:3674:3674)) - (PORT datad (3640:3640:3640) (3640:3640:3640)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[28\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~90.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2821:2821:2821) (2821:2821:2821)) - (PORT datab (4056:4056:4056) (4056:4056:4056)) - (PORT datac (823:823:823) (823:823:823)) - (PORT datad (1303:1303:1303) (1303:1303:1303)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[29\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2557:2557:2557) (2557:2557:2557)) - (PORT datab (900:900:900) (900:900:900)) - (PORT datac (2974:2974:2974) (2974:2974:2974)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[29\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[29\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2558:2558:2558) (2558:2558:2558)) - (PORT datab (2401:2401:2401) (2401:2401:2401)) - (PORT datac (2332:2332:2332) (2332:2332:2332)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[29\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3159:3159:3159) (3159:3159:3159)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[29\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2245:2245:2245) (2245:2245:2245)) - (PORT datab (934:934:934) (934:934:934)) - (PORT datac (2430:2430:2430) (2430:2430:2430)) - (PORT datad (4311:4311:4311) (4311:4311:4311)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[29\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~91.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3604:3604:3604) (3604:3604:3604)) - (PORT datab (3336:3336:3336) (3336:3336:3336)) - (PORT datac (4289:4289:4289) (4289:4289:4289)) - (PORT datad (792:792:792) (792:792:792)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[30\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2935:2935:2935) (2935:2935:2935)) - (PORT datab (892:892:892) (892:892:892)) - (PORT datac (2704:2704:2704) (2704:2704:2704)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[30\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[30\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2064:2064:2064) (2064:2064:2064)) - (PORT datac (2349:2349:2349) (2349:2349:2349)) - (PORT datad (3426:3426:3426) (3426:3426:3426)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[30\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3086:3086:3086) (3086:3086:3086)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[30\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2770:2770:2770) (2770:2770:2770)) - (PORT datab (3143:3143:3143) (3143:3143:3143)) - (PORT datac (5000:5000:5000) (5000:5000:5000)) - (PORT datad (1942:1942:1942) (1942:1942:1942)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[30\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~92.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2827:2827:2827) (2827:2827:2827)) - (PORT datab (4054:4054:4054) (4054:4054:4054)) - (PORT datac (821:821:821) (821:821:821)) - (PORT datad (1301:1301:1301) (1301:1301:1301)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[31\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2555:2555:2555) (2555:2555:2555)) - (PORT datab (2855:2855:2855) (2855:2855:2855)) - (PORT datac (2984:2984:2984) (2984:2984:2984)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[31\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[31\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2773:2773:2773) (2773:2773:2773)) - (PORT datac (2842:2842:2842) (2842:2842:2842)) - (PORT datad (2041:2041:2041) (2041:2041:2041)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[31\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (1906:1906:1906) (1906:1906:1906)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[31\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2052:2052:2052) (2052:2052:2052)) - (PORT datab (3149:3149:3149) (3149:3149:3149)) - (PORT datac (5006:5006:5006) (5006:5006:5006)) - (PORT datad (2878:2878:2878) (2878:2878:2878)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[31\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~118.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3117:3117:3117) (3117:3117:3117)) - (PORT datab (2534:2534:2534) (2534:2534:2534)) - (PORT datac (2375:2375:2375) (2375:2375:2375)) - (PORT datad (1947:1947:1947) (1947:1947:1947)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[32\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (883:883:883) (883:883:883)) - (PORT datab (3446:3446:3446) (3446:3446:3446)) - (PORT datac (2638:2638:2638) (2638:2638:2638)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[32\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[32\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2086:2086:2086) (2086:2086:2086)) - (PORT datab (2123:2123:2123) (2123:2123:2123)) - (PORT datac (3348:3348:3348) (3348:3348:3348)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[32\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2370:2370:2370) (2370:2370:2370)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[32\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3809:3809:3809) (3809:3809:3809)) - (PORT datab (4493:4493:4493) (4493:4493:4493)) - (PORT datac (3175:3175:3175) (3175:3175:3175)) - (PORT datad (2015:2015:2015) (2015:2015:2015)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[32\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~93.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3123:3123:3123) (3123:3123:3123)) - (PORT datab (2529:2529:2529) (2529:2529:2529)) - (PORT datac (2381:2381:2381) (2381:2381:2381)) - (PORT datad (1954:1954:1954) (1954:1954:1954)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[33\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2596:2596:2596) (2596:2596:2596)) - (PORT datab (891:891:891) (891:891:891)) - (PORT datac (3498:3498:3498) (3498:3498:3498)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[33\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[33\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2364:2364:2364) (2364:2364:2364)) - (PORT datac (2323:2323:2323) (2323:2323:2323)) - (PORT datad (2720:2720:2720) (2720:2720:2720)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[33\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2985:2985:2985) (2985:2985:2985)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[33\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2387:2387:2387) (2387:2387:2387)) - (PORT datab (917:917:917) (917:917:917)) - (PORT datac (2342:2342:2342) (2342:2342:2342)) - (PORT datad (3773:3773:3773) (3773:3773:3773)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[33\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~119.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2851:2851:2851) (2851:2851:2851)) - (PORT datab (3392:3392:3392) (3392:3392:3392)) - (PORT datac (1236:1236:1236) (1236:1236:1236)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[34\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1231:1231:1231) (1231:1231:1231)) - (PORT datab (892:892:892) (892:892:892)) - (PORT datac (4221:4221:4221) (4221:4221:4221)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[34\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[34\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2786:2786:2786) (2786:2786:2786)) - (PORT datac (2857:2857:2857) (2857:2857:2857)) - (PORT datad (3733:3733:3733) (3733:3733:3733)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[34\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (1906:1906:1906) (1906:1906:1906)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[34\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (5204:5204:5204) (5204:5204:5204)) - (PORT datab (3621:3621:3621) (3621:3621:3621)) - (PORT datac (3662:3662:3662) (3662:3662:3662)) - (PORT datad (2128:2128:2128) (2128:2128:2128)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[34\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~120.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3370:3370:3370) (3370:3370:3370)) - (PORT datab (4192:4192:4192) (4192:4192:4192)) - (PORT datac (2818:2818:2818) (2818:2818:2818)) - (PORT datad (2065:2065:2065) (2065:2065:2065)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[35\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2920:2920:2920) (2920:2920:2920)) - (PORT datab (891:891:891) (891:891:891)) - (PORT datac (2179:2179:2179) (2179:2179:2179)) - (PORT datad (727:727:727) (727:727:727)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[35\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[35\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2387:2387:2387) (2387:2387:2387)) - (PORT datac (2318:2318:2318) (2318:2318:2318)) - (PORT datad (2668:2668:2668) (2668:2668:2668)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[35\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3159:3159:3159) (3159:3159:3159)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[35\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2248:2248:2248) (2248:2248:2248)) - (PORT datab (930:930:930) (930:930:930)) - (PORT datac (2439:2439:2439) (2439:2439:2439)) - (PORT datad (4311:4311:4311) (4311:4311:4311)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[35\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~94.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3860:3860:3860) (3860:3860:3860)) - (PORT datab (3163:3163:3163) (3163:3163:3163)) - (PORT datac (3583:3583:3583) (3583:3583:3583)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~95.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3442:3442:3442) (3442:3442:3442)) - (PORT datab (4084:4084:4084) (4084:4084:4084)) - (PORT datac (1258:1258:1258) (1258:1258:1258)) - (PORT datad (2586:2586:2586) (2586:2586:2586)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[36\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2644:2644:2644) (2644:2644:2644)) - (PORT datab (930:930:930) (930:930:930)) - (PORT datac (3454:3454:3454) (3454:3454:3454)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[36\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[36\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2874:2874:2874) (2874:2874:2874)) - (PORT datac (4283:4283:4283) (4283:4283:4283)) - (PORT datad (933:933:933) (933:933:933)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[36\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3165:3165:3165) (3165:3165:3165)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[36\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3721:3721:3721) (3721:3721:3721)) - (PORT datab (2560:2560:2560) (2560:2560:2560)) - (PORT datac (2760:2760:2760) (2760:2760:2760)) - (PORT datad (2994:2994:2994) (2994:2994:2994)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[36\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~121.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3467:3467:3467) (3467:3467:3467)) - (PORT datab (4062:4062:4062) (4062:4062:4062)) - (PORT datac (4113:4113:4113) (4113:4113:4113)) - (PORT datad (1914:1914:1914) (1914:1914:1914)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[37\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (913:913:913) (913:913:913)) - (PORT datab (3615:3615:3615) (3615:3615:3615)) - (PORT datac (2022:2022:2022) (2022:2022:2022)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[37\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[37\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (915:915:915) (915:915:915)) - (PORT datab (2117:2117:2117) (2117:2117:2117)) - (PORT datac (3342:3342:3342) (3342:3342:3342)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[37\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2370:2370:2370) (2370:2370:2370)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[37\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2387:2387:2387) (2387:2387:2387)) - (PORT datab (3761:3761:3761) (3761:3761:3761)) - (PORT datac (2343:2343:2343) (2343:2343:2343)) - (PORT datad (1974:1974:1974) (1974:1974:1974)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[37\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~122.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2615:2615:2615) (2615:2615:2615)) - (PORT datab (1218:1218:1218) (1218:1218:1218)) - (PORT datac (3327:3327:3327) (3327:3327:3327)) - (PORT datad (1751:1751:1751) (1751:1751:1751)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[38\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (874:874:874) (874:874:874)) - (PORT datab (1977:1977:1977) (1977:1977:1977)) - (PORT datac (3010:3010:3010) (3010:3010:3010)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[38\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[38\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2006:2006:2006) (2006:2006:2006)) - (PORT datac (1495:1495:1495) (1495:1495:1495)) - (PORT datad (2692:2692:2692) (2692:2692:2692)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[38\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3096:3096:3096) (3096:3096:3096)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[38\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2601:2601:2601) (2601:2601:2601)) - (PORT datab (4133:4133:4133) (4133:4133:4133)) - (PORT datac (2537:2537:2537) (2537:2537:2537)) - (PORT datad (3674:3674:3674) (3674:3674:3674)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[38\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~123.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4154:4154:4154) (4154:4154:4154)) - (PORT datab (2530:2530:2530) (2530:2530:2530)) - (PORT datac (2697:2697:2697) (2697:2697:2697)) - (PORT datad (1847:1847:1847) (1847:1847:1847)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[39\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2593:2593:2593) (2593:2593:2593)) - (PORT datab (3452:3452:3452) (3452:3452:3452)) - (PORT datac (940:940:940) (940:940:940)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[39\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[39\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3814:3814:3814) (3814:3814:3814)) - (PORT datab (4492:4492:4492) (4492:4492:4492)) - (PORT datad (2686:2686:2686) (2686:2686:2686)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[39\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3090:3090:3090) (3090:3090:3090)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[39\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3826:3826:3826) (3826:3826:3826)) - (PORT datab (4496:4496:4496) (4496:4496:4496)) - (PORT datac (3183:3183:3183) (3183:3183:3183)) - (PORT datad (919:919:919) (919:919:919)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[39\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~96.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3450:3450:3450) (3450:3450:3450)) - (PORT datab (4090:4090:4090) (4090:4090:4090)) - (PORT datac (1254:1254:1254) (1254:1254:1254)) - (PORT datad (2583:2583:2583) (2583:2583:2583)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[40\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2637:2637:2637) (2637:2637:2637)) - (PORT datab (928:928:928) (928:928:928)) - (PORT datac (3457:3457:3457) (3457:3457:3457)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[40\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[40\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2874:2874:2874) (2874:2874:2874)) - (PORT datac (4283:4283:4283) (4283:4283:4283)) - (PORT datad (938:938:938) (938:938:938)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[40\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3165:3165:3165) (3165:3165:3165)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[40\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3756:3756:3756) (3756:3756:3756)) - (PORT datab (1913:1913:1913) (1913:1913:1913)) - (PORT datac (3128:3128:3128) (3128:3128:3128)) - (PORT datad (3741:3741:3741) (3741:3741:3741)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[40\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~124.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3455:3455:3455) (3455:3455:3455)) - (PORT datab (4053:4053:4053) (4053:4053:4053)) - (PORT datac (4109:4109:4109) (4109:4109:4109)) - (PORT datad (1921:1921:1921) (1921:1921:1921)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[41\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (894:894:894) (894:894:894)) - (PORT datab (3621:3621:3621) (3621:3621:3621)) - (PORT datac (2011:2011:2011) (2011:2011:2011)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[41\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[41\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3287:3287:3287) (3287:3287:3287)) - (PORT datac (964:964:964) (964:964:964)) - (PORT datad (2123:2123:2123) (2123:2123:2123)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[41\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2370:2370:2370) (2370:2370:2370)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[41\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2359:2359:2359) (2359:2359:2359)) - (PORT datab (1984:1984:1984) (1984:1984:1984)) - (PORT datac (2324:2324:2324) (2324:2324:2324)) - (PORT datad (3768:3768:3768) (3768:3768:3768)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[41\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~125.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3341:3341:3341) (3341:3341:3341)) - (PORT datab (3415:3415:3415) (3415:3415:3415)) - (PORT datac (1981:1981:1981) (1981:1981:1981)) - (PORT datad (1927:1927:1927) (1927:1927:1927)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[42\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2870:2870:2870) (2870:2870:2870)) - (PORT datab (3270:3270:3270) (3270:3270:3270)) - (PORT datac (958:958:958) (958:958:958)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[42\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[42\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3010:3010:3010) (3010:3010:3010)) - (PORT datab (3549:3549:3549) (3549:3549:3549)) - (PORT datad (1982:1982:1982) (1982:1982:1982)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[42\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3148:3148:3148) (3148:3148:3148)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[42\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2973:2973:2973) (2973:2973:2973)) - (PORT datab (1987:1987:1987) (1987:1987:1987)) - (PORT datac (2528:2528:2528) (2528:2528:2528)) - (PORT datad (2937:2937:2937) (2937:2937:2937)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[42\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~126.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2674:2674:2674) (2674:2674:2674)) - (PORT datab (2713:2713:2713) (2713:2713:2713)) - (PORT datac (4421:4421:4421) (4421:4421:4421)) - (PORT datad (1135:1135:1135) (1135:1135:1135)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[43\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3579:3579:3579) (3579:3579:3579)) - (PORT datab (2597:2597:2597) (2597:2597:2597)) - (PORT datac (949:949:949) (949:949:949)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[43\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[43\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (4489:4489:4489) (4489:4489:4489)) - (PORT datac (2035:2035:2035) (2035:2035:2035)) - (PORT datad (3835:3835:3835) (3835:3835:3835)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[43\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3090:3090:3090) (3090:3090:3090)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[43\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (878:878:878) (878:878:878)) - (PORT datab (4499:4499:4499) (4499:4499:4499)) - (PORT datac (3185:3185:3185) (3185:3185:3185)) - (PORT datad (3847:3847:3847) (3847:3847:3847)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[43\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~97.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3448:3448:3448) (3448:3448:3448)) - (PORT datab (4089:4089:4089) (4089:4089:4089)) - (PORT datac (1254:1254:1254) (1254:1254:1254)) - (PORT datad (2583:2583:2583) (2583:2583:2583)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[44\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2647:2647:2647) (2647:2647:2647)) - (PORT datab (3421:3421:3421) (3421:3421:3421)) - (PORT datac (939:939:939) (939:939:939)) - (PORT datad (534:534:534) (534:534:534)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[44\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[44\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3005:3005:3005) (3005:3005:3005)) - (PORT datab (3543:3543:3543) (3543:3543:3543)) - (PORT datad (1302:1302:1302) (1302:1302:1302)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[44\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3148:3148:3148) (3148:3148:3148)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[44\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3740:3740:3740) (3740:3740:3740)) - (PORT datab (2012:2012:2012) (2012:2012:2012)) - (PORT datac (3114:3114:3114) (3114:3114:3114)) - (PORT datad (3736:3736:3736) (3736:3736:3736)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[44\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~98.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2683:2683:2683) (2683:2683:2683)) - (PORT datab (2721:2721:2721) (2721:2721:2721)) - (PORT datac (4441:4441:4441) (4441:4441:4441)) - (PORT datad (1338:1338:1338) (1338:1338:1338)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[45\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3569:3569:3569) (3569:3569:3569)) - (PORT datab (2602:2602:2602) (2602:2602:2602)) - (PORT datac (950:950:950) (950:950:950)) - (PORT datad (305:305:305) (305:305:305)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[45\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[45\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2386:2386:2386) (2386:2386:2386)) - (PORT datac (2341:2341:2341) (2341:2341:2341)) - (PORT datad (2620:2620:2620) (2620:2620:2620)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[45\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (2985:2985:2985) (2985:2985:2985)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[45\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2264:2264:2264) (2264:2264:2264)) - (PORT datab (894:894:894) (894:894:894)) - (PORT datac (2453:2453:2453) (2453:2453:2453)) - (PORT datad (3770:3770:3770) (3770:3770:3770)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[45\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~99.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2859:2859:2859) (2859:2859:2859)) - (PORT datab (3395:3395:3395) (3395:3395:3395)) - (PORT datac (801:801:801) (801:801:801)) - (PORT datad (1896:1896:1896) (1896:1896:1896)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[46\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1239:1239:1239) (1239:1239:1239)) - (PORT datab (920:920:920) (920:920:920)) - (PORT datac (4215:4215:4215) (4215:4215:4215)) - (PORT datad (728:728:728) (728:728:728)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[46\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[46\].lecomb) - (DELAY - (ABSOLUTE - (PORT datab (921:921:921) (921:921:921)) - (PORT datac (1486:1486:1486) (1486:1486:1486)) - (PORT datad (2687:2687:2687) (2687:2687:2687)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[46\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3096:3096:3096) (3096:3096:3096)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[46\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3756:3756:3756) (3756:3756:3756)) - (PORT datab (3729:3729:3729) (3729:3729:3729)) - (PORT datac (3127:3127:3127) (3127:3127:3127)) - (PORT datad (2818:2818:2818) (2818:2818:2818)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[46\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE Decoder0\~100.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3247:3247:3247) (3247:3247:3247)) - (PORT datab (1931:1931:1931) (1931:1931:1931)) - (PORT datac (4799:4799:4799) (4799:4799:4799)) - (PORT datad (719:719:719) (719:719:719)) - (IOPATH dataa combout (914:914:914) (914:914:914)) - (IOPATH datab combout (740:740:740) (740:740:740)) - (IOPATH datac combout (511:511:511) (511:511:511)) - (IOPATH datad combout (200:200:200) (200:200:200)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache_line_sdata\[47\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1910:1910:1910) (1910:1910:1910)) - (PORT datab (911:911:911) (911:911:911)) - (PORT datac (3391:3391:3391) (3391:3391:3391)) - (PORT datad (1122:1122:1122) (1122:1122:1122)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache_line_sdata\[47\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE cache2_line_sdata\[47\].lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2432:2432:2432) (2432:2432:2432)) - (PORT datac (3514:3514:3514) (3514:3514:3514)) - (PORT datad (3913:3913:3913) (3913:3913:3913)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE cache2_line_sdata\[47\].lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (PORT ena (3290:3290:3290) (3290:3290:3290)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (SETUP ena (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - (HOLD ena (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_high_voltage\[47\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3752:3752:3752) (3752:3752:3752)) - (PORT datab (2604:2604:2604) (2604:2604:2604)) - (PORT datac (3124:3124:3124) (3124:3124:3124)) - (PORT datad (3739:3739:3739) (3739:3739:3739)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_high_voltage\[47\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[0\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3735:3735:3735) (3735:3735:3735)) - (PORT datac (2783:2783:2783) (2783:2783:2783)) - (PORT datad (3371:3371:3371) (3371:3371:3371)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[0\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[1\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2490:2490:2490) (2490:2490:2490)) - (PORT datac (3043:3043:3043) (3043:3043:3043)) - (PORT datad (3852:3852:3852) (3852:3852:3852)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[1\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[2\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2984:2984:2984) (2984:2984:2984)) - (PORT datab (2099:2099:2099) (2099:2099:2099)) - (PORT datac (2538:2538:2538) (2538:2538:2538)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[2\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[3\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1936:1936:1936) (1936:1936:1936)) - (PORT datac (3019:3019:3019) (3019:3019:3019)) - (PORT datad (4249:4249:4249) (4249:4249:4249)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[3\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[4\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (1933:1933:1933) (1933:1933:1933)) - (PORT datac (3016:3016:3016) (3016:3016:3016)) - (PORT datad (4245:4245:4245) (4245:4245:4245)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[4\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[5\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2263:2263:2263) (2263:2263:2263)) - (PORT datab (920:920:920) (920:920:920)) - (PORT datac (2454:2454:2454) (2454:2454:2454)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[5\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[6\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2897:2897:2897) (2897:2897:2897)) - (PORT datac (1977:1977:1977) (1977:1977:1977)) - (PORT datad (4065:4065:4065) (4065:4065:4065)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[6\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[7\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2023:2023:2023) (2023:2023:2023)) - (PORT datac (4086:4086:4086) (4086:4086:4086)) - (PORT datad (3011:3011:3011) (3011:3011:3011)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[7\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[8\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3736:3736:3736) (3736:3736:3736)) - (PORT datac (2784:2784:2784) (2784:2784:2784)) - (PORT datad (2028:2028:2028) (2028:2028:2028)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[8\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[9\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3069:3069:3069) (3069:3069:3069)) - (PORT datac (3583:3583:3583) (3583:3583:3583)) - (PORT datad (2118:2118:2118) (2118:2118:2118)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[9\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[10\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3642:3642:3642) (3642:3642:3642)) - (PORT datac (5249:5249:5249) (5249:5249:5249)) - (PORT datad (2209:2209:2209) (2209:2209:2209)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[10\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[11\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3067:3067:3067) (3067:3067:3067)) - (PORT datac (3581:3581:3581) (3581:3581:3581)) - (PORT datad (2605:2605:2605) (2605:2605:2605)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[11\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[12\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3728:3728:3728) (3728:3728:3728)) - (PORT datac (2776:2776:2776) (2776:2776:2776)) - (PORT datad (2135:2135:2135) (2135:2135:2135)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[12\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[13\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3060:3060:3060) (3060:3060:3060)) - (PORT datac (3573:3573:3573) (3573:3573:3573)) - (PORT datad (2661:2661:2661) (2661:2661:2661)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[13\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[14\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2341:2341:2341) (2341:2341:2341)) - (PORT datac (4088:4088:4088) (4088:4088:4088)) - (PORT datad (3012:3012:3012) (3012:3012:3012)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[14\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[15\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3546:3546:3546) (3546:3546:3546)) - (PORT datac (5317:5317:5317) (5317:5317:5317)) - (PORT datad (2048:2048:2048) (2048:2048:2048)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[15\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[16\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2141:2141:2141) (2141:2141:2141)) - (PORT datab (3641:3641:3641) (3641:3641:3641)) - (PORT datac (5248:5248:5248) (5248:5248:5248)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[16\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[17\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1914:1914:1914) (1914:1914:1914)) - (PORT datac (5314:5314:5314) (5314:5314:5314)) - (PORT datad (3553:3553:3553) (3553:3553:3553)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[17\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[18\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3539:3539:3539) (3539:3539:3539)) - (PORT datac (5313:5313:5313) (5313:5313:5313)) - (PORT datad (1377:1377:1377) (1377:1377:1377)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[18\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[19\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2039:2039:2039) (2039:2039:2039)) - (PORT datac (3009:3009:3009) (3009:3009:3009)) - (PORT datad (4231:4231:4231) (4231:4231:4231)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[19\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[20\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4071:4071:4071) (4071:4071:4071)) - (PORT datab (2909:2909:2909) (2909:2909:2909)) - (PORT datad (1868:1868:1868) (1868:1868:1868)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[20\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[21\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (1860:1860:1860) (1860:1860:1860)) - (PORT datac (4971:4971:4971) (4971:4971:4971)) - (PORT datad (3512:3512:3512) (3512:3512:3512)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[21\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[22\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3545:3545:3545) (3545:3545:3545)) - (PORT datac (5317:5317:5317) (5317:5317:5317)) - (PORT datad (1916:1916:1916) (1916:1916:1916)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[22\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[23\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3536:3536:3536) (3536:3536:3536)) - (PORT datac (5167:5167:5167) (5167:5167:5167)) - (PORT datad (2102:2102:2102) (2102:2102:2102)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[23\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[24\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3523:3523:3523) (3523:3523:3523)) - (PORT datac (5159:5159:5159) (5159:5159:5159)) - (PORT datad (2025:2025:2025) (2025:2025:2025)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[24\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[25\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3534:3534:3534) (3534:3534:3534)) - (PORT datac (5164:5164:5164) (5164:5164:5164)) - (PORT datad (1904:1904:1904) (1904:1904:1904)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[25\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[26\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (4051:4051:4051) (4051:4051:4051)) - (PORT datab (2898:2898:2898) (2898:2898:2898)) - (PORT datad (915:915:915) (915:915:915)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[26\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[27\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3526:3526:3526) (3526:3526:3526)) - (PORT datac (5301:5301:5301) (5301:5301:5301)) - (PORT datad (1992:1992:1992) (1992:1992:1992)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[27\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[28\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (5207:5207:5207) (5207:5207:5207)) - (PORT datab (2068:2068:2068) (2068:2068:2068)) - (PORT datac (3664:3664:3664) (3664:3664:3664)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[28\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[29\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2264:2264:2264) (2264:2264:2264)) - (PORT datab (930:930:930) (930:930:930)) - (PORT datac (2456:2456:2456) (2456:2456:2456)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[29\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[30\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2860:2860:2860) (2860:2860:2860)) - (PORT datac (4997:4997:4997) (4997:4997:4997)) - (PORT datad (1943:1943:1943) (1943:1943:1943)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[30\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[31\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2866:2866:2866) (2866:2866:2866)) - (PORT datac (5006:5006:5006) (5006:5006:5006)) - (PORT datad (2075:2075:2075) (2075:2075:2075)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[31\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[32\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3831:3831:3831) (3831:3831:3831)) - (PORT datab (4498:4498:4498) (4498:4498:4498)) - (PORT datad (2005:2005:2005) (2005:2005:2005)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[32\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[33\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2368:2368:2368) (2368:2368:2368)) - (PORT datab (911:911:911) (911:911:911)) - (PORT datac (2327:2327:2327) (2327:2327:2327)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[33\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[34\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (3628:3628:3628) (3628:3628:3628)) - (PORT datac (5234:5234:5234) (5234:5234:5234)) - (PORT datad (2126:2126:2126) (2126:2126:2126)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[34\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[35\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2251:2251:2251) (2251:2251:2251)) - (PORT datab (931:931:931) (931:931:931)) - (PORT datac (2442:2442:2442) (2442:2442:2442)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[35\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[36\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3719:3719:3719) (3719:3719:3719)) - (PORT datac (2758:2758:2758) (2758:2758:2758)) - (PORT datad (2558:2558:2558) (2558:2558:2558)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[36\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[37\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2372:2372:2372) (2372:2372:2372)) - (PORT datac (2331:2331:2331) (2331:2331:2331)) - (PORT datad (1969:1969:1969) (1969:1969:1969)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[37\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[38\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (4133:4133:4133) (4133:4133:4133)) - (PORT datac (2664:2664:2664) (2664:2664:2664)) - (PORT datad (2492:2492:2492) (2492:2492:2492)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[38\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[39\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3829:3829:3829) (3829:3829:3829)) - (PORT datab (4497:4497:4497) (4497:4497:4497)) - (PORT datad (920:920:920) (920:920:920)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[39\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[40\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3745:3745:3745) (3745:3745:3745)) - (PORT datac (3117:3117:3117) (3117:3117:3117)) - (PORT datad (1916:1916:1916) (1916:1916:1916)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[40\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[41\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (2381:2381:2381) (2381:2381:2381)) - (PORT datac (2340:2340:2340) (2340:2340:2340)) - (PORT datad (1976:1976:1976) (1976:1976:1976)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[41\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[42\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2476:2476:2476) (2476:2476:2476)) - (PORT datac (3027:3027:3027) (3027:3027:3027)) - (PORT datad (1988:1988:1988) (1988:1988:1988)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[42\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[43\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT datab (2405:2405:2405) (2405:2405:2405)) - (PORT datac (2336:2336:2336) (2336:2336:2336)) - (PORT datad (2646:2646:2646) (2646:2646:2646)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[43\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[44\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3732:3732:3732) (3732:3732:3732)) - (PORT datac (3111:3111:3111) (3111:3111:3111)) - (PORT datad (2010:2010:2010) (2010:2010:2010)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[44\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[45\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3736:3736:3736) (3736:3736:3736)) - (PORT datab (3063:3063:3063) (3063:3063:3063)) - (PORT datad (2185:2185:2185) (2185:2185:2185)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datab regin (1061:1061:1061) (1061:1061:1061)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[45\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[46\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3757:3757:3757) (3757:3757:3757)) - (PORT datac (3128:3128:3128) (3128:3128:3128)) - (PORT datad (2820:2820:2820) (2820:2820:2820)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[46\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_asynch_lcell") - (INSTANCE signal_low_voltage\[47\]\~reg0.lecomb) - (DELAY - (ABSOLUTE - (PORT dataa (3754:3754:3754) (3754:3754:3754)) - (PORT datac (3125:3125:3125) (3125:3125:3125)) - (PORT datad (2603:2603:2603) (2603:2603:2603)) - (IOPATH dataa regin (1183:1183:1183) (1183:1183:1183)) - (IOPATH datac regin (804:804:804) (804:804:804)) - (IOPATH datad regin (591:591:591) (591:591:591)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_lcell_register") - (INSTANCE signal_low_voltage\[47\]\~reg0.lereg) - (DELAY - (ABSOLUTE - (PORT aclr (9558:9558:9558) (9558:9558:9558)) - (PORT clk (2656:2656:2656) (2656:2656:2656)) - (IOPATH (posedge clk) regout (376:376:376) (376:376:376)) - (IOPATH (posedge aclr) regout (577:577:577) (577:577:577)) - ) - ) - (TIMINGCHECK - (SETUP datain (posedge clk) (333:333:333)) - (HOLD datain (posedge clk) (221:221:221)) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[0\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2514:2514:2514) (2514:2514:2514)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[1\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2597:2597:2597) (2597:2597:2597)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[2\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2035:2035:2035) (2035:2035:2035)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[3\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2523:2523:2523) (2523:2523:2523)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[4\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1951:1951:1951) (1951:1951:1951)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[5\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3285:3285:3285) (3285:3285:3285)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[6\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3258:3258:3258) (3258:3258:3258)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[7\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2485:2485:2485) (2485:2485:2485)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[8\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2456:2456:2456) (2456:2456:2456)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[9\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2667:2667:2667) (2667:2667:2667)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[10\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2922:2922:2922) (2922:2922:2922)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[11\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2655:2655:2655) (2655:2655:2655)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[12\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3339:3339:3339) (3339:3339:3339)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[13\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3199:3199:3199) (3199:3199:3199)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[14\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3178:3178:3178) (3178:3178:3178)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[15\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3396:3396:3396) (3396:3396:3396)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[16\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2824:2824:2824) (2824:2824:2824)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[17\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2689:2689:2689) (2689:2689:2689)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[18\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2861:2861:2861) (2861:2861:2861)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[19\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2743:2743:2743) (2743:2743:2743)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[20\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2794:2794:2794) (2794:2794:2794)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[21\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1991:1991:1991) (1991:1991:1991)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[22\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2793:2793:2793) (2793:2793:2793)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[23\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2745:2745:2745) (2745:2745:2745)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[24\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2721:2721:2721) (2721:2721:2721)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[25\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2044:2044:2044) (2044:2044:2044)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[26\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2024:2024:2024) (2024:2024:2024)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[27\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2551:2551:2551) (2551:2551:2551)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[28\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2127:2127:2127) (2127:2127:2127)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[29\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3425:3425:3425) (3425:3425:3425)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[30\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1981:1981:1981) (1981:1981:1981)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[31\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2029:2029:2029) (2029:2029:2029)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[32\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1953:1953:1953) (1953:1953:1953)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[33\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2535:2535:2535) (2535:2535:2535)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[34\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2757:2757:2757) (2757:2757:2757)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[35\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2740:2740:2740) (2740:2740:2740)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[36\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2648:2648:2648) (2648:2648:2648)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[37\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2028:2028:2028) (2028:2028:2028)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[38\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1941:1941:1941) (1941:1941:1941)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[39\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2580:2580:2580) (2580:2580:2580)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[40\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3231:3231:3231) (3231:3231:3231)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[41\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3072:3072:3072) (3072:3072:3072)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[42\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3189:3189:3189) (3189:3189:3189)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[43\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3106:3106:3106) (3106:3106:3106)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[44\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3119:3119:3119) (3119:3119:3119)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[45\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3165:3165:3165) (3165:3165:3165)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[46\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3155:3155:3155) (3155:3155:3155)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_high_voltage\[47\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3142:3142:3142) (3142:3142:3142)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[0\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1946:1946:1946) (1946:1946:1946)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[1\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2043:2043:2043) (2043:2043:2043)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[2\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2049:2049:2049) (2049:2049:2049)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[3\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1946:1946:1946) (1946:1946:1946)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[4\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1941:1941:1941) (1941:1941:1941)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[5\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3117:3117:3117) (3117:3117:3117)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[6\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3237:3237:3237) (3237:3237:3237)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[7\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1873:1873:1873) (1873:1873:1873)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[8\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3445:3445:3445) (3445:3445:3445)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[9\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2820:2820:2820) (2820:2820:2820)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[10\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3322:3322:3322) (3322:3322:3322)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[11\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3128:3128:3128) (3128:3128:3128)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[12\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3317:3317:3317) (3317:3317:3317)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[13\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3189:3189:3189) (3189:3189:3189)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[14\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3124:3124:3124) (3124:3124:3124)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[15\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2914:2914:2914) (2914:2914:2914)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[16\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2714:2714:2714) (2714:2714:2714)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[17\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2802:2802:2802) (2802:2802:2802)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[18\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2713:2713:2713) (2713:2713:2713)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[19\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2736:2736:2736) (2736:2736:2736)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[20\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3196:3196:3196) (3196:3196:3196)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[21\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (1931:1931:1931) (1931:1931:1931)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[22\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2736:2736:2736) (2736:2736:2736)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[23\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2707:2707:2707) (2707:2707:2707)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[24\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2487:2487:2487) (2487:2487:2487)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[25\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2431:2431:2431) (2431:2431:2431)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[26\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2656:2656:2656) (2656:2656:2656)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[27\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2031:2031:2031) (2031:2031:2031)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[28\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2284:2284:2284) (2284:2284:2284)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[29\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3097:3097:3097) (3097:3097:3097)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[30\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2116:2116:2116) (2116:2116:2116)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[31\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2107:2107:2107) (2107:2107:2107)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[32\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2508:2508:2508) (2508:2508:2508)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[33\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2680:2680:2680) (2680:2680:2680)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[34\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2739:2739:2739) (2739:2739:2739)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[35\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2593:2593:2593) (2593:2593:2593)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[36\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3231:3231:3231) (3231:3231:3231)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[37\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2612:2612:2612) (2612:2612:2612)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[38\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2519:2519:2519) (2519:2519:2519)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[39\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3094:3094:3094) (3094:3094:3094)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[40\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3192:3192:3192) (3192:3192:3192)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[41\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3037:3037:3037) (3037:3037:3037)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[42\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (3262:3262:3262) (3262:3262:3262)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[43\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2018:2018:2018) (2018:2018:2018)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[44\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2461:2461:2461) (2461:2461:2461)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[45\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2454:2454:2454) (2454:2454:2454)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[46\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2631:2631:2631) (2631:2631:2631)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) - (CELL - (CELLTYPE "maxii_io") - (INSTANCE signal_low_voltage\[47\]\~I) - (DELAY - (ABSOLUTE - (PORT datain (2451:2451:2451) (2451:2451:2451)) - (IOPATH datain padio (2322:2322:2322) (2322:2322:2322)) - ) - ) - ) -) diff --git a/firmware/simulation/modelsim/PF1_v.sdo_typ.csd b/firmware/simulation/modelsim/PF1_v.sdo_typ.csd deleted file mode 100644 index af2d706..0000000 Binary files a/firmware/simulation/modelsim/PF1_v.sdo_typ.csd and /dev/null differ diff --git a/firmware/simulation/modelsim/gate_work/_info b/firmware/simulation/modelsim/gate_work/_info deleted file mode 100644 index 9177f4e..0000000 --- a/firmware/simulation/modelsim/gate_work/_info +++ /dev/null @@ -1,61 +0,0 @@ -m255 -K4 -z2 -!s11f vlog 2020.1 2020.02, Feb 28 2020 -13 -!s112 1.1 -!i10d 8192 -!i10e 25 -!i10f 100 -cModel Technology -Z0 dC:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim -vPF1 -!s110 1636361877 -!i10b 1 -!s100 2iN[EhbCcBKG7nD^PggF22 -Z1 !s11b Dg1SIo80bB@j0V0VzS_@n1 -ILFl@_b88>>PT3nUVA@jHQ1 -Z2 VDg1SIo80bB@j0V0VzS_@n1 -R0 -w1636031352 -8PF1.vo -FPF1.vo -!i122 0 -L0 32 18511 -Z3 OV;L;2020.1;71 -r1 -!s85 0 -31 -!s108 1636361877.000000 -!s107 PF1.vo| -!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+.|PF1.vo| -!i113 1 -Z4 o-vlog01compat -work work -!s92 -vlog01compat -work work +incdir+. -Z5 tCvgOpt 0 -n@p@f1 -vtb_PF1 -!s110 1636361878 -!i10b 1 -!s100 AdJ>?JjY3I]?hdKECEN3>0 -R1 -IalfQ]oI7eEk>K9CEfaTc[3 -R2 -R0 -w1636027979 -8C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v -FC:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v -!i122 1 -L0 2 57 -R3 -r1 -!s85 0 -31 -!s108 1636361878.000000 -!s107 C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v| -!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/Users/miaow/Desktop/valve_board_kun|C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v| -!i113 1 -R4 -!s92 -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun -R5 -ntb_@p@f1 diff --git a/firmware/simulation/modelsim/gate_work/_lib.qdb b/firmware/simulation/modelsim/gate_work/_lib.qdb deleted file mode 100644 index 4db8108..0000000 Binary files a/firmware/simulation/modelsim/gate_work/_lib.qdb and /dev/null differ diff --git a/firmware/simulation/modelsim/gate_work/_lib1_0.qdb b/firmware/simulation/modelsim/gate_work/_lib1_0.qdb deleted file mode 100644 index c0efc1c..0000000 Binary files a/firmware/simulation/modelsim/gate_work/_lib1_0.qdb and /dev/null differ diff --git a/firmware/simulation/modelsim/gate_work/_lib1_0.qpg b/firmware/simulation/modelsim/gate_work/_lib1_0.qpg deleted file mode 100644 index 32cf9a1..0000000 Binary files a/firmware/simulation/modelsim/gate_work/_lib1_0.qpg and /dev/null differ diff --git a/firmware/simulation/modelsim/gate_work/_lib1_0.qtl b/firmware/simulation/modelsim/gate_work/_lib1_0.qtl deleted file mode 100644 index df79b77..0000000 Binary files a/firmware/simulation/modelsim/gate_work/_lib1_0.qtl and /dev/null differ diff --git a/firmware/simulation/modelsim/gate_work/_vmake b/firmware/simulation/modelsim/gate_work/_vmake deleted file mode 100644 index 37aa36a..0000000 --- a/firmware/simulation/modelsim/gate_work/_vmake +++ /dev/null @@ -1,4 +0,0 @@ -m255 -K4 -z0 -cModel Technology diff --git a/firmware/simulation/modelsim/modelsim.ini b/firmware/simulation/modelsim/modelsim.ini deleted file mode 100644 index 29480d4..0000000 --- a/firmware/simulation/modelsim/modelsim.ini +++ /dev/null @@ -1,324 +0,0 @@ -; Copyright 1991-2009 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -others = $MODEL_TECH/../modelsim.ini - -; Altera Primitive libraries -; -; VHDL Section -; -; -; Verilog Section -; - -work = rtl_work -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -; Default or value of 3 or 2008 for VHDL-2008. -VHDL93 = 2002 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -[vlog] - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Turn on incremental compilation of modules. Default is off. -; Incremental = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -[vsim] -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = ps - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 5000 - -; Directive to license manager: -; vhdl Immediately reserve a VHDL license -; vlog Immediately reserve a Verilog license -; plus Immediately reserve a VHDL and Verilog license -; nomgc Do not look for Mentor Graphics Licenses -; nomti Do not look for Model Technology Licenses -; noqueue Do not wait in the license queue when a license isn't available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license -; License = plus - -; Stop the simulator after a VHDL/Verilog assertion message -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Assertion Message Format -; %S - Severity Level -; %R - Report Message -; %T - Time of assertion -; %D - Delta -; %I - Instance or Region pathname (if available) -; %% - print '%' character -; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Assertion File - alternate file for storing VHDL/Verilog assertion messages -; AssertFile = assert.log - -; Default radix for all windows and commands... -; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned -DefaultRadix = symbolic - -; VSIM Startup command -; Startup = do startup.do - -; File for saving command transcript -TranscriptFile = transcript - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example, sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings from the std_logic_arith, std_logic_unsigned -; and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from the IEEE numeric_std and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Control the format of the (VHDL) FOR generate statement label -; for each iteration. Do not quote it. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate_label; the %d represents the generate parameter value -; at a particular generate iteration (this is the position number if -; the generate parameter is of an enumeration type). Embedded whitespace -; is allowed (but discouraged); leading and trailing whitespace is ignored. -; Application of the format must result in a unique scope name over all -; such names in the design so that name lookup can function properly. -; GenerateFormat = %s__%d - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -; DefaultRestartOptions = -force - -; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs -; (> 500 megabyte memory footprint). Default is disabled. -; Specify number of megabytes to lock. -; LockedMemory = 1000 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -; Automatic SDF compilation -; Disables automatic compilation of SDF files in flows that support it. -; Default is on, uncomment to turn off. -; NoAutoSDFCompile = 1 - -[lmc] - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; Examples: -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3043 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of elaboration/runtime messages. -; The default is to have messages appear in the transcript and -; recorded in the wlf file (messages that are recorded in the -; wlf file can be viewed in the MsgViewer). The other settings -; are to send messages only to the transcript or only to the -; wlf file. The valid values are -; both {default} -; tran {transcript only} -; wlf {wlf file only} -; msgmode = both diff --git a/firmware/simulation/modelsim/msim_transcript b/firmware/simulation/modelsim/msim_transcript deleted file mode 100644 index 412ee64..0000000 --- a/firmware/simulation/modelsim/msim_transcript +++ /dev/null @@ -1,57 +0,0 @@ -# Reading pref.tcl -# do PF1_run_msim_rtl_verilog.do -# if {[file exists rtl_work]} { -# vdel -lib rtl_work -all -# } -# vlib rtl_work -# vmap work rtl_work -# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020 -# vmap work rtl_work -# Copying C:/ProgramData/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini -# Modifying modelsim.ini -# -# vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/PF1.v} -# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -# Start time: 12:49:27 on Nov 09,2021 -# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/miaow/Desktop/valve_board_kun" C:/Users/miaow/Desktop/valve_board_kun/PF1.v -# -- Compiling module PF1 -# -# Top level modules: -# PF1 -# End time: 12:49:28 on Nov 09,2021, Elapsed time: 0:00:01 -# Errors: 0, Warnings: 0 -# -# vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v} -# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -# Start time: 12:49:28 on Nov 09,2021 -# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/miaow/Desktop/valve_board_kun" C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v -# -- Compiling module tb_PF1 -# -# Top level modules: -# tb_PF1 -# End time: 12:49:28 on Nov 09,2021, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -# -# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_PF1 -# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs=""+acc"" tb_PF1 -# Start time: 12:49:28 on Nov 09,2021 -# Loading work.tb_PF1 -# Loading work.PF1 -# ** Warning: (vsim-3015) [PCDPC] - Port size (48) does not match connection size (49) for port 'signal_high_voltage'. The port definition is at: C:/Users/miaow/Desktop/valve_board_kun/PF1.v(13). -# Time: 0 ps Iteration: 0 Instance: /tb_PF1/inst_PF1 File: C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v Line: 12 -# ** Warning: (vsim-3015) [PCDPC] - Port size (48) does not match connection size (49) for port 'signal_low_voltage'. The port definition is at: C:/Users/miaow/Desktop/valve_board_kun/PF1.v(14). -# Time: 0 ps Iteration: 0 Instance: /tb_PF1/inst_PF1 File: C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v Line: 12 -# -# add wave * -# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf -# File in use by: miaow Hostname: DESKTOP-RVHBS6P ProcessID: 1008 -# Attempting to use alternate WLF file "./wlftyh13a8". -# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf -# Using alternate file: ./wlftyh13a8 -# view structure -# .main_pane.structure.interior.cs.body.struct -# view signals -# .main_pane.objects.interior.cs.body.tree -# run 5 ms -# End time: 12:49:48 on Nov 09,2021, Elapsed time: 0:00:20 -# Errors: 0, Warnings: 4 diff --git a/firmware/simulation/modelsim/rtl_work/_info b/firmware/simulation/modelsim/rtl_work/_info deleted file mode 100644 index 5264fdf..0000000 --- a/firmware/simulation/modelsim/rtl_work/_info +++ /dev/null @@ -1,61 +0,0 @@ -m255 -K4 -z2 -!s11f vlog 2020.1 2020.02, Feb 28 2020 -13 -!s112 1.1 -!i10d 8192 -!i10e 25 -!i10f 100 -cModel Technology -Z0 dC:/Users/miaow/Desktop/valve_board_kun/simulation/modelsim -vPF1 -Z1 !s110 1636433368 -!i10b 1 -!s100 gUW?JjY3I]?hdKECEN3>0 -R2 -IalfQ]oI7eEk>K9CEfaTc[3 -R3 -R0 -w1636027979 -8C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v -FC:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v -!i122 1 -L0 2 57 -R4 -r1 -!s85 0 -31 -!s108 1636433368.000000 -!s107 C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v| -!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/Users/miaow/Desktop/valve_board_kun|C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v| -!i113 1 -R5 -R6 -R7 -ntb_@p@f1 diff --git a/firmware/simulation/modelsim/rtl_work/_lib.qdb b/firmware/simulation/modelsim/rtl_work/_lib.qdb deleted file mode 100644 index 4ee8f1d..0000000 Binary files a/firmware/simulation/modelsim/rtl_work/_lib.qdb and /dev/null differ diff --git a/firmware/simulation/modelsim/rtl_work/_lib1_0.qdb b/firmware/simulation/modelsim/rtl_work/_lib1_0.qdb deleted file mode 100644 index 2f35024..0000000 Binary files a/firmware/simulation/modelsim/rtl_work/_lib1_0.qdb and /dev/null differ diff --git a/firmware/simulation/modelsim/rtl_work/_lib1_0.qpg b/firmware/simulation/modelsim/rtl_work/_lib1_0.qpg deleted file mode 100644 index f37e0f6..0000000 Binary files a/firmware/simulation/modelsim/rtl_work/_lib1_0.qpg and /dev/null differ diff --git a/firmware/simulation/modelsim/rtl_work/_lib1_0.qtl b/firmware/simulation/modelsim/rtl_work/_lib1_0.qtl deleted file mode 100644 index eb61ee6..0000000 Binary files a/firmware/simulation/modelsim/rtl_work/_lib1_0.qtl and /dev/null differ diff --git a/firmware/simulation/modelsim/rtl_work/_vmake b/firmware/simulation/modelsim/rtl_work/_vmake deleted file mode 100644 index 37aa36a..0000000 --- a/firmware/simulation/modelsim/rtl_work/_vmake +++ /dev/null @@ -1,4 +0,0 @@ -m255 -K4 -z0 -cModel Technology diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/_info b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/_info deleted file mode 100644 index 8d71b2c..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/_info +++ /dev/null @@ -1,549 +0,0 @@ -m255 -K3 -13 -cModel Technology -Z0 dC:\Users\3304\Desktop\codes\codes from HY\PF_old bottom\PF_DS0401\PF_DS\simulation\modelsim -Xaltera_lnsim_functions -Z1 DXx6 sv_std 3 std 0 22 :CP]PHbGOHGT_H:3KF`8L2 -!s100 kUO@2c`XBVEV3[6_1V8bL0 -IQHU`?VeblhY[:6iMnlacT3 -VQHU`?VeblhY[:6iMnlacT3 -S1 -Z2 dC:\Users\3304\Desktop\codes\codes from HY\PF_old bottom\PF_DS0401\PF_DS\simulation\modelsim -Z3 w1303970098 -Z4 8d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv -Z5 Fd:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv -L0 237 -Z6 OL;L;10.0c;49 -r1 -!s85 0 -31 -Z7 !s108 1386757432.922000 -Z8 !s107 d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv| -Z9 !s90 -reportprogress|300|-sv|-work|altera_lnsim_ver|d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv| -Z10 o-sv -work altera_lnsim_ver -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF -valtera_mult_add -R1 -!s100 1^=QnN[8_GUAhXVhmZ3GM2 -IZFMi;3a4WchB6]aNF^N1h0 -VZOnS3Xkji;G9J1Rb>A`N^0 -Z11 !s105 altera_lnsim_sv_unit -S1 -R2 -R3 -R4 -R5 -L0 3572 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -valtera_pll -R1 -!s100 ]hPSV0cIc0Pi1ALfR]NL@0 -I95CB?boLE8^]G^7ko2L?O1 -VK:O6aMf91bjIzA:g?k5Bl3 -R11 -S1 -R2 -R3 -R4 -R5 -L0 14 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vama_accumulator_function -R1 -!s100 7LWL4KhAR]T^UH[N026e@3 -Iz@^IAobnFHXM]CVQ2A>k20 -VILb]XIj2_^R35[1S;@@_Q2 -R11 -S1 -R2 -R3 -R4 -R5 -L0 5523 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vama_adder_function -R1 -!s100 UeQTA7CaN5[3RiEmZJ`P_TnCKUJOXO2nF3 -VM3?e1@C2k>HAXlF:gg7JT3 -R11 -S1 -R2 -R3 -R4 -R5 -L0 5042 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vama_coef_reg_ext_function -R1 -!s100 11gfKmz>;XiaSz`zZE2KY0 -I`E@NJ=V]S>9@DNL_P:2 -R11 -S1 -R2 -R3 -R4 -R5 -L0 4454 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vama_multiplier_function -R1 -!s100 o9MUWznTYI=P]68J573[5:F0dKI9b0kWCb^3 -I=nno[]`hRSOk3 -R11 -S1 -R2 -R3 -R4 -R5 -L0 4625 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vama_scanchain -R1 -!s100 Lfb9hI1^cbJoIh40dCnaz1 -IJ=>6z7HS3@0eabLH]A`S[1 -VT`g>zAn8SzZWc>D<7Rz2C3 -R11 -S1 -R2 -R3 -R4 -R5 -L0 5732 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vama_signed_extension_function -R1 -!s100 53HnYLQX7d@G03IYAgOi9MF4VMj2 -Ic?0C>mVe`fUFWZPOFhGFe2 -R11 -S1 -R2 -R3 -R4 -R5 -L0 5616 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vcommon_28nm_mlab_cell -R1 -Z12 DXx4 work 22 altera_lnsim_functions 0 22 QHU`?VeblhY[:6iMnlacT3 -!s100 EN@@6`oI6gRh`=j;L4VFFMj8X?5I3 -Vi7Md`63=]JPM?EY8zHUfa0 -R11 -S1 -R2 -R3 -R4 -R5 -L0 3002 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vcommon_28nm_mlab_cell_pulse_generator -R1 -!s100 YB:i2J5T59fH^[SLQbEU[1 -ITkLbURHRK??eidC]k_alW0 -VQ8S5lOVPl0j^[<4H<1>d32 -R11 -S1 -R2 -R3 -R4 -R5 -L0 2955 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vcommon_28nm_ram_block -R1 -R12 -!s100 ^8Y?;:LO9GlAmRjk>7hnk1 -ICH;[1AmNC[]mHVhaDo6mO3 -V>:9834Ag3A6z_Faf8c?fl1 -R11 -S1 -R2 -R3 -R4 -R5 -L0 1160 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vcommon_28nm_ram_pulse_generator -R1 -!s100 j0i`UY`aQK@Kh8F;^BNI3Y5_Xi;YFX[MG1 -R11 -S1 -R2 -R3 -R4 -R5 -L0 1029 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vcommon_28nm_ram_register -R1 -!s100 kQQmL1T0C5B9DjbIcY4BQ2 -Ie^0PcizK<>O;0]a08[ZfE0 -V?7BDXa^bNl33^RRRmfIR4M0 -R11 -S1 -R2 -R3 -R4 -R5 -L0 3395 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vgeneric_m10k -R1 -!s100 kTV[cBggLJR7R@2kF46Zmo;U0 -Vh1mGA;?5oKfLi]56>E?]=0 -R11 -S1 -R2 -R3 -R4 -R5 -L0 2453 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 -vgeneric_mlab_cell -R1 -!s100 P=>R7UIc8PQMeF0fN2 -I8Y`bZY5WSkVn]F>^NjEg_2 -V9g=59G::AlAMeGM3BAQ520 -R11 -S1 -R2 -R3 -R4 -R5 -L0 681 -R6 -r1 -!s85 0 -31 -R7 -R8 -R9 -R10 diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/_vmake b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/_vmake deleted file mode 100644 index 2f7e729..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/_vmake +++ /dev/null @@ -1,3 +0,0 @@ -m255 -K3 -cModel Technology diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_lnsim_functions/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_lnsim_functions/_primary.dat deleted file mode 100644 index 4b2369a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_lnsim_functions/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_lnsim_functions/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_lnsim_functions/_primary.dbs deleted file mode 100644 index 75941d0..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_lnsim_functions/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_lnsim_functions/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_lnsim_functions/_primary.vhd deleted file mode 100644 index bb8ed2e..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_lnsim_functions/_primary.vhd +++ /dev/null @@ -1,4 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altera_lnsim_functions is -end altera_lnsim_functions; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_mult_add/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_mult_add/_primary.dat deleted file mode 100644 index 0b88efb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_mult_add/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_mult_add/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_mult_add/_primary.dbs deleted file mode 100644 index 1017003..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_mult_add/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_mult_add/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_mult_add/_primary.vhd deleted file mode 100644 index 56e0cae..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_mult_add/_primary.vhd +++ /dev/null @@ -1,633 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altera_mult_add is - generic( - extra_latency : integer := 0; - dedicated_multiplier_circuitry: string := "AUTO"; - dsp_block_balancing: string := "AUTO"; - selected_device_family: string := "Stratix V"; - lpm_type : string := "altmult_add"; - lpm_hint : string := "UNUSED"; - width_a : integer := 1; - input_register_a0: string := "CLOCK0"; - input_aclr_a0 : string := "ACLR0"; - input_source_a0 : string := "DATAA"; - input_register_a1: string := "CLOCK0"; - input_aclr_a1 : string := "ACLR0"; - input_source_a1 : string := "DATAA"; - input_register_a2: string := "CLOCK0"; - input_aclr_a2 : string := "ACLR0"; - input_source_a2 : string := "DATAA"; - input_register_a3: string := "CLOCK0"; - input_aclr_a3 : string := "ACLR0"; - input_source_a3 : string := "DATAA"; - width_b : integer := 1; - input_register_b0: string := "CLOCK0"; - input_aclr_b0 : string := "ACLR0"; - input_source_b0 : string := "DATAB"; - input_register_b1: string := "CLOCK0"; - input_aclr_b1 : string := "ACLR0"; - input_source_b1 : string := "DATAB"; - input_register_b2: string := "CLOCK0"; - input_aclr_b2 : string := "ACLR0"; - input_source_b2 : string := "DATAB"; - input_register_b3: string := "CLOCK0"; - input_aclr_b3 : string := "ACLR0"; - input_source_b3 : string := "DATAB"; - width_c : integer := 1; - input_register_c0: string := "CLOCK0"; - input_aclr_c0 : string := "ACLR0"; - input_register_c1: string := "CLOCK0"; - input_aclr_c1 : string := "ACLR0"; - input_register_c2: string := "CLOCK0"; - input_aclr_c2 : string := "ACLR0"; - input_register_c3: string := "CLOCK0"; - input_aclr_c3 : string := "ACLR0"; - width_result : integer := 34; - output_register : string := "CLOCK0"; - output_aclr : string := "ACLR3"; - port_signa : string := "PORT_CONNECTIVITY"; - representation_a: string := "UNSIGNED"; - signed_register_a: string := "CLOCK0"; - signed_aclr_a : string := "ACLR0"; - signed_pipeline_register_a: string := "CLOCK0"; - signed_pipeline_aclr_a: string := "ACLR3"; - port_signb : string := "PORT_CONNECTIVITY"; - representation_b: string := "UNSIGNED"; - signed_register_b: string := "CLOCK0"; - signed_aclr_b : string := "ACLR0"; - signed_pipeline_register_b: string := "CLOCK0"; - signed_pipeline_aclr_b: string := "ACLR3"; - number_of_multipliers: integer := 1; - multiplier1_direction: string := "UNUSED"; - multiplier3_direction: string := "UNUSED"; - multiplier_register0: string := "CLOCK0"; - multiplier_aclr0: string := "ACLR3"; - multiplier_register1: string := "CLOCK0"; - multiplier_aclr1: string := "ACLR3"; - multiplier_register2: string := "CLOCK0"; - multiplier_aclr2: string := "ACLR3"; - multiplier_register3: string := "CLOCK0"; - multiplier_aclr3: string := "ACLR3"; - port_addnsub1 : string := "PORT_CONNECTIVITY"; - addnsub_multiplier_register1: string := "CLOCK0"; - addnsub_multiplier_aclr1: string := "ACLR3"; - addnsub_multiplier_pipeline_register1: string := "CLOCK0"; - addnsub_multiplier_pipeline_aclr1: string := "ACLR3"; - port_addnsub3 : string := "PORT_CONNECTIVITY"; - addnsub_multiplier_register3: string := "CLOCK0"; - addnsub_multiplier_aclr3: string := "ACLR3"; - addnsub_multiplier_pipeline_register3: string := "CLOCK0"; - addnsub_multiplier_pipeline_aclr3: string := "ACLR3"; - adder1_rounding : string := "NO"; - addnsub1_round_register: string := "CLOCK0"; - addnsub1_round_aclr: string := "ACLR3"; - addnsub1_round_pipeline_register: string := "CLOCK0"; - addnsub1_round_pipeline_aclr: string := "ACLR3"; - adder3_rounding : string := "NO"; - addnsub3_round_register: string := "CLOCK0"; - addnsub3_round_aclr: string := "ACLR3"; - addnsub3_round_pipeline_register: string := "CLOCK0"; - addnsub3_round_pipeline_aclr: string := "ACLR3"; - multiplier01_rounding: string := "NO"; - mult01_round_register: string := "CLOCK0"; - mult01_round_aclr: string := "ACLR3"; - multiplier23_rounding: string := "NO"; - mult23_round_register: string := "CLOCK0"; - mult23_round_aclr: string := "ACLR3"; - width_msb : integer := 17; - output_rounding : string := "NO"; - output_round_type: string := "NEAREST_INTEGER"; - output_round_register: string := "UNREGISTERED"; - output_round_aclr: string := "NONE"; - output_round_pipeline_register: string := "UNREGISTERED"; - output_round_pipeline_aclr: string := "NONE"; - chainout_rounding: string := "NO"; - chainout_round_register: string := "UNREGISTERED"; - chainout_round_aclr: string := "NONE"; - chainout_round_pipeline_register: string := "UNREGISTERED"; - chainout_round_pipeline_aclr: string := "NONE"; - chainout_round_output_register: string := "UNREGISTERED"; - chainout_round_output_aclr: string := "NONE"; - multiplier01_saturation: string := "NO"; - mult01_saturation_register: string := "CLOCK0"; - mult01_saturation_aclr: string := "ACLR3"; - multiplier23_saturation: string := "NO"; - mult23_saturation_register: string := "CLOCK0"; - mult23_saturation_aclr: string := "ACLR3"; - port_mult0_is_saturated: string := "UNUSED"; - port_mult1_is_saturated: string := "UNUSED"; - port_mult2_is_saturated: string := "UNUSED"; - port_mult3_is_saturated: string := "UNUSED"; - width_saturate_sign: integer := 1; - output_saturation: string := "NO"; - port_output_is_overflow: string := "PORT_UNUSED"; - output_saturate_type: string := "ASYMMETRIC"; - output_saturate_register: string := "UNREGISTERED"; - output_saturate_aclr: string := "NONE"; - output_saturate_pipeline_register: string := "UNREGISTERED"; - output_saturate_pipeline_aclr: string := "NONE"; - chainout_saturation: string := "NO"; - port_chainout_sat_is_overflow: string := "PORT_UNUSED"; - chainout_saturate_register: string := "UNREGISTERED"; - chainout_saturate_aclr: string := "NONE"; - chainout_saturate_pipeline_register: string := "UNREGISTERED"; - chainout_saturate_pipeline_aclr: string := "NONE"; - chainout_saturate_output_register: string := "UNREGISTERED"; - chainout_saturate_output_aclr: string := "NONE"; - scanouta_register: string := "UNREGISTERED"; - scanouta_aclr : string := "NONE"; - width_chainin : integer := 1; - chainout_adder : string := "NO"; - chainout_register: string := "UNREGISTERED"; - chainout_aclr : string := "ACLR3"; - zero_chainout_output_register: string := "UNREGISTERED"; - zero_chainout_output_aclr: string := "NONE"; - shift_mode : string := "NO"; - rotate_register : string := "UNREGISTERED"; - rotate_aclr : string := "NONE"; - rotate_pipeline_register: string := "UNREGISTERED"; - rotate_pipeline_aclr: string := "NONE"; - rotate_output_register: string := "UNREGISTERED"; - rotate_output_aclr: string := "NONE"; - shift_right_register: string := "UNREGISTERED"; - shift_right_aclr: string := "NONE"; - shift_right_pipeline_register: string := "UNREGISTERED"; - shift_right_pipeline_aclr: string := "NONE"; - shift_right_output_register: string := "UNREGISTERED"; - shift_right_output_aclr: string := "NONE"; - zero_loopback_register: string := "UNREGISTERED"; - zero_loopback_aclr: string := "NONE"; - zero_loopback_pipeline_register: string := "UNREGISTERED"; - zero_loopback_pipeline_aclr: string := "NONE"; - zero_loopback_output_register: string := "UNREGISTERED"; - zero_loopback_output_aclr: string := "NONE"; - accumulator : string := "NO"; - accum_direction : string := "ADD"; - loadconst_value : integer := 0; - accum_sload_register: string := "UNREGISTERED"; - accum_sload_aclr: string := "NONE"; - accum_sload_pipeline_register: string := "UNREGISTERED"; - accum_sload_pipeline_aclr: string := "NONE"; - loadconst_control_register: string := "CLOCK0"; - loadconst_control_aclr: string := "ACLR0"; - systolic_delay1 : string := "UNREGISTERED"; - systolic_delay3 : string := "UNREGISTERED"; - systolic_aclr1 : string := "NONE"; - systolic_aclr3 : string := "NONE"; - preadder_mode : string := "SIMPLE"; - preadder_direction_0: string := "ADD"; - preadder_direction_1: string := "ADD"; - preadder_direction_2: string := "ADD"; - preadder_direction_3: string := "ADD"; - width_coef : integer := 1; - coefsel0_register: string := "CLOCK0"; - coefsel0_aclr : string := "ACLR0"; - coefsel1_register: string := "CLOCK0"; - coefsel1_aclr : string := "ACLR0"; - coefsel2_register: string := "CLOCK0"; - coefsel2_aclr : string := "ACLR0"; - coefsel3_register: string := "CLOCK0"; - coefsel3_aclr : string := "ACLR0"; - coef0_0 : integer := 0; - coef0_1 : integer := 0; - coef0_2 : integer := 0; - coef0_3 : integer := 0; - coef0_4 : integer := 0; - coef0_5 : integer := 0; - coef0_6 : integer := 0; - coef0_7 : integer := 0; - coef1_0 : integer := 0; - coef1_1 : integer := 0; - coef1_2 : integer := 0; - coef1_3 : integer := 0; - coef1_4 : integer := 0; - coef1_5 : integer := 0; - coef1_6 : integer := 0; - coef1_7 : integer := 0; - coef2_0 : integer := 0; - coef2_1 : integer := 0; - coef2_2 : integer := 0; - coef2_3 : integer := 0; - coef2_4 : integer := 0; - coef2_5 : integer := 0; - coef2_6 : integer := 0; - coef2_7 : integer := 0; - coef3_0 : integer := 0; - coef3_1 : integer := 0; - coef3_2 : integer := 0; - coef3_3 : integer := 0; - coef3_4 : integer := 0; - coef3_5 : integer := 0; - coef3_6 : integer := 0; - coef3_7 : integer := 0; - width_clock_all_wire_msb: integer := 3; - width_aclr_all_wire_msb: integer := 3; - width_ena_all_wire_msb: integer := 3; - width_a_total_msb: vl_notype; - width_a_msb : vl_notype; - width_b_total_msb: vl_notype; - width_b_msb : vl_notype; - datac_number_of_multiplier: integer := 1; - width_c_total_msb: vl_notype; - width_c_msb : vl_notype; - width_scanina : vl_notype; - width_scanina_msb: vl_notype; - width_scaninb : vl_notype; - width_scaninb_msb: vl_notype; - width_sourcea_msb: vl_notype; - width_sourceb_msb: vl_notype; - width_scanouta_msb: vl_notype; - width_scanoutb_msb: vl_notype; - width_chainin_msb: vl_notype; - width_result_msb: vl_notype; - width_coef_msb : vl_notype; - dataa_split_ext_require: vl_notype; - dataa_port_sign : vl_notype; - width_a_ext : vl_notype; - width_a_ext_msb : vl_notype; - datab_split_ext_require: vl_notype; - datab_port_sign : vl_notype; - width_b_ext : vl_notype; - width_b_ext_msb : vl_notype; - coef_ext_require: vl_notype; - coef_port_sign : vl_notype; - width_coef_ext : vl_notype; - width_coef_ext_msb: vl_notype; - datac_split_ext_require: vl_notype; - datac_port_sign : vl_notype; - width_c_ext : vl_notype; - width_c_ext_msb : vl_notype; - width_scanchain : vl_notype; - width_scanchain_msb: vl_notype; - scanchain_port_sign: vl_notype; - preadder_representation: vl_notype; - width_preadder_input_a: vl_notype; - width_preadder_input_a_msb: vl_notype; - width_preadder_adder_result: vl_notype; - width_preadder_output_a: vl_notype; - width_preadder_output_a_msb: vl_notype; - width_preadder_output_b: vl_notype; - width_preadder_output_b_msb: vl_notype; - multiplier_input_representation_a: vl_notype; - multiplier_input_representation_b: vl_notype; - width_mult_source_a: vl_notype; - width_mult_source_a_msb: vl_notype; - width_mult_source_b: vl_notype; - width_mult_source_b_msb: vl_notype; - width_mult_result: vl_notype; - width_mult_result_msb: vl_notype; - width_adder_source: vl_notype; - width_adder_source_msb: vl_notype; - width_adder_result: vl_notype; - width_adder_result_msb: vl_notype; - width_chainin_ext: vl_notype; - width_original_result: vl_notype; - width_original_result_msb: vl_notype; - result_ext_width: vl_notype; - width_result_output: vl_notype; - width_result_output_msb: vl_notype; - width_chainout_adder_output: vl_notype - ); - port( - dataa : in vl_logic_vector; - datab : in vl_logic_vector; - datac : in vl_logic_vector; - scanina : in vl_logic_vector; - scaninb : in vl_logic_vector; - sourcea : in vl_logic_vector; - sourceb : in vl_logic_vector; - clock3 : in vl_logic; - clock2 : in vl_logic; - clock1 : in vl_logic; - clock0 : in vl_logic; - aclr3 : in vl_logic; - aclr2 : in vl_logic; - aclr1 : in vl_logic; - aclr0 : in vl_logic; - ena3 : in vl_logic; - ena2 : in vl_logic; - ena1 : in vl_logic; - ena0 : in vl_logic; - signa : in vl_logic; - signb : in vl_logic; - addnsub1 : in vl_logic; - addnsub3 : in vl_logic; - result : out vl_logic_vector; - scanouta : out vl_logic_vector; - scanoutb : out vl_logic_vector; - mult01_round : in vl_logic; - mult23_round : in vl_logic; - mult01_saturation: in vl_logic; - mult23_saturation: in vl_logic; - addnsub1_round : in vl_logic; - addnsub3_round : in vl_logic; - mult0_is_saturated: out vl_logic; - mult1_is_saturated: out vl_logic; - mult2_is_saturated: out vl_logic; - mult3_is_saturated: out vl_logic; - output_round : in vl_logic; - chainout_round : in vl_logic; - output_saturate : in vl_logic; - chainout_saturate: in vl_logic; - overflow : out vl_logic; - chainout_sat_overflow: out vl_logic; - chainin : in vl_logic_vector; - zero_chainout : in vl_logic; - rotate : in vl_logic; - shift_right : in vl_logic; - zero_loopback : in vl_logic; - accum_sload : in vl_logic; - coefsel0 : in vl_logic_vector(2 downto 0); - coefsel1 : in vl_logic_vector(2 downto 0); - coefsel2 : in vl_logic_vector(2 downto 0); - coefsel3 : in vl_logic_vector(2 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of extra_latency : constant is 1; - attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1; - attribute mti_svvh_generic_type of dsp_block_balancing : constant is 1; - attribute mti_svvh_generic_type of selected_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of width_a : constant is 1; - attribute mti_svvh_generic_type of input_register_a0 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_a0 : constant is 1; - attribute mti_svvh_generic_type of input_source_a0 : constant is 1; - attribute mti_svvh_generic_type of input_register_a1 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_a1 : constant is 1; - attribute mti_svvh_generic_type of input_source_a1 : constant is 1; - attribute mti_svvh_generic_type of input_register_a2 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_a2 : constant is 1; - attribute mti_svvh_generic_type of input_source_a2 : constant is 1; - attribute mti_svvh_generic_type of input_register_a3 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_a3 : constant is 1; - attribute mti_svvh_generic_type of input_source_a3 : constant is 1; - attribute mti_svvh_generic_type of width_b : constant is 1; - attribute mti_svvh_generic_type of input_register_b0 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_b0 : constant is 1; - attribute mti_svvh_generic_type of input_source_b0 : constant is 1; - attribute mti_svvh_generic_type of input_register_b1 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_b1 : constant is 1; - attribute mti_svvh_generic_type of input_source_b1 : constant is 1; - attribute mti_svvh_generic_type of input_register_b2 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_b2 : constant is 1; - attribute mti_svvh_generic_type of input_source_b2 : constant is 1; - attribute mti_svvh_generic_type of input_register_b3 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_b3 : constant is 1; - attribute mti_svvh_generic_type of input_source_b3 : constant is 1; - attribute mti_svvh_generic_type of width_c : constant is 1; - attribute mti_svvh_generic_type of input_register_c0 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_c0 : constant is 1; - attribute mti_svvh_generic_type of input_register_c1 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_c1 : constant is 1; - attribute mti_svvh_generic_type of input_register_c2 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_c2 : constant is 1; - attribute mti_svvh_generic_type of input_register_c3 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_c3 : constant is 1; - attribute mti_svvh_generic_type of width_result : constant is 1; - attribute mti_svvh_generic_type of output_register : constant is 1; - attribute mti_svvh_generic_type of output_aclr : constant is 1; - attribute mti_svvh_generic_type of port_signa : constant is 1; - attribute mti_svvh_generic_type of representation_a : constant is 1; - attribute mti_svvh_generic_type of signed_register_a : constant is 1; - attribute mti_svvh_generic_type of signed_aclr_a : constant is 1; - attribute mti_svvh_generic_type of signed_pipeline_register_a : constant is 1; - attribute mti_svvh_generic_type of signed_pipeline_aclr_a : constant is 1; - attribute mti_svvh_generic_type of port_signb : constant is 1; - attribute mti_svvh_generic_type of representation_b : constant is 1; - attribute mti_svvh_generic_type of signed_register_b : constant is 1; - attribute mti_svvh_generic_type of signed_aclr_b : constant is 1; - attribute mti_svvh_generic_type of signed_pipeline_register_b : constant is 1; - attribute mti_svvh_generic_type of signed_pipeline_aclr_b : constant is 1; - attribute mti_svvh_generic_type of number_of_multipliers : constant is 1; - attribute mti_svvh_generic_type of multiplier1_direction : constant is 1; - attribute mti_svvh_generic_type of multiplier3_direction : constant is 1; - attribute mti_svvh_generic_type of multiplier_register0 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register1 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register2 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register3 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1; - attribute mti_svvh_generic_type of port_addnsub1 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_register1 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_aclr1 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register1 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr1 : constant is 1; - attribute mti_svvh_generic_type of port_addnsub3 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_register3 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_aclr3 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register3 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr3 : constant is 1; - attribute mti_svvh_generic_type of adder1_rounding : constant is 1; - attribute mti_svvh_generic_type of addnsub1_round_register : constant is 1; - attribute mti_svvh_generic_type of addnsub1_round_aclr : constant is 1; - attribute mti_svvh_generic_type of addnsub1_round_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of addnsub1_round_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of adder3_rounding : constant is 1; - attribute mti_svvh_generic_type of addnsub3_round_register : constant is 1; - attribute mti_svvh_generic_type of addnsub3_round_aclr : constant is 1; - attribute mti_svvh_generic_type of addnsub3_round_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of addnsub3_round_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of multiplier01_rounding : constant is 1; - attribute mti_svvh_generic_type of mult01_round_register : constant is 1; - attribute mti_svvh_generic_type of mult01_round_aclr : constant is 1; - attribute mti_svvh_generic_type of multiplier23_rounding : constant is 1; - attribute mti_svvh_generic_type of mult23_round_register : constant is 1; - attribute mti_svvh_generic_type of mult23_round_aclr : constant is 1; - attribute mti_svvh_generic_type of width_msb : constant is 1; - attribute mti_svvh_generic_type of output_rounding : constant is 1; - attribute mti_svvh_generic_type of output_round_type : constant is 1; - attribute mti_svvh_generic_type of output_round_register : constant is 1; - attribute mti_svvh_generic_type of output_round_aclr : constant is 1; - attribute mti_svvh_generic_type of output_round_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of output_round_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_rounding : constant is 1; - attribute mti_svvh_generic_type of chainout_round_register : constant is 1; - attribute mti_svvh_generic_type of chainout_round_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_round_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of chainout_round_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_round_output_register : constant is 1; - attribute mti_svvh_generic_type of chainout_round_output_aclr : constant is 1; - attribute mti_svvh_generic_type of multiplier01_saturation : constant is 1; - attribute mti_svvh_generic_type of mult01_saturation_register : constant is 1; - attribute mti_svvh_generic_type of mult01_saturation_aclr : constant is 1; - attribute mti_svvh_generic_type of multiplier23_saturation : constant is 1; - attribute mti_svvh_generic_type of mult23_saturation_register : constant is 1; - attribute mti_svvh_generic_type of mult23_saturation_aclr : constant is 1; - attribute mti_svvh_generic_type of port_mult0_is_saturated : constant is 1; - attribute mti_svvh_generic_type of port_mult1_is_saturated : constant is 1; - attribute mti_svvh_generic_type of port_mult2_is_saturated : constant is 1; - attribute mti_svvh_generic_type of port_mult3_is_saturated : constant is 1; - attribute mti_svvh_generic_type of width_saturate_sign : constant is 1; - attribute mti_svvh_generic_type of output_saturation : constant is 1; - attribute mti_svvh_generic_type of port_output_is_overflow : constant is 1; - attribute mti_svvh_generic_type of output_saturate_type : constant is 1; - attribute mti_svvh_generic_type of output_saturate_register : constant is 1; - attribute mti_svvh_generic_type of output_saturate_aclr : constant is 1; - attribute mti_svvh_generic_type of output_saturate_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of output_saturate_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_saturation : constant is 1; - attribute mti_svvh_generic_type of port_chainout_sat_is_overflow : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_register : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_output_register : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_output_aclr : constant is 1; - attribute mti_svvh_generic_type of scanouta_register : constant is 1; - attribute mti_svvh_generic_type of scanouta_aclr : constant is 1; - attribute mti_svvh_generic_type of width_chainin : constant is 1; - attribute mti_svvh_generic_type of chainout_adder : constant is 1; - attribute mti_svvh_generic_type of chainout_register : constant is 1; - attribute mti_svvh_generic_type of chainout_aclr : constant is 1; - attribute mti_svvh_generic_type of zero_chainout_output_register : constant is 1; - attribute mti_svvh_generic_type of zero_chainout_output_aclr : constant is 1; - attribute mti_svvh_generic_type of shift_mode : constant is 1; - attribute mti_svvh_generic_type of rotate_register : constant is 1; - attribute mti_svvh_generic_type of rotate_aclr : constant is 1; - attribute mti_svvh_generic_type of rotate_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of rotate_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of rotate_output_register : constant is 1; - attribute mti_svvh_generic_type of rotate_output_aclr : constant is 1; - attribute mti_svvh_generic_type of shift_right_register : constant is 1; - attribute mti_svvh_generic_type of shift_right_aclr : constant is 1; - attribute mti_svvh_generic_type of shift_right_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of shift_right_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of shift_right_output_register : constant is 1; - attribute mti_svvh_generic_type of shift_right_output_aclr : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_register : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_aclr : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_output_register : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_output_aclr : constant is 1; - attribute mti_svvh_generic_type of accumulator : constant is 1; - attribute mti_svvh_generic_type of accum_direction : constant is 1; - attribute mti_svvh_generic_type of loadconst_value : constant is 1; - attribute mti_svvh_generic_type of accum_sload_register : constant is 1; - attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_sload_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of accum_sload_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of loadconst_control_register : constant is 1; - attribute mti_svvh_generic_type of loadconst_control_aclr : constant is 1; - attribute mti_svvh_generic_type of systolic_delay1 : constant is 1; - attribute mti_svvh_generic_type of systolic_delay3 : constant is 1; - attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1; - attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1; - attribute mti_svvh_generic_type of preadder_mode : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1; - attribute mti_svvh_generic_type of width_coef : constant is 1; - attribute mti_svvh_generic_type of coefsel0_register : constant is 1; - attribute mti_svvh_generic_type of coefsel0_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel1_register : constant is 1; - attribute mti_svvh_generic_type of coefsel1_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel2_register : constant is 1; - attribute mti_svvh_generic_type of coefsel2_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel3_register : constant is 1; - attribute mti_svvh_generic_type of coefsel3_aclr : constant is 1; - attribute mti_svvh_generic_type of coef0_0 : constant is 1; - attribute mti_svvh_generic_type of coef0_1 : constant is 1; - attribute mti_svvh_generic_type of coef0_2 : constant is 1; - attribute mti_svvh_generic_type of coef0_3 : constant is 1; - attribute mti_svvh_generic_type of coef0_4 : constant is 1; - attribute mti_svvh_generic_type of coef0_5 : constant is 1; - attribute mti_svvh_generic_type of coef0_6 : constant is 1; - attribute mti_svvh_generic_type of coef0_7 : constant is 1; - attribute mti_svvh_generic_type of coef1_0 : constant is 1; - attribute mti_svvh_generic_type of coef1_1 : constant is 1; - attribute mti_svvh_generic_type of coef1_2 : constant is 1; - attribute mti_svvh_generic_type of coef1_3 : constant is 1; - attribute mti_svvh_generic_type of coef1_4 : constant is 1; - attribute mti_svvh_generic_type of coef1_5 : constant is 1; - attribute mti_svvh_generic_type of coef1_6 : constant is 1; - attribute mti_svvh_generic_type of coef1_7 : constant is 1; - attribute mti_svvh_generic_type of coef2_0 : constant is 1; - attribute mti_svvh_generic_type of coef2_1 : constant is 1; - attribute mti_svvh_generic_type of coef2_2 : constant is 1; - attribute mti_svvh_generic_type of coef2_3 : constant is 1; - attribute mti_svvh_generic_type of coef2_4 : constant is 1; - attribute mti_svvh_generic_type of coef2_5 : constant is 1; - attribute mti_svvh_generic_type of coef2_6 : constant is 1; - attribute mti_svvh_generic_type of coef2_7 : constant is 1; - attribute mti_svvh_generic_type of coef3_0 : constant is 1; - attribute mti_svvh_generic_type of coef3_1 : constant is 1; - attribute mti_svvh_generic_type of coef3_2 : constant is 1; - attribute mti_svvh_generic_type of coef3_3 : constant is 1; - attribute mti_svvh_generic_type of coef3_4 : constant is 1; - attribute mti_svvh_generic_type of coef3_5 : constant is 1; - attribute mti_svvh_generic_type of coef3_6 : constant is 1; - attribute mti_svvh_generic_type of coef3_7 : constant is 1; - attribute mti_svvh_generic_type of width_clock_all_wire_msb : constant is 1; - attribute mti_svvh_generic_type of width_aclr_all_wire_msb : constant is 1; - attribute mti_svvh_generic_type of width_ena_all_wire_msb : constant is 1; - attribute mti_svvh_generic_type of width_a_total_msb : constant is 3; - attribute mti_svvh_generic_type of width_a_msb : constant is 3; - attribute mti_svvh_generic_type of width_b_total_msb : constant is 3; - attribute mti_svvh_generic_type of width_b_msb : constant is 3; - attribute mti_svvh_generic_type of datac_number_of_multiplier : constant is 1; - attribute mti_svvh_generic_type of width_c_total_msb : constant is 3; - attribute mti_svvh_generic_type of width_c_msb : constant is 3; - attribute mti_svvh_generic_type of width_scanina : constant is 3; - attribute mti_svvh_generic_type of width_scanina_msb : constant is 3; - attribute mti_svvh_generic_type of width_scaninb : constant is 3; - attribute mti_svvh_generic_type of width_scaninb_msb : constant is 3; - attribute mti_svvh_generic_type of width_sourcea_msb : constant is 3; - attribute mti_svvh_generic_type of width_sourceb_msb : constant is 3; - attribute mti_svvh_generic_type of width_scanouta_msb : constant is 3; - attribute mti_svvh_generic_type of width_scanoutb_msb : constant is 3; - attribute mti_svvh_generic_type of width_chainin_msb : constant is 3; - attribute mti_svvh_generic_type of width_result_msb : constant is 3; - attribute mti_svvh_generic_type of width_coef_msb : constant is 3; - attribute mti_svvh_generic_type of dataa_split_ext_require : constant is 3; - attribute mti_svvh_generic_type of dataa_port_sign : constant is 3; - attribute mti_svvh_generic_type of width_a_ext : constant is 3; - attribute mti_svvh_generic_type of width_a_ext_msb : constant is 3; - attribute mti_svvh_generic_type of datab_split_ext_require : constant is 3; - attribute mti_svvh_generic_type of datab_port_sign : constant is 3; - attribute mti_svvh_generic_type of width_b_ext : constant is 3; - attribute mti_svvh_generic_type of width_b_ext_msb : constant is 3; - attribute mti_svvh_generic_type of coef_ext_require : constant is 3; - attribute mti_svvh_generic_type of coef_port_sign : constant is 3; - attribute mti_svvh_generic_type of width_coef_ext : constant is 3; - attribute mti_svvh_generic_type of width_coef_ext_msb : constant is 3; - attribute mti_svvh_generic_type of datac_split_ext_require : constant is 3; - attribute mti_svvh_generic_type of datac_port_sign : constant is 3; - attribute mti_svvh_generic_type of width_c_ext : constant is 3; - attribute mti_svvh_generic_type of width_c_ext_msb : constant is 3; - attribute mti_svvh_generic_type of width_scanchain : constant is 3; - attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3; - attribute mti_svvh_generic_type of scanchain_port_sign : constant is 3; - attribute mti_svvh_generic_type of preadder_representation : constant is 3; - attribute mti_svvh_generic_type of width_preadder_input_a : constant is 3; - attribute mti_svvh_generic_type of width_preadder_input_a_msb : constant is 3; - attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3; - attribute mti_svvh_generic_type of width_preadder_output_a : constant is 3; - attribute mti_svvh_generic_type of width_preadder_output_a_msb : constant is 3; - attribute mti_svvh_generic_type of width_preadder_output_b : constant is 3; - attribute mti_svvh_generic_type of width_preadder_output_b_msb : constant is 3; - attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 3; - attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 3; - attribute mti_svvh_generic_type of width_mult_source_a : constant is 3; - attribute mti_svvh_generic_type of width_mult_source_a_msb : constant is 3; - attribute mti_svvh_generic_type of width_mult_source_b : constant is 3; - attribute mti_svvh_generic_type of width_mult_source_b_msb : constant is 3; - attribute mti_svvh_generic_type of width_mult_result : constant is 3; - attribute mti_svvh_generic_type of width_mult_result_msb : constant is 3; - attribute mti_svvh_generic_type of width_adder_source : constant is 3; - attribute mti_svvh_generic_type of width_adder_source_msb : constant is 3; - attribute mti_svvh_generic_type of width_adder_result : constant is 3; - attribute mti_svvh_generic_type of width_adder_result_msb : constant is 3; - attribute mti_svvh_generic_type of width_chainin_ext : constant is 3; - attribute mti_svvh_generic_type of width_original_result : constant is 3; - attribute mti_svvh_generic_type of width_original_result_msb : constant is 3; - attribute mti_svvh_generic_type of result_ext_width : constant is 3; - attribute mti_svvh_generic_type of width_result_output : constant is 3; - attribute mti_svvh_generic_type of width_result_output_msb : constant is 3; - attribute mti_svvh_generic_type of width_chainout_adder_output : constant is 3; -end altera_mult_add; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_pll/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_pll/_primary.dat deleted file mode 100644 index a0e529d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_pll/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_pll/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_pll/_primary.dbs deleted file mode 100644 index 9e6edbb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_pll/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_pll/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_pll/_primary.vhd deleted file mode 100644 index 6714b09..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/altera_pll/_primary.vhd +++ /dev/null @@ -1,142 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altera_pll is - generic( - reference_clock_frequency: string := "0 ps"; - pll_type : string := "General"; - number_of_clocks: integer := 1; - operation_mode : string := "internal feedback"; - deserialization_factor: integer := 4; - data_rate : integer := 0; - clock_switchover_mode: string := "Auto"; - clock_switchover_delay: integer := 3; - sim_additional_refclk_cycles_to_lock: integer := 0; - output_clock_frequency0: string := "0 ps"; - phase_shift0 : string := "0 ps"; - duty_cycle0 : integer := 50; - output_clock_frequency1: string := "0 ps"; - phase_shift1 : string := "0 ps"; - duty_cycle1 : integer := 50; - output_clock_frequency2: string := "0 ps"; - phase_shift2 : string := "0 ps"; - duty_cycle2 : integer := 50; - output_clock_frequency3: string := "0 ps"; - phase_shift3 : string := "0 ps"; - duty_cycle3 : integer := 50; - output_clock_frequency4: string := "0 ps"; - phase_shift4 : string := "0 ps"; - duty_cycle4 : integer := 50; - output_clock_frequency5: string := "0 ps"; - phase_shift5 : string := "0 ps"; - duty_cycle5 : integer := 50; - output_clock_frequency6: string := "0 ps"; - phase_shift6 : string := "0 ps"; - duty_cycle6 : integer := 50; - output_clock_frequency7: string := "0 ps"; - phase_shift7 : string := "0 ps"; - duty_cycle7 : integer := 50; - output_clock_frequency8: string := "0 ps"; - phase_shift8 : string := "0 ps"; - duty_cycle8 : integer := 50; - output_clock_frequency9: string := "0 ps"; - phase_shift9 : string := "0 ps"; - duty_cycle9 : integer := 50; - output_clock_frequency10: string := "0 ps"; - phase_shift10 : string := "0 ps"; - duty_cycle10 : integer := 50; - output_clock_frequency11: string := "0 ps"; - phase_shift11 : string := "0 ps"; - duty_cycle11 : integer := 50; - output_clock_frequency12: string := "0 ps"; - phase_shift12 : string := "0 ps"; - duty_cycle12 : integer := 50; - output_clock_frequency13: string := "0 ps"; - phase_shift13 : string := "0 ps"; - duty_cycle13 : integer := 50; - output_clock_frequency14: string := "0 ps"; - phase_shift14 : string := "0 ps"; - duty_cycle14 : integer := 50; - output_clock_frequency15: string := "0 ps"; - phase_shift15 : string := "0 ps"; - duty_cycle15 : integer := 50; - output_clock_frequency16: string := "0 ps"; - phase_shift16 : string := "0 ps"; - duty_cycle16 : integer := 50; - output_clock_frequency17: string := "0 ps"; - phase_shift17 : string := "0 ps"; - duty_cycle17 : integer := 50 - ); - port( - refclk : in vl_logic; - fbclk : in vl_logic; - rst : in vl_logic; - outclk : out vl_logic_vector; - fboutclk : out vl_logic; - locked : out vl_logic; - zdbfbclk : inout vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1; - attribute mti_svvh_generic_type of pll_type : constant is 1; - attribute mti_svvh_generic_type of number_of_clocks : constant is 1; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of data_rate : constant is 1; - attribute mti_svvh_generic_type of clock_switchover_mode : constant is 1; - attribute mti_svvh_generic_type of clock_switchover_delay : constant is 1; - attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency0 : constant is 1; - attribute mti_svvh_generic_type of phase_shift0 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle0 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency1 : constant is 1; - attribute mti_svvh_generic_type of phase_shift1 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle1 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency2 : constant is 1; - attribute mti_svvh_generic_type of phase_shift2 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle2 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency3 : constant is 1; - attribute mti_svvh_generic_type of phase_shift3 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle3 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency4 : constant is 1; - attribute mti_svvh_generic_type of phase_shift4 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle4 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency5 : constant is 1; - attribute mti_svvh_generic_type of phase_shift5 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle5 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency6 : constant is 1; - attribute mti_svvh_generic_type of phase_shift6 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle6 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency7 : constant is 1; - attribute mti_svvh_generic_type of phase_shift7 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle7 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency8 : constant is 1; - attribute mti_svvh_generic_type of phase_shift8 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle8 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency9 : constant is 1; - attribute mti_svvh_generic_type of phase_shift9 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle9 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency10 : constant is 1; - attribute mti_svvh_generic_type of phase_shift10 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle10 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency11 : constant is 1; - attribute mti_svvh_generic_type of phase_shift11 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle11 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency12 : constant is 1; - attribute mti_svvh_generic_type of phase_shift12 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle12 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency13 : constant is 1; - attribute mti_svvh_generic_type of phase_shift13 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle13 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency14 : constant is 1; - attribute mti_svvh_generic_type of phase_shift14 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle14 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency15 : constant is 1; - attribute mti_svvh_generic_type of phase_shift15 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle15 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency16 : constant is 1; - attribute mti_svvh_generic_type of phase_shift16 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle16 : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency17 : constant is 1; - attribute mti_svvh_generic_type of phase_shift17 : constant is 1; - attribute mti_svvh_generic_type of duty_cycle17 : constant is 1; -end altera_pll; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_accumulator_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_accumulator_function/_primary.dat deleted file mode 100644 index 6095d3e..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_accumulator_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_accumulator_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_accumulator_function/_primary.dbs deleted file mode 100644 index 9013655..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_accumulator_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_accumulator_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_accumulator_function/_primary.vhd deleted file mode 100644 index aeb3242..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_accumulator_function/_primary.vhd +++ /dev/null @@ -1,30 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_accumulator_function is - generic( - width_result : integer := 1; - accumulator : string := "NO"; - accum_direction : string := "ADD"; - loadconst_value : integer := 0; - accum_sload_register: string := "UNREGISTERED"; - accum_sload_aclr: string := "NONE"; - width_result_msb: vl_notype - ); - port( - clock : in vl_logic_vector(3 downto 0); - aclr : in vl_logic_vector(3 downto 0); - ena : in vl_logic_vector(3 downto 0); - accum_sload : in vl_logic; - data_result : in vl_logic_vector; - prev_result : in vl_logic_vector; - result : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_result : constant is 1; - attribute mti_svvh_generic_type of accumulator : constant is 1; - attribute mti_svvh_generic_type of accum_direction : constant is 1; - attribute mti_svvh_generic_type of loadconst_value : constant is 1; - attribute mti_svvh_generic_type of accum_sload_register : constant is 1; - attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1; - attribute mti_svvh_generic_type of width_result_msb : constant is 3; -end ama_accumulator_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_adder_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_adder_function/_primary.dat deleted file mode 100644 index 5a51fa3..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_adder_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_adder_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_adder_function/_primary.dbs deleted file mode 100644 index f381717..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_adder_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_adder_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_adder_function/_primary.vhd deleted file mode 100644 index 95b2419..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_adder_function/_primary.vhd +++ /dev/null @@ -1,42 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_adder_function is - generic( - width_data_in : integer := 1; - width_data_out : integer := 1; - number_of_adder_input: integer := 1; - adder1_direction: string := "UNUSED"; - adder3_direction: string := "UNUSED"; - representation : string := "UNSIGNED"; - width_data_in_msb: vl_notype; - width_data_out_msb: vl_notype; - width_adder_lvl_1: vl_notype; - width_adder_lvl_1_msb: vl_notype; - width_adder_lvl_2: vl_notype; - width_adder_lvl_2_msb: vl_notype; - width_data_out_wire: vl_notype; - width_data_out_wire_msb: vl_notype - ); - port( - data_in_0 : in vl_logic_vector; - data_in_1 : in vl_logic_vector; - data_in_2 : in vl_logic_vector; - data_in_3 : in vl_logic_vector; - data_out : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_data_in : constant is 1; - attribute mti_svvh_generic_type of width_data_out : constant is 1; - attribute mti_svvh_generic_type of number_of_adder_input : constant is 1; - attribute mti_svvh_generic_type of adder1_direction : constant is 1; - attribute mti_svvh_generic_type of adder3_direction : constant is 1; - attribute mti_svvh_generic_type of representation : constant is 1; - attribute mti_svvh_generic_type of width_data_in_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_msb : constant is 3; - attribute mti_svvh_generic_type of width_adder_lvl_1 : constant is 3; - attribute mti_svvh_generic_type of width_adder_lvl_1_msb : constant is 3; - attribute mti_svvh_generic_type of width_adder_lvl_2 : constant is 3; - attribute mti_svvh_generic_type of width_adder_lvl_2_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_wire : constant is 3; - attribute mti_svvh_generic_type of width_data_out_wire_msb : constant is 3; -end ama_adder_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_coef_reg_ext_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_coef_reg_ext_function/_primary.dat deleted file mode 100644 index efba886..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_coef_reg_ext_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_coef_reg_ext_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_coef_reg_ext_function/_primary.dbs deleted file mode 100644 index 5c36a27..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_coef_reg_ext_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_coef_reg_ext_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_coef_reg_ext_function/_primary.vhd deleted file mode 100644 index 2ea6312..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_coef_reg_ext_function/_primary.vhd +++ /dev/null @@ -1,115 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_coef_reg_ext_function is - generic( - width_coef : integer := 1; - width_data_out : vl_notype; - register_clock_0: string := "UNREGISTERED"; - register_aclr_0 : string := "UNUSED"; - register_clock_1: string := "UNREGISTERED"; - register_aclr_1 : string := "UNUSED"; - register_clock_2: string := "UNREGISTERED"; - register_aclr_2 : string := "UNUSED"; - register_clock_3: string := "UNREGISTERED"; - register_aclr_3 : string := "UNUSED"; - number_of_multipliers: integer := 1; - port_sign : string := "PORT_CONNECTIVITY"; - width_coef_msb : vl_notype; - width_data_out_msb: vl_notype; - width_coef_ext : vl_notype; - coef0_0 : vl_logic_vector; - coef0_1 : vl_logic_vector; - coef0_2 : vl_logic_vector; - coef0_3 : vl_logic_vector; - coef0_4 : vl_logic_vector; - coef0_5 : vl_logic_vector; - coef0_6 : vl_logic_vector; - coef0_7 : vl_logic_vector; - coef1_0 : vl_logic_vector; - coef1_1 : vl_logic_vector; - coef1_2 : vl_logic_vector; - coef1_3 : vl_logic_vector; - coef1_4 : vl_logic_vector; - coef1_5 : vl_logic_vector; - coef1_6 : vl_logic_vector; - coef1_7 : vl_logic_vector; - coef2_0 : vl_logic_vector; - coef2_1 : vl_logic_vector; - coef2_2 : vl_logic_vector; - coef2_3 : vl_logic_vector; - coef2_4 : vl_logic_vector; - coef2_5 : vl_logic_vector; - coef2_6 : vl_logic_vector; - coef2_7 : vl_logic_vector; - coef3_0 : vl_logic_vector; - coef3_1 : vl_logic_vector; - coef3_2 : vl_logic_vector; - coef3_3 : vl_logic_vector; - coef3_4 : vl_logic_vector; - coef3_5 : vl_logic_vector; - coef3_6 : vl_logic_vector; - coef3_7 : vl_logic_vector - ); - port( - clock : in vl_logic_vector(3 downto 0); - aclr : in vl_logic_vector(3 downto 0); - ena : in vl_logic_vector(3 downto 0); - sign : in vl_logic; - coefsel0 : in vl_logic_vector(2 downto 0); - coefsel1 : in vl_logic_vector(2 downto 0); - coefsel2 : in vl_logic_vector(2 downto 0); - coefsel3 : in vl_logic_vector(2 downto 0); - data_out_0 : out vl_logic_vector; - data_out_1 : out vl_logic_vector; - data_out_2 : out vl_logic_vector; - data_out_3 : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_coef : constant is 1; - attribute mti_svvh_generic_type of width_data_out : constant is 3; - attribute mti_svvh_generic_type of register_clock_0 : constant is 1; - attribute mti_svvh_generic_type of register_aclr_0 : constant is 1; - attribute mti_svvh_generic_type of register_clock_1 : constant is 1; - attribute mti_svvh_generic_type of register_aclr_1 : constant is 1; - attribute mti_svvh_generic_type of register_clock_2 : constant is 1; - attribute mti_svvh_generic_type of register_aclr_2 : constant is 1; - attribute mti_svvh_generic_type of register_clock_3 : constant is 1; - attribute mti_svvh_generic_type of register_aclr_3 : constant is 1; - attribute mti_svvh_generic_type of number_of_multipliers : constant is 1; - attribute mti_svvh_generic_type of port_sign : constant is 1; - attribute mti_svvh_generic_type of width_coef_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_msb : constant is 3; - attribute mti_svvh_generic_type of width_coef_ext : constant is 3; - attribute mti_svvh_generic_type of coef0_0 : constant is 4; - attribute mti_svvh_generic_type of coef0_1 : constant is 4; - attribute mti_svvh_generic_type of coef0_2 : constant is 4; - attribute mti_svvh_generic_type of coef0_3 : constant is 4; - attribute mti_svvh_generic_type of coef0_4 : constant is 4; - attribute mti_svvh_generic_type of coef0_5 : constant is 4; - attribute mti_svvh_generic_type of coef0_6 : constant is 4; - attribute mti_svvh_generic_type of coef0_7 : constant is 4; - attribute mti_svvh_generic_type of coef1_0 : constant is 4; - attribute mti_svvh_generic_type of coef1_1 : constant is 4; - attribute mti_svvh_generic_type of coef1_2 : constant is 4; - attribute mti_svvh_generic_type of coef1_3 : constant is 4; - attribute mti_svvh_generic_type of coef1_4 : constant is 4; - attribute mti_svvh_generic_type of coef1_5 : constant is 4; - attribute mti_svvh_generic_type of coef1_6 : constant is 4; - attribute mti_svvh_generic_type of coef1_7 : constant is 4; - attribute mti_svvh_generic_type of coef2_0 : constant is 4; - attribute mti_svvh_generic_type of coef2_1 : constant is 4; - attribute mti_svvh_generic_type of coef2_2 : constant is 4; - attribute mti_svvh_generic_type of coef2_3 : constant is 4; - attribute mti_svvh_generic_type of coef2_4 : constant is 4; - attribute mti_svvh_generic_type of coef2_5 : constant is 4; - attribute mti_svvh_generic_type of coef2_6 : constant is 4; - attribute mti_svvh_generic_type of coef2_7 : constant is 4; - attribute mti_svvh_generic_type of coef3_0 : constant is 4; - attribute mti_svvh_generic_type of coef3_1 : constant is 4; - attribute mti_svvh_generic_type of coef3_2 : constant is 4; - attribute mti_svvh_generic_type of coef3_3 : constant is 4; - attribute mti_svvh_generic_type of coef3_4 : constant is 4; - attribute mti_svvh_generic_type of coef3_5 : constant is 4; - attribute mti_svvh_generic_type of coef3_6 : constant is 4; - attribute mti_svvh_generic_type of coef3_7 : constant is 4; -end ama_coef_reg_ext_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_data_split_reg_ext_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_data_split_reg_ext_function/_primary.dat deleted file mode 100644 index 83bafdb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_data_split_reg_ext_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_data_split_reg_ext_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_data_split_reg_ext_function/_primary.dbs deleted file mode 100644 index ba19e90..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_data_split_reg_ext_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_data_split_reg_ext_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_data_split_reg_ext_function/_primary.vhd deleted file mode 100644 index e3bbf4d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_data_split_reg_ext_function/_primary.vhd +++ /dev/null @@ -1,64 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_data_split_reg_ext_function is - generic( - width_data_in : integer := 1; - width_data_out : vl_notype; - register_clock_0: string := "UNREGISTERED"; - register_aclr_0 : string := "UNUSED"; - register_clock_1: string := "UNREGISTERED"; - register_aclr_1 : string := "UNUSED"; - register_clock_2: string := "UNREGISTERED"; - register_aclr_2 : string := "UNUSED"; - register_clock_3: string := "UNREGISTERED"; - register_aclr_3 : string := "UNUSED"; - number_of_multipliers: integer := 1; - port_sign : string := "PORT_CONNECTIVITY"; - width_data_in_msb: vl_notype; - width_data_in_total_msb: vl_notype; - width_data_out_msb: vl_notype; - width_data_in_0_msb: vl_notype; - width_data_in_0_lsb: integer := 0; - width_data_in_1_msb: vl_notype; - width_data_in_1_lsb: vl_notype; - width_data_in_2_msb: vl_notype; - width_data_in_2_lsb: vl_notype; - width_data_in_3_msb: vl_notype; - width_data_in_3_lsb: vl_notype - ); - port( - clock : in vl_logic_vector(3 downto 0); - aclr : in vl_logic_vector(3 downto 0); - ena : in vl_logic_vector(3 downto 0); - sign : in vl_logic; - data_in : in vl_logic_vector; - data_out_0 : out vl_logic_vector; - data_out_1 : out vl_logic_vector; - data_out_2 : out vl_logic_vector; - data_out_3 : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_data_in : constant is 1; - attribute mti_svvh_generic_type of width_data_out : constant is 3; - attribute mti_svvh_generic_type of register_clock_0 : constant is 1; - attribute mti_svvh_generic_type of register_aclr_0 : constant is 1; - attribute mti_svvh_generic_type of register_clock_1 : constant is 1; - attribute mti_svvh_generic_type of register_aclr_1 : constant is 1; - attribute mti_svvh_generic_type of register_clock_2 : constant is 1; - attribute mti_svvh_generic_type of register_aclr_2 : constant is 1; - attribute mti_svvh_generic_type of register_clock_3 : constant is 1; - attribute mti_svvh_generic_type of register_aclr_3 : constant is 1; - attribute mti_svvh_generic_type of number_of_multipliers : constant is 1; - attribute mti_svvh_generic_type of port_sign : constant is 1; - attribute mti_svvh_generic_type of width_data_in_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_in_total_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_in_0_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_in_0_lsb : constant is 1; - attribute mti_svvh_generic_type of width_data_in_1_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_in_1_lsb : constant is 3; - attribute mti_svvh_generic_type of width_data_in_2_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_in_2_lsb : constant is 3; - attribute mti_svvh_generic_type of width_data_in_3_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_in_3_lsb : constant is 3; -end ama_data_split_reg_ext_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_dynamic_signed_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_dynamic_signed_function/_primary.dat deleted file mode 100644 index d1e28a5..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_dynamic_signed_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_dynamic_signed_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_dynamic_signed_function/_primary.dbs deleted file mode 100644 index 705ce13..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_dynamic_signed_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_dynamic_signed_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_dynamic_signed_function/_primary.vhd deleted file mode 100644 index 3267ef2..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_dynamic_signed_function/_primary.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_dynamic_signed_function is - generic( - port_sign : string := "PORT_CONNECTIVITY"; - width_data_in : integer := 1; - width_data_out : vl_notype; - width_data_in_msb: vl_notype; - width_data_out_msb: vl_notype; - width_data_out_wire: vl_notype; - width_data_out_wire_msb: vl_notype - ); - port( - data_in : in vl_logic_vector; - sign : in vl_logic; - data_out : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of port_sign : constant is 1; - attribute mti_svvh_generic_type of width_data_in : constant is 1; - attribute mti_svvh_generic_type of width_data_out : constant is 3; - attribute mti_svvh_generic_type of width_data_in_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_wire : constant is 3; - attribute mti_svvh_generic_type of width_data_out_wire_msb : constant is 3; -end ama_dynamic_signed_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_multiplier_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_multiplier_function/_primary.dat deleted file mode 100644 index b357e41..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_multiplier_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_multiplier_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_multiplier_function/_primary.dbs deleted file mode 100644 index 2fc3b80..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_multiplier_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_multiplier_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_multiplier_function/_primary.vhd deleted file mode 100644 index 033ba1e..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_multiplier_function/_primary.vhd +++ /dev/null @@ -1,68 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_multiplier_function is - generic( - width_data_in_a : integer := 1; - width_data_in_b : integer := 1; - width_data_out : integer := 1; - number_of_multipliers: integer := 1; - multiplier_input_representation_a: string := "UNSIGNED"; - multiplier_input_representation_b: string := "UNSIGNED"; - multiplier_register0: string := "UNREGISTERED"; - multiplier_register1: string := "UNREGISTERED"; - multiplier_register2: string := "UNREGISTERED"; - multiplier_register3: string := "UNREGISTERED"; - multiplier_aclr0: string := "UNUSED"; - multiplier_aclr1: string := "UNUSED"; - multiplier_aclr2: string := "UNUSED"; - multiplier_aclr3: string := "UNUSED"; - width_data_in_a_msb: vl_notype; - width_data_in_b_msb: vl_notype; - width_data_out_msb: vl_notype; - width_mult_input_a: vl_notype; - width_mult_input_a_msb: vl_notype; - width_mult_input_b: vl_notype; - width_mult_input_b_msb: vl_notype; - width_mult_output: vl_notype - ); - port( - clock : in vl_logic_vector(3 downto 0); - aclr : in vl_logic_vector(3 downto 0); - ena : in vl_logic_vector(3 downto 0); - data_in_a0 : in vl_logic_vector; - data_in_a1 : in vl_logic_vector; - data_in_a2 : in vl_logic_vector; - data_in_a3 : in vl_logic_vector; - data_in_b0 : in vl_logic_vector; - data_in_b1 : in vl_logic_vector; - data_in_b2 : in vl_logic_vector; - data_in_b3 : in vl_logic_vector; - data_out_0 : out vl_logic_vector; - data_out_1 : out vl_logic_vector; - data_out_2 : out vl_logic_vector; - data_out_3 : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_data_in_a : constant is 1; - attribute mti_svvh_generic_type of width_data_in_b : constant is 1; - attribute mti_svvh_generic_type of width_data_out : constant is 1; - attribute mti_svvh_generic_type of number_of_multipliers : constant is 1; - attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 1; - attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 1; - attribute mti_svvh_generic_type of multiplier_register0 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register1 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register2 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register3 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1; - attribute mti_svvh_generic_type of width_data_in_a_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_in_b_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_msb : constant is 3; - attribute mti_svvh_generic_type of width_mult_input_a : constant is 3; - attribute mti_svvh_generic_type of width_mult_input_a_msb : constant is 3; - attribute mti_svvh_generic_type of width_mult_input_b : constant is 3; - attribute mti_svvh_generic_type of width_mult_input_b_msb : constant is 3; - attribute mti_svvh_generic_type of width_mult_output : constant is 3; -end ama_multiplier_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_preadder_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_preadder_function/_primary.dat deleted file mode 100644 index 167f4d0..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_preadder_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_preadder_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_preadder_function/_primary.dbs deleted file mode 100644 index 7226659..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_preadder_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_preadder_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_preadder_function/_primary.vhd deleted file mode 100644 index 9ef05c5..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_preadder_function/_primary.vhd +++ /dev/null @@ -1,101 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_preadder_function is - generic( - preadder_mode : string := "SIMPLE"; - width_in_a : integer := 1; - width_in_b : integer := 1; - width_in_c : integer := 1; - width_in_coef : integer := 1; - width_result_a : integer := 1; - width_result_b : integer := 1; - preadder_direction_0: string := "ADD"; - preadder_direction_1: string := "ADD"; - preadder_direction_2: string := "ADD"; - preadder_direction_3: string := "ADD"; - representation_preadder_adder: string := "UNSIGNED"; - width_in_a_msb : vl_notype; - width_in_b_msb : vl_notype; - width_in_c_msb : vl_notype; - width_in_coef_msb: vl_notype; - width_result_a_msb: vl_notype; - width_result_b_msb: vl_notype; - width_preadder_adder_input: vl_notype; - width_preadder_adder_input_msb: vl_notype; - width_preadder_adder_result: vl_notype; - width_preadder_adder_result_msb: vl_notype; - width_preadder_adder_input_wire: vl_notype; - width_preadder_adder_input_wire_msb: vl_notype; - width_in_a_ext : vl_notype; - width_in_b_ext : vl_notype; - width_output_preadder: vl_notype; - width_output_preadder_msb: vl_notype; - width_output_coef: vl_notype; - width_output_coef_msb: vl_notype; - width_output_datab: vl_notype; - width_output_datab_msb: vl_notype; - width_output_datac: vl_notype; - width_output_datac_msb: vl_notype - ); - port( - dataa_in_0 : in vl_logic_vector; - dataa_in_1 : in vl_logic_vector; - dataa_in_2 : in vl_logic_vector; - dataa_in_3 : in vl_logic_vector; - datab_in_0 : in vl_logic_vector; - datab_in_1 : in vl_logic_vector; - datab_in_2 : in vl_logic_vector; - datab_in_3 : in vl_logic_vector; - datac_in_0 : in vl_logic_vector; - datac_in_1 : in vl_logic_vector; - datac_in_2 : in vl_logic_vector; - datac_in_3 : in vl_logic_vector; - coef0 : in vl_logic_vector; - coef1 : in vl_logic_vector; - coef2 : in vl_logic_vector; - coef3 : in vl_logic_vector; - result_a0 : out vl_logic_vector; - result_a1 : out vl_logic_vector; - result_a2 : out vl_logic_vector; - result_a3 : out vl_logic_vector; - result_b0 : out vl_logic_vector; - result_b1 : out vl_logic_vector; - result_b2 : out vl_logic_vector; - result_b3 : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of preadder_mode : constant is 1; - attribute mti_svvh_generic_type of width_in_a : constant is 1; - attribute mti_svvh_generic_type of width_in_b : constant is 1; - attribute mti_svvh_generic_type of width_in_c : constant is 1; - attribute mti_svvh_generic_type of width_in_coef : constant is 1; - attribute mti_svvh_generic_type of width_result_a : constant is 1; - attribute mti_svvh_generic_type of width_result_b : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1; - attribute mti_svvh_generic_type of representation_preadder_adder : constant is 1; - attribute mti_svvh_generic_type of width_in_a_msb : constant is 3; - attribute mti_svvh_generic_type of width_in_b_msb : constant is 3; - attribute mti_svvh_generic_type of width_in_c_msb : constant is 3; - attribute mti_svvh_generic_type of width_in_coef_msb : constant is 3; - attribute mti_svvh_generic_type of width_result_a_msb : constant is 3; - attribute mti_svvh_generic_type of width_result_b_msb : constant is 3; - attribute mti_svvh_generic_type of width_preadder_adder_input : constant is 3; - attribute mti_svvh_generic_type of width_preadder_adder_input_msb : constant is 3; - attribute mti_svvh_generic_type of width_preadder_adder_result : constant is 3; - attribute mti_svvh_generic_type of width_preadder_adder_result_msb : constant is 3; - attribute mti_svvh_generic_type of width_preadder_adder_input_wire : constant is 3; - attribute mti_svvh_generic_type of width_preadder_adder_input_wire_msb : constant is 3; - attribute mti_svvh_generic_type of width_in_a_ext : constant is 3; - attribute mti_svvh_generic_type of width_in_b_ext : constant is 3; - attribute mti_svvh_generic_type of width_output_preadder : constant is 3; - attribute mti_svvh_generic_type of width_output_preadder_msb : constant is 3; - attribute mti_svvh_generic_type of width_output_coef : constant is 3; - attribute mti_svvh_generic_type of width_output_coef_msb : constant is 3; - attribute mti_svvh_generic_type of width_output_datab : constant is 3; - attribute mti_svvh_generic_type of width_output_datab_msb : constant is 3; - attribute mti_svvh_generic_type of width_output_datac : constant is 3; - attribute mti_svvh_generic_type of width_output_datac_msb : constant is 3; -end ama_preadder_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_function/_primary.dat deleted file mode 100644 index 6e68fe5..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_function/_primary.dbs deleted file mode 100644 index c657a3a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_function/_primary.vhd deleted file mode 100644 index e5e35e2..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_function/_primary.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_register_function is - generic( - width_data_in : integer := 1; - width_data_out : integer := 1; - register_clock : string := "UNREGISTERED"; - register_aclr : string := "UNUSED"; - width_data_in_msb: vl_notype; - width_data_out_msb: vl_notype - ); - port( - clock : in vl_logic_vector(3 downto 0); - aclr : in vl_logic_vector(3 downto 0); - ena : in vl_logic_vector(3 downto 0); - data_in : in vl_logic_vector; - data_out : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_data_in : constant is 1; - attribute mti_svvh_generic_type of width_data_out : constant is 1; - attribute mti_svvh_generic_type of register_clock : constant is 1; - attribute mti_svvh_generic_type of register_aclr : constant is 1; - attribute mti_svvh_generic_type of width_data_in_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_msb : constant is 3; -end ama_register_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_with_ext_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_with_ext_function/_primary.dat deleted file mode 100644 index cc43599..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_with_ext_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_with_ext_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_with_ext_function/_primary.dbs deleted file mode 100644 index ddb7757..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_with_ext_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_with_ext_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_with_ext_function/_primary.vhd deleted file mode 100644 index 7002d73..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_register_with_ext_function/_primary.vhd +++ /dev/null @@ -1,33 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_register_with_ext_function is - generic( - width_data_in : integer := 1; - width_data_out : vl_notype; - register_clock : string := "UNREGISTERED"; - register_aclr : string := "UNUSED"; - port_sign : string := "PORT_CONNECTIVITY"; - width_data_in_msb: vl_notype; - width_data_out_msb: vl_notype; - width_sign_ext_output: vl_notype; - width_sign_ext_output_msb: vl_notype - ); - port( - clock : in vl_logic_vector(3 downto 0); - aclr : in vl_logic_vector(3 downto 0); - ena : in vl_logic_vector(3 downto 0); - sign : in vl_logic; - data_in : in vl_logic_vector; - data_out : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_data_in : constant is 1; - attribute mti_svvh_generic_type of width_data_out : constant is 3; - attribute mti_svvh_generic_type of register_clock : constant is 1; - attribute mti_svvh_generic_type of register_aclr : constant is 1; - attribute mti_svvh_generic_type of port_sign : constant is 1; - attribute mti_svvh_generic_type of width_data_in_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_msb : constant is 3; - attribute mti_svvh_generic_type of width_sign_ext_output : constant is 3; - attribute mti_svvh_generic_type of width_sign_ext_output_msb : constant is 3; -end ama_register_with_ext_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_scanchain/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_scanchain/_primary.dat deleted file mode 100644 index 7bebbf0..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_scanchain/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_scanchain/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_scanchain/_primary.dbs deleted file mode 100644 index 11834ca..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_scanchain/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_scanchain/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_scanchain/_primary.vhd deleted file mode 100644 index ee68f3d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_scanchain/_primary.vhd +++ /dev/null @@ -1,51 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_scanchain is - generic( - width_scanin : integer := 1; - width_scanchain : integer := 1; - input_register_clock_0: string := "UNREGISTERED"; - input_register_aclr_0: string := "UNUSED"; - input_register_clock_1: string := "UNREGISTERED"; - input_register_aclr_1: string := "UNUSED"; - input_register_clock_2: string := "UNREGISTERED"; - input_register_aclr_2: string := "UNUSED"; - input_register_clock_3: string := "UNREGISTERED"; - input_register_aclr_3: string := "UNUSED"; - scanchain_register_clock: string := "UNREGISTERED"; - scanchain_register_aclr: string := "UNUSED"; - port_sign : string := "PORT_CONNECTIVITY"; - number_of_multipliers: integer := 1; - width_scanin_msb: vl_notype; - width_scanchain_msb: vl_notype - ); - port( - clock : in vl_logic_vector(3 downto 0); - aclr : in vl_logic_vector(3 downto 0); - ena : in vl_logic_vector(3 downto 0); - sign : in vl_logic; - scanin : in vl_logic_vector; - data_out_0 : out vl_logic_vector; - data_out_1 : out vl_logic_vector; - data_out_2 : out vl_logic_vector; - data_out_3 : out vl_logic_vector; - scanout : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_scanin : constant is 1; - attribute mti_svvh_generic_type of width_scanchain : constant is 1; - attribute mti_svvh_generic_type of input_register_clock_0 : constant is 1; - attribute mti_svvh_generic_type of input_register_aclr_0 : constant is 1; - attribute mti_svvh_generic_type of input_register_clock_1 : constant is 1; - attribute mti_svvh_generic_type of input_register_aclr_1 : constant is 1; - attribute mti_svvh_generic_type of input_register_clock_2 : constant is 1; - attribute mti_svvh_generic_type of input_register_aclr_2 : constant is 1; - attribute mti_svvh_generic_type of input_register_clock_3 : constant is 1; - attribute mti_svvh_generic_type of input_register_aclr_3 : constant is 1; - attribute mti_svvh_generic_type of scanchain_register_clock : constant is 1; - attribute mti_svvh_generic_type of scanchain_register_aclr : constant is 1; - attribute mti_svvh_generic_type of port_sign : constant is 1; - attribute mti_svvh_generic_type of number_of_multipliers : constant is 1; - attribute mti_svvh_generic_type of width_scanin_msb : constant is 3; - attribute mti_svvh_generic_type of width_scanchain_msb : constant is 3; -end ama_scanchain; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_signed_extension_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_signed_extension_function/_primary.dat deleted file mode 100644 index 5b3fd3d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_signed_extension_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_signed_extension_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_signed_extension_function/_primary.dbs deleted file mode 100644 index 514c06a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_signed_extension_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_signed_extension_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_signed_extension_function/_primary.vhd deleted file mode 100644 index 2f2a53e..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_signed_extension_function/_primary.vhd +++ /dev/null @@ -1,25 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_signed_extension_function is - generic( - representation : string := "UNSIGNED"; - width_data_in : integer := 1; - width_data_out : vl_notype; - width_data_in_msb: vl_notype; - width_data_out_msb: vl_notype; - width_data_ext : vl_notype; - wdith_data_ext_msb: vl_notype - ); - port( - data_in : in vl_logic_vector; - data_out : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of representation : constant is 1; - attribute mti_svvh_generic_type of width_data_in : constant is 1; - attribute mti_svvh_generic_type of width_data_out : constant is 3; - attribute mti_svvh_generic_type of width_data_in_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_ext : constant is 3; - attribute mti_svvh_generic_type of wdith_data_ext_msb : constant is 3; -end ama_signed_extension_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_systolic_adder_function/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_systolic_adder_function/_primary.dat deleted file mode 100644 index 38ea14f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_systolic_adder_function/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_systolic_adder_function/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_systolic_adder_function/_primary.dbs deleted file mode 100644 index a6a0eb4..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_systolic_adder_function/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_systolic_adder_function/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_systolic_adder_function/_primary.vhd deleted file mode 100644 index 78e424f..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/ama_systolic_adder_function/_primary.vhd +++ /dev/null @@ -1,50 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ama_systolic_adder_function is - generic( - width_data_in : integer := 1; - width_chainin : integer := 1; - width_data_out : integer := 1; - number_of_adder_input: integer := 1; - systolic_delay1 : string := "UNREGISTERED"; - systolic_aclr1 : string := "UNUSED"; - systolic_delay3 : string := "UNREGISTERED"; - systolic_aclr3 : string := "UNUSED"; - adder1_direction: string := "UNUSED"; - adder3_direction: string := "UNUSED"; - width_data_in_msb: vl_notype; - width_data_out_msb: vl_notype; - width_chainin_msb: vl_notype; - width_systolic_ext: vl_notype; - width_systolic_ext_msb: vl_notype; - input_ext_width : vl_notype - ); - port( - data_in_0 : in vl_logic_vector; - data_in_1 : in vl_logic_vector; - data_in_2 : in vl_logic_vector; - data_in_3 : in vl_logic_vector; - chainin : in vl_logic_vector; - clock : in vl_logic_vector(3 downto 0); - aclr : in vl_logic_vector(3 downto 0); - ena : in vl_logic_vector(3 downto 0); - data_out : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_data_in : constant is 1; - attribute mti_svvh_generic_type of width_chainin : constant is 1; - attribute mti_svvh_generic_type of width_data_out : constant is 1; - attribute mti_svvh_generic_type of number_of_adder_input : constant is 1; - attribute mti_svvh_generic_type of systolic_delay1 : constant is 1; - attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1; - attribute mti_svvh_generic_type of systolic_delay3 : constant is 1; - attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1; - attribute mti_svvh_generic_type of adder1_direction : constant is 1; - attribute mti_svvh_generic_type of adder3_direction : constant is 1; - attribute mti_svvh_generic_type of width_data_in_msb : constant is 3; - attribute mti_svvh_generic_type of width_data_out_msb : constant is 3; - attribute mti_svvh_generic_type of width_chainin_msb : constant is 3; - attribute mti_svvh_generic_type of width_systolic_ext : constant is 3; - attribute mti_svvh_generic_type of width_systolic_ext_msb : constant is 3; - attribute mti_svvh_generic_type of input_ext_width : constant is 3; -end ama_systolic_adder_function; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell/_primary.dat deleted file mode 100644 index 2122061..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell/_primary.dbs deleted file mode 100644 index d8c9881..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell/_primary.vhd deleted file mode 100644 index 77c7d6e..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell/_primary.vhd +++ /dev/null @@ -1,64 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity common_28nm_mlab_cell is - generic( - logical_ram_name: string := "lutram"; - logical_ram_depth: integer := 0; - logical_ram_width: integer := 0; - first_address : integer := 0; - last_address : integer := 0; - first_bit_number: integer := 0; - mixed_port_feed_through_mode: string := "new"; - init_file : string := "NONE"; - data_width : integer := 20; - address_width : integer := 6; - byte_enable_mask_width: integer := 1; - byte_size : integer := 1; - port_b_data_out_clock: string := "none"; - port_b_data_out_clear: string := "none"; - lpm_type : string := "common_28nm_mlab_cell"; - lpm_hint : string := "true"; - mem_init0 : string := ""; - MEM_INIT_STRING_LENGTH: integer := 160; - port_byte_size : vl_notype; - num_rows : vl_notype; - num_cols : integer := 1 - ); - port( - portadatain : in vl_logic_vector; - portaaddr : in vl_logic_vector; - portabyteenamasks: in vl_logic_vector; - portbaddr : in vl_logic_vector; - clk0 : in vl_logic; - clk1 : in vl_logic; - ena0 : in vl_logic; - ena1 : in vl_logic; - ena2 : in vl_logic; - clr : in vl_logic; - devclrn : in vl_logic; - devpor : in vl_logic; - portbdataout : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of logical_ram_name : constant is 1; - attribute mti_svvh_generic_type of logical_ram_depth : constant is 1; - attribute mti_svvh_generic_type of logical_ram_width : constant is 1; - attribute mti_svvh_generic_type of first_address : constant is 1; - attribute mti_svvh_generic_type of last_address : constant is 1; - attribute mti_svvh_generic_type of first_bit_number : constant is 1; - attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1; - attribute mti_svvh_generic_type of init_file : constant is 1; - attribute mti_svvh_generic_type of data_width : constant is 1; - attribute mti_svvh_generic_type of address_width : constant is 1; - attribute mti_svvh_generic_type of byte_enable_mask_width : constant is 1; - attribute mti_svvh_generic_type of byte_size : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of mem_init0 : constant is 1; - attribute mti_svvh_generic_type of MEM_INIT_STRING_LENGTH : constant is 1; - attribute mti_svvh_generic_type of port_byte_size : constant is 3; - attribute mti_svvh_generic_type of num_rows : constant is 3; - attribute mti_svvh_generic_type of num_cols : constant is 1; -end common_28nm_mlab_cell; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell_pulse_generator/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell_pulse_generator/_primary.dat deleted file mode 100644 index 3c12740..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell_pulse_generator/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell_pulse_generator/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell_pulse_generator/_primary.dbs deleted file mode 100644 index a00470f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell_pulse_generator/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell_pulse_generator/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell_pulse_generator/_primary.vhd deleted file mode 100644 index 0fd4cbb..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_mlab_cell_pulse_generator/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity common_28nm_mlab_cell_pulse_generator is - port( - clk : in vl_logic; - ena : in vl_logic; - pulse : out vl_logic; - cycle : out vl_logic - ); -end common_28nm_mlab_cell_pulse_generator; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_block/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_block/_primary.dat deleted file mode 100644 index 1bf5bde..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_block/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_block/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_block/_primary.dbs deleted file mode 100644 index 3d6ca00..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_block/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_block/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_block/_primary.vhd deleted file mode 100644 index 71815dd..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_block/_primary.vhd +++ /dev/null @@ -1,228 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity common_28nm_ram_block is - generic( - operation_mode : string := "single_port"; - mixed_port_feed_through_mode: string := "dont_care"; - ram_block_type : string := "auto"; - logical_ram_name: string := "ram_name"; - init_file : string := "init_file.hex"; - init_file_layout: string := "none"; - ecc_pipeline_stage_enabled: string := "false"; - enable_ecc : string := "false"; - width_eccstatus : integer := 2; - data_interleave_width_in_bits: integer := 1; - data_interleave_offset_in_bits: integer := 1; - port_a_logical_ram_depth: integer := 0; - port_a_logical_ram_width: integer := 0; - port_a_first_address: integer := 0; - port_a_last_address: integer := 0; - port_a_first_bit_number: integer := 0; - port_a_data_out_clear: string := "none"; - port_a_data_out_clock: string := "none"; - port_a_data_width: integer := 1; - port_a_address_width: integer := 1; - port_a_byte_enable_mask_width: integer := 1; - port_b_logical_ram_depth: integer := 0; - port_b_logical_ram_width: integer := 0; - port_b_first_address: integer := 0; - port_b_last_address: integer := 0; - port_b_first_bit_number: integer := 0; - port_b_address_clear: string := "none"; - port_b_data_out_clear: string := "none"; - port_b_data_in_clock: string := "clock1"; - port_b_address_clock: string := "clock1"; - port_b_write_enable_clock: string := "clock1"; - port_b_read_enable_clock: string := "clock1"; - port_b_byte_enable_clock: string := "clock1"; - port_b_data_out_clock: string := "none"; - port_b_data_width: integer := 1; - port_b_address_width: integer := 1; - port_b_byte_enable_mask_width: integer := 1; - port_a_read_during_write_mode: string := "new_data_no_nbe_read"; - port_b_read_during_write_mode: string := "new_data_no_nbe_read"; - power_up_uninitialized: string := "false"; - lpm_type : string := "stratixv_ram_block"; - lpm_hint : string := "true"; - connectivity_checking: string := "off"; - mem_init0 : string := ""; - mem_init1 : string := ""; - mem_init2 : string := ""; - mem_init3 : string := ""; - mem_init4 : string := ""; - mem_init5 : string := ""; - mem_init6 : string := ""; - mem_init7 : string := ""; - mem_init8 : string := ""; - mem_init9 : string := ""; - port_a_byte_size: integer := 0; - port_b_byte_size: integer := 0; - clk0_input_clock_enable: string := "none"; - clk0_core_clock_enable: string := "none"; - clk0_output_clock_enable: string := "none"; - clk1_input_clock_enable: string := "none"; - clk1_core_clock_enable: string := "none"; - clk1_output_clock_enable: string := "none"; - bist_ena : string := "false"; - port_a_address_clear: string := "none"; - port_a_data_in_clock: string := "clock0"; - port_a_address_clock: string := "clock0"; - port_a_write_enable_clock: string := "clock0"; - port_a_byte_enable_clock: string := "clock0"; - port_a_read_enable_clock: string := "clock0"; - MEM_INIT_STRING_LENGTH: integer := 512; - primary_port_is_a: vl_notype; - primary_port_is_b: vl_notype; - mode_is_rom_or_sp: vl_notype; - data_width : vl_notype; - data_unit_width : vl_notype; - address_width : vl_notype; - address_unit_width: vl_notype; - wired_mode : vl_notype; - num_rows : vl_notype; - num_cols : vl_notype; - mask_width_prime: vl_notype; - mask_width_sec : vl_notype; - byte_size_a : vl_notype; - byte_size_b : vl_notype; - mode_is_dp : vl_notype; - dual_clock : vl_notype; - both_new_data_same_port: vl_notype; - hw_write_mode_a : vl_notype; - hw_write_mode_b : vl_notype; - delay_write_pulse_a: vl_notype; - delay_write_pulse_b: vl_notype; - be_mask_write_a : vl_notype; - be_mask_write_b : vl_notype; - old_data_write_a: vl_notype; - old_data_write_b: vl_notype; - read_before_write_a: vl_notype; - read_before_write_b: vl_notype - ); - port( - portadatain : in vl_logic_vector; - portaaddr : in vl_logic_vector; - portawe : in vl_logic; - portare : in vl_logic; - portbdatain : in vl_logic_vector; - portbaddr : in vl_logic_vector; - portbwe : in vl_logic; - portbre : in vl_logic; - clk0 : in vl_logic; - clk1 : in vl_logic; - ena0 : in vl_logic; - ena1 : in vl_logic; - ena2 : in vl_logic; - ena3 : in vl_logic; - clr0 : in vl_logic; - clr1 : in vl_logic; - nerror : in vl_logic; - portabyteenamasks: in vl_logic_vector; - portbbyteenamasks: in vl_logic_vector; - portaaddrstall : in vl_logic; - portbaddrstall : in vl_logic; - devclrn : in vl_logic; - devpor : in vl_logic; - eccstatus : out vl_logic_vector; - portadataout : out vl_logic_vector; - portbdataout : out vl_logic_vector; - dftout : out vl_logic_vector(8 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1; - attribute mti_svvh_generic_type of ram_block_type : constant is 1; - attribute mti_svvh_generic_type of logical_ram_name : constant is 1; - attribute mti_svvh_generic_type of init_file : constant is 1; - attribute mti_svvh_generic_type of init_file_layout : constant is 1; - attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1; - attribute mti_svvh_generic_type of enable_ecc : constant is 1; - attribute mti_svvh_generic_type of width_eccstatus : constant is 1; - attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1; - attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1; - attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1; - attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1; - attribute mti_svvh_generic_type of port_a_first_address : constant is 1; - attribute mti_svvh_generic_type of port_a_last_address : constant is 1; - attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1; - attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1; - attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_data_width : constant is 1; - attribute mti_svvh_generic_type of port_a_address_width : constant is 1; - attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1; - attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1; - attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1; - attribute mti_svvh_generic_type of port_b_first_address : constant is 1; - attribute mti_svvh_generic_type of port_b_last_address : constant is 1; - attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1; - attribute mti_svvh_generic_type of port_b_address_clear : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1; - attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_address_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_data_width : constant is 1; - attribute mti_svvh_generic_type of port_b_address_width : constant is 1; - attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1; - attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1; - attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1; - attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of connectivity_checking : constant is 1; - attribute mti_svvh_generic_type of mem_init0 : constant is 1; - attribute mti_svvh_generic_type of mem_init1 : constant is 1; - attribute mti_svvh_generic_type of mem_init2 : constant is 1; - attribute mti_svvh_generic_type of mem_init3 : constant is 1; - attribute mti_svvh_generic_type of mem_init4 : constant is 1; - attribute mti_svvh_generic_type of mem_init5 : constant is 1; - attribute mti_svvh_generic_type of mem_init6 : constant is 1; - attribute mti_svvh_generic_type of mem_init7 : constant is 1; - attribute mti_svvh_generic_type of mem_init8 : constant is 1; - attribute mti_svvh_generic_type of mem_init9 : constant is 1; - attribute mti_svvh_generic_type of port_a_byte_size : constant is 1; - attribute mti_svvh_generic_type of port_b_byte_size : constant is 1; - attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1; - attribute mti_svvh_generic_type of bist_ena : constant is 1; - attribute mti_svvh_generic_type of port_a_address_clear : constant is 1; - attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_address_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1; - attribute mti_svvh_generic_type of MEM_INIT_STRING_LENGTH : constant is 1; - attribute mti_svvh_generic_type of primary_port_is_a : constant is 3; - attribute mti_svvh_generic_type of primary_port_is_b : constant is 3; - attribute mti_svvh_generic_type of mode_is_rom_or_sp : constant is 3; - attribute mti_svvh_generic_type of data_width : constant is 3; - attribute mti_svvh_generic_type of data_unit_width : constant is 3; - attribute mti_svvh_generic_type of address_width : constant is 3; - attribute mti_svvh_generic_type of address_unit_width : constant is 3; - attribute mti_svvh_generic_type of wired_mode : constant is 3; - attribute mti_svvh_generic_type of num_rows : constant is 3; - attribute mti_svvh_generic_type of num_cols : constant is 3; - attribute mti_svvh_generic_type of mask_width_prime : constant is 3; - attribute mti_svvh_generic_type of mask_width_sec : constant is 3; - attribute mti_svvh_generic_type of byte_size_a : constant is 3; - attribute mti_svvh_generic_type of byte_size_b : constant is 3; - attribute mti_svvh_generic_type of mode_is_dp : constant is 3; - attribute mti_svvh_generic_type of dual_clock : constant is 3; - attribute mti_svvh_generic_type of both_new_data_same_port : constant is 3; - attribute mti_svvh_generic_type of hw_write_mode_a : constant is 3; - attribute mti_svvh_generic_type of hw_write_mode_b : constant is 3; - attribute mti_svvh_generic_type of delay_write_pulse_a : constant is 3; - attribute mti_svvh_generic_type of delay_write_pulse_b : constant is 3; - attribute mti_svvh_generic_type of be_mask_write_a : constant is 3; - attribute mti_svvh_generic_type of be_mask_write_b : constant is 3; - attribute mti_svvh_generic_type of old_data_write_a : constant is 3; - attribute mti_svvh_generic_type of old_data_write_b : constant is 3; - attribute mti_svvh_generic_type of read_before_write_a : constant is 3; - attribute mti_svvh_generic_type of read_before_write_b : constant is 3; -end common_28nm_ram_block; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_pulse_generator/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_pulse_generator/_primary.dat deleted file mode 100644 index 6ca95f0..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_pulse_generator/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_pulse_generator/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_pulse_generator/_primary.dbs deleted file mode 100644 index 847aede..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_pulse_generator/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_pulse_generator/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_pulse_generator/_primary.vhd deleted file mode 100644 index 99fd0db..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_pulse_generator/_primary.vhd +++ /dev/null @@ -1,17 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity common_28nm_ram_pulse_generator is - generic( - delay_pulse : vl_logic := Hi0; - start_delay : vl_notype - ); - port( - clk : in vl_logic; - ena : in vl_logic; - pulse : out vl_logic; - cycle : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of delay_pulse : constant is 1; - attribute mti_svvh_generic_type of start_delay : constant is 3; -end common_28nm_ram_pulse_generator; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_register/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_register/_primary.dat deleted file mode 100644 index 6d6dce0..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_register/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_register/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_register/_primary.dbs deleted file mode 100644 index 2b5f0fa..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_register/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_register/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_register/_primary.vhd deleted file mode 100644 index e43f018..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/common_28nm_ram_register/_primary.vhd +++ /dev/null @@ -1,22 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity common_28nm_ram_register is - generic( - width : integer := 1; - preset : vl_logic := Hi0 - ); - port( - d : in vl_logic_vector; - clk : in vl_logic; - aclr : in vl_logic; - devclrn : in vl_logic; - devpor : in vl_logic; - stall : in vl_logic; - ena : in vl_logic; - q : out vl_logic_vector; - aclrout : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of preset : constant is 1; -end common_28nm_ram_register; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_cdr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_cdr/_primary.dat deleted file mode 100644 index 9b9d262..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_cdr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_cdr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_cdr/_primary.dbs deleted file mode 100644 index 1e64dbe..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_cdr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_cdr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_cdr/_primary.vhd deleted file mode 100644 index 89cbdda..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_cdr/_primary.vhd +++ /dev/null @@ -1,33 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity generic_cdr is - generic( - reference_clock_frequency: string := "0 ps"; - output_clock_frequency: string := "0 ps"; - sim_debug_msg : string := "false" - ); - port( - extclk : in vl_logic; - ltd : in vl_logic; - ltr : in vl_logic; - pciel : in vl_logic; - pciem : in vl_logic; - ppmlock : in vl_logic; - refclk : in vl_logic; - rst : in vl_logic; - sd : in vl_logic; - rxp : in vl_logic; - clk90bdes : out vl_logic; - clk270bdes : out vl_logic; - clklow : out vl_logic; - deven : out vl_logic; - dodd : out vl_logic; - fref : out vl_logic; - pfdmodelock : out vl_logic; - rxplllock : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency : constant is 1; - attribute mti_svvh_generic_type of sim_debug_msg : constant is 1; -end generic_cdr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_device_pll/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_device_pll/_primary.dat deleted file mode 100644 index 1887c0f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_device_pll/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_device_pll/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_device_pll/_primary.dbs deleted file mode 100644 index f327ae2..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_device_pll/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_device_pll/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_device_pll/_primary.vhd deleted file mode 100644 index d3688dd..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_device_pll/_primary.vhd +++ /dev/null @@ -1,64 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity generic_device_pll is - generic( - reference_clock_frequency: string := "0 ps"; - output_clock_frequency: string := "0 ps"; - forcelock : string := "false"; - nreset_invert : string := "false"; - pll_enable : string := "false"; - pll_fbclk_mux_1 : string := "glb"; - pll_fbclk_mux_2 : string := "fb_1"; - pll_m_cnt_bypass_en: string := "false"; - pll_m_cnt_hi_div: integer := 1; - pll_m_cnt_in_src: string := "ph_mux_clk"; - pll_m_cnt_lo_div: integer := 1; - pll_n_cnt_bypass_en: string := "false"; - pll_n_cnt_hi_div: integer := 1; - pll_n_cnt_lo_div: integer := 1; - pll_vco_ph0_en : string := "false"; - pll_vco_ph1_en : string := "false"; - pll_vco_ph2_en : string := "false"; - pll_vco_ph3_en : string := "false"; - pll_vco_ph4_en : string := "false"; - pll_vco_ph5_en : string := "false"; - pll_vco_ph6_en : string := "false"; - pll_vco_ph7_en : string := "false" - ); - port( - coreclkfb : in vl_logic; - fbclkfpll : in vl_logic; - lvdsfbin : in vl_logic; - nresync : in vl_logic; - pfden : in vl_logic; - refclkin : in vl_logic; - zdb : in vl_logic; - fbclk : out vl_logic; - fblvdsout : out vl_logic; - lock : out vl_logic; - vcoph : out vl_logic_vector(7 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency : constant is 1; - attribute mti_svvh_generic_type of forcelock : constant is 1; - attribute mti_svvh_generic_type of nreset_invert : constant is 1; - attribute mti_svvh_generic_type of pll_enable : constant is 1; - attribute mti_svvh_generic_type of pll_fbclk_mux_1 : constant is 1; - attribute mti_svvh_generic_type of pll_fbclk_mux_2 : constant is 1; - attribute mti_svvh_generic_type of pll_m_cnt_bypass_en : constant is 1; - attribute mti_svvh_generic_type of pll_m_cnt_hi_div : constant is 1; - attribute mti_svvh_generic_type of pll_m_cnt_in_src : constant is 1; - attribute mti_svvh_generic_type of pll_m_cnt_lo_div : constant is 1; - attribute mti_svvh_generic_type of pll_n_cnt_bypass_en : constant is 1; - attribute mti_svvh_generic_type of pll_n_cnt_hi_div : constant is 1; - attribute mti_svvh_generic_type of pll_n_cnt_lo_div : constant is 1; - attribute mti_svvh_generic_type of pll_vco_ph0_en : constant is 1; - attribute mti_svvh_generic_type of pll_vco_ph1_en : constant is 1; - attribute mti_svvh_generic_type of pll_vco_ph2_en : constant is 1; - attribute mti_svvh_generic_type of pll_vco_ph3_en : constant is 1; - attribute mti_svvh_generic_type of pll_vco_ph4_en : constant is 1; - attribute mti_svvh_generic_type of pll_vco_ph5_en : constant is 1; - attribute mti_svvh_generic_type of pll_vco_ph6_en : constant is 1; - attribute mti_svvh_generic_type of pll_vco_ph7_en : constant is 1; -end generic_device_pll; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m10k/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m10k/_primary.dat deleted file mode 100644 index 65612bb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m10k/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m10k/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m10k/_primary.dbs deleted file mode 100644 index 3bf28ab..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m10k/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m10k/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m10k/_primary.vhd deleted file mode 100644 index 0a698e2..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m10k/_primary.vhd +++ /dev/null @@ -1,162 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity generic_m10k is - generic( - operation_mode : string := "single_port"; - mixed_port_feed_through_mode: string := "dont_care"; - ram_block_type : string := "auto"; - logical_ram_name: string := "ram_name"; - init_file : string := "init_file.hex"; - init_file_layout: string := "none"; - ecc_pipeline_stage_enabled: string := "false"; - enable_ecc : string := "false"; - width_eccstatus : integer := 2; - data_interleave_width_in_bits: integer := 1; - data_interleave_offset_in_bits: integer := 1; - port_a_logical_ram_depth: integer := 0; - port_a_logical_ram_width: integer := 0; - port_a_first_address: integer := 0; - port_a_last_address: integer := 0; - port_a_first_bit_number: integer := 0; - port_a_data_out_clear: string := "none"; - port_a_data_out_clock: string := "none"; - port_a_data_width: integer := 1; - port_a_address_width: integer := 1; - port_a_byte_enable_mask_width: integer := 1; - port_b_logical_ram_depth: integer := 0; - port_b_logical_ram_width: integer := 0; - port_b_first_address: integer := 0; - port_b_last_address: integer := 0; - port_b_first_bit_number: integer := 0; - port_b_address_clear: string := "none"; - port_b_data_out_clear: string := "none"; - port_b_data_in_clock: string := "clock1"; - port_b_address_clock: string := "clock1"; - port_b_write_enable_clock: string := "clock1"; - port_b_read_enable_clock: string := "clock1"; - port_b_byte_enable_clock: string := "clock1"; - port_b_data_out_clock: string := "none"; - port_b_data_width: integer := 1; - port_b_address_width: integer := 1; - port_b_byte_enable_mask_width: integer := 1; - port_a_read_during_write_mode: string := "new_data_no_nbe_read"; - port_b_read_during_write_mode: string := "new_data_no_nbe_read"; - power_up_uninitialized: string := "false"; - lpm_type : string := "arriav_ram_block"; - lpm_hint : string := "true"; - connectivity_checking: string := "off"; - mem_init0 : string := ""; - mem_init1 : string := ""; - mem_init2 : string := ""; - mem_init3 : string := ""; - mem_init4 : string := ""; - port_a_byte_size: integer := 0; - port_b_byte_size: integer := 0; - clk0_input_clock_enable: string := "none"; - clk0_core_clock_enable: string := "none"; - clk0_output_clock_enable: string := "none"; - clk1_input_clock_enable: string := "none"; - clk1_core_clock_enable: string := "none"; - clk1_output_clock_enable: string := "none"; - bist_ena : string := "false"; - port_a_address_clear: string := "none"; - port_a_data_in_clock: string := "clock0"; - port_a_address_clock: string := "clock0"; - port_a_write_enable_clock: string := "clock0"; - port_a_byte_enable_clock: string := "clock0"; - port_a_read_enable_clock: string := "clock0" - ); - port( - portadatain : in vl_logic_vector; - portaaddr : in vl_logic_vector; - portawe : in vl_logic; - portare : in vl_logic; - portbdatain : in vl_logic_vector; - portbaddr : in vl_logic_vector; - portbwe : in vl_logic; - portbre : in vl_logic; - clk0 : in vl_logic; - clk1 : in vl_logic; - ena0 : in vl_logic; - ena1 : in vl_logic; - ena2 : in vl_logic; - ena3 : in vl_logic; - clr0 : in vl_logic; - clr1 : in vl_logic; - nerror : in vl_logic; - portabyteenamasks: in vl_logic_vector; - portbbyteenamasks: in vl_logic_vector; - portaaddrstall : in vl_logic; - portbaddrstall : in vl_logic; - devclrn : in vl_logic; - devpor : in vl_logic; - eccstatus : out vl_logic_vector; - portadataout : out vl_logic_vector; - portbdataout : out vl_logic_vector; - dftout : out vl_logic_vector(8 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1; - attribute mti_svvh_generic_type of ram_block_type : constant is 1; - attribute mti_svvh_generic_type of logical_ram_name : constant is 1; - attribute mti_svvh_generic_type of init_file : constant is 1; - attribute mti_svvh_generic_type of init_file_layout : constant is 1; - attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1; - attribute mti_svvh_generic_type of enable_ecc : constant is 1; - attribute mti_svvh_generic_type of width_eccstatus : constant is 1; - attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1; - attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1; - attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1; - attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1; - attribute mti_svvh_generic_type of port_a_first_address : constant is 1; - attribute mti_svvh_generic_type of port_a_last_address : constant is 1; - attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1; - attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1; - attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_data_width : constant is 1; - attribute mti_svvh_generic_type of port_a_address_width : constant is 1; - attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1; - attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1; - attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1; - attribute mti_svvh_generic_type of port_b_first_address : constant is 1; - attribute mti_svvh_generic_type of port_b_last_address : constant is 1; - attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1; - attribute mti_svvh_generic_type of port_b_address_clear : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1; - attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_address_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_data_width : constant is 1; - attribute mti_svvh_generic_type of port_b_address_width : constant is 1; - attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1; - attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1; - attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1; - attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of connectivity_checking : constant is 1; - attribute mti_svvh_generic_type of mem_init0 : constant is 1; - attribute mti_svvh_generic_type of mem_init1 : constant is 1; - attribute mti_svvh_generic_type of mem_init2 : constant is 1; - attribute mti_svvh_generic_type of mem_init3 : constant is 1; - attribute mti_svvh_generic_type of mem_init4 : constant is 1; - attribute mti_svvh_generic_type of port_a_byte_size : constant is 1; - attribute mti_svvh_generic_type of port_b_byte_size : constant is 1; - attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1; - attribute mti_svvh_generic_type of bist_ena : constant is 1; - attribute mti_svvh_generic_type of port_a_address_clear : constant is 1; - attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_address_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1; -end generic_m10k; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m20k/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m20k/_primary.dat deleted file mode 100644 index d35d790..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m20k/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m20k/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m20k/_primary.dbs deleted file mode 100644 index 656ad21..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m20k/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m20k/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m20k/_primary.vhd deleted file mode 100644 index 1fbdbfe..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_m20k/_primary.vhd +++ /dev/null @@ -1,172 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity generic_m20k is - generic( - operation_mode : string := "single_port"; - mixed_port_feed_through_mode: string := "dont_care"; - ram_block_type : string := "auto"; - logical_ram_name: string := "ram_name"; - init_file : string := "init_file.hex"; - init_file_layout: string := "none"; - ecc_pipeline_stage_enabled: string := "false"; - enable_ecc : string := "false"; - width_eccstatus : integer := 2; - data_interleave_width_in_bits: integer := 1; - data_interleave_offset_in_bits: integer := 1; - port_a_logical_ram_depth: integer := 0; - port_a_logical_ram_width: integer := 0; - port_a_first_address: integer := 0; - port_a_last_address: integer := 0; - port_a_first_bit_number: integer := 0; - port_a_data_out_clear: string := "none"; - port_a_data_out_clock: string := "none"; - port_a_data_width: integer := 1; - port_a_address_width: integer := 1; - port_a_byte_enable_mask_width: integer := 1; - port_b_logical_ram_depth: integer := 0; - port_b_logical_ram_width: integer := 0; - port_b_first_address: integer := 0; - port_b_last_address: integer := 0; - port_b_first_bit_number: integer := 0; - port_b_address_clear: string := "none"; - port_b_data_out_clear: string := "none"; - port_b_data_in_clock: string := "clock1"; - port_b_address_clock: string := "clock1"; - port_b_write_enable_clock: string := "clock1"; - port_b_read_enable_clock: string := "clock1"; - port_b_byte_enable_clock: string := "clock1"; - port_b_data_out_clock: string := "none"; - port_b_data_width: integer := 1; - port_b_address_width: integer := 1; - port_b_byte_enable_mask_width: integer := 1; - port_a_read_during_write_mode: string := "new_data_no_nbe_read"; - port_b_read_during_write_mode: string := "new_data_no_nbe_read"; - power_up_uninitialized: string := "false"; - lpm_type : string := "stratixv_ram_block"; - lpm_hint : string := "true"; - connectivity_checking: string := "off"; - mem_init0 : string := ""; - mem_init1 : string := ""; - mem_init2 : string := ""; - mem_init3 : string := ""; - mem_init4 : string := ""; - mem_init5 : string := ""; - mem_init6 : string := ""; - mem_init7 : string := ""; - mem_init8 : string := ""; - mem_init9 : string := ""; - port_a_byte_size: integer := 0; - port_b_byte_size: integer := 0; - clk0_input_clock_enable: string := "none"; - clk0_core_clock_enable: string := "none"; - clk0_output_clock_enable: string := "none"; - clk1_input_clock_enable: string := "none"; - clk1_core_clock_enable: string := "none"; - clk1_output_clock_enable: string := "none"; - bist_ena : string := "false"; - port_a_address_clear: string := "none"; - port_a_data_in_clock: string := "clock0"; - port_a_address_clock: string := "clock0"; - port_a_write_enable_clock: string := "clock0"; - port_a_byte_enable_clock: string := "clock0"; - port_a_read_enable_clock: string := "clock0" - ); - port( - portadatain : in vl_logic_vector; - portaaddr : in vl_logic_vector; - portawe : in vl_logic; - portare : in vl_logic; - portbdatain : in vl_logic_vector; - portbaddr : in vl_logic_vector; - portbwe : in vl_logic; - portbre : in vl_logic; - clk0 : in vl_logic; - clk1 : in vl_logic; - ena0 : in vl_logic; - ena1 : in vl_logic; - ena2 : in vl_logic; - ena3 : in vl_logic; - clr0 : in vl_logic; - clr1 : in vl_logic; - nerror : in vl_logic; - portabyteenamasks: in vl_logic_vector; - portbbyteenamasks: in vl_logic_vector; - portaaddrstall : in vl_logic; - portbaddrstall : in vl_logic; - devclrn : in vl_logic; - devpor : in vl_logic; - eccstatus : out vl_logic_vector; - portadataout : out vl_logic_vector; - portbdataout : out vl_logic_vector; - dftout : out vl_logic_vector(8 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1; - attribute mti_svvh_generic_type of ram_block_type : constant is 1; - attribute mti_svvh_generic_type of logical_ram_name : constant is 1; - attribute mti_svvh_generic_type of init_file : constant is 1; - attribute mti_svvh_generic_type of init_file_layout : constant is 1; - attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1; - attribute mti_svvh_generic_type of enable_ecc : constant is 1; - attribute mti_svvh_generic_type of width_eccstatus : constant is 1; - attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1; - attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1; - attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1; - attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1; - attribute mti_svvh_generic_type of port_a_first_address : constant is 1; - attribute mti_svvh_generic_type of port_a_last_address : constant is 1; - attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1; - attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1; - attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_data_width : constant is 1; - attribute mti_svvh_generic_type of port_a_address_width : constant is 1; - attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1; - attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1; - attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1; - attribute mti_svvh_generic_type of port_b_first_address : constant is 1; - attribute mti_svvh_generic_type of port_b_last_address : constant is 1; - attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1; - attribute mti_svvh_generic_type of port_b_address_clear : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1; - attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_address_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_data_width : constant is 1; - attribute mti_svvh_generic_type of port_b_address_width : constant is 1; - attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1; - attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1; - attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1; - attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of connectivity_checking : constant is 1; - attribute mti_svvh_generic_type of mem_init0 : constant is 1; - attribute mti_svvh_generic_type of mem_init1 : constant is 1; - attribute mti_svvh_generic_type of mem_init2 : constant is 1; - attribute mti_svvh_generic_type of mem_init3 : constant is 1; - attribute mti_svvh_generic_type of mem_init4 : constant is 1; - attribute mti_svvh_generic_type of mem_init5 : constant is 1; - attribute mti_svvh_generic_type of mem_init6 : constant is 1; - attribute mti_svvh_generic_type of mem_init7 : constant is 1; - attribute mti_svvh_generic_type of mem_init8 : constant is 1; - attribute mti_svvh_generic_type of mem_init9 : constant is 1; - attribute mti_svvh_generic_type of port_a_byte_size : constant is 1; - attribute mti_svvh_generic_type of port_b_byte_size : constant is 1; - attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1; - attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1; - attribute mti_svvh_generic_type of bist_ena : constant is 1; - attribute mti_svvh_generic_type of port_a_address_clear : constant is 1; - attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_address_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1; - attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1; -end generic_m20k; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mlab_cell/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mlab_cell/_primary.dat deleted file mode 100644 index 0124138..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mlab_cell/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mlab_cell/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mlab_cell/_primary.dbs deleted file mode 100644 index d70e1fa..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mlab_cell/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mlab_cell/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mlab_cell/_primary.vhd deleted file mode 100644 index 8d22e3f..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mlab_cell/_primary.vhd +++ /dev/null @@ -1,56 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity generic_mlab_cell is - generic( - logical_ram_name: string := "lutram"; - logical_ram_depth: integer := 0; - logical_ram_width: integer := 0; - first_address : integer := 0; - last_address : integer := 0; - first_bit_number: integer := 0; - mixed_port_feed_through_mode: string := "new"; - init_file : string := "NONE"; - data_width : integer := 20; - address_width : integer := 6; - byte_enable_mask_width: integer := 1; - byte_size : integer := 1; - port_b_data_out_clock: string := "none"; - port_b_data_out_clear: string := "none"; - lpm_type : string := "common_28nm_mlab_cell"; - lpm_hint : string := "true"; - mem_init0 : string := "" - ); - port( - portadatain : in vl_logic_vector; - portaaddr : in vl_logic_vector; - portabyteenamasks: in vl_logic_vector; - portbaddr : in vl_logic_vector; - clk0 : in vl_logic; - clk1 : in vl_logic; - ena0 : in vl_logic; - ena1 : in vl_logic; - ena2 : in vl_logic; - clr : in vl_logic; - devclrn : in vl_logic; - devpor : in vl_logic; - portbdataout : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of logical_ram_name : constant is 1; - attribute mti_svvh_generic_type of logical_ram_depth : constant is 1; - attribute mti_svvh_generic_type of logical_ram_width : constant is 1; - attribute mti_svvh_generic_type of first_address : constant is 1; - attribute mti_svvh_generic_type of last_address : constant is 1; - attribute mti_svvh_generic_type of first_bit_number : constant is 1; - attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1; - attribute mti_svvh_generic_type of init_file : constant is 1; - attribute mti_svvh_generic_type of data_width : constant is 1; - attribute mti_svvh_generic_type of address_width : constant is 1; - attribute mti_svvh_generic_type of byte_enable_mask_width : constant is 1; - attribute mti_svvh_generic_type of byte_size : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1; - attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of mem_init0 : constant is 1; -end generic_mlab_cell; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mux/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mux/_primary.dat deleted file mode 100644 index dc33cc6..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mux/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mux/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mux/_primary.dbs deleted file mode 100644 index 733010b..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mux/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mux/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mux/_primary.vhd deleted file mode 100644 index dc959ec..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_mux/_primary.vhd +++ /dev/null @@ -1,9 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity generic_mux is - port( - din : in vl_logic_vector(63 downto 0); - sel : in vl_logic_vector(5 downto 0); - dout : out vl_logic - ); -end generic_mux; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_pll/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_pll/_primary.dat deleted file mode 100644 index 9a0c019..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_pll/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_pll/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_pll/_primary.dbs deleted file mode 100644 index f9a7fbf..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_pll/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_pll/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_pll/_primary.vhd deleted file mode 100644 index f168551..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_lnsim_ver/generic_pll/_primary.vhd +++ /dev/null @@ -1,35 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity generic_pll is - generic( - lpm_type : string := "generic_pll"; - duty_cycle : integer := 50; - output_clock_frequency: string := "0 ps"; - phase_shift : string := "0 ps"; - reference_clock_frequency: string := "0 ps"; - sim_additional_refclk_cycles_to_lock: integer := 0 - ); - port( - refclk : in vl_logic; - rst : in vl_logic; - fbclk : in vl_logic; - writerefclkdata : in vl_logic_vector(63 downto 0); - writeoutclkdata : in vl_logic_vector(63 downto 0); - writephaseshiftdata: in vl_logic_vector(63 downto 0); - writedutycycledata: in vl_logic_vector(63 downto 0); - outclk : out vl_logic; - locked : out vl_logic; - fboutclk : out vl_logic; - readrefclkdata : out vl_logic_vector(63 downto 0); - readoutclkdata : out vl_logic_vector(63 downto 0); - readphaseshiftdata: out vl_logic_vector(63 downto 0); - readdutycycledata: out vl_logic_vector(63 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of duty_cycle : constant is 1; - attribute mti_svvh_generic_type of output_clock_frequency : constant is 1; - attribute mti_svvh_generic_type of phase_shift : constant is 1; - attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1; - attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1; -end generic_pll; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat deleted file mode 100644 index ed2e92f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dbs deleted file mode 100644 index 836f475..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd deleted file mode 100644 index 9e3a331..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd +++ /dev/null @@ -1,4 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ALTERA_DEVICE_FAMILIES is -end ALTERA_DEVICE_FAMILIES; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat deleted file mode 100644 index d9c84fa..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dbs deleted file mode 100644 index d4f33ff..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd deleted file mode 100644 index 772b615..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd +++ /dev/null @@ -1,4 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ALTERA_MF_HINT_EVALUATION is -end ALTERA_MF_HINT_EVALUATION; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat deleted file mode 100644 index 91ecd7e..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dbs deleted file mode 100644 index 63364a8..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd deleted file mode 100644 index 7996838..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd +++ /dev/null @@ -1,4 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ALTERA_MF_MEMORY_INITIALIZATION is -end ALTERA_MF_MEMORY_INITIALIZATION; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.dat deleted file mode 100644 index 6489ef9..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.dbs deleted file mode 100644 index 4845f71..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.vhd deleted file mode 100644 index b7cfe8f..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiii_pll/_primary.vhd +++ /dev/null @@ -1,331 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity MF_cycloneiii_pll is - generic( - operation_mode : string := "normal"; - pll_type : string := "auto"; - compensate_clock: string := "clock0"; - inclk0_input_frequency: integer := 0; - inclk1_input_frequency: integer := 0; - self_reset_on_loss_lock: string := "off"; - switch_over_type: string := "auto"; - switch_over_counter: integer := 1; - enable_switch_over_counter: string := "off"; - bandwidth : integer := 0; - bandwidth_type : string := "auto"; - use_dc_coupling : string := "false"; - lock_high : integer := 0; - lock_low : integer := 0; - lock_window_ui : string := "0.05"; - test_bypass_lock_detect: string := "off"; - clk0_output_frequency: integer := 0; - clk0_multiply_by: integer := 0; - clk0_divide_by : integer := 0; - clk0_phase_shift: string := "0"; - clk0_duty_cycle : integer := 50; - clk1_output_frequency: integer := 0; - clk1_multiply_by: integer := 0; - clk1_divide_by : integer := 0; - clk1_phase_shift: string := "0"; - clk1_duty_cycle : integer := 50; - clk2_output_frequency: integer := 0; - clk2_multiply_by: integer := 0; - clk2_divide_by : integer := 0; - clk2_phase_shift: string := "0"; - clk2_duty_cycle : integer := 50; - clk3_output_frequency: integer := 0; - clk3_multiply_by: integer := 0; - clk3_divide_by : integer := 0; - clk3_phase_shift: string := "0"; - clk3_duty_cycle : integer := 50; - clk4_output_frequency: integer := 0; - clk4_multiply_by: integer := 0; - clk4_divide_by : integer := 0; - clk4_phase_shift: string := "0"; - clk4_duty_cycle : integer := 50; - pfd_min : integer := 0; - pfd_max : integer := 0; - vco_min : integer := 0; - vco_max : integer := 0; - vco_center : integer := 0; - m_initial : integer := 1; - m : integer := 0; - n : integer := 1; - c0_high : integer := 1; - c0_low : integer := 1; - c0_initial : integer := 1; - c0_mode : string := "bypass"; - c0_ph : integer := 0; - c1_high : integer := 1; - c1_low : integer := 1; - c1_initial : integer := 1; - c1_mode : string := "bypass"; - c1_ph : integer := 0; - c2_high : integer := 1; - c2_low : integer := 1; - c2_initial : integer := 1; - c2_mode : string := "bypass"; - c2_ph : integer := 0; - c3_high : integer := 1; - c3_low : integer := 1; - c3_initial : integer := 1; - c3_mode : string := "bypass"; - c3_ph : integer := 0; - c4_high : integer := 1; - c4_low : integer := 1; - c4_initial : integer := 1; - c4_mode : string := "bypass"; - c4_ph : integer := 0; - m_ph : integer := 0; - clk0_counter : string := "unused"; - clk1_counter : string := "unused"; - clk2_counter : string := "unused"; - clk3_counter : string := "unused"; - clk4_counter : string := "unused"; - c1_use_casc_in : string := "off"; - c2_use_casc_in : string := "off"; - c3_use_casc_in : string := "off"; - c4_use_casc_in : string := "off"; - m_test_source : integer := -1; - c0_test_source : integer := -1; - c1_test_source : integer := -1; - c2_test_source : integer := -1; - c3_test_source : integer := -1; - c4_test_source : integer := -1; - vco_multiply_by : integer := 0; - vco_divide_by : integer := 0; - vco_post_scale : integer := 1; - vco_frequency_control: string := "auto"; - vco_phase_shift_step: integer := 0; - charge_pump_current: integer := 10; - loop_filter_r : string := "1.0"; - loop_filter_c : integer := 0; - pll_compensation_delay: integer := 0; - simulation_type : string := "functional"; - down_spread : string := "0.0"; - lock_c : integer := 4; - sim_gate_lock_device_behavior: string := "off"; - clk0_phase_shift_num: integer := 0; - clk1_phase_shift_num: integer := 0; - clk2_phase_shift_num: integer := 0; - clk3_phase_shift_num: integer := 0; - clk4_phase_shift_num: integer := 0; - family_name : string := "StratixIII"; - clk0_use_even_counter_mode: string := "off"; - clk1_use_even_counter_mode: string := "off"; - clk2_use_even_counter_mode: string := "off"; - clk3_use_even_counter_mode: string := "off"; - clk4_use_even_counter_mode: string := "off"; - clk0_use_even_counter_value: string := "off"; - clk1_use_even_counter_value: string := "off"; - clk2_use_even_counter_value: string := "off"; - clk3_use_even_counter_value: string := "off"; - clk4_use_even_counter_value: string := "off"; - init_block_reset_a_count: integer := 1; - init_block_reset_b_count: integer := 1; - phase_counter_select_width: integer := 3; - lock_window : integer := 5; - inclk0_freq : vl_notype; - inclk1_freq : vl_notype; - charge_pump_current_bits: integer := 0; - lock_window_ui_bits: integer := 0; - loop_filter_c_bits: integer := 0; - loop_filter_r_bits: integer := 0; - test_counter_c0_delay_chain_bits: integer := 0; - test_counter_c1_delay_chain_bits: integer := 0; - test_counter_c2_delay_chain_bits: integer := 0; - test_counter_c3_delay_chain_bits: integer := 0; - test_counter_c4_delay_chain_bits: integer := 0; - test_counter_c5_delay_chain_bits: integer := 0; - test_counter_m_delay_chain_bits: integer := 0; - test_counter_n_delay_chain_bits: integer := 0; - test_feedback_comp_delay_chain_bits: integer := 0; - test_input_comp_delay_chain_bits: integer := 0; - test_volt_reg_output_mode_bits: integer := 0; - test_volt_reg_output_voltage_bits: integer := 0; - test_volt_reg_test_mode: string := "false"; - vco_range_detector_high_bits: integer := -1; - vco_range_detector_low_bits: integer := -1; - scan_chain_mif_file: string := ""; - auto_settings : string := "true"; - SCAN_CHAIN : integer := 144; - GPP_SCAN_CHAIN : integer := 234; - FAST_SCAN_CHAIN : integer := 180; - num_phase_taps : integer := 8 - ); - port( - inclk : in vl_logic_vector(1 downto 0); - fbin : in vl_logic; - fbout : out vl_logic; - clkswitch : in vl_logic; - areset : in vl_logic; - pfdena : in vl_logic; - scanclk : in vl_logic; - scandata : in vl_logic; - scanclkena : in vl_logic; - configupdate : in vl_logic; - clk : out vl_logic_vector(4 downto 0); - phasecounterselect: in vl_logic_vector; - phaseupdown : in vl_logic; - phasestep : in vl_logic; - clkbad : out vl_logic_vector(1 downto 0); - activeclock : out vl_logic; - locked : out vl_logic; - scandataout : out vl_logic; - scandone : out vl_logic; - phasedone : out vl_logic; - vcooverrange : out vl_logic; - vcounderrange : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of pll_type : constant is 1; - attribute mti_svvh_generic_type of compensate_clock : constant is 1; - attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1; - attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1; - attribute mti_svvh_generic_type of self_reset_on_loss_lock : constant is 1; - attribute mti_svvh_generic_type of switch_over_type : constant is 1; - attribute mti_svvh_generic_type of switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of bandwidth : constant is 1; - attribute mti_svvh_generic_type of bandwidth_type : constant is 1; - attribute mti_svvh_generic_type of use_dc_coupling : constant is 1; - attribute mti_svvh_generic_type of lock_high : constant is 1; - attribute mti_svvh_generic_type of lock_low : constant is 1; - attribute mti_svvh_generic_type of lock_window_ui : constant is 1; - attribute mti_svvh_generic_type of test_bypass_lock_detect : constant is 1; - attribute mti_svvh_generic_type of clk0_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk0_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk1_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk1_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk2_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk2_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk3_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk3_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk4_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk4_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of pfd_min : constant is 1; - attribute mti_svvh_generic_type of pfd_max : constant is 1; - attribute mti_svvh_generic_type of vco_min : constant is 1; - attribute mti_svvh_generic_type of vco_max : constant is 1; - attribute mti_svvh_generic_type of vco_center : constant is 1; - attribute mti_svvh_generic_type of m_initial : constant is 1; - attribute mti_svvh_generic_type of m : constant is 1; - attribute mti_svvh_generic_type of n : constant is 1; - attribute mti_svvh_generic_type of c0_high : constant is 1; - attribute mti_svvh_generic_type of c0_low : constant is 1; - attribute mti_svvh_generic_type of c0_initial : constant is 1; - attribute mti_svvh_generic_type of c0_mode : constant is 1; - attribute mti_svvh_generic_type of c0_ph : constant is 1; - attribute mti_svvh_generic_type of c1_high : constant is 1; - attribute mti_svvh_generic_type of c1_low : constant is 1; - attribute mti_svvh_generic_type of c1_initial : constant is 1; - attribute mti_svvh_generic_type of c1_mode : constant is 1; - attribute mti_svvh_generic_type of c1_ph : constant is 1; - attribute mti_svvh_generic_type of c2_high : constant is 1; - attribute mti_svvh_generic_type of c2_low : constant is 1; - attribute mti_svvh_generic_type of c2_initial : constant is 1; - attribute mti_svvh_generic_type of c2_mode : constant is 1; - attribute mti_svvh_generic_type of c2_ph : constant is 1; - attribute mti_svvh_generic_type of c3_high : constant is 1; - attribute mti_svvh_generic_type of c3_low : constant is 1; - attribute mti_svvh_generic_type of c3_initial : constant is 1; - attribute mti_svvh_generic_type of c3_mode : constant is 1; - attribute mti_svvh_generic_type of c3_ph : constant is 1; - attribute mti_svvh_generic_type of c4_high : constant is 1; - attribute mti_svvh_generic_type of c4_low : constant is 1; - attribute mti_svvh_generic_type of c4_initial : constant is 1; - attribute mti_svvh_generic_type of c4_mode : constant is 1; - attribute mti_svvh_generic_type of c4_ph : constant is 1; - attribute mti_svvh_generic_type of m_ph : constant is 1; - attribute mti_svvh_generic_type of clk0_counter : constant is 1; - attribute mti_svvh_generic_type of clk1_counter : constant is 1; - attribute mti_svvh_generic_type of clk2_counter : constant is 1; - attribute mti_svvh_generic_type of clk3_counter : constant is 1; - attribute mti_svvh_generic_type of clk4_counter : constant is 1; - attribute mti_svvh_generic_type of c1_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c2_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c3_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c4_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of m_test_source : constant is 1; - attribute mti_svvh_generic_type of c0_test_source : constant is 1; - attribute mti_svvh_generic_type of c1_test_source : constant is 1; - attribute mti_svvh_generic_type of c2_test_source : constant is 1; - attribute mti_svvh_generic_type of c3_test_source : constant is 1; - attribute mti_svvh_generic_type of c4_test_source : constant is 1; - attribute mti_svvh_generic_type of vco_multiply_by : constant is 1; - attribute mti_svvh_generic_type of vco_divide_by : constant is 1; - attribute mti_svvh_generic_type of vco_post_scale : constant is 1; - attribute mti_svvh_generic_type of vco_frequency_control : constant is 1; - attribute mti_svvh_generic_type of vco_phase_shift_step : constant is 1; - attribute mti_svvh_generic_type of charge_pump_current : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c : constant is 1; - attribute mti_svvh_generic_type of pll_compensation_delay : constant is 1; - attribute mti_svvh_generic_type of simulation_type : constant is 1; - attribute mti_svvh_generic_type of down_spread : constant is 1; - attribute mti_svvh_generic_type of lock_c : constant is 1; - attribute mti_svvh_generic_type of sim_gate_lock_device_behavior : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk3_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk4_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of family_name : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of init_block_reset_a_count : constant is 1; - attribute mti_svvh_generic_type of init_block_reset_b_count : constant is 1; - attribute mti_svvh_generic_type of phase_counter_select_width : constant is 1; - attribute mti_svvh_generic_type of lock_window : constant is 1; - attribute mti_svvh_generic_type of inclk0_freq : constant is 3; - attribute mti_svvh_generic_type of inclk1_freq : constant is 3; - attribute mti_svvh_generic_type of charge_pump_current_bits : constant is 1; - attribute mti_svvh_generic_type of lock_window_ui_bits : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c_bits : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c0_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c1_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c2_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c3_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c4_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c5_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_m_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_n_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_feedback_comp_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_input_comp_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_volt_reg_output_mode_bits : constant is 1; - attribute mti_svvh_generic_type of test_volt_reg_output_voltage_bits : constant is 1; - attribute mti_svvh_generic_type of test_volt_reg_test_mode : constant is 1; - attribute mti_svvh_generic_type of vco_range_detector_high_bits : constant is 1; - attribute mti_svvh_generic_type of vco_range_detector_low_bits : constant is 1; - attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1; - attribute mti_svvh_generic_type of auto_settings : constant is 1; - attribute mti_svvh_generic_type of SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of GPP_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of FAST_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of num_phase_taps : constant is 1; -end MF_cycloneiii_pll; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.dat deleted file mode 100644 index 39cd316..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.dbs deleted file mode 100644 index a5dee09..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.vhd deleted file mode 100644 index 7c54f7c..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_m_cntr/_primary.vhd +++ /dev/null @@ -1,12 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity MF_cycloneiiigl_m_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - initial_value : in vl_logic_vector(31 downto 0); - modulus : in vl_logic_vector(31 downto 0); - time_delay : in vl_logic_vector(31 downto 0) - ); -end MF_cycloneiiigl_m_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.dat deleted file mode 100644 index fa28fb9..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.dbs deleted file mode 100644 index ffa910a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.vhd deleted file mode 100644 index 75ea422..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_n_cntr/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity MF_cycloneiiigl_n_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - modulus : in vl_logic_vector(31 downto 0) - ); -end MF_cycloneiiigl_n_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.dat deleted file mode 100644 index 322cb4f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.dbs deleted file mode 100644 index 8e21d50..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.vhd deleted file mode 100644 index 8f32edc..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_pll/_primary.vhd +++ /dev/null @@ -1,337 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity MF_cycloneiiigl_pll is - generic( - operation_mode : string := "normal"; - pll_type : string := "auto"; - compensate_clock: string := "clock0"; - inclk0_input_frequency: integer := 0; - inclk1_input_frequency: integer := 0; - self_reset_on_loss_lock: string := "off"; - switch_over_type: string := "auto"; - switch_over_counter: integer := 1; - enable_switch_over_counter: string := "off"; - bandwidth : integer := 0; - bandwidth_type : string := "auto"; - use_dc_coupling : string := "false"; - lock_high : integer := 0; - lock_low : integer := 0; - lock_window_ui : string := "0.05"; - test_bypass_lock_detect: string := "off"; - clk0_output_frequency: integer := 0; - clk0_multiply_by: integer := 0; - clk0_divide_by : integer := 0; - clk0_phase_shift: string := "0"; - clk0_duty_cycle : integer := 50; - clk1_output_frequency: integer := 0; - clk1_multiply_by: integer := 0; - clk1_divide_by : integer := 0; - clk1_phase_shift: string := "0"; - clk1_duty_cycle : integer := 50; - clk2_output_frequency: integer := 0; - clk2_multiply_by: integer := 0; - clk2_divide_by : integer := 0; - clk2_phase_shift: string := "0"; - clk2_duty_cycle : integer := 50; - clk3_output_frequency: integer := 0; - clk3_multiply_by: integer := 0; - clk3_divide_by : integer := 0; - clk3_phase_shift: string := "0"; - clk3_duty_cycle : integer := 50; - clk4_output_frequency: integer := 0; - clk4_multiply_by: integer := 0; - clk4_divide_by : integer := 0; - clk4_phase_shift: string := "0"; - clk4_duty_cycle : integer := 50; - pfd_min : integer := 0; - pfd_max : integer := 0; - vco_min : integer := 0; - vco_max : integer := 0; - vco_center : integer := 0; - m_initial : integer := 1; - m : integer := 0; - n : integer := 1; - c0_high : integer := 1; - c0_low : integer := 1; - c0_initial : integer := 1; - c0_mode : string := "bypass"; - c0_ph : integer := 0; - c1_high : integer := 1; - c1_low : integer := 1; - c1_initial : integer := 1; - c1_mode : string := "bypass"; - c1_ph : integer := 0; - c2_high : integer := 1; - c2_low : integer := 1; - c2_initial : integer := 1; - c2_mode : string := "bypass"; - c2_ph : integer := 0; - c3_high : integer := 1; - c3_low : integer := 1; - c3_initial : integer := 1; - c3_mode : string := "bypass"; - c3_ph : integer := 0; - c4_high : integer := 1; - c4_low : integer := 1; - c4_initial : integer := 1; - c4_mode : string := "bypass"; - c4_ph : integer := 0; - m_ph : integer := 0; - clk0_counter : string := "unused"; - clk1_counter : string := "unused"; - clk2_counter : string := "unused"; - clk3_counter : string := "unused"; - clk4_counter : string := "unused"; - c1_use_casc_in : string := "off"; - c2_use_casc_in : string := "off"; - c3_use_casc_in : string := "off"; - c4_use_casc_in : string := "off"; - m_test_source : integer := -1; - c0_test_source : integer := -1; - c1_test_source : integer := -1; - c2_test_source : integer := -1; - c3_test_source : integer := -1; - c4_test_source : integer := -1; - vco_multiply_by : integer := 0; - vco_divide_by : integer := 0; - vco_post_scale : integer := 1; - vco_frequency_control: string := "auto"; - vco_phase_shift_step: integer := 0; - dpa_multiply_by : integer := 0; - dpa_divide_by : integer := 0; - dpa_divider : integer := 1; - charge_pump_current: integer := 10; - loop_filter_r : string := "1.0"; - loop_filter_c : integer := 0; - pll_compensation_delay: integer := 0; - simulation_type : string := "functional"; - down_spread : string := "0.0"; - lock_c : integer := 4; - sim_gate_lock_device_behavior: string := "off"; - clk0_phase_shift_num: integer := 0; - clk1_phase_shift_num: integer := 0; - clk2_phase_shift_num: integer := 0; - clk3_phase_shift_num: integer := 0; - clk4_phase_shift_num: integer := 0; - family_name : string := "cycloneiiigl"; - clk0_use_even_counter_mode: string := "off"; - clk1_use_even_counter_mode: string := "off"; - clk2_use_even_counter_mode: string := "off"; - clk3_use_even_counter_mode: string := "off"; - clk4_use_even_counter_mode: string := "off"; - clk0_use_even_counter_value: string := "off"; - clk1_use_even_counter_value: string := "off"; - clk2_use_even_counter_value: string := "off"; - clk3_use_even_counter_value: string := "off"; - clk4_use_even_counter_value: string := "off"; - init_block_reset_a_count: integer := 1; - init_block_reset_b_count: integer := 1; - phase_counter_select_width: integer := 3; - lock_window : integer := 5000; - inclk0_freq : vl_notype; - inclk1_freq : vl_notype; - charge_pump_current_bits: integer := 0; - lock_window_ui_bits: integer := 0; - loop_filter_c_bits: integer := 0; - loop_filter_r_bits: integer := 0; - test_counter_c0_delay_chain_bits: integer := 0; - test_counter_c1_delay_chain_bits: integer := 0; - test_counter_c2_delay_chain_bits: integer := 0; - test_counter_c3_delay_chain_bits: integer := 0; - test_counter_c4_delay_chain_bits: integer := 0; - test_counter_m_delay_chain_bits: integer := 0; - test_counter_n_delay_chain_bits: integer := 0; - test_feedback_comp_delay_chain_bits: integer := 0; - test_input_comp_delay_chain_bits: integer := 0; - test_volt_reg_output_mode_bits: integer := 0; - test_volt_reg_output_voltage_bits: integer := 0; - test_volt_reg_test_mode: string := "false"; - vco_range_detector_high_bits: integer := -1; - vco_range_detector_low_bits: integer := -1; - scan_chain_mif_file: string := ""; - auto_settings : string := "true"; - SCAN_CHAIN : integer := 144; - GPP_SCAN_CHAIN : integer := 234; - FAST_SCAN_CHAIN : integer := 180; - num_phase_taps : integer := 8 - ); - port( - inclk : in vl_logic_vector(1 downto 0); - fbin : in vl_logic; - fbout : out vl_logic; - clkswitch : in vl_logic; - areset : in vl_logic; - pfdena : in vl_logic; - scanclk : in vl_logic; - scandata : in vl_logic; - scanclkena : in vl_logic; - configupdate : in vl_logic; - clk : out vl_logic_vector(4 downto 0); - phasecounterselect: in vl_logic_vector; - phaseupdown : in vl_logic; - phasestep : in vl_logic; - clkbad : out vl_logic_vector(1 downto 0); - activeclock : out vl_logic; - locked : out vl_logic; - scandataout : out vl_logic; - scandone : out vl_logic; - phasedone : out vl_logic; - vcooverrange : out vl_logic; - vcounderrange : out vl_logic; - fref : out vl_logic; - icdrclk : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of pll_type : constant is 1; - attribute mti_svvh_generic_type of compensate_clock : constant is 1; - attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1; - attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1; - attribute mti_svvh_generic_type of self_reset_on_loss_lock : constant is 1; - attribute mti_svvh_generic_type of switch_over_type : constant is 1; - attribute mti_svvh_generic_type of switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of bandwidth : constant is 1; - attribute mti_svvh_generic_type of bandwidth_type : constant is 1; - attribute mti_svvh_generic_type of use_dc_coupling : constant is 1; - attribute mti_svvh_generic_type of lock_high : constant is 1; - attribute mti_svvh_generic_type of lock_low : constant is 1; - attribute mti_svvh_generic_type of lock_window_ui : constant is 1; - attribute mti_svvh_generic_type of test_bypass_lock_detect : constant is 1; - attribute mti_svvh_generic_type of clk0_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk0_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk1_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk1_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk2_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk2_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk3_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk3_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk4_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk4_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of pfd_min : constant is 1; - attribute mti_svvh_generic_type of pfd_max : constant is 1; - attribute mti_svvh_generic_type of vco_min : constant is 1; - attribute mti_svvh_generic_type of vco_max : constant is 1; - attribute mti_svvh_generic_type of vco_center : constant is 1; - attribute mti_svvh_generic_type of m_initial : constant is 1; - attribute mti_svvh_generic_type of m : constant is 1; - attribute mti_svvh_generic_type of n : constant is 1; - attribute mti_svvh_generic_type of c0_high : constant is 1; - attribute mti_svvh_generic_type of c0_low : constant is 1; - attribute mti_svvh_generic_type of c0_initial : constant is 1; - attribute mti_svvh_generic_type of c0_mode : constant is 1; - attribute mti_svvh_generic_type of c0_ph : constant is 1; - attribute mti_svvh_generic_type of c1_high : constant is 1; - attribute mti_svvh_generic_type of c1_low : constant is 1; - attribute mti_svvh_generic_type of c1_initial : constant is 1; - attribute mti_svvh_generic_type of c1_mode : constant is 1; - attribute mti_svvh_generic_type of c1_ph : constant is 1; - attribute mti_svvh_generic_type of c2_high : constant is 1; - attribute mti_svvh_generic_type of c2_low : constant is 1; - attribute mti_svvh_generic_type of c2_initial : constant is 1; - attribute mti_svvh_generic_type of c2_mode : constant is 1; - attribute mti_svvh_generic_type of c2_ph : constant is 1; - attribute mti_svvh_generic_type of c3_high : constant is 1; - attribute mti_svvh_generic_type of c3_low : constant is 1; - attribute mti_svvh_generic_type of c3_initial : constant is 1; - attribute mti_svvh_generic_type of c3_mode : constant is 1; - attribute mti_svvh_generic_type of c3_ph : constant is 1; - attribute mti_svvh_generic_type of c4_high : constant is 1; - attribute mti_svvh_generic_type of c4_low : constant is 1; - attribute mti_svvh_generic_type of c4_initial : constant is 1; - attribute mti_svvh_generic_type of c4_mode : constant is 1; - attribute mti_svvh_generic_type of c4_ph : constant is 1; - attribute mti_svvh_generic_type of m_ph : constant is 1; - attribute mti_svvh_generic_type of clk0_counter : constant is 1; - attribute mti_svvh_generic_type of clk1_counter : constant is 1; - attribute mti_svvh_generic_type of clk2_counter : constant is 1; - attribute mti_svvh_generic_type of clk3_counter : constant is 1; - attribute mti_svvh_generic_type of clk4_counter : constant is 1; - attribute mti_svvh_generic_type of c1_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c2_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c3_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c4_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of m_test_source : constant is 1; - attribute mti_svvh_generic_type of c0_test_source : constant is 1; - attribute mti_svvh_generic_type of c1_test_source : constant is 1; - attribute mti_svvh_generic_type of c2_test_source : constant is 1; - attribute mti_svvh_generic_type of c3_test_source : constant is 1; - attribute mti_svvh_generic_type of c4_test_source : constant is 1; - attribute mti_svvh_generic_type of vco_multiply_by : constant is 1; - attribute mti_svvh_generic_type of vco_divide_by : constant is 1; - attribute mti_svvh_generic_type of vco_post_scale : constant is 1; - attribute mti_svvh_generic_type of vco_frequency_control : constant is 1; - attribute mti_svvh_generic_type of vco_phase_shift_step : constant is 1; - attribute mti_svvh_generic_type of dpa_multiply_by : constant is 1; - attribute mti_svvh_generic_type of dpa_divide_by : constant is 1; - attribute mti_svvh_generic_type of dpa_divider : constant is 1; - attribute mti_svvh_generic_type of charge_pump_current : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c : constant is 1; - attribute mti_svvh_generic_type of pll_compensation_delay : constant is 1; - attribute mti_svvh_generic_type of simulation_type : constant is 1; - attribute mti_svvh_generic_type of down_spread : constant is 1; - attribute mti_svvh_generic_type of lock_c : constant is 1; - attribute mti_svvh_generic_type of sim_gate_lock_device_behavior : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk3_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk4_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of family_name : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of init_block_reset_a_count : constant is 1; - attribute mti_svvh_generic_type of init_block_reset_b_count : constant is 1; - attribute mti_svvh_generic_type of phase_counter_select_width : constant is 1; - attribute mti_svvh_generic_type of lock_window : constant is 1; - attribute mti_svvh_generic_type of inclk0_freq : constant is 3; - attribute mti_svvh_generic_type of inclk1_freq : constant is 3; - attribute mti_svvh_generic_type of charge_pump_current_bits : constant is 1; - attribute mti_svvh_generic_type of lock_window_ui_bits : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c_bits : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c0_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c1_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c2_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c3_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c4_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_m_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_n_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_feedback_comp_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_input_comp_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_volt_reg_output_mode_bits : constant is 1; - attribute mti_svvh_generic_type of test_volt_reg_output_voltage_bits : constant is 1; - attribute mti_svvh_generic_type of test_volt_reg_test_mode : constant is 1; - attribute mti_svvh_generic_type of vco_range_detector_high_bits : constant is 1; - attribute mti_svvh_generic_type of vco_range_detector_low_bits : constant is 1; - attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1; - attribute mti_svvh_generic_type of auto_settings : constant is 1; - attribute mti_svvh_generic_type of SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of GPP_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of FAST_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of num_phase_taps : constant is 1; -end MF_cycloneiiigl_pll; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.dat deleted file mode 100644 index 8009f80..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.dbs deleted file mode 100644 index 9492ee2..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.vhd deleted file mode 100644 index 0c36f4a..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_cycloneiiigl_scale_cntr/_primary.vhd +++ /dev/null @@ -1,14 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity MF_cycloneiiigl_scale_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - high : in vl_logic_vector(31 downto 0); - low : in vl_logic_vector(31 downto 0); - initial_value : in vl_logic_vector(31 downto 0); - mode : in vl_logic_vector(48 downto 1); - ph_tap : in vl_logic_vector(31 downto 0) - ); -end MF_cycloneiiigl_scale_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.dat deleted file mode 100644 index c7e68d3..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.dbs deleted file mode 100644 index 6fe3fec..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.vhd deleted file mode 100644 index 3115a45..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_pll_reg/_primary.vhd +++ /dev/null @@ -1,12 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity MF_pll_reg is - port( - q : out vl_logic; - clk : in vl_logic; - ena : in vl_logic; - d : in vl_logic; - clrn : in vl_logic; - prn : in vl_logic - ); -end MF_pll_reg; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratix_pll/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratix_pll/_primary.dat deleted file mode 100644 index f29bf49..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratix_pll/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratix_pll/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratix_pll/_primary.dbs deleted file mode 100644 index 71c41d7..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratix_pll/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratix_pll/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratix_pll/_primary.vhd deleted file mode 100644 index 1e855b1..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratix_pll/_primary.vhd +++ /dev/null @@ -1,422 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity MF_stratix_pll is - generic( - operation_mode : string := "normal"; - qualify_conf_done: string := "off"; - compensate_clock: string := "clk0"; - pll_type : string := "auto"; - scan_chain : string := "long"; - clk0_multiply_by: integer := 1; - clk0_divide_by : integer := 1; - clk0_phase_shift: integer := 0; - clk0_time_delay : integer := 0; - clk0_duty_cycle : integer := 50; - clk1_multiply_by: integer := 1; - clk1_divide_by : integer := 1; - clk1_phase_shift: integer := 0; - clk1_time_delay : integer := 0; - clk1_duty_cycle : integer := 50; - clk2_multiply_by: integer := 1; - clk2_divide_by : integer := 1; - clk2_phase_shift: integer := 0; - clk2_time_delay : integer := 0; - clk2_duty_cycle : integer := 50; - clk3_multiply_by: integer := 1; - clk3_divide_by : integer := 1; - clk3_phase_shift: integer := 0; - clk3_time_delay : integer := 0; - clk3_duty_cycle : integer := 50; - clk4_multiply_by: integer := 1; - clk4_divide_by : integer := 1; - clk4_phase_shift: integer := 0; - clk4_time_delay : integer := 0; - clk4_duty_cycle : integer := 50; - clk5_multiply_by: integer := 1; - clk5_divide_by : integer := 1; - clk5_phase_shift: integer := 0; - clk5_time_delay : integer := 0; - clk5_duty_cycle : integer := 50; - extclk0_multiply_by: integer := 1; - extclk0_divide_by: integer := 1; - extclk0_phase_shift: integer := 0; - extclk0_time_delay: integer := 0; - extclk0_duty_cycle: integer := 50; - extclk1_multiply_by: integer := 1; - extclk1_divide_by: integer := 1; - extclk1_phase_shift: integer := 0; - extclk1_time_delay: integer := 0; - extclk1_duty_cycle: integer := 50; - extclk2_multiply_by: integer := 1; - extclk2_divide_by: integer := 1; - extclk2_phase_shift: integer := 0; - extclk2_time_delay: integer := 0; - extclk2_duty_cycle: integer := 50; - extclk3_multiply_by: integer := 1; - extclk3_divide_by: integer := 1; - extclk3_phase_shift: integer := 0; - extclk3_time_delay: integer := 0; - extclk3_duty_cycle: integer := 50; - primary_clock : string := "inclk0"; - inclk0_input_frequency: integer := 10000; - inclk1_input_frequency: integer := 10000; - gate_lock_signal: string := "no"; - gate_lock_counter: integer := 1; - valid_lock_multiplier: integer := 5; - invalid_lock_multiplier: integer := 5; - switch_over_on_lossclk: string := "off"; - switch_over_on_gated_lock: string := "off"; - switch_over_counter: integer := 1; - enable_switch_over_counter: string := "off"; - feedback_source : string := "extclk0"; - bandwidth : integer := 0; - bandwidth_type : string := "auto"; - spread_frequency: integer := 0; - common_rx_tx : string := "off"; - rx_outclock_resource: string := "auto"; - use_vco_bypass : string := "false"; - use_dc_coupling : string := "false"; - pfd_min : integer := 0; - pfd_max : integer := 0; - vco_min : integer := 0; - vco_max : integer := 0; - vco_center : integer := 0; - m_initial : integer := 1; - m : integer := 0; - n : integer := 1; - m2 : integer := 1; - n2 : integer := 1; - ss : integer := 0; - l0_high : integer := 1; - l0_low : integer := 1; - l0_initial : integer := 1; - l0_mode : string := "bypass"; - l0_ph : integer := 0; - l0_time_delay : integer := 0; - l1_high : integer := 1; - l1_low : integer := 1; - l1_initial : integer := 1; - l1_mode : string := "bypass"; - l1_ph : integer := 0; - l1_time_delay : integer := 0; - g0_high : integer := 1; - g0_low : integer := 1; - g0_initial : integer := 1; - g0_mode : string := "bypass"; - g0_ph : integer := 0; - g0_time_delay : integer := 0; - g1_high : integer := 1; - g1_low : integer := 1; - g1_initial : integer := 1; - g1_mode : string := "bypass"; - g1_ph : integer := 0; - g1_time_delay : integer := 0; - g2_high : integer := 1; - g2_low : integer := 1; - g2_initial : integer := 1; - g2_mode : string := "bypass"; - g2_ph : integer := 0; - g2_time_delay : integer := 0; - g3_high : integer := 1; - g3_low : integer := 1; - g3_initial : integer := 1; - g3_mode : string := "bypass"; - g3_ph : integer := 0; - g3_time_delay : integer := 0; - e0_high : integer := 1; - e0_low : integer := 1; - e0_initial : integer := 1; - e0_mode : string := "bypass"; - e0_ph : integer := 0; - e0_time_delay : integer := 0; - e1_high : integer := 1; - e1_low : integer := 1; - e1_initial : integer := 1; - e1_mode : string := "bypass"; - e1_ph : integer := 0; - e1_time_delay : integer := 0; - e2_high : integer := 1; - e2_low : integer := 1; - e2_initial : integer := 1; - e2_mode : string := "bypass"; - e2_ph : integer := 0; - e2_time_delay : integer := 0; - e3_high : integer := 1; - e3_low : integer := 1; - e3_initial : integer := 1; - e3_mode : string := "bypass"; - e3_ph : integer := 0; - e3_time_delay : integer := 0; - m_ph : integer := 0; - m_time_delay : integer := 0; - n_time_delay : integer := 0; - extclk0_counter : string := "e0"; - extclk1_counter : string := "e1"; - extclk2_counter : string := "e2"; - extclk3_counter : string := "e3"; - clk0_counter : string := "g0"; - clk1_counter : string := "g1"; - clk2_counter : string := "g2"; - clk3_counter : string := "g3"; - clk4_counter : string := "l0"; - clk5_counter : string := "l1"; - enable0_counter : string := "l0"; - enable1_counter : string := "l0"; - charge_pump_current: integer := 0; - loop_filter_r : string := "1.0"; - loop_filter_c : integer := 1; - pll_compensation_delay: integer := 0; - simulation_type : string := "timing"; - down_spread : string := "0.0"; - clk0_phase_shift_num: integer := 0; - clk1_phase_shift_num: integer := 0; - clk2_phase_shift_num: integer := 0; - family_name : string := "Stratix"; - skip_vco : string := "off"; - clk0_use_even_counter_mode: string := "off"; - clk1_use_even_counter_mode: string := "off"; - clk2_use_even_counter_mode: string := "off"; - clk3_use_even_counter_mode: string := "off"; - clk4_use_even_counter_mode: string := "off"; - clk5_use_even_counter_mode: string := "off"; - extclk0_use_even_counter_mode: string := "off"; - extclk1_use_even_counter_mode: string := "off"; - extclk2_use_even_counter_mode: string := "off"; - extclk3_use_even_counter_mode: string := "off"; - clk0_use_even_counter_value: string := "off"; - clk1_use_even_counter_value: string := "off"; - clk2_use_even_counter_value: string := "off"; - clk3_use_even_counter_value: string := "off"; - clk4_use_even_counter_value: string := "off"; - clk5_use_even_counter_value: string := "off"; - extclk0_use_even_counter_value: string := "off"; - extclk1_use_even_counter_value: string := "off"; - extclk2_use_even_counter_value: string := "off"; - extclk3_use_even_counter_value: string := "off"; - scan_chain_mif_file: string := ""; - EGPP_SCAN_CHAIN : integer := 289; - GPP_SCAN_CHAIN : integer := 193; - TRST : integer := 5000; - TRSTCLK : integer := 5000 - ); - port( - inclk : in vl_logic_vector(1 downto 0); - fbin : in vl_logic; - ena : in vl_logic; - clkswitch : in vl_logic; - areset : in vl_logic; - pfdena : in vl_logic; - clkena : in vl_logic_vector(5 downto 0); - extclkena : in vl_logic_vector(3 downto 0); - scanclk : in vl_logic; - scanaclr : in vl_logic; - scandata : in vl_logic; - clk : out vl_logic_vector(5 downto 0); - extclk : out vl_logic_vector(3 downto 0); - clkbad : out vl_logic_vector(1 downto 0); - activeclock : out vl_logic; - locked : out vl_logic; - clkloss : out vl_logic; - scandataout : out vl_logic; - comparator : in vl_logic; - enable0 : out vl_logic; - enable1 : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of qualify_conf_done : constant is 1; - attribute mti_svvh_generic_type of compensate_clock : constant is 1; - attribute mti_svvh_generic_type of pll_type : constant is 1; - attribute mti_svvh_generic_type of scan_chain : constant is 1; - attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk0_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk0_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk1_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk1_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk2_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk2_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk3_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk3_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk4_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk4_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk5_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk5_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk5_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk5_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk5_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of extclk0_multiply_by : constant is 1; - attribute mti_svvh_generic_type of extclk0_divide_by : constant is 1; - attribute mti_svvh_generic_type of extclk0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of extclk0_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk0_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of extclk1_multiply_by : constant is 1; - attribute mti_svvh_generic_type of extclk1_divide_by : constant is 1; - attribute mti_svvh_generic_type of extclk1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of extclk1_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk1_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of extclk2_multiply_by : constant is 1; - attribute mti_svvh_generic_type of extclk2_divide_by : constant is 1; - attribute mti_svvh_generic_type of extclk2_phase_shift : constant is 1; - attribute mti_svvh_generic_type of extclk2_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk2_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of extclk3_multiply_by : constant is 1; - attribute mti_svvh_generic_type of extclk3_divide_by : constant is 1; - attribute mti_svvh_generic_type of extclk3_phase_shift : constant is 1; - attribute mti_svvh_generic_type of extclk3_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk3_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of primary_clock : constant is 1; - attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1; - attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1; - attribute mti_svvh_generic_type of gate_lock_signal : constant is 1; - attribute mti_svvh_generic_type of gate_lock_counter : constant is 1; - attribute mti_svvh_generic_type of valid_lock_multiplier : constant is 1; - attribute mti_svvh_generic_type of invalid_lock_multiplier : constant is 1; - attribute mti_svvh_generic_type of switch_over_on_lossclk : constant is 1; - attribute mti_svvh_generic_type of switch_over_on_gated_lock : constant is 1; - attribute mti_svvh_generic_type of switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of feedback_source : constant is 1; - attribute mti_svvh_generic_type of bandwidth : constant is 1; - attribute mti_svvh_generic_type of bandwidth_type : constant is 1; - attribute mti_svvh_generic_type of spread_frequency : constant is 1; - attribute mti_svvh_generic_type of common_rx_tx : constant is 1; - attribute mti_svvh_generic_type of rx_outclock_resource : constant is 1; - attribute mti_svvh_generic_type of use_vco_bypass : constant is 1; - attribute mti_svvh_generic_type of use_dc_coupling : constant is 1; - attribute mti_svvh_generic_type of pfd_min : constant is 1; - attribute mti_svvh_generic_type of pfd_max : constant is 1; - attribute mti_svvh_generic_type of vco_min : constant is 1; - attribute mti_svvh_generic_type of vco_max : constant is 1; - attribute mti_svvh_generic_type of vco_center : constant is 1; - attribute mti_svvh_generic_type of m_initial : constant is 1; - attribute mti_svvh_generic_type of m : constant is 1; - attribute mti_svvh_generic_type of n : constant is 1; - attribute mti_svvh_generic_type of m2 : constant is 1; - attribute mti_svvh_generic_type of n2 : constant is 1; - attribute mti_svvh_generic_type of ss : constant is 1; - attribute mti_svvh_generic_type of l0_high : constant is 1; - attribute mti_svvh_generic_type of l0_low : constant is 1; - attribute mti_svvh_generic_type of l0_initial : constant is 1; - attribute mti_svvh_generic_type of l0_mode : constant is 1; - attribute mti_svvh_generic_type of l0_ph : constant is 1; - attribute mti_svvh_generic_type of l0_time_delay : constant is 1; - attribute mti_svvh_generic_type of l1_high : constant is 1; - attribute mti_svvh_generic_type of l1_low : constant is 1; - attribute mti_svvh_generic_type of l1_initial : constant is 1; - attribute mti_svvh_generic_type of l1_mode : constant is 1; - attribute mti_svvh_generic_type of l1_ph : constant is 1; - attribute mti_svvh_generic_type of l1_time_delay : constant is 1; - attribute mti_svvh_generic_type of g0_high : constant is 1; - attribute mti_svvh_generic_type of g0_low : constant is 1; - attribute mti_svvh_generic_type of g0_initial : constant is 1; - attribute mti_svvh_generic_type of g0_mode : constant is 1; - attribute mti_svvh_generic_type of g0_ph : constant is 1; - attribute mti_svvh_generic_type of g0_time_delay : constant is 1; - attribute mti_svvh_generic_type of g1_high : constant is 1; - attribute mti_svvh_generic_type of g1_low : constant is 1; - attribute mti_svvh_generic_type of g1_initial : constant is 1; - attribute mti_svvh_generic_type of g1_mode : constant is 1; - attribute mti_svvh_generic_type of g1_ph : constant is 1; - attribute mti_svvh_generic_type of g1_time_delay : constant is 1; - attribute mti_svvh_generic_type of g2_high : constant is 1; - attribute mti_svvh_generic_type of g2_low : constant is 1; - attribute mti_svvh_generic_type of g2_initial : constant is 1; - attribute mti_svvh_generic_type of g2_mode : constant is 1; - attribute mti_svvh_generic_type of g2_ph : constant is 1; - attribute mti_svvh_generic_type of g2_time_delay : constant is 1; - attribute mti_svvh_generic_type of g3_high : constant is 1; - attribute mti_svvh_generic_type of g3_low : constant is 1; - attribute mti_svvh_generic_type of g3_initial : constant is 1; - attribute mti_svvh_generic_type of g3_mode : constant is 1; - attribute mti_svvh_generic_type of g3_ph : constant is 1; - attribute mti_svvh_generic_type of g3_time_delay : constant is 1; - attribute mti_svvh_generic_type of e0_high : constant is 1; - attribute mti_svvh_generic_type of e0_low : constant is 1; - attribute mti_svvh_generic_type of e0_initial : constant is 1; - attribute mti_svvh_generic_type of e0_mode : constant is 1; - attribute mti_svvh_generic_type of e0_ph : constant is 1; - attribute mti_svvh_generic_type of e0_time_delay : constant is 1; - attribute mti_svvh_generic_type of e1_high : constant is 1; - attribute mti_svvh_generic_type of e1_low : constant is 1; - attribute mti_svvh_generic_type of e1_initial : constant is 1; - attribute mti_svvh_generic_type of e1_mode : constant is 1; - attribute mti_svvh_generic_type of e1_ph : constant is 1; - attribute mti_svvh_generic_type of e1_time_delay : constant is 1; - attribute mti_svvh_generic_type of e2_high : constant is 1; - attribute mti_svvh_generic_type of e2_low : constant is 1; - attribute mti_svvh_generic_type of e2_initial : constant is 1; - attribute mti_svvh_generic_type of e2_mode : constant is 1; - attribute mti_svvh_generic_type of e2_ph : constant is 1; - attribute mti_svvh_generic_type of e2_time_delay : constant is 1; - attribute mti_svvh_generic_type of e3_high : constant is 1; - attribute mti_svvh_generic_type of e3_low : constant is 1; - attribute mti_svvh_generic_type of e3_initial : constant is 1; - attribute mti_svvh_generic_type of e3_mode : constant is 1; - attribute mti_svvh_generic_type of e3_ph : constant is 1; - attribute mti_svvh_generic_type of e3_time_delay : constant is 1; - attribute mti_svvh_generic_type of m_ph : constant is 1; - attribute mti_svvh_generic_type of m_time_delay : constant is 1; - attribute mti_svvh_generic_type of n_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk0_counter : constant is 1; - attribute mti_svvh_generic_type of extclk1_counter : constant is 1; - attribute mti_svvh_generic_type of extclk2_counter : constant is 1; - attribute mti_svvh_generic_type of extclk3_counter : constant is 1; - attribute mti_svvh_generic_type of clk0_counter : constant is 1; - attribute mti_svvh_generic_type of clk1_counter : constant is 1; - attribute mti_svvh_generic_type of clk2_counter : constant is 1; - attribute mti_svvh_generic_type of clk3_counter : constant is 1; - attribute mti_svvh_generic_type of clk4_counter : constant is 1; - attribute mti_svvh_generic_type of clk5_counter : constant is 1; - attribute mti_svvh_generic_type of enable0_counter : constant is 1; - attribute mti_svvh_generic_type of enable1_counter : constant is 1; - attribute mti_svvh_generic_type of charge_pump_current : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c : constant is 1; - attribute mti_svvh_generic_type of pll_compensation_delay : constant is 1; - attribute mti_svvh_generic_type of simulation_type : constant is 1; - attribute mti_svvh_generic_type of down_spread : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of family_name : constant is 1; - attribute mti_svvh_generic_type of skip_vco : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk5_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of extclk0_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of extclk1_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of extclk2_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of extclk3_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk5_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of extclk0_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of extclk1_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of extclk2_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of extclk3_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1; - attribute mti_svvh_generic_type of EGPP_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of GPP_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of TRST : constant is 1; - attribute mti_svvh_generic_type of TRSTCLK : constant is 1; -end MF_stratix_pll; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixii_pll/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixii_pll/_primary.dat deleted file mode 100644 index ae398a3..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixii_pll/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixii_pll/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixii_pll/_primary.dbs deleted file mode 100644 index 058e80d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixii_pll/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixii_pll/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixii_pll/_primary.vhd deleted file mode 100644 index 5628629..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixii_pll/_primary.vhd +++ /dev/null @@ -1,330 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity MF_stratixii_pll is - generic( - operation_mode : string := "normal"; - pll_type : string := "auto"; - compensate_clock: string := "clk0"; - feedback_source : string := "clk0"; - qualify_conf_done: string := "off"; - test_input_comp_delay_chain_bits: integer := 0; - test_feedback_comp_delay_chain_bits: integer := 0; - inclk0_input_frequency: integer := 10000; - inclk1_input_frequency: integer := 10000; - gate_lock_signal: string := "no"; - gate_lock_counter: integer := 1; - self_reset_on_gated_loss_lock: string := "off"; - valid_lock_multiplier: integer := 1; - invalid_lock_multiplier: integer := 5; - switch_over_type: string := "auto"; - switch_over_on_lossclk: string := "off"; - switch_over_on_gated_lock: string := "off"; - switch_over_counter: integer := 1; - enable_switch_over_counter: string := "on"; - bandwidth : integer := 0; - bandwidth_type : string := "auto"; - spread_frequency: integer := 0; - common_rx_tx : string := "off"; - use_dc_coupling : string := "false"; - clk0_output_frequency: integer := 0; - clk0_multiply_by: integer := 1; - clk0_divide_by : integer := 1; - clk0_phase_shift: string := "0"; - clk0_duty_cycle : integer := 50; - clk1_output_frequency: integer := 0; - clk1_multiply_by: integer := 1; - clk1_divide_by : integer := 1; - clk1_phase_shift: string := "0"; - clk1_duty_cycle : integer := 50; - clk2_output_frequency: integer := 0; - clk2_multiply_by: integer := 1; - clk2_divide_by : integer := 1; - clk2_phase_shift: string := "0"; - clk2_duty_cycle : integer := 50; - clk3_output_frequency: integer := 0; - clk3_multiply_by: integer := 1; - clk3_divide_by : integer := 1; - clk3_phase_shift: string := "0"; - clk3_duty_cycle : integer := 50; - clk4_output_frequency: integer := 0; - clk4_multiply_by: integer := 1; - clk4_divide_by : integer := 1; - clk4_phase_shift: string := "0"; - clk4_duty_cycle : integer := 50; - clk5_output_frequency: integer := 0; - clk5_multiply_by: integer := 1; - clk5_divide_by : integer := 1; - clk5_phase_shift: string := "0"; - clk5_duty_cycle : integer := 50; - pfd_min : integer := 0; - pfd_max : integer := 0; - vco_min : integer := 0; - vco_max : integer := 0; - vco_center : integer := 0; - m_initial : integer := 1; - m : integer := 0; - n : integer := 1; - m2 : integer := 1; - n2 : integer := 1; - ss : integer := 0; - c0_high : integer := 1; - c0_low : integer := 1; - c0_initial : integer := 1; - c0_mode : string := "bypass"; - c0_ph : integer := 0; - c1_high : integer := 1; - c1_low : integer := 1; - c1_initial : integer := 1; - c1_mode : string := "bypass"; - c1_ph : integer := 0; - c2_high : integer := 1; - c2_low : integer := 1; - c2_initial : integer := 1; - c2_mode : string := "bypass"; - c2_ph : integer := 0; - c3_high : integer := 1; - c3_low : integer := 1; - c3_initial : integer := 1; - c3_mode : string := "bypass"; - c3_ph : integer := 0; - c4_high : integer := 1; - c4_low : integer := 1; - c4_initial : integer := 1; - c4_mode : string := "bypass"; - c4_ph : integer := 0; - c5_high : integer := 1; - c5_low : integer := 1; - c5_initial : integer := 1; - c5_mode : string := "bypass"; - c5_ph : integer := 0; - m_ph : integer := 0; - clk0_counter : string := "c0"; - clk1_counter : string := "c1"; - clk2_counter : string := "c2"; - clk3_counter : string := "c3"; - clk4_counter : string := "c4"; - clk5_counter : string := "c5"; - c1_use_casc_in : string := "off"; - c2_use_casc_in : string := "off"; - c3_use_casc_in : string := "off"; - c4_use_casc_in : string := "off"; - c5_use_casc_in : string := "off"; - m_test_source : integer := 5; - c0_test_source : integer := 5; - c1_test_source : integer := 5; - c2_test_source : integer := 5; - c3_test_source : integer := 5; - c4_test_source : integer := 5; - c5_test_source : integer := 5; - enable0_counter : string := "c0"; - enable1_counter : string := "c1"; - sclkout0_phase_shift: string := "0"; - sclkout1_phase_shift: string := "0"; - vco_multiply_by : integer := 0; - vco_divide_by : integer := 0; - vco_post_scale : integer := 1; - charge_pump_current: integer := 52; - loop_filter_r : string := "1.0"; - loop_filter_c : integer := 16; - pll_compensation_delay: integer := 0; - simulation_type : string := "functional"; - down_spread : string := "0.0"; - sim_gate_lock_device_behavior: string := "off"; - clk0_phase_shift_num: integer := 0; - clk1_phase_shift_num: integer := 0; - clk2_phase_shift_num: integer := 0; - family_name : string := "StratixII"; - clk0_use_even_counter_mode: string := "off"; - clk1_use_even_counter_mode: string := "off"; - clk2_use_even_counter_mode: string := "off"; - clk3_use_even_counter_mode: string := "off"; - clk4_use_even_counter_mode: string := "off"; - clk5_use_even_counter_mode: string := "off"; - clk0_use_even_counter_value: string := "off"; - clk1_use_even_counter_value: string := "off"; - clk2_use_even_counter_value: string := "off"; - clk3_use_even_counter_value: string := "off"; - clk4_use_even_counter_value: string := "off"; - clk5_use_even_counter_value: string := "off"; - scan_chain_mif_file: string := ""; - GPP_SCAN_CHAIN : integer := 174; - FAST_SCAN_CHAIN : integer := 75; - prim_clk : string := "inclk0"; - GATE_LOCK_CYCLES: integer := 7 - ); - port( - inclk : in vl_logic_vector(1 downto 0); - fbin : in vl_logic; - ena : in vl_logic; - clkswitch : in vl_logic; - areset : in vl_logic; - pfdena : in vl_logic; - scanclk : in vl_logic; - scanread : in vl_logic; - scanwrite : in vl_logic; - scandata : in vl_logic; - testin : in vl_logic_vector(3 downto 0); - clk : out vl_logic_vector(5 downto 0); - clkbad : out vl_logic_vector(1 downto 0); - activeclock : out vl_logic; - locked : out vl_logic; - clkloss : out vl_logic; - scandataout : out vl_logic; - scandone : out vl_logic; - enable0 : out vl_logic; - enable1 : out vl_logic; - testupout : out vl_logic; - testdownout : out vl_logic; - sclkout : out vl_logic_vector(1 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of pll_type : constant is 1; - attribute mti_svvh_generic_type of compensate_clock : constant is 1; - attribute mti_svvh_generic_type of feedback_source : constant is 1; - attribute mti_svvh_generic_type of qualify_conf_done : constant is 1; - attribute mti_svvh_generic_type of test_input_comp_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_feedback_comp_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1; - attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1; - attribute mti_svvh_generic_type of gate_lock_signal : constant is 1; - attribute mti_svvh_generic_type of gate_lock_counter : constant is 1; - attribute mti_svvh_generic_type of self_reset_on_gated_loss_lock : constant is 1; - attribute mti_svvh_generic_type of valid_lock_multiplier : constant is 1; - attribute mti_svvh_generic_type of invalid_lock_multiplier : constant is 1; - attribute mti_svvh_generic_type of switch_over_type : constant is 1; - attribute mti_svvh_generic_type of switch_over_on_lossclk : constant is 1; - attribute mti_svvh_generic_type of switch_over_on_gated_lock : constant is 1; - attribute mti_svvh_generic_type of switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of bandwidth : constant is 1; - attribute mti_svvh_generic_type of bandwidth_type : constant is 1; - attribute mti_svvh_generic_type of spread_frequency : constant is 1; - attribute mti_svvh_generic_type of common_rx_tx : constant is 1; - attribute mti_svvh_generic_type of use_dc_coupling : constant is 1; - attribute mti_svvh_generic_type of clk0_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk0_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk1_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk1_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk2_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk2_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk3_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk3_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk4_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk4_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk5_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk5_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk5_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk5_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk5_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of pfd_min : constant is 1; - attribute mti_svvh_generic_type of pfd_max : constant is 1; - attribute mti_svvh_generic_type of vco_min : constant is 1; - attribute mti_svvh_generic_type of vco_max : constant is 1; - attribute mti_svvh_generic_type of vco_center : constant is 1; - attribute mti_svvh_generic_type of m_initial : constant is 1; - attribute mti_svvh_generic_type of m : constant is 1; - attribute mti_svvh_generic_type of n : constant is 1; - attribute mti_svvh_generic_type of m2 : constant is 1; - attribute mti_svvh_generic_type of n2 : constant is 1; - attribute mti_svvh_generic_type of ss : constant is 1; - attribute mti_svvh_generic_type of c0_high : constant is 1; - attribute mti_svvh_generic_type of c0_low : constant is 1; - attribute mti_svvh_generic_type of c0_initial : constant is 1; - attribute mti_svvh_generic_type of c0_mode : constant is 1; - attribute mti_svvh_generic_type of c0_ph : constant is 1; - attribute mti_svvh_generic_type of c1_high : constant is 1; - attribute mti_svvh_generic_type of c1_low : constant is 1; - attribute mti_svvh_generic_type of c1_initial : constant is 1; - attribute mti_svvh_generic_type of c1_mode : constant is 1; - attribute mti_svvh_generic_type of c1_ph : constant is 1; - attribute mti_svvh_generic_type of c2_high : constant is 1; - attribute mti_svvh_generic_type of c2_low : constant is 1; - attribute mti_svvh_generic_type of c2_initial : constant is 1; - attribute mti_svvh_generic_type of c2_mode : constant is 1; - attribute mti_svvh_generic_type of c2_ph : constant is 1; - attribute mti_svvh_generic_type of c3_high : constant is 1; - attribute mti_svvh_generic_type of c3_low : constant is 1; - attribute mti_svvh_generic_type of c3_initial : constant is 1; - attribute mti_svvh_generic_type of c3_mode : constant is 1; - attribute mti_svvh_generic_type of c3_ph : constant is 1; - attribute mti_svvh_generic_type of c4_high : constant is 1; - attribute mti_svvh_generic_type of c4_low : constant is 1; - attribute mti_svvh_generic_type of c4_initial : constant is 1; - attribute mti_svvh_generic_type of c4_mode : constant is 1; - attribute mti_svvh_generic_type of c4_ph : constant is 1; - attribute mti_svvh_generic_type of c5_high : constant is 1; - attribute mti_svvh_generic_type of c5_low : constant is 1; - attribute mti_svvh_generic_type of c5_initial : constant is 1; - attribute mti_svvh_generic_type of c5_mode : constant is 1; - attribute mti_svvh_generic_type of c5_ph : constant is 1; - attribute mti_svvh_generic_type of m_ph : constant is 1; - attribute mti_svvh_generic_type of clk0_counter : constant is 1; - attribute mti_svvh_generic_type of clk1_counter : constant is 1; - attribute mti_svvh_generic_type of clk2_counter : constant is 1; - attribute mti_svvh_generic_type of clk3_counter : constant is 1; - attribute mti_svvh_generic_type of clk4_counter : constant is 1; - attribute mti_svvh_generic_type of clk5_counter : constant is 1; - attribute mti_svvh_generic_type of c1_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c2_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c3_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c4_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c5_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of m_test_source : constant is 1; - attribute mti_svvh_generic_type of c0_test_source : constant is 1; - attribute mti_svvh_generic_type of c1_test_source : constant is 1; - attribute mti_svvh_generic_type of c2_test_source : constant is 1; - attribute mti_svvh_generic_type of c3_test_source : constant is 1; - attribute mti_svvh_generic_type of c4_test_source : constant is 1; - attribute mti_svvh_generic_type of c5_test_source : constant is 1; - attribute mti_svvh_generic_type of enable0_counter : constant is 1; - attribute mti_svvh_generic_type of enable1_counter : constant is 1; - attribute mti_svvh_generic_type of sclkout0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of sclkout1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of vco_multiply_by : constant is 1; - attribute mti_svvh_generic_type of vco_divide_by : constant is 1; - attribute mti_svvh_generic_type of vco_post_scale : constant is 1; - attribute mti_svvh_generic_type of charge_pump_current : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c : constant is 1; - attribute mti_svvh_generic_type of pll_compensation_delay : constant is 1; - attribute mti_svvh_generic_type of simulation_type : constant is 1; - attribute mti_svvh_generic_type of down_spread : constant is 1; - attribute mti_svvh_generic_type of sim_gate_lock_device_behavior : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of family_name : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk5_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk5_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1; - attribute mti_svvh_generic_type of GPP_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of FAST_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of prim_clk : constant is 1; - attribute mti_svvh_generic_type of GATE_LOCK_CYCLES : constant is 1; -end MF_stratixii_pll; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixiii_pll/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixiii_pll/_primary.dat deleted file mode 100644 index de760a6..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixiii_pll/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixiii_pll/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixiii_pll/_primary.dbs deleted file mode 100644 index baf9b6d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixiii_pll/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixiii_pll/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixiii_pll/_primary.vhd deleted file mode 100644 index 0e25499..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/@m@f_stratixiii_pll/_primary.vhd +++ /dev/null @@ -1,503 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity MF_stratixiii_pll is - generic( - operation_mode : string := "normal"; - pll_type : string := "auto"; - compensate_clock: string := "clock0"; - inclk0_input_frequency: integer := 0; - inclk1_input_frequency: integer := 0; - self_reset_on_loss_lock: string := "off"; - switch_over_type: string := "auto"; - switch_over_counter: integer := 1; - enable_switch_over_counter: string := "off"; - dpa_multiply_by : integer := 0; - dpa_divide_by : integer := 0; - dpa_divider : integer := 0; - bandwidth : integer := 0; - bandwidth_type : string := "auto"; - use_dc_coupling : string := "false"; - lock_high : integer := 0; - lock_low : integer := 0; - lock_window_ui : string := "0.05"; - test_bypass_lock_detect: string := "off"; - clk0_output_frequency: integer := 0; - clk0_multiply_by: integer := 0; - clk0_divide_by : integer := 0; - clk0_phase_shift: string := "0"; - clk0_duty_cycle : integer := 50; - clk1_output_frequency: integer := 0; - clk1_multiply_by: integer := 0; - clk1_divide_by : integer := 0; - clk1_phase_shift: string := "0"; - clk1_duty_cycle : integer := 50; - clk2_output_frequency: integer := 0; - clk2_multiply_by: integer := 0; - clk2_divide_by : integer := 0; - clk2_phase_shift: string := "0"; - clk2_duty_cycle : integer := 50; - clk3_output_frequency: integer := 0; - clk3_multiply_by: integer := 0; - clk3_divide_by : integer := 0; - clk3_phase_shift: string := "0"; - clk3_duty_cycle : integer := 50; - clk4_output_frequency: integer := 0; - clk4_multiply_by: integer := 0; - clk4_divide_by : integer := 0; - clk4_phase_shift: string := "0"; - clk4_duty_cycle : integer := 50; - clk5_output_frequency: integer := 0; - clk5_multiply_by: integer := 0; - clk5_divide_by : integer := 0; - clk5_phase_shift: string := "0"; - clk5_duty_cycle : integer := 50; - clk6_output_frequency: integer := 0; - clk6_multiply_by: integer := 0; - clk6_divide_by : integer := 0; - clk6_phase_shift: string := "0"; - clk6_duty_cycle : integer := 50; - clk7_output_frequency: integer := 0; - clk7_multiply_by: integer := 0; - clk7_divide_by : integer := 0; - clk7_phase_shift: string := "0"; - clk7_duty_cycle : integer := 50; - clk8_output_frequency: integer := 0; - clk8_multiply_by: integer := 0; - clk8_divide_by : integer := 0; - clk8_phase_shift: string := "0"; - clk8_duty_cycle : integer := 50; - clk9_output_frequency: integer := 0; - clk9_multiply_by: integer := 0; - clk9_divide_by : integer := 0; - clk9_phase_shift: string := "0"; - clk9_duty_cycle : integer := 50; - pfd_min : integer := 0; - pfd_max : integer := 0; - vco_min : integer := 0; - vco_max : integer := 0; - vco_center : integer := 0; - m_initial : integer := 1; - m : integer := 0; - n : integer := 1; - c0_high : integer := 1; - c0_low : integer := 1; - c0_initial : integer := 1; - c0_mode : string := "bypass"; - c0_ph : integer := 0; - c1_high : integer := 1; - c1_low : integer := 1; - c1_initial : integer := 1; - c1_mode : string := "bypass"; - c1_ph : integer := 0; - c2_high : integer := 1; - c2_low : integer := 1; - c2_initial : integer := 1; - c2_mode : string := "bypass"; - c2_ph : integer := 0; - c3_high : integer := 1; - c3_low : integer := 1; - c3_initial : integer := 1; - c3_mode : string := "bypass"; - c3_ph : integer := 0; - c4_high : integer := 1; - c4_low : integer := 1; - c4_initial : integer := 1; - c4_mode : string := "bypass"; - c4_ph : integer := 0; - c5_high : integer := 1; - c5_low : integer := 1; - c5_initial : integer := 1; - c5_mode : string := "bypass"; - c5_ph : integer := 0; - c6_high : integer := 1; - c6_low : integer := 1; - c6_initial : integer := 1; - c6_mode : string := "bypass"; - c6_ph : integer := 0; - c7_high : integer := 1; - c7_low : integer := 1; - c7_initial : integer := 1; - c7_mode : string := "bypass"; - c7_ph : integer := 0; - c8_high : integer := 1; - c8_low : integer := 1; - c8_initial : integer := 1; - c8_mode : string := "bypass"; - c8_ph : integer := 0; - c9_high : integer := 1; - c9_low : integer := 1; - c9_initial : integer := 1; - c9_mode : string := "bypass"; - c9_ph : integer := 0; - m_ph : integer := 0; - clk0_counter : string := "unused"; - clk1_counter : string := "unused"; - clk2_counter : string := "unused"; - clk3_counter : string := "unused"; - clk4_counter : string := "unused"; - clk5_counter : string := "unused"; - clk6_counter : string := "unused"; - clk7_counter : string := "unused"; - clk8_counter : string := "unused"; - clk9_counter : string := "unused"; - c1_use_casc_in : string := "off"; - c2_use_casc_in : string := "off"; - c3_use_casc_in : string := "off"; - c4_use_casc_in : string := "off"; - c5_use_casc_in : string := "off"; - c6_use_casc_in : string := "off"; - c7_use_casc_in : string := "off"; - c8_use_casc_in : string := "off"; - c9_use_casc_in : string := "off"; - m_test_source : integer := -1; - c0_test_source : integer := -1; - c1_test_source : integer := -1; - c2_test_source : integer := -1; - c3_test_source : integer := -1; - c4_test_source : integer := -1; - c5_test_source : integer := -1; - c6_test_source : integer := -1; - c7_test_source : integer := -1; - c8_test_source : integer := -1; - c9_test_source : integer := -1; - vco_multiply_by : integer := 0; - vco_divide_by : integer := 0; - vco_post_scale : integer := 1; - vco_frequency_control: string := "auto"; - vco_phase_shift_step: integer := 0; - charge_pump_current: integer := 10; - loop_filter_r : string := "1.0"; - loop_filter_c : integer := 0; - pll_compensation_delay: integer := 0; - simulation_type : string := "functional"; - down_spread : string := "0.0"; - lock_c : integer := 4; - sim_gate_lock_device_behavior: string := "off"; - clk0_phase_shift_num: integer := 0; - clk1_phase_shift_num: integer := 0; - clk2_phase_shift_num: integer := 0; - clk3_phase_shift_num: integer := 0; - clk4_phase_shift_num: integer := 0; - family_name : string := "StratixIII"; - clk0_use_even_counter_mode: string := "off"; - clk1_use_even_counter_mode: string := "off"; - clk2_use_even_counter_mode: string := "off"; - clk3_use_even_counter_mode: string := "off"; - clk4_use_even_counter_mode: string := "off"; - clk5_use_even_counter_mode: string := "off"; - clk6_use_even_counter_mode: string := "off"; - clk7_use_even_counter_mode: string := "off"; - clk8_use_even_counter_mode: string := "off"; - clk9_use_even_counter_mode: string := "off"; - clk0_use_even_counter_value: string := "off"; - clk1_use_even_counter_value: string := "off"; - clk2_use_even_counter_value: string := "off"; - clk3_use_even_counter_value: string := "off"; - clk4_use_even_counter_value: string := "off"; - clk5_use_even_counter_value: string := "off"; - clk6_use_even_counter_value: string := "off"; - clk7_use_even_counter_value: string := "off"; - clk8_use_even_counter_value: string := "off"; - clk9_use_even_counter_value: string := "off"; - init_block_reset_a_count: integer := 1; - init_block_reset_b_count: integer := 1; - phase_counter_select_width: integer := 4; - lock_window : integer := 5; - inclk0_freq : vl_notype; - inclk1_freq : vl_notype; - charge_pump_current_bits: integer := 0; - lock_window_ui_bits: integer := 0; - loop_filter_c_bits: integer := 0; - loop_filter_r_bits: integer := 0; - test_counter_c0_delay_chain_bits: integer := 0; - test_counter_c1_delay_chain_bits: integer := 0; - test_counter_c2_delay_chain_bits: integer := 0; - test_counter_c3_delay_chain_bits: integer := 0; - test_counter_c4_delay_chain_bits: integer := 0; - test_counter_c5_delay_chain_bits: integer := 0; - test_counter_c6_delay_chain_bits: integer := 0; - test_counter_c7_delay_chain_bits: integer := 0; - test_counter_c8_delay_chain_bits: integer := 0; - test_counter_c9_delay_chain_bits: integer := 0; - test_counter_m_delay_chain_bits: integer := 0; - test_counter_n_delay_chain_bits: integer := 0; - test_feedback_comp_delay_chain_bits: integer := 0; - test_input_comp_delay_chain_bits: integer := 0; - test_volt_reg_output_mode_bits: integer := 0; - test_volt_reg_output_voltage_bits: integer := 0; - test_volt_reg_test_mode: string := "false"; - vco_range_detector_high_bits: integer := -1; - vco_range_detector_low_bits: integer := -1; - scan_chain_mif_file: string := ""; - test_counter_c3_sclk_delay_chain_bits: integer := -1; - test_counter_c4_sclk_delay_chain_bits: integer := -1; - test_counter_c5_lden_delay_chain_bits: integer := -1; - test_counter_c6_lden_delay_chain_bits: integer := -1; - auto_settings : string := "true"; - SCAN_CHAIN : integer := 144; - GPP_SCAN_CHAIN : integer := 234; - FAST_SCAN_CHAIN : integer := 180; - num_phase_taps : integer := 8 - ); - port( - inclk : in vl_logic_vector(1 downto 0); - fbin : in vl_logic; - fbout : out vl_logic; - clkswitch : in vl_logic; - areset : in vl_logic; - pfdena : in vl_logic; - scanclk : in vl_logic; - scandata : in vl_logic; - scanclkena : in vl_logic; - configupdate : in vl_logic; - clk : out vl_logic_vector(9 downto 0); - phasecounterselect: in vl_logic_vector; - phaseupdown : in vl_logic; - phasestep : in vl_logic; - clkbad : out vl_logic_vector(1 downto 0); - activeclock : out vl_logic; - locked : out vl_logic; - scandataout : out vl_logic; - scandone : out vl_logic; - phasedone : out vl_logic; - vcooverrange : out vl_logic; - vcounderrange : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of pll_type : constant is 1; - attribute mti_svvh_generic_type of compensate_clock : constant is 1; - attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1; - attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1; - attribute mti_svvh_generic_type of self_reset_on_loss_lock : constant is 1; - attribute mti_svvh_generic_type of switch_over_type : constant is 1; - attribute mti_svvh_generic_type of switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of dpa_multiply_by : constant is 1; - attribute mti_svvh_generic_type of dpa_divide_by : constant is 1; - attribute mti_svvh_generic_type of dpa_divider : constant is 1; - attribute mti_svvh_generic_type of bandwidth : constant is 1; - attribute mti_svvh_generic_type of bandwidth_type : constant is 1; - attribute mti_svvh_generic_type of use_dc_coupling : constant is 1; - attribute mti_svvh_generic_type of lock_high : constant is 1; - attribute mti_svvh_generic_type of lock_low : constant is 1; - attribute mti_svvh_generic_type of lock_window_ui : constant is 1; - attribute mti_svvh_generic_type of test_bypass_lock_detect : constant is 1; - attribute mti_svvh_generic_type of clk0_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk0_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk1_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk1_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk2_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk2_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk3_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk3_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk4_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk4_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk5_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk5_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk5_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk5_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk5_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk6_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk6_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk6_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk6_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk6_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk7_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk7_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk7_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk7_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk7_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk8_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk8_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk8_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk8_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk8_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk9_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk9_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk9_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk9_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk9_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of pfd_min : constant is 1; - attribute mti_svvh_generic_type of pfd_max : constant is 1; - attribute mti_svvh_generic_type of vco_min : constant is 1; - attribute mti_svvh_generic_type of vco_max : constant is 1; - attribute mti_svvh_generic_type of vco_center : constant is 1; - attribute mti_svvh_generic_type of m_initial : constant is 1; - attribute mti_svvh_generic_type of m : constant is 1; - attribute mti_svvh_generic_type of n : constant is 1; - attribute mti_svvh_generic_type of c0_high : constant is 1; - attribute mti_svvh_generic_type of c0_low : constant is 1; - attribute mti_svvh_generic_type of c0_initial : constant is 1; - attribute mti_svvh_generic_type of c0_mode : constant is 1; - attribute mti_svvh_generic_type of c0_ph : constant is 1; - attribute mti_svvh_generic_type of c1_high : constant is 1; - attribute mti_svvh_generic_type of c1_low : constant is 1; - attribute mti_svvh_generic_type of c1_initial : constant is 1; - attribute mti_svvh_generic_type of c1_mode : constant is 1; - attribute mti_svvh_generic_type of c1_ph : constant is 1; - attribute mti_svvh_generic_type of c2_high : constant is 1; - attribute mti_svvh_generic_type of c2_low : constant is 1; - attribute mti_svvh_generic_type of c2_initial : constant is 1; - attribute mti_svvh_generic_type of c2_mode : constant is 1; - attribute mti_svvh_generic_type of c2_ph : constant is 1; - attribute mti_svvh_generic_type of c3_high : constant is 1; - attribute mti_svvh_generic_type of c3_low : constant is 1; - attribute mti_svvh_generic_type of c3_initial : constant is 1; - attribute mti_svvh_generic_type of c3_mode : constant is 1; - attribute mti_svvh_generic_type of c3_ph : constant is 1; - attribute mti_svvh_generic_type of c4_high : constant is 1; - attribute mti_svvh_generic_type of c4_low : constant is 1; - attribute mti_svvh_generic_type of c4_initial : constant is 1; - attribute mti_svvh_generic_type of c4_mode : constant is 1; - attribute mti_svvh_generic_type of c4_ph : constant is 1; - attribute mti_svvh_generic_type of c5_high : constant is 1; - attribute mti_svvh_generic_type of c5_low : constant is 1; - attribute mti_svvh_generic_type of c5_initial : constant is 1; - attribute mti_svvh_generic_type of c5_mode : constant is 1; - attribute mti_svvh_generic_type of c5_ph : constant is 1; - attribute mti_svvh_generic_type of c6_high : constant is 1; - attribute mti_svvh_generic_type of c6_low : constant is 1; - attribute mti_svvh_generic_type of c6_initial : constant is 1; - attribute mti_svvh_generic_type of c6_mode : constant is 1; - attribute mti_svvh_generic_type of c6_ph : constant is 1; - attribute mti_svvh_generic_type of c7_high : constant is 1; - attribute mti_svvh_generic_type of c7_low : constant is 1; - attribute mti_svvh_generic_type of c7_initial : constant is 1; - attribute mti_svvh_generic_type of c7_mode : constant is 1; - attribute mti_svvh_generic_type of c7_ph : constant is 1; - attribute mti_svvh_generic_type of c8_high : constant is 1; - attribute mti_svvh_generic_type of c8_low : constant is 1; - attribute mti_svvh_generic_type of c8_initial : constant is 1; - attribute mti_svvh_generic_type of c8_mode : constant is 1; - attribute mti_svvh_generic_type of c8_ph : constant is 1; - attribute mti_svvh_generic_type of c9_high : constant is 1; - attribute mti_svvh_generic_type of c9_low : constant is 1; - attribute mti_svvh_generic_type of c9_initial : constant is 1; - attribute mti_svvh_generic_type of c9_mode : constant is 1; - attribute mti_svvh_generic_type of c9_ph : constant is 1; - attribute mti_svvh_generic_type of m_ph : constant is 1; - attribute mti_svvh_generic_type of clk0_counter : constant is 1; - attribute mti_svvh_generic_type of clk1_counter : constant is 1; - attribute mti_svvh_generic_type of clk2_counter : constant is 1; - attribute mti_svvh_generic_type of clk3_counter : constant is 1; - attribute mti_svvh_generic_type of clk4_counter : constant is 1; - attribute mti_svvh_generic_type of clk5_counter : constant is 1; - attribute mti_svvh_generic_type of clk6_counter : constant is 1; - attribute mti_svvh_generic_type of clk7_counter : constant is 1; - attribute mti_svvh_generic_type of clk8_counter : constant is 1; - attribute mti_svvh_generic_type of clk9_counter : constant is 1; - attribute mti_svvh_generic_type of c1_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c2_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c3_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c4_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c5_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c6_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c7_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c8_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c9_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of m_test_source : constant is 1; - attribute mti_svvh_generic_type of c0_test_source : constant is 1; - attribute mti_svvh_generic_type of c1_test_source : constant is 1; - attribute mti_svvh_generic_type of c2_test_source : constant is 1; - attribute mti_svvh_generic_type of c3_test_source : constant is 1; - attribute mti_svvh_generic_type of c4_test_source : constant is 1; - attribute mti_svvh_generic_type of c5_test_source : constant is 1; - attribute mti_svvh_generic_type of c6_test_source : constant is 1; - attribute mti_svvh_generic_type of c7_test_source : constant is 1; - attribute mti_svvh_generic_type of c8_test_source : constant is 1; - attribute mti_svvh_generic_type of c9_test_source : constant is 1; - attribute mti_svvh_generic_type of vco_multiply_by : constant is 1; - attribute mti_svvh_generic_type of vco_divide_by : constant is 1; - attribute mti_svvh_generic_type of vco_post_scale : constant is 1; - attribute mti_svvh_generic_type of vco_frequency_control : constant is 1; - attribute mti_svvh_generic_type of vco_phase_shift_step : constant is 1; - attribute mti_svvh_generic_type of charge_pump_current : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c : constant is 1; - attribute mti_svvh_generic_type of pll_compensation_delay : constant is 1; - attribute mti_svvh_generic_type of simulation_type : constant is 1; - attribute mti_svvh_generic_type of down_spread : constant is 1; - attribute mti_svvh_generic_type of lock_c : constant is 1; - attribute mti_svvh_generic_type of sim_gate_lock_device_behavior : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk3_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of clk4_phase_shift_num : constant is 1; - attribute mti_svvh_generic_type of family_name : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk5_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk6_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk7_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk8_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk9_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk5_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk6_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk7_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk8_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk9_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of init_block_reset_a_count : constant is 1; - attribute mti_svvh_generic_type of init_block_reset_b_count : constant is 1; - attribute mti_svvh_generic_type of phase_counter_select_width : constant is 1; - attribute mti_svvh_generic_type of lock_window : constant is 1; - attribute mti_svvh_generic_type of inclk0_freq : constant is 3; - attribute mti_svvh_generic_type of inclk1_freq : constant is 3; - attribute mti_svvh_generic_type of charge_pump_current_bits : constant is 1; - attribute mti_svvh_generic_type of lock_window_ui_bits : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c_bits : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c0_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c1_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c2_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c3_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c4_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c5_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c6_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c7_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c8_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c9_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_m_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_n_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_feedback_comp_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_input_comp_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_volt_reg_output_mode_bits : constant is 1; - attribute mti_svvh_generic_type of test_volt_reg_output_voltage_bits : constant is 1; - attribute mti_svvh_generic_type of test_volt_reg_test_mode : constant is 1; - attribute mti_svvh_generic_type of vco_range_detector_high_bits : constant is 1; - attribute mti_svvh_generic_type of vco_range_detector_low_bits : constant is 1; - attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1; - attribute mti_svvh_generic_type of test_counter_c3_sclk_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c4_sclk_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c5_lden_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of test_counter_c6_lden_delay_chain_bits : constant is 1; - attribute mti_svvh_generic_type of auto_settings : constant is 1; - attribute mti_svvh_generic_type of SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of GPP_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of FAST_SCAN_CHAIN : constant is 1; - attribute mti_svvh_generic_type of num_phase_taps : constant is 1; -end MF_stratixiii_pll; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/_info b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/_info deleted file mode 100644 index aef64de..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/_info +++ /dev/null @@ -1,1445 +0,0 @@ -m255 -K3 -13 -cModel Technology -Z0 dC:\Users\3304\Desktop\codes\codes from HY\PF_old bottom\PF_DS0401\PF_DS\simulation\modelsim -va_graycounter -!s100 >cNXlNL8]X]AbgD^BPX;91 -IZ`i:D=17F1X34IlWm7^:?2 -VDf]LUSeG959GAjb>XD]GQ3 -Z1 dC:\Users\3304\Desktop\codes\codes from HY\PF_old bottom\PF_DS0401\PF_DS\simulation\modelsim -Z2 w1303981859 -Z3 8d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v -Z4 Fd:/altera/11.0/quartus/eda/sim_lib/altera_mf.v -L0 48603 -Z5 OL;L;10.0c;49 -r1 -!s85 0 -31 -Z6 !s108 1386757422.935000 -Z7 !s107 d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v| -Z8 !s90 -reportprogress|300|-vlog01compat|-work|altera_mf_ver|d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v| -Z9 o-vlog01compat -work altera_mf_ver -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF -valt3pram -!s100 `>9TKcbKdMCCScL>o9WZY2 -IV;W>3483HK_VFYnCW_>H]2 -Van=jdhFiA>nlKzFh<1 -I]`kL2kTC6Zf9e[[QQ:?S[2 -V@E5j__dc@^a;@@8RaPH0c3 -R1 -R2 -R3 -R4 -L0 49456 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valt_cal -!s100 BaogO@ghm_`G1CVo`n;Il8A<04j0 -VRXTXX5n6SY=Rhi@dnZVSX1 -R1 -R2 -R3 -R4 -L0 49023 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valt_cal_c3gxb -!s100 12nmKnDS:_^QY9H5XdlO]3 -I37lB@Ml^Bn`OOMjRBj=>g2 -V?If`n[=Fh[^b?ET:b4G1z0 -R1 -R2 -R3 -R4 -L0 49250 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valt_cal_mm -!s100 PE>o__@j41TaCD[NXPg?m3 -Ikf5>0=VX36@D;ElNIzdF9P9geA=hb0 -IcV1REz7?I]ecF=5C>Lezl1 -V7Vi>bi2@bRT@md[U3NeQO1 -R1 -R2 -R3 -R4 -L0 41830 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtddio_bidir -!s100 N;BzEUA:bbYYJ[mVg]7ja2 -IB7?]PcOT]4]cL_hjkQlHL2 -VZ^GYY?k[6Ji8DUNDflFS@3 -R1 -R2 -R3 -R4 -L0 43267 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtddio_in -!s100 63`iNG1X:fULOdblc5[eU3 -I`jYkORMAVl;Wbllb<^obI3 -VHM]GLg3Gf96Y=OU_R;Ek43 -R1 -R2 -R3 -R4 -L0 42756 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtddio_out -!s100 M141:Gon8=zPImXe[ia@_0 -IhibcRbCl>h6NHnbiVM:i@1 -VMMOQhNXJH2lD2aVj=_^:K0 -R1 -R2 -R3 -R4 -L0 43019 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtdpram -!s100 PS`^LiV:kC3OoZGHfY2KH3 -InK3mU@0?0YDEE1 -R1 -R2 -R3 -R4 -L0 43406 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vALTERA_DEVICE_FAMILIES -!s100 IBL]0Uj^d<]8[Re2 -ImGfYdCM`g3KdgUmJC5R[h1 -VQ9;YfM0O8Tb_Z0 -R1 -R2 -R3 -R4 -L0 1234 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -n@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n -vALTERA_MF_MEMORY_INITIALIZATION -!s100 6YhAI??_5W;[Ff`JYjCbU2 -IY_Xc>QF7h4@i=Oi7flOzn3 -VdGgz5CJfH?XAb0VYP`BUe[;KLU_X1 -R1 -R2 -R3 -R4 -L0 48829 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtera_std_synchronizer_bundle -!s100 1hH98J@Kb<9=T>]kMN3XQ2 -IdDWmQRiiYQQaINM1MW=DV2 -V_Ic[PWl9n@Z`fX2[dFD`41 -R1 -R2 -R3 -R4 -L0 48988 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtfp_mult -!s100 U0zT@2NL:inzAj>oYZhjd0 -I23O3azXJ@k5lYMH=jAfnD3 -VWz]bAzTDMN3A[X>3L[JQ@0 -R1 -R2 -R3 -R4 -L0 40943 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtlvds_rx -!s100 CV5lMb;>a5i[EQnh@BYE03 -I2d:GFag5JK1 -V1 -IomUhc1P`S?zFKD7^CjWmP0 -VdKVNGEmeECk`3k9[3HWhWd?T3 -R1 -R2 -R3 -R4 -L0 33691 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtparallel_flash_loader -!s100 L?W6KCYd0Y`a]@DJE;9E_2 -I6DcofVZ?`O2GKN@n9kQ2E0 -VhRj60aPV;na]knXo^RK_41 -R1 -R2 -R3 -R4 -L0 51710 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtpll -!s100 bDQ1Ha0L=DF5V;>R=jX2U0 -I6N;02j@hO:=bkaVzUl>X=0 -V1]6ZE4bASeVHoDRB8`Pz_0 -R1 -R2 -R3 -R4 -L0 21540 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtserial_flash_loader -!s100 W495>K6OW=PMR0n6A8WRV3 -IJ4M7]DO@WEmU3AW7N6Naa2 -Vn]I4bMI:Mz0G52=X^7eRQ1 -R1 -R2 -R3 -R4 -L0 51823 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtshift_taps -!s100 16RKCRXb^23Qlgf]]NGC]2 -IQB?PoCQf:0j^QDo[?81JXzQg1 -R1 -R2 -R3 -R4 -L0 51933 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtsqrt -!s100 hHgcmFIZzDTfOgomLK8bZ1 -IHJA8SUoPJQ4aUQO?k`H31 -R1 -R2 -R3 -R4 -L0 48694 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtstratixii_oct -!s100 fmgVl;?FdXhl`PDS@D]7K1 -I]a=d032ZT7hi0@RNR0SAk1 -V?S_nHHnOUMZJ@SDT=?H]o0 -R1 -R2 -R3 -R4 -L0 51694 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -valtsyncram -!s100 zCd7<:6maXIj0ZEMmz2E72 -I9O0?edl=ofVLWiJ>]2SFl0 -V6mo5i7Om9oQzKd8c1MY;l1 -R1 -R2 -R3 -R4 -L0 43939 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -varm_m_cntr -!s100 Do>2cDfC2lUM3b@d?a@80nohIm81 -IPYRl[4BX]?R5WEo<4o6iz3 -V;Zbk3ONaD>:D1BV2c0>nDGn4cXh2 -VSZ:RS?[@mA;M4Im<[m?9>2 -R1 -R2 -R3 -R4 -L0 14289 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vcda_scale_cntr -!s100 7IVbKCM5X;o2YB1i^`X1R3 -IiSc0h:@UzZ7h7AGLiCT8X1 -VS<5Xi@4Ba>4H^82]e]BXQ0 -R1 -R2 -R3 -R4 -L0 14360 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vcycloneiiigl_post_divider -!s100 LE5^O=NEj:[f=U4bl1<:z0 -I?k;hFDehDD=jf=CMUc[8A2 -VE[DCIBKzdZ_5J1e=a>ciB3 -R1 -R2 -R3 -R4 -L0 18078 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vdcfifo -!s100 CjLH26c_odin:fNTH6aj^1 -IEfdhJ@IPfVJ5dUFK8MU8?2 -VOzMi6nTjX3B;VkM]0i[Y80 -R1 -R2 -R3 -R4 -L0 31126 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vdcfifo_async -!s100 nEMN0:f3k2hcPEbR^HoJA2 -IcIfgIUGOI81 -I=P^ahPX0ei7?k3F;CML_E1 -V[2]E0llHYReD`f3Q@PoUN1 -R1 -R2 -R3 -R4 -L0 29220 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vdcfifo_fefifo -!s100 EK;gZlQCSB@cQAPkz4=e33 -IobTIZOkOo>ha44Y?9R`C`2 -V@Q7OA=F^`dje0[SFMXkS11 -R1 -R2 -R3 -R4 -L0 29298 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vdcfifo_low_latency -!s100 B_mmC_X:k[7O]?Ln_;9Da0 -I^_YYoH7gHl0o0I]b>7W`A2 -V?XcBZ>=nD4BX4ooI12 -VozISN2GIhM_G`e?:08V@@0 -R1 -R2 -R3 -R4 -L0 29936 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vdffp -!s100 KcG;c4BlfW;gGAz@EEWVD2 -I<5b2:N`D4bF^NZlgNR2B31 -VheeUl3zRZ0fNAP7CaC4WR1 -R1 -R2 -R3 -R4 -L0 2047 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vdummy_hub -!s100 XWVl:n98DfT9EJVZ;KzJm0 -ID^SLle0Tg38XcRR>FMD?63 -VoZ4KRLn6iG^^j8eOfh5`]3 -R1 -R2 -R3 -R4 -L0 51204 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vflexible_lvds_rx -!s100 7]TM`mEj[FPJjK7i1U:ma2 -I0X>cYTLRV:7lAeF=[L<7L0 -VlRUL40907KXEJMR:c^AoB3 -R1 -R2 -R3 -R4 -L0 25581 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vflexible_lvds_tx -!s100 WnmPLnO04Dd_;C:?1NVzJ3 -IOmWn3GN4iPFP3YSYTg9;C2 -VgXmTNzk=Z0i;64]lbL>Ej3 -R1 -R2 -R3 -R4 -L0 28660 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vjtag_tap_controller -!s100 k3mYIV;noNW7]JT:=7daJ2 -I=DQI45Yl9abSAizLbhgGn1 -Vmnmn`[hUOMH6AK2I_QN8Q1 -R1 -R2 -R3 -R4 -L0 50747 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vlcell -!s100 0iHR7LCSWH`2lX8KA=J;13 -I2nfgh1D=kPnFnm=>>F:l33 -VJ?L2VaGMcgJV7T`@^5DkR1 -R1 -R2 -R3 -R4 -L0 34 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vMF_cycloneiii_pll -!s100 IU[BaCno4d@3oG21R22=D1 -IYd:aeDM`c[8[jJY^;4^TQ2 -V8SACR3]mCQFb;Fhcz1 -R1 -R2 -R3 -R4 -L0 14487 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -n@m@f_cycloneiii_pll -vMF_cycloneiiigl_m_cntr -!s100 M]7HCga4ghT8Zn@mPd5272 -InZ>=4A?TN8nz3NR=CMKTX2 -V3m_Jz6C;W8>1i>E5DR]XP2 -R1 -R2 -R3 -R4 -L0 17816 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -n@m@f_cycloneiiigl_m_cntr -vMF_cycloneiiigl_n_cntr -!s100 zTJ4b2I_4IiDMgPhF[D5:1 -IZcO0MEI]k]UcZ`B^[1 -R1 -R2 -R3 -R4 -L0 17968 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -n@m@f_cycloneiiigl_scale_cntr -vMF_pll_reg -!s100 k>Hed0^D[APkVCUOIEMEf1 -I=m`2^]VXm@]V0 -V0?hlOYD6Z>E5^II12 -R1 -R2 -R3 -R4 -L0 2463 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -n@m@f_stratix_pll -vMF_stratixii_pll -!s100 =Nhi:Z>^i?7KUhccKDL2d1 -ICZWnA1W49cC3ZfY`El72n1 -V]ZTC;GJ]^ZXMZmG8?R3E32 -R1 -R2 -R3 -R4 -L0 6554 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -n@m@f_stratixii_pll -vMF_stratixiii_pll -!s100 lZF]B0a3 -R1 -R2 -R3 -R4 -L0 10385 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -n@m@f_stratixiii_pll -vparallel_add -!s100 0 -V_JQk5nE5WD?]hX7An^HMH2 -R1 -R2 -R3 -R4 -L0 51588 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vsld_virtual_jtag -!s100 71KS=KU?Il`RDk`XoUgH1 -I^a7bO_Nl7R9lL2cFFH^z^0 -VgN1]76z1 -IzMz?jO?cMXScFX3]LO3PP1 -V39zBWPn2G7n8FGOMRmNJB0 -R1 -R2 -R3 -R4 -L0 24744 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vstratix_tx_outclk -!s100 7Ehc;dKNXoN52EdTRg6_z1 -Io=_2 -I;;W8:cW1fW[^L6TR6L1cS3 -V`[XhBYMJchCjeXnWloPH;3 -R1 -R2 -R3 -R4 -L0 24852 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vstratixii_lvds_rx -!s100 Ca34DFSRXh3=Nm=hc48Kd2 -R1 -R2 -R3 -R4 -L0 25255 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vstratixii_tx_outclk -!s100 _N5Y173?1@0B9Ja^[LY8W3 -I8R[bcB<`[30^DiQ@3 -V:[2:D[_10ghn[bgc=CD302 -R1 -R2 -R3 -R4 -L0 2106 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vstx_n_cntr -!s100 mKfU[_RDZK3=49RC3I6ZI0 -I:_iK^T6^eS`@8a5]knm@E0 -V4CiQB5Uz?;=OULO:MD>Eo1 -R1 -R2 -R3 -R4 -L0 2184 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vstx_scale_cntr -!s100 f_]QB0V;0;TIAQD8_N^2P1 -I4jaeb7z6F=nQiPX45^]=P2 -VG8KIUm2mDHoX1DjR8TDdJ1 -R1 -R2 -R3 -R4 -L0 2269 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vttn_m_cntr -!s100 he47A??6]3glAN_Ek=XX[3 -IUheCI39Y78=4j?j^`nFhTJL0 -IC28fb1?:IC[DFY>6__0z:0 -VWh8a]<5HCnf>2[=d=L3E[FIMMSj_oTAYj3 -Iee1TLJ@=TzQhJJgS7I9GN2 -VXPfdhMTXDmY9JYEiBjd?Q2 -R1 -R2 -R3 -R4 -L0 10258 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/_vmake b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/_vmake deleted file mode 100644 index 2f7e729..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/_vmake +++ /dev/null @@ -1,3 +0,0 @@ -m255 -K3 -cModel Technology diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/a_graycounter/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/a_graycounter/_primary.dat deleted file mode 100644 index 3aa5865..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/a_graycounter/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/a_graycounter/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/a_graycounter/_primary.dbs deleted file mode 100644 index 673122a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/a_graycounter/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/a_graycounter/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/a_graycounter/_primary.vhd deleted file mode 100644 index fe436a5..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/a_graycounter/_primary.vhd +++ /dev/null @@ -1,25 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity a_graycounter is - generic( - width : integer := 3; - pvalue : integer := 0; - lpm_hint : string := "UNUSED"; - lpm_type : string := "a_graycounter" - ); - port( - clock : in vl_logic; - cnt_en : in vl_logic; - clk_en : in vl_logic; - updown : in vl_logic; - aclr : in vl_logic; - sclr : in vl_logic; - q : out vl_logic_vector; - qbin : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of pvalue : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end a_graycounter; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt3pram/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt3pram/_primary.dat deleted file mode 100644 index 0052215..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt3pram/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt3pram/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt3pram/_primary.dbs deleted file mode 100644 index 4e912a9..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt3pram/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt3pram/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt3pram/_primary.vhd deleted file mode 100644 index a95ae8a..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt3pram/_primary.vhd +++ /dev/null @@ -1,73 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity alt3pram is - generic( - width : integer := 1; - widthad : integer := 1; - numwords : integer := 0; - lpm_file : string := "UNUSED"; - lpm_hint : string := "USE_EAB=ON"; - indata_reg : string := "UNREGISTERED"; - indata_aclr : string := "ON"; - write_reg : string := "UNREGISTERED"; - write_aclr : string := "ON"; - rdaddress_reg_a : string := "UNREGISTERED"; - rdaddress_aclr_a: string := "ON"; - rdcontrol_reg_a : string := "UNREGISTERED"; - rdcontrol_aclr_a: string := "ON"; - rdaddress_reg_b : string := "UNREGISTERED"; - rdaddress_aclr_b: string := "ON"; - rdcontrol_reg_b : string := "UNREGISTERED"; - rdcontrol_aclr_b: string := "ON"; - outdata_reg_a : string := "UNREGISTERED"; - outdata_aclr_a : string := "ON"; - outdata_reg_b : string := "UNREGISTERED"; - outdata_aclr_b : string := "ON"; - intended_device_family: string := "Stratix"; - ram_block_type : string := "AUTO"; - maximum_depth : integer := 0; - lpm_type : string := "alt3pram" - ); - port( - wren : in vl_logic; - data : in vl_logic_vector; - wraddress : in vl_logic_vector; - inclock : in vl_logic; - inclocken : in vl_logic; - rden_a : in vl_logic; - rden_b : in vl_logic; - rdaddress_a : in vl_logic_vector; - rdaddress_b : in vl_logic_vector; - outclock : in vl_logic; - outclocken : in vl_logic; - aclr : in vl_logic; - qa : out vl_logic_vector; - qb : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of widthad : constant is 1; - attribute mti_svvh_generic_type of numwords : constant is 1; - attribute mti_svvh_generic_type of lpm_file : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of indata_reg : constant is 1; - attribute mti_svvh_generic_type of indata_aclr : constant is 1; - attribute mti_svvh_generic_type of write_reg : constant is 1; - attribute mti_svvh_generic_type of write_aclr : constant is 1; - attribute mti_svvh_generic_type of rdaddress_reg_a : constant is 1; - attribute mti_svvh_generic_type of rdaddress_aclr_a : constant is 1; - attribute mti_svvh_generic_type of rdcontrol_reg_a : constant is 1; - attribute mti_svvh_generic_type of rdcontrol_aclr_a : constant is 1; - attribute mti_svvh_generic_type of rdaddress_reg_b : constant is 1; - attribute mti_svvh_generic_type of rdaddress_aclr_b : constant is 1; - attribute mti_svvh_generic_type of rdcontrol_reg_b : constant is 1; - attribute mti_svvh_generic_type of rdcontrol_aclr_b : constant is 1; - attribute mti_svvh_generic_type of outdata_reg_a : constant is 1; - attribute mti_svvh_generic_type of outdata_aclr_a : constant is 1; - attribute mti_svvh_generic_type of outdata_reg_b : constant is 1; - attribute mti_svvh_generic_type of outdata_aclr_b : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of ram_block_type : constant is 1; - attribute mti_svvh_generic_type of maximum_depth : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end alt3pram; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_aeq_s4/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_aeq_s4/_primary.dat deleted file mode 100644 index fb69e27..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_aeq_s4/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_aeq_s4/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_aeq_s4/_primary.dbs deleted file mode 100644 index 0d32d9a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_aeq_s4/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_aeq_s4/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_aeq_s4/_primary.vhd deleted file mode 100644 index ff2c468..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_aeq_s4/_primary.vhd +++ /dev/null @@ -1,50 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity alt_aeq_s4 is - generic( - show_errors : string := "NO"; - radce_hflck : vl_logic_vector(0 to 14) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); - radce_lflck : vl_logic_vector(0 to 14) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); - use_hw_conv_det : vl_logic := Hi0; - number_of_channels: integer := 5; - channel_address_width: integer := 3; - lpm_type : string := "alt_aeq_s4"; - lpm_hint : string := "UNUSED" - ); - port( - reconfig_clk : in vl_logic; - aclr : in vl_logic; - calibrate : in vl_logic; - shutdown : in vl_logic; - all_channels : in vl_logic; - logical_channel_address: in vl_logic_vector; - remap_address : in vl_logic_vector(11 downto 0); - quad_address : out vl_logic_vector(8 downto 0); - adce_done : in vl_logic_vector; - busy : out vl_logic; - adce_standby : out vl_logic_vector; - adce_continuous : in vl_logic; - adce_cal_busy : out vl_logic; - dprio_busy : in vl_logic; - dprio_in : in vl_logic_vector(15 downto 0); - dprio_wren : out vl_logic; - dprio_rden : out vl_logic; - dprio_addr : out vl_logic_vector(15 downto 0); - dprio_data : out vl_logic_vector(15 downto 0); - eqout : out vl_logic_vector(3 downto 0); - timeout : out vl_logic; - testbuses : in vl_logic_vector; - testbus_sels : out vl_logic_vector; - conv_error : out vl_logic_vector; - error : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of show_errors : constant is 1; - attribute mti_svvh_generic_type of radce_hflck : constant is 1; - attribute mti_svvh_generic_type of radce_lflck : constant is 1; - attribute mti_svvh_generic_type of use_hw_conv_det : constant is 1; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of channel_address_width : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; -end alt_aeq_s4; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal/_primary.dat deleted file mode 100644 index b90b77b..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal/_primary.dbs deleted file mode 100644 index 884bc34..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal/_primary.vhd deleted file mode 100644 index 85a88ea..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal/_primary.vhd +++ /dev/null @@ -1,35 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity alt_cal is - generic( - number_of_channels: integer := 1; - channel_address_width: integer := 1; - sim_model_mode : string := "TRUE"; - lpm_type : string := "alt_cal"; - lpm_hint : string := "UNUSED" - ); - port( - busy : out vl_logic; - cal_error : out vl_logic_vector; - clock : in vl_logic; - dprio_addr : out vl_logic_vector(15 downto 0); - dprio_busy : in vl_logic; - dprio_datain : in vl_logic_vector(15 downto 0); - dprio_dataout : out vl_logic_vector(15 downto 0); - dprio_rden : out vl_logic; - dprio_wren : out vl_logic; - quad_addr : out vl_logic_vector(8 downto 0); - remap_addr : in vl_logic_vector(11 downto 0); - reset : in vl_logic; - retain_addr : out vl_logic_vector(0 downto 0); - start : in vl_logic; - transceiver_init: in vl_logic; - testbuses : in vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of channel_address_width : constant is 1; - attribute mti_svvh_generic_type of sim_model_mode : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; -end alt_cal; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_c3gxb/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_c3gxb/_primary.dat deleted file mode 100644 index f7a4fad..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_c3gxb/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_c3gxb/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_c3gxb/_primary.dbs deleted file mode 100644 index 09d346c..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_c3gxb/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_c3gxb/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_c3gxb/_primary.vhd deleted file mode 100644 index 602cd4f..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_c3gxb/_primary.vhd +++ /dev/null @@ -1,34 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity alt_cal_c3gxb is - generic( - number_of_channels: integer := 1; - channel_address_width: integer := 1; - sim_model_mode : string := "TRUE"; - lpm_type : string := "alt_cal_c3gxb"; - lpm_hint : string := "UNUSED" - ); - port( - busy : out vl_logic; - cal_error : out vl_logic_vector; - clock : in vl_logic; - dprio_addr : out vl_logic_vector(15 downto 0); - dprio_busy : in vl_logic; - dprio_datain : in vl_logic_vector(15 downto 0); - dprio_dataout : out vl_logic_vector(15 downto 0); - dprio_rden : out vl_logic; - dprio_wren : out vl_logic; - quad_addr : out vl_logic_vector(8 downto 0); - remap_addr : in vl_logic_vector(11 downto 0); - reset : in vl_logic; - retain_addr : out vl_logic_vector(0 downto 0); - start : in vl_logic; - testbuses : in vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of channel_address_width : constant is 1; - attribute mti_svvh_generic_type of sim_model_mode : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; -end alt_cal_c3gxb; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_mm/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_mm/_primary.dat deleted file mode 100644 index b75b529..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_mm/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_mm/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_mm/_primary.dbs deleted file mode 100644 index 032f7b6..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_mm/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_mm/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_mm/_primary.vhd deleted file mode 100644 index 22bfa83..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_mm/_primary.vhd +++ /dev/null @@ -1,73 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity alt_cal_mm is - generic( - number_of_channels: integer := 1; - channel_address_width: integer := 1; - sim_model_mode : string := "TRUE"; - lpm_type : string := "alt_cal_mm"; - lpm_hint : string := "UNUSED"; - idle : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi0, Hi0); - ch_wait : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi0, Hi1); - testbus_set : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi1, Hi0); - offsets_pden_rd : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi0, Hi1, Hi1); - offsets_pden_wr : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi0, Hi0); - cal_pd_wr : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi0, Hi1); - cal_rx_rd : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi1, Hi0); - cal_rx_wr : vl_logic_vector(0 to 4) := (Hi0, Hi0, Hi1, Hi1, Hi1); - dprio_wait : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi0, Hi0); - sample_tb : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi0, Hi1); - test_input : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi0, Hi1, Hi0); - ch_adv : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi0, Hi0); - dprio_read : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi1, Hi0); - dprio_write : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi1, Hi1); - kick_start_rd : vl_logic_vector(0 to 4) := (Hi0, Hi1, Hi1, Hi0, Hi1); - kick_start_wr : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi0, Hi0); - kick_pause : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi0, Hi1); - kick_delay_oc : vl_logic_vector(0 to 4) := (Hi1, Hi0, Hi0, Hi1, Hi0); - sample_length : vl_logic_vector(0 to 7) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0) - ); - port( - busy : out vl_logic; - cal_error : out vl_logic_vector; - clock : in vl_logic; - dprio_addr : out vl_logic_vector(15 downto 0); - dprio_busy : in vl_logic; - dprio_datain : in vl_logic_vector(15 downto 0); - dprio_dataout : out vl_logic_vector(15 downto 0); - dprio_rden : out vl_logic; - dprio_wren : out vl_logic; - quad_addr : out vl_logic_vector(8 downto 0); - remap_addr : in vl_logic_vector(11 downto 0); - reset : in vl_logic; - retain_addr : out vl_logic_vector(0 downto 0); - start : in vl_logic; - transceiver_init: in vl_logic; - testbuses : in vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of channel_address_width : constant is 1; - attribute mti_svvh_generic_type of sim_model_mode : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of idle : constant is 1; - attribute mti_svvh_generic_type of ch_wait : constant is 1; - attribute mti_svvh_generic_type of testbus_set : constant is 1; - attribute mti_svvh_generic_type of offsets_pden_rd : constant is 1; - attribute mti_svvh_generic_type of offsets_pden_wr : constant is 1; - attribute mti_svvh_generic_type of cal_pd_wr : constant is 1; - attribute mti_svvh_generic_type of cal_rx_rd : constant is 1; - attribute mti_svvh_generic_type of cal_rx_wr : constant is 1; - attribute mti_svvh_generic_type of dprio_wait : constant is 1; - attribute mti_svvh_generic_type of sample_tb : constant is 1; - attribute mti_svvh_generic_type of test_input : constant is 1; - attribute mti_svvh_generic_type of ch_adv : constant is 1; - attribute mti_svvh_generic_type of dprio_read : constant is 1; - attribute mti_svvh_generic_type of dprio_write : constant is 1; - attribute mti_svvh_generic_type of kick_start_rd : constant is 1; - attribute mti_svvh_generic_type of kick_start_wr : constant is 1; - attribute mti_svvh_generic_type of kick_pause : constant is 1; - attribute mti_svvh_generic_type of kick_delay_oc : constant is 1; - attribute mti_svvh_generic_type of sample_length : constant is 1; -end alt_cal_mm; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_sv/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_sv/_primary.dat deleted file mode 100644 index 9df311a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_sv/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_sv/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_sv/_primary.dbs deleted file mode 100644 index e0af500..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_sv/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_sv/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_sv/_primary.vhd deleted file mode 100644 index 3998ad2..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_cal_sv/_primary.vhd +++ /dev/null @@ -1,36 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity alt_cal_sv is - generic( - number_of_channels: integer := 1; - channel_address_width: integer := 1; - sim_model_mode : string := "TRUE"; - lpm_type : string := "alt_cal_sv"; - lpm_hint : string := "UNUSED"; - sample_length : vl_logic_vector(0 to 7) := (Hi0, Hi1, Hi1, Hi0, Hi0, Hi1, Hi0, Hi0); - pma_base_address: vl_logic_vector(0 to 11) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0) - ); - port( - busy : out vl_logic; - clock : in vl_logic; - dprio_addr : out vl_logic_vector(15 downto 0); - dprio_busy : in vl_logic; - dprio_datain : in vl_logic_vector(15 downto 0); - dprio_dataout : out vl_logic_vector(15 downto 0); - dprio_rden : out vl_logic; - dprio_wren : out vl_logic; - quad_addr : out vl_logic_vector(8 downto 0); - remap_addr : in vl_logic_vector(11 downto 0); - reset : in vl_logic; - start : in vl_logic; - testbuses : in vl_logic_vector(7 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of channel_address_width : constant is 1; - attribute mti_svvh_generic_type of sim_model_mode : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of sample_length : constant is 1; - attribute mti_svvh_generic_type of pma_base_address : constant is 1; -end alt_cal_sv; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_dfe/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_dfe/_primary.dat deleted file mode 100644 index df8c163..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_dfe/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_dfe/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_dfe/_primary.dbs deleted file mode 100644 index 8e1e440..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_dfe/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_dfe/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_dfe/_primary.vhd deleted file mode 100644 index e995828..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_dfe/_primary.vhd +++ /dev/null @@ -1,60 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity alt_dfe is - generic( - channel_address_width: integer := 3; - lpm_type : string := "alt_dfe"; - lpm_hint : string := "UNUSED"; - avmm_slave_addr_width: integer := 16; - avmm_slave_rdata_width: integer := 16; - avmm_slave_wdata_width: integer := 16; - avmm_master_addr_width: integer := 16; - avmm_master_rdata_width: integer := 16; - avmm_master_wdata_width: integer := 16; - dprio_addr_width: integer := 16; - dprio_data_width: integer := 16; - ireg_chaddr_width: vl_notype; - ireg_wdaddr_width: integer := 2; - ireg_data_width : integer := 16; - ST_IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0); - ST_WRITE : vl_logic_vector(0 to 1) := (Hi0, Hi1); - ST_READ : vl_logic_vector(0 to 1) := (Hi1, Hi0) - ); - port( - i_resetn : in vl_logic; - i_avmm_clk : in vl_logic; - i_avmm_saddress : in vl_logic_vector; - i_avmm_sread : in vl_logic; - i_avmm_swrite : in vl_logic; - i_avmm_swritedata: in vl_logic_vector; - o_avmm_sreaddata: out vl_logic_vector; - o_avmm_swaitrequest: out vl_logic; - i_remap_address : in vl_logic_vector(11 downto 0); - o_quad_address : out vl_logic_vector(8 downto 0); - o_reconfig_busy : out vl_logic; - i_dprio_busy : in vl_logic; - i_dprio_in : in vl_logic_vector; - o_dprio_wren : out vl_logic; - o_dprio_rden : out vl_logic; - o_dprio_addr : out vl_logic_vector; - o_dprio_data : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of channel_address_width : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of avmm_slave_addr_width : constant is 1; - attribute mti_svvh_generic_type of avmm_slave_rdata_width : constant is 1; - attribute mti_svvh_generic_type of avmm_slave_wdata_width : constant is 1; - attribute mti_svvh_generic_type of avmm_master_addr_width : constant is 1; - attribute mti_svvh_generic_type of avmm_master_rdata_width : constant is 1; - attribute mti_svvh_generic_type of avmm_master_wdata_width : constant is 1; - attribute mti_svvh_generic_type of dprio_addr_width : constant is 1; - attribute mti_svvh_generic_type of dprio_data_width : constant is 1; - attribute mti_svvh_generic_type of ireg_chaddr_width : constant is 3; - attribute mti_svvh_generic_type of ireg_wdaddr_width : constant is 1; - attribute mti_svvh_generic_type of ireg_data_width : constant is 1; - attribute mti_svvh_generic_type of ST_IDLE : constant is 1; - attribute mti_svvh_generic_type of ST_WRITE : constant is 1; - attribute mti_svvh_generic_type of ST_READ : constant is 1; -end alt_dfe; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_eyemon/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_eyemon/_primary.dat deleted file mode 100644 index 2d009d3..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_eyemon/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_eyemon/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_eyemon/_primary.dbs deleted file mode 100644 index 17fd47b..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_eyemon/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_eyemon/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_eyemon/_primary.vhd deleted file mode 100644 index f24a31a..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/alt_eyemon/_primary.vhd +++ /dev/null @@ -1,61 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity alt_eyemon is - generic( - channel_address_width: integer := 3; - lpm_type : string := "alt_eyemon"; - lpm_hint : string := "UNUSED"; - avmm_slave_addr_width: integer := 16; - avmm_slave_rdata_width: integer := 16; - avmm_slave_wdata_width: integer := 16; - avmm_master_addr_width: integer := 16; - avmm_master_rdata_width: integer := 16; - avmm_master_wdata_width: integer := 16; - dprio_addr_width: integer := 16; - dprio_data_width: integer := 16; - ireg_chaddr_width: vl_notype; - ireg_wdaddr_width: integer := 2; - ireg_data_width : integer := 16; - ST_IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0); - ST_WRITE : vl_logic_vector(0 to 1) := (Hi0, Hi1); - ST_READ : vl_logic_vector(0 to 1) := (Hi1, Hi0) - ); - port( - i_resetn : in vl_logic; - i_avmm_clk : in vl_logic; - i_avmm_saddress : in vl_logic_vector; - i_avmm_sread : in vl_logic; - i_avmm_swrite : in vl_logic; - i_avmm_swritedata: in vl_logic_vector; - o_avmm_sreaddata: out vl_logic_vector; - o_avmm_swaitrequest: out vl_logic; - i_remap_phase : in vl_logic; - i_remap_address : in vl_logic_vector(11 downto 0); - o_quad_address : out vl_logic_vector(8 downto 0); - o_reconfig_busy : out vl_logic; - i_dprio_busy : in vl_logic; - i_dprio_in : in vl_logic_vector; - o_dprio_wren : out vl_logic; - o_dprio_rden : out vl_logic; - o_dprio_addr : out vl_logic_vector; - o_dprio_data : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of channel_address_width : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of avmm_slave_addr_width : constant is 1; - attribute mti_svvh_generic_type of avmm_slave_rdata_width : constant is 1; - attribute mti_svvh_generic_type of avmm_slave_wdata_width : constant is 1; - attribute mti_svvh_generic_type of avmm_master_addr_width : constant is 1; - attribute mti_svvh_generic_type of avmm_master_rdata_width : constant is 1; - attribute mti_svvh_generic_type of avmm_master_wdata_width : constant is 1; - attribute mti_svvh_generic_type of dprio_addr_width : constant is 1; - attribute mti_svvh_generic_type of dprio_data_width : constant is 1; - attribute mti_svvh_generic_type of ireg_chaddr_width : constant is 3; - attribute mti_svvh_generic_type of ireg_wdaddr_width : constant is 1; - attribute mti_svvh_generic_type of ireg_data_width : constant is 1; - attribute mti_svvh_generic_type of ST_IDLE : constant is 1; - attribute mti_svvh_generic_type of ST_WRITE : constant is 1; - attribute mti_svvh_generic_type of ST_READ : constant is 1; -end alt_eyemon; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altaccumulate/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altaccumulate/_primary.dat deleted file mode 100644 index 9f5e49c..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altaccumulate/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altaccumulate/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altaccumulate/_primary.dbs deleted file mode 100644 index 9446ee7..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altaccumulate/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altaccumulate/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altaccumulate/_primary.vhd deleted file mode 100644 index 5176d4d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altaccumulate/_primary.vhd +++ /dev/null @@ -1,34 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altaccumulate is - generic( - width_in : integer := 4; - width_out : integer := 8; - lpm_representation: string := "UNSIGNED"; - extra_latency : integer := 0; - use_wys : string := "ON"; - lpm_hint : string := "UNUSED"; - lpm_type : string := "altaccumulate" - ); - port( - cin : in vl_logic; - data : in vl_logic_vector; - add_sub : in vl_logic; - clock : in vl_logic; - sload : in vl_logic; - clken : in vl_logic; - sign_data : in vl_logic; - aclr : in vl_logic; - result : out vl_logic_vector; - cout : out vl_logic; - overflow : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_in : constant is 1; - attribute mti_svvh_generic_type of width_out : constant is 1; - attribute mti_svvh_generic_type of lpm_representation : constant is 1; - attribute mti_svvh_generic_type of extra_latency : constant is 1; - attribute mti_svvh_generic_type of use_wys : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end altaccumulate; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altclklock/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altclklock/_primary.dat deleted file mode 100644 index 15349dd..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altclklock/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altclklock/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altclklock/_primary.dbs deleted file mode 100644 index 434c1ca..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altclklock/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altclklock/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altclklock/_primary.vhd deleted file mode 100644 index ef88daf..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altclklock/_primary.vhd +++ /dev/null @@ -1,71 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altclklock is - generic( - inclock_period : integer := 10000; - inclock_settings: string := "UNUSED"; - valid_lock_cycles: integer := 5; - invalid_lock_cycles: integer := 5; - valid_lock_multiplier: integer := 5; - invalid_lock_multiplier: integer := 5; - operation_mode : string := "NORMAL"; - clock0_boost : integer := 1; - clock0_divide : integer := 1; - clock0_settings : string := "UNUSED"; - clock0_time_delay: string := "0"; - clock1_boost : integer := 1; - clock1_divide : integer := 1; - clock1_settings : string := "UNUSED"; - clock1_time_delay: string := "0"; - clock2_boost : integer := 1; - clock2_divide : integer := 1; - clock2_settings : string := "UNUSED"; - clock2_time_delay: string := "0"; - clock_ext_boost : integer := 1; - clock_ext_divide: integer := 1; - clock_ext_settings: string := "UNUSED"; - clock_ext_time_delay: string := "0"; - outclock_phase_shift: integer := 0; - intended_device_family: string := "Stratix"; - lpm_type : string := "altclklock"; - lpm_hint : string := "UNUSED" - ); - port( - inclock : in vl_logic; - inclocken : in vl_logic; - fbin : in vl_logic; - clock0 : out vl_logic; - clock1 : out vl_logic; - clock2 : out vl_logic; - clock_ext : out vl_logic; - locked : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of inclock_period : constant is 1; - attribute mti_svvh_generic_type of inclock_settings : constant is 1; - attribute mti_svvh_generic_type of valid_lock_cycles : constant is 1; - attribute mti_svvh_generic_type of invalid_lock_cycles : constant is 1; - attribute mti_svvh_generic_type of valid_lock_multiplier : constant is 1; - attribute mti_svvh_generic_type of invalid_lock_multiplier : constant is 1; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of clock0_boost : constant is 1; - attribute mti_svvh_generic_type of clock0_divide : constant is 1; - attribute mti_svvh_generic_type of clock0_settings : constant is 1; - attribute mti_svvh_generic_type of clock0_time_delay : constant is 1; - attribute mti_svvh_generic_type of clock1_boost : constant is 1; - attribute mti_svvh_generic_type of clock1_divide : constant is 1; - attribute mti_svvh_generic_type of clock1_settings : constant is 1; - attribute mti_svvh_generic_type of clock1_time_delay : constant is 1; - attribute mti_svvh_generic_type of clock2_boost : constant is 1; - attribute mti_svvh_generic_type of clock2_divide : constant is 1; - attribute mti_svvh_generic_type of clock2_settings : constant is 1; - attribute mti_svvh_generic_type of clock2_time_delay : constant is 1; - attribute mti_svvh_generic_type of clock_ext_boost : constant is 1; - attribute mti_svvh_generic_type of clock_ext_divide : constant is 1; - attribute mti_svvh_generic_type of clock_ext_settings : constant is 1; - attribute mti_svvh_generic_type of clock_ext_time_delay : constant is 1; - attribute mti_svvh_generic_type of outclock_phase_shift : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; -end altclklock; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_bidir/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_bidir/_primary.dat deleted file mode 100644 index 6396c4a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_bidir/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_bidir/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_bidir/_primary.dbs deleted file mode 100644 index b1b8e16..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_bidir/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_bidir/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_bidir/_primary.vhd deleted file mode 100644 index 93a16d4..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_bidir/_primary.vhd +++ /dev/null @@ -1,44 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altddio_bidir is - generic( - width : integer := 1; - power_up_high : string := "OFF"; - oe_reg : string := "UNUSED"; - extend_oe_disable: string := "UNUSED"; - implement_input_in_lcell: string := "UNUSED"; - invert_output : string := "OFF"; - intended_device_family: string := "Stratix"; - lpm_type : string := "altddio_bidir"; - lpm_hint : string := "UNUSED" - ); - port( - datain_h : in vl_logic_vector; - datain_l : in vl_logic_vector; - inclock : in vl_logic; - inclocken : in vl_logic; - outclock : in vl_logic; - outclocken : in vl_logic; - aset : in vl_logic; - aclr : in vl_logic; - sset : in vl_logic; - sclr : in vl_logic; - oe : in vl_logic; - dataout_h : out vl_logic_vector; - dataout_l : out vl_logic_vector; - combout : out vl_logic_vector; - oe_out : out vl_logic_vector; - dqsundelayedout : out vl_logic_vector; - padio : inout vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of power_up_high : constant is 1; - attribute mti_svvh_generic_type of oe_reg : constant is 1; - attribute mti_svvh_generic_type of extend_oe_disable : constant is 1; - attribute mti_svvh_generic_type of implement_input_in_lcell : constant is 1; - attribute mti_svvh_generic_type of invert_output : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; -end altddio_bidir; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_in/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_in/_primary.dat deleted file mode 100644 index f16f611..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_in/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_in/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_in/_primary.dbs deleted file mode 100644 index abb5b65..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_in/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_in/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_in/_primary.vhd deleted file mode 100644 index b2f58e7..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_in/_primary.vhd +++ /dev/null @@ -1,30 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altddio_in is - generic( - width : integer := 1; - power_up_high : string := "OFF"; - invert_input_clocks: string := "OFF"; - intended_device_family: string := "Stratix"; - lpm_type : string := "altddio_in"; - lpm_hint : string := "UNUSED" - ); - port( - datain : in vl_logic_vector; - inclock : in vl_logic; - inclocken : in vl_logic; - aset : in vl_logic; - aclr : in vl_logic; - sset : in vl_logic; - sclr : in vl_logic; - dataout_h : out vl_logic_vector; - dataout_l : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of power_up_high : constant is 1; - attribute mti_svvh_generic_type of invert_input_clocks : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; -end altddio_in; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_out/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_out/_primary.dat deleted file mode 100644 index 857679f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_out/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_out/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_out/_primary.dbs deleted file mode 100644 index ff028fb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_out/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_out/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_out/_primary.vhd deleted file mode 100644 index 0f93c66..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altddio_out/_primary.vhd +++ /dev/null @@ -1,37 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altddio_out is - generic( - width : integer := 1; - power_up_high : string := "OFF"; - oe_reg : string := "UNUSED"; - extend_oe_disable: string := "UNUSED"; - intended_device_family: string := "Stratix"; - invert_output : string := "OFF"; - lpm_type : string := "altddio_out"; - lpm_hint : string := "UNUSED" - ); - port( - datain_h : in vl_logic_vector; - datain_l : in vl_logic_vector; - outclock : in vl_logic; - outclocken : in vl_logic; - aset : in vl_logic; - aclr : in vl_logic; - sset : in vl_logic; - sclr : in vl_logic; - oe : in vl_logic; - hrbypass : in vl_logic; - dataout : out vl_logic_vector; - oe_out : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of power_up_high : constant is 1; - attribute mti_svvh_generic_type of oe_reg : constant is 1; - attribute mti_svvh_generic_type of extend_oe_disable : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of invert_output : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; -end altddio_out; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altdpram/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altdpram/_primary.dat deleted file mode 100644 index 60cbf10..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altdpram/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altdpram/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altdpram/_primary.dbs deleted file mode 100644 index ad8431a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altdpram/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altdpram/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altdpram/_primary.vhd deleted file mode 100644 index 7f37cef..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altdpram/_primary.vhd +++ /dev/null @@ -1,83 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altdpram is - generic( - width : integer := 1; - widthad : integer := 1; - numwords : integer := 0; - lpm_file : string := "UNUSED"; - lpm_hint : string := "USE_EAB=ON"; - use_eab : string := "ON"; - lpm_type : string := "altdpram"; - indata_reg : string := "INCLOCK"; - indata_aclr : string := "ON"; - wraddress_reg : string := "INCLOCK"; - wraddress_aclr : string := "ON"; - wrcontrol_reg : string := "INCLOCK"; - wrcontrol_aclr : string := "ON"; - rdaddress_reg : string := "OUTCLOCK"; - rdaddress_aclr : string := "ON"; - rdcontrol_reg : string := "OUTCLOCK"; - rdcontrol_aclr : string := "ON"; - outdata_reg : string := "UNREGISTERED"; - outdata_aclr : string := "ON"; - maximum_depth : integer := 2048; - intended_device_family: string := "Stratix"; - ram_block_type : string := "AUTO"; - width_byteena : integer := 1; - byte_size : integer := 0; - read_during_write_mode_mixed_ports: string := "DONT_CARE"; - i_byte_size : vl_notype; - is_lutram : vl_notype; - i_width_byteena : vl_notype; - i_read_during_write: vl_notype; - write_at_low_clock: vl_notype - ); - port( - wren : in vl_logic; - data : in vl_logic_vector; - wraddress : in vl_logic_vector; - inclock : in vl_logic; - inclocken : in vl_logic; - rden : in vl_logic; - rdaddress : in vl_logic_vector; - wraddressstall : in vl_logic; - rdaddressstall : in vl_logic; - byteena : in vl_logic_vector; - outclock : in vl_logic; - outclocken : in vl_logic; - aclr : in vl_logic; - q : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of widthad : constant is 1; - attribute mti_svvh_generic_type of numwords : constant is 1; - attribute mti_svvh_generic_type of lpm_file : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of use_eab : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of indata_reg : constant is 1; - attribute mti_svvh_generic_type of indata_aclr : constant is 1; - attribute mti_svvh_generic_type of wraddress_reg : constant is 1; - attribute mti_svvh_generic_type of wraddress_aclr : constant is 1; - attribute mti_svvh_generic_type of wrcontrol_reg : constant is 1; - attribute mti_svvh_generic_type of wrcontrol_aclr : constant is 1; - attribute mti_svvh_generic_type of rdaddress_reg : constant is 1; - attribute mti_svvh_generic_type of rdaddress_aclr : constant is 1; - attribute mti_svvh_generic_type of rdcontrol_reg : constant is 1; - attribute mti_svvh_generic_type of rdcontrol_aclr : constant is 1; - attribute mti_svvh_generic_type of outdata_reg : constant is 1; - attribute mti_svvh_generic_type of outdata_aclr : constant is 1; - attribute mti_svvh_generic_type of maximum_depth : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of ram_block_type : constant is 1; - attribute mti_svvh_generic_type of width_byteena : constant is 1; - attribute mti_svvh_generic_type of byte_size : constant is 1; - attribute mti_svvh_generic_type of read_during_write_mode_mixed_ports : constant is 1; - attribute mti_svvh_generic_type of i_byte_size : constant is 3; - attribute mti_svvh_generic_type of is_lutram : constant is 3; - attribute mti_svvh_generic_type of i_width_byteena : constant is 3; - attribute mti_svvh_generic_type of i_read_during_write : constant is 3; - attribute mti_svvh_generic_type of write_at_low_clock : constant is 3; -end altdpram; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer/_primary.dat deleted file mode 100644 index 538ae13..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer/_primary.dbs deleted file mode 100644 index b5ca071..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer/_primary.vhd deleted file mode 100644 index 595de75..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer/_primary.vhd +++ /dev/null @@ -1,15 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altera_std_synchronizer is - generic( - depth : integer := 3 - ); - port( - clk : in vl_logic; - reset_n : in vl_logic; - din : in vl_logic; - dout : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of depth : constant is 1; -end altera_std_synchronizer; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer_bundle/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer_bundle/_primary.dat deleted file mode 100644 index 1d756dd..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer_bundle/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer_bundle/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer_bundle/_primary.dbs deleted file mode 100644 index 22a0c76..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer_bundle/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer_bundle/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer_bundle/_primary.vhd deleted file mode 100644 index 390dcf1..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altera_std_synchronizer_bundle/_primary.vhd +++ /dev/null @@ -1,17 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altera_std_synchronizer_bundle is - generic( - width : integer := 1; - depth : integer := 3 - ); - port( - clk : in vl_logic; - reset_n : in vl_logic; - din : in vl_logic_vector; - dout : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of depth : constant is 1; -end altera_std_synchronizer_bundle; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altfp_mult/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altfp_mult/_primary.dat deleted file mode 100644 index 2043abf..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altfp_mult/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altfp_mult/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altfp_mult/_primary.dbs deleted file mode 100644 index 57a35f8..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altfp_mult/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altfp_mult/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altfp_mult/_primary.vhd deleted file mode 100644 index 21ad578..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altfp_mult/_primary.vhd +++ /dev/null @@ -1,43 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altfp_mult is - generic( - width_exp : integer := 8; - width_man : integer := 23; - dedicated_multiplier_circuitry: string := "AUTO"; - reduced_functionality: string := "NO"; - pipeline : integer := 5; - denormal_support: string := "YES"; - exception_handling: string := "YES"; - lpm_hint : string := "UNUSED"; - lpm_type : string := "altfp_mult"; - LATENCY : vl_notype; - WIDTH_MAN_EXP : vl_notype - ); - port( - clock : in vl_logic; - clk_en : in vl_logic; - aclr : in vl_logic; - dataa : in vl_logic_vector; - datab : in vl_logic_vector; - result : out vl_logic_vector; - overflow : out vl_logic; - underflow : out vl_logic; - zero : out vl_logic; - denormal : out vl_logic; - indefinite : out vl_logic; - nan : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_exp : constant is 1; - attribute mti_svvh_generic_type of width_man : constant is 1; - attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1; - attribute mti_svvh_generic_type of reduced_functionality : constant is 1; - attribute mti_svvh_generic_type of pipeline : constant is 1; - attribute mti_svvh_generic_type of denormal_support : constant is 1; - attribute mti_svvh_generic_type of exception_handling : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of LATENCY : constant is 3; - attribute mti_svvh_generic_type of WIDTH_MAN_EXP : constant is 3; -end altfp_mult; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_rx/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_rx/_primary.dat deleted file mode 100644 index 651c2a1..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_rx/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_rx/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_rx/_primary.dbs deleted file mode 100644 index 574203a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_rx/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_rx/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_rx/_primary.vhd deleted file mode 100644 index 6ffff1e..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_rx/_primary.vhd +++ /dev/null @@ -1,185 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altlvds_rx is - generic( - number_of_channels: integer := 1; - deserialization_factor: integer := 4; - registered_output: string := "ON"; - inclock_period : integer := 10000; - inclock_boost : vl_notype; - cds_mode : string := "UNUSED"; - intended_device_family: string := "Stratix"; - input_data_rate : integer := 0; - inclock_data_alignment: string := "UNUSED"; - registered_data_align_input: string := "ON"; - common_rx_tx_pll: string := "ON"; - enable_dpa_mode : string := "OFF"; - enable_dpa_calibration: string := "ON"; - enable_dpa_pll_calibration: string := "OFF"; - enable_dpa_fifo : string := "ON"; - use_dpll_rawperror: string := "OFF"; - use_coreclock_input: string := "OFF"; - dpll_lock_count : integer := 0; - dpll_lock_window: integer := 0; - outclock_resource: string := "AUTO"; - data_align_rollover: vl_notype; - lose_lock_on_one_change: string := "OFF"; - reset_fifo_at_first_lock: string := "ON"; - use_external_pll: string := "OFF"; - implement_in_les: string := "OFF"; - buffer_implementation: string := "RAM"; - port_rx_data_align: string := "PORT_CONNECTIVITY"; - port_rx_channel_data_align: string := "PORT_CONNECTIVITY"; - pll_operation_mode: string := "NORMAL"; - x_on_bitslip : string := "ON"; - use_no_phase_shift: string := "ON"; - rx_align_data_reg: string := "RISING_EDGE"; - inclock_phase_shift: integer := 0; - enable_soft_cdr_mode: string := "OFF"; - sim_dpa_output_clock_phase_shift: integer := 0; - sim_dpa_is_negative_ppm_drift: string := "OFF"; - sim_dpa_net_ppm_variation: integer := 0; - enable_dpa_align_to_rising_edge_only: string := "OFF"; - enable_dpa_initial_phase_selection: string := "OFF"; - dpa_initial_phase_value: integer := 0; - pll_self_reset_on_loss_lock: string := "OFF"; - refclk_frequency: string := "UNUSED"; - data_rate : string := "UNUSED"; - lpm_hint : string := "UNUSED"; - lpm_type : string := "altlvds_rx"; - clk_src_is_pll : string := "off"; - STRATIX_RX_STYLE: vl_notype; - STRATIXGX_DPA_RX_STYLE: vl_notype; - STRATIXII_RX_STYLE: vl_notype; - CYCLONE_RX_STYLE: vl_notype; - CYCLONEII_RX_STYLE: vl_notype; - STRATIXIII_RX_STYLE: vl_notype; - ARRIAII_RX_STYLE: vl_notype; - STRATIXV_RX_STYLE: vl_notype; - CYCLONEIII_RX_STYLE: vl_notype; - FAMILY_HAS_FLEXIBLE_LVDS: vl_notype; - FAMILY_HAS_STRATIX_STYLE_PLL: vl_notype; - FAMILY_HAS_STRATIXII_STYLE_PLL: vl_notype; - FAMILY_HAS_STRATIXIII_STYLE_PLL: vl_notype; - INT_CLOCK_BOOST : vl_notype; - PLL_M_VALUE : vl_notype; - PLL_D_VALUE : vl_notype; - STRATIX_INCLOCK_BOOST: vl_notype; - PHASE_SHIFT : vl_notype; - STXII_PHASE_SHIFT: vl_notype; - STXII_LE_PHASE_SHIFT: vl_notype; - STXIII_LE_PHASE_SHIFT: vl_notype; - REGISTER_WIDTH : vl_notype; - CLOCK_PERIOD : vl_notype; - FAST_CLK_ENA_PHASE_SHIFT: vl_notype; - use_dpa_calibration: vl_notype - ); - port( - rx_in : in vl_logic_vector; - rx_inclock : in vl_logic; - rx_syncclock : in vl_logic; - rx_dpaclock : in vl_logic; - rx_readclock : in vl_logic; - rx_enable : in vl_logic; - rx_deskew : in vl_logic; - rx_pll_enable : in vl_logic; - rx_data_align : in vl_logic; - rx_data_align_reset: in vl_logic; - rx_reset : in vl_logic_vector; - rx_dpll_reset : in vl_logic_vector; - rx_dpll_hold : in vl_logic_vector; - rx_dpll_enable : in vl_logic_vector; - rx_fifo_reset : in vl_logic_vector; - rx_channel_data_align: in vl_logic_vector; - rx_cda_reset : in vl_logic_vector; - rx_coreclk : in vl_logic_vector; - pll_areset : in vl_logic; - pll_phasedone : in vl_logic; - dpa_pll_recal : in vl_logic; - rx_dpa_lock_reset: in vl_logic_vector; - rx_out : out vl_logic_vector; - rx_outclock : out vl_logic; - rx_locked : out vl_logic; - rx_dpa_locked : out vl_logic_vector; - rx_cda_max : out vl_logic_vector; - rx_divfwdclk : out vl_logic_vector; - pll_phasestep : out vl_logic; - pll_phaseupdown : out vl_logic; - pll_phasecounterselect: out vl_logic_vector(3 downto 0); - pll_scanclk : out vl_logic; - dpa_pll_cal_busy: out vl_logic; - rx_data_reset : in vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of registered_output : constant is 1; - attribute mti_svvh_generic_type of inclock_period : constant is 1; - attribute mti_svvh_generic_type of inclock_boost : constant is 3; - attribute mti_svvh_generic_type of cds_mode : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of input_data_rate : constant is 1; - attribute mti_svvh_generic_type of inclock_data_alignment : constant is 1; - attribute mti_svvh_generic_type of registered_data_align_input : constant is 1; - attribute mti_svvh_generic_type of common_rx_tx_pll : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_mode : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_calibration : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_pll_calibration : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_fifo : constant is 1; - attribute mti_svvh_generic_type of use_dpll_rawperror : constant is 1; - attribute mti_svvh_generic_type of use_coreclock_input : constant is 1; - attribute mti_svvh_generic_type of dpll_lock_count : constant is 1; - attribute mti_svvh_generic_type of dpll_lock_window : constant is 1; - attribute mti_svvh_generic_type of outclock_resource : constant is 1; - attribute mti_svvh_generic_type of data_align_rollover : constant is 3; - attribute mti_svvh_generic_type of lose_lock_on_one_change : constant is 1; - attribute mti_svvh_generic_type of reset_fifo_at_first_lock : constant is 1; - attribute mti_svvh_generic_type of use_external_pll : constant is 1; - attribute mti_svvh_generic_type of implement_in_les : constant is 1; - attribute mti_svvh_generic_type of buffer_implementation : constant is 1; - attribute mti_svvh_generic_type of port_rx_data_align : constant is 1; - attribute mti_svvh_generic_type of port_rx_channel_data_align : constant is 1; - attribute mti_svvh_generic_type of pll_operation_mode : constant is 1; - attribute mti_svvh_generic_type of x_on_bitslip : constant is 1; - attribute mti_svvh_generic_type of use_no_phase_shift : constant is 1; - attribute mti_svvh_generic_type of rx_align_data_reg : constant is 1; - attribute mti_svvh_generic_type of inclock_phase_shift : constant is 1; - attribute mti_svvh_generic_type of enable_soft_cdr_mode : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_output_clock_phase_shift : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_is_negative_ppm_drift : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_net_ppm_variation : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_align_to_rising_edge_only : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_initial_phase_selection : constant is 1; - attribute mti_svvh_generic_type of dpa_initial_phase_value : constant is 1; - attribute mti_svvh_generic_type of pll_self_reset_on_loss_lock : constant is 1; - attribute mti_svvh_generic_type of refclk_frequency : constant is 1; - attribute mti_svvh_generic_type of data_rate : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of clk_src_is_pll : constant is 1; - attribute mti_svvh_generic_type of STRATIX_RX_STYLE : constant is 3; - attribute mti_svvh_generic_type of STRATIXGX_DPA_RX_STYLE : constant is 3; - attribute mti_svvh_generic_type of STRATIXII_RX_STYLE : constant is 3; - attribute mti_svvh_generic_type of CYCLONE_RX_STYLE : constant is 3; - attribute mti_svvh_generic_type of CYCLONEII_RX_STYLE : constant is 3; - attribute mti_svvh_generic_type of STRATIXIII_RX_STYLE : constant is 3; - attribute mti_svvh_generic_type of ARRIAII_RX_STYLE : constant is 3; - attribute mti_svvh_generic_type of STRATIXV_RX_STYLE : constant is 3; - attribute mti_svvh_generic_type of CYCLONEIII_RX_STYLE : constant is 3; - attribute mti_svvh_generic_type of FAMILY_HAS_FLEXIBLE_LVDS : constant is 3; - attribute mti_svvh_generic_type of FAMILY_HAS_STRATIX_STYLE_PLL : constant is 3; - attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXII_STYLE_PLL : constant is 3; - attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXIII_STYLE_PLL : constant is 3; - attribute mti_svvh_generic_type of INT_CLOCK_BOOST : constant is 3; - attribute mti_svvh_generic_type of PLL_M_VALUE : constant is 3; - attribute mti_svvh_generic_type of PLL_D_VALUE : constant is 3; - attribute mti_svvh_generic_type of STRATIX_INCLOCK_BOOST : constant is 3; - attribute mti_svvh_generic_type of PHASE_SHIFT : constant is 3; - attribute mti_svvh_generic_type of STXII_PHASE_SHIFT : constant is 3; - attribute mti_svvh_generic_type of STXII_LE_PHASE_SHIFT : constant is 3; - attribute mti_svvh_generic_type of STXIII_LE_PHASE_SHIFT : constant is 3; - attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3; - attribute mti_svvh_generic_type of CLOCK_PERIOD : constant is 3; - attribute mti_svvh_generic_type of FAST_CLK_ENA_PHASE_SHIFT : constant is 3; - attribute mti_svvh_generic_type of use_dpa_calibration : constant is 3; -end altlvds_rx; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_tx/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_tx/_primary.dat deleted file mode 100644 index 3ad93a2..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_tx/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_tx/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_tx/_primary.dbs deleted file mode 100644 index abc47ff..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_tx/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_tx/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_tx/_primary.vhd deleted file mode 100644 index 4eb3808..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altlvds_tx/_primary.vhd +++ /dev/null @@ -1,139 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altlvds_tx is - generic( - number_of_channels: integer := 1; - deserialization_factor: integer := 4; - registered_input: string := "ON"; - multi_clock : string := "OFF"; - inclock_period : integer := 10000; - outclock_divide_by: vl_notype; - inclock_boost : vl_notype; - center_align_msb: string := "OFF"; - intended_device_family: string := "Stratix"; - output_data_rate: integer := 0; - inclock_data_alignment: string := "EDGE_ALIGNED"; - outclock_alignment: string := "EDGE_ALIGNED"; - common_rx_tx_pll: string := "ON"; - outclock_resource: string := "AUTO"; - use_external_pll: string := "OFF"; - implement_in_les: string := "OFF"; - preemphasis_setting: integer := 0; - vod_setting : integer := 0; - differential_drive: integer := 0; - outclock_multiply_by: integer := 1; - coreclock_divide_by: integer := 2; - outclock_duty_cycle: integer := 50; - inclock_phase_shift: integer := 0; - outclock_phase_shift: integer := 0; - use_no_phase_shift: string := "ON"; - pll_self_reset_on_loss_lock: string := "OFF"; - refclk_frequency: string := "UNUSED"; - data_rate : string := "UNUSED"; - lpm_type : string := "altlvds_tx"; - lpm_hint : string := "UNUSED"; - clk_src_is_pll : string := "off"; - STRATIX_TX_STYLE: vl_notype; - STRATIXII_TX_STYLE: vl_notype; - CYCLONE_TX_STYLE: vl_notype; - CYCLONEII_TX_STYLE: vl_notype; - STRATIXIII_TX_STYLE: vl_notype; - CYCLONEIII_TX_STYLE: vl_notype; - MAXV_TX_STYLE : vl_notype; - FAMILY_HAS_FLEXIBLE_LVDS: vl_notype; - FAMILY_HAS_STRATIX_STYLE_PLL: vl_notype; - FAMILY_HAS_STRATIXII_STYLE_PLL: vl_notype; - FAMILY_HAS_STRATIXIII_STYLE_PLL: vl_notype; - INT_CLOCK_BOOST : vl_notype; - PLL_M_VALUE : vl_notype; - PLL_D_VALUE : vl_notype; - STRATIX_INCLOCK_BOOST: vl_notype; - PHASE_INCLOCK : vl_notype; - STXII_PHASE_INCLOCK: vl_notype; - PHASE_OUTCLOCK : vl_notype; - STX_PHASE_OUTCLOCK: vl_notype; - STXII_PHASE_OUTCLOCK: vl_notype; - STXII_LE_PHASE_INCLOCK: vl_notype; - STXII_LE_PHASE_OUTCLOCK: vl_notype; - STXIII_LE_PHASE_INCLOCK: vl_notype; - STXIII_LE_PHASE_OUTCLOCK: vl_notype; - REGISTER_WIDTH : vl_notype; - FAST_CLK_ENA_PHASE_SHIFT: vl_notype; - CLOCK_PERIOD : vl_notype; - USE_NEW_CORECLK_CKT: vl_notype - ); - port( - tx_in : in vl_logic_vector; - tx_inclock : in vl_logic; - tx_syncclock : in vl_logic; - tx_enable : in vl_logic; - sync_inclock : in vl_logic; - tx_pll_enable : in vl_logic; - pll_areset : in vl_logic; - tx_data_reset : in vl_logic; - tx_out : out vl_logic_vector; - tx_outclock : out vl_logic; - tx_coreclock : out vl_logic; - tx_locked : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of registered_input : constant is 1; - attribute mti_svvh_generic_type of multi_clock : constant is 1; - attribute mti_svvh_generic_type of inclock_period : constant is 1; - attribute mti_svvh_generic_type of outclock_divide_by : constant is 3; - attribute mti_svvh_generic_type of inclock_boost : constant is 3; - attribute mti_svvh_generic_type of center_align_msb : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of output_data_rate : constant is 1; - attribute mti_svvh_generic_type of inclock_data_alignment : constant is 1; - attribute mti_svvh_generic_type of outclock_alignment : constant is 1; - attribute mti_svvh_generic_type of common_rx_tx_pll : constant is 1; - attribute mti_svvh_generic_type of outclock_resource : constant is 1; - attribute mti_svvh_generic_type of use_external_pll : constant is 1; - attribute mti_svvh_generic_type of implement_in_les : constant is 1; - attribute mti_svvh_generic_type of preemphasis_setting : constant is 1; - attribute mti_svvh_generic_type of vod_setting : constant is 1; - attribute mti_svvh_generic_type of differential_drive : constant is 1; - attribute mti_svvh_generic_type of outclock_multiply_by : constant is 1; - attribute mti_svvh_generic_type of coreclock_divide_by : constant is 1; - attribute mti_svvh_generic_type of outclock_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of inclock_phase_shift : constant is 1; - attribute mti_svvh_generic_type of outclock_phase_shift : constant is 1; - attribute mti_svvh_generic_type of use_no_phase_shift : constant is 1; - attribute mti_svvh_generic_type of pll_self_reset_on_loss_lock : constant is 1; - attribute mti_svvh_generic_type of refclk_frequency : constant is 1; - attribute mti_svvh_generic_type of data_rate : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of clk_src_is_pll : constant is 1; - attribute mti_svvh_generic_type of STRATIX_TX_STYLE : constant is 3; - attribute mti_svvh_generic_type of STRATIXII_TX_STYLE : constant is 3; - attribute mti_svvh_generic_type of CYCLONE_TX_STYLE : constant is 3; - attribute mti_svvh_generic_type of CYCLONEII_TX_STYLE : constant is 3; - attribute mti_svvh_generic_type of STRATIXIII_TX_STYLE : constant is 3; - attribute mti_svvh_generic_type of CYCLONEIII_TX_STYLE : constant is 3; - attribute mti_svvh_generic_type of MAXV_TX_STYLE : constant is 3; - attribute mti_svvh_generic_type of FAMILY_HAS_FLEXIBLE_LVDS : constant is 3; - attribute mti_svvh_generic_type of FAMILY_HAS_STRATIX_STYLE_PLL : constant is 3; - attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXII_STYLE_PLL : constant is 3; - attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXIII_STYLE_PLL : constant is 3; - attribute mti_svvh_generic_type of INT_CLOCK_BOOST : constant is 3; - attribute mti_svvh_generic_type of PLL_M_VALUE : constant is 3; - attribute mti_svvh_generic_type of PLL_D_VALUE : constant is 3; - attribute mti_svvh_generic_type of STRATIX_INCLOCK_BOOST : constant is 3; - attribute mti_svvh_generic_type of PHASE_INCLOCK : constant is 3; - attribute mti_svvh_generic_type of STXII_PHASE_INCLOCK : constant is 3; - attribute mti_svvh_generic_type of PHASE_OUTCLOCK : constant is 3; - attribute mti_svvh_generic_type of STX_PHASE_OUTCLOCK : constant is 3; - attribute mti_svvh_generic_type of STXII_PHASE_OUTCLOCK : constant is 3; - attribute mti_svvh_generic_type of STXII_LE_PHASE_INCLOCK : constant is 3; - attribute mti_svvh_generic_type of STXII_LE_PHASE_OUTCLOCK : constant is 3; - attribute mti_svvh_generic_type of STXIII_LE_PHASE_INCLOCK : constant is 3; - attribute mti_svvh_generic_type of STXIII_LE_PHASE_OUTCLOCK : constant is 3; - attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3; - attribute mti_svvh_generic_type of FAST_CLK_ENA_PHASE_SHIFT : constant is 3; - attribute mti_svvh_generic_type of CLOCK_PERIOD : constant is 3; - attribute mti_svvh_generic_type of USE_NEW_CORECLK_CKT : constant is 3; -end altlvds_tx; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_accum/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_accum/_primary.dat deleted file mode 100644 index 6d47663..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_accum/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_accum/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_accum/_primary.dbs deleted file mode 100644 index fc1f905..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_accum/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_accum/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_accum/_primary.vhd deleted file mode 100644 index 1ca32f1..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_accum/_primary.vhd +++ /dev/null @@ -1,315 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altmult_accum is - generic( - width_a : integer := 2; - width_b : integer := 2; - width_c : integer := 22; - width_result : integer := 5; - number_of_multipliers: integer := 1; - input_reg_a : string := "CLOCK0"; - input_aclr_a : string := "ACLR3"; - multiplier1_direction: string := "UNUSED"; - multiplier3_direction: string := "UNUSED"; - input_reg_b : string := "CLOCK0"; - input_aclr_b : string := "ACLR3"; - port_addnsub : string := "PORT_CONNECTIVITY"; - addnsub_reg : string := "CLOCK0"; - addnsub_aclr : string := "ACLR3"; - addnsub_pipeline_reg: string := "CLOCK0"; - addnsub_pipeline_aclr: string := "ACLR3"; - accum_direction : string := "ADD"; - accum_sload_reg : string := "CLOCK0"; - accum_sload_aclr: string := "ACLR3"; - accum_sload_pipeline_reg: string := "CLOCK0"; - accum_sload_pipeline_aclr: string := "ACLR3"; - representation_a: string := "UNSIGNED"; - port_signa : string := "PORT_CONNECTIVITY"; - sign_reg_a : string := "CLOCK0"; - sign_aclr_a : string := "ACLR3"; - sign_pipeline_reg_a: string := "CLOCK0"; - sign_pipeline_aclr_a: string := "ACLR3"; - port_signb : string := "PORT_CONNECTIVITY"; - representation_b: string := "UNSIGNED"; - sign_reg_b : string := "CLOCK0"; - sign_aclr_b : string := "ACLR3"; - sign_pipeline_reg_b: string := "CLOCK0"; - sign_pipeline_aclr_b: string := "ACLR3"; - multiplier_reg : string := "CLOCK0"; - multiplier_aclr : string := "ACLR3"; - output_reg : string := "CLOCK0"; - output_aclr : string := "ACLR3"; - lpm_type : string := "altmult_accum"; - lpm_hint : string := "UNUSED"; - extra_multiplier_latency: integer := 0; - extra_accumulator_latency: integer := 0; - dedicated_multiplier_circuitry: string := "AUTO"; - dsp_block_balancing: string := "AUTO"; - intended_device_family: string := "Stratix"; - accum_round_aclr: string := "ACLR3"; - accum_round_pipeline_aclr: string := "ACLR3"; - accum_round_pipeline_reg: string := "CLOCK0"; - accum_round_reg : string := "CLOCK0"; - accum_saturation_aclr: string := "ACLR3"; - accum_saturation_pipeline_aclr: string := "ACLR3"; - accum_saturation_pipeline_reg: string := "CLOCK0"; - accum_saturation_reg: string := "CLOCK0"; - accum_sload_upper_data_aclr: string := "ACLR3"; - accum_sload_upper_data_pipeline_aclr: string := "ACLR3"; - accum_sload_upper_data_pipeline_reg: string := "CLOCK0"; - accum_sload_upper_data_reg: string := "CLOCK0"; - mult_round_aclr : string := "ACLR3"; - mult_round_reg : string := "CLOCK0"; - mult_saturation_aclr: string := "ACLR3"; - mult_saturation_reg: string := "CLOCK0"; - input_source_a : string := "DATAA"; - input_source_b : string := "DATAB"; - width_upper_data: integer := 1; - multiplier_rounding: string := "NO"; - multiplier_saturation: string := "NO"; - accumulator_rounding: string := "NO"; - accumulator_saturation: string := "NO"; - port_mult_is_saturated: string := "UNUSED"; - port_accum_is_saturated: string := "UNUSED"; - int_width_a : vl_notype; - int_width_b : vl_notype; - int_width_result: vl_notype; - int_extra_width : vl_notype; - diff_width_a : vl_notype; - diff_width_b : vl_notype; - sat_for_ini : vl_notype; - mult_round_for_ini: vl_notype; - bits_to_round : vl_notype; - sload_for_limit : vl_notype; - accum_sat_for_limit: vl_notype; - int_width_extra_bit: vl_notype; - preadder_mode : string := "SIMPLE"; - loadconst_value : integer := 0; - width_coef : integer := 0; - loadconst_control_register: string := "CLOCK0"; - loadconst_control_aclr: string := "ACLR0"; - coefsel0_register: string := "CLOCK0"; - coefsel1_register: string := "CLOCK0"; - coefsel2_register: string := "CLOCK0"; - coefsel3_register: string := "CLOCK0"; - coefsel0_aclr : string := "ACLR0"; - coefsel1_aclr : string := "ACLR0"; - coefsel2_aclr : string := "ACLR0"; - coefsel3_aclr : string := "ACLR0"; - preadder_direction_0: string := "ADD"; - preadder_direction_1: string := "ADD"; - preadder_direction_2: string := "ADD"; - preadder_direction_3: string := "ADD"; - systolic_delay1 : string := "UNREGISTERED"; - systolic_delay3 : string := "UNREGISTERED"; - systolic_aclr1 : string := "NONE"; - systolic_aclr3 : string := "NONE"; - coef0_0 : integer := 0; - coef0_1 : integer := 0; - coef0_2 : integer := 0; - coef0_3 : integer := 0; - coef0_4 : integer := 0; - coef0_5 : integer := 0; - coef0_6 : integer := 0; - coef0_7 : integer := 0; - coef1_0 : integer := 0; - coef1_1 : integer := 0; - coef1_2 : integer := 0; - coef1_3 : integer := 0; - coef1_4 : integer := 0; - coef1_5 : integer := 0; - coef1_6 : integer := 0; - coef1_7 : integer := 0; - coef2_0 : integer := 0; - coef2_1 : integer := 0; - coef2_2 : integer := 0; - coef2_3 : integer := 0; - coef2_4 : integer := 0; - coef2_5 : integer := 0; - coef2_6 : integer := 0; - coef2_7 : integer := 0; - coef3_0 : integer := 0; - coef3_1 : integer := 0; - coef3_2 : integer := 0; - coef3_3 : integer := 0; - coef3_4 : integer := 0; - coef3_5 : integer := 0; - coef3_6 : integer := 0; - coef3_7 : integer := 0 - ); - port( - dataa : in vl_logic_vector; - datab : in vl_logic_vector; - datac : in vl_logic_vector; - scanina : in vl_logic_vector; - scaninb : in vl_logic_vector; - sourcea : in vl_logic; - sourceb : in vl_logic; - accum_sload_upper_data: in vl_logic_vector; - addnsub : in vl_logic; - accum_sload : in vl_logic; - signa : in vl_logic; - signb : in vl_logic; - clock0 : in vl_logic; - clock1 : in vl_logic; - clock2 : in vl_logic; - clock3 : in vl_logic; - ena0 : in vl_logic; - ena1 : in vl_logic; - ena2 : in vl_logic; - ena3 : in vl_logic; - aclr0 : in vl_logic; - aclr1 : in vl_logic; - aclr2 : in vl_logic; - aclr3 : in vl_logic; - result : out vl_logic_vector; - overflow : out vl_logic; - scanouta : out vl_logic_vector; - scanoutb : out vl_logic_vector; - mult_round : in vl_logic; - mult_saturation : in vl_logic; - accum_round : in vl_logic; - accum_saturation: in vl_logic; - mult_is_saturated: out vl_logic; - accum_is_saturated: out vl_logic; - coefsel0 : in vl_logic_vector(2 downto 0); - coefsel1 : in vl_logic_vector(2 downto 0); - coefsel2 : in vl_logic_vector(2 downto 0); - coefsel3 : in vl_logic_vector(2 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_a : constant is 1; - attribute mti_svvh_generic_type of width_b : constant is 1; - attribute mti_svvh_generic_type of width_c : constant is 1; - attribute mti_svvh_generic_type of width_result : constant is 1; - attribute mti_svvh_generic_type of number_of_multipliers : constant is 1; - attribute mti_svvh_generic_type of input_reg_a : constant is 1; - attribute mti_svvh_generic_type of input_aclr_a : constant is 1; - attribute mti_svvh_generic_type of multiplier1_direction : constant is 1; - attribute mti_svvh_generic_type of multiplier3_direction : constant is 1; - attribute mti_svvh_generic_type of input_reg_b : constant is 1; - attribute mti_svvh_generic_type of input_aclr_b : constant is 1; - attribute mti_svvh_generic_type of port_addnsub : constant is 1; - attribute mti_svvh_generic_type of addnsub_reg : constant is 1; - attribute mti_svvh_generic_type of addnsub_aclr : constant is 1; - attribute mti_svvh_generic_type of addnsub_pipeline_reg : constant is 1; - attribute mti_svvh_generic_type of addnsub_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_direction : constant is 1; - attribute mti_svvh_generic_type of accum_sload_reg : constant is 1; - attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_sload_pipeline_reg : constant is 1; - attribute mti_svvh_generic_type of accum_sload_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of representation_a : constant is 1; - attribute mti_svvh_generic_type of port_signa : constant is 1; - attribute mti_svvh_generic_type of sign_reg_a : constant is 1; - attribute mti_svvh_generic_type of sign_aclr_a : constant is 1; - attribute mti_svvh_generic_type of sign_pipeline_reg_a : constant is 1; - attribute mti_svvh_generic_type of sign_pipeline_aclr_a : constant is 1; - attribute mti_svvh_generic_type of port_signb : constant is 1; - attribute mti_svvh_generic_type of representation_b : constant is 1; - attribute mti_svvh_generic_type of sign_reg_b : constant is 1; - attribute mti_svvh_generic_type of sign_aclr_b : constant is 1; - attribute mti_svvh_generic_type of sign_pipeline_reg_b : constant is 1; - attribute mti_svvh_generic_type of sign_pipeline_aclr_b : constant is 1; - attribute mti_svvh_generic_type of multiplier_reg : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr : constant is 1; - attribute mti_svvh_generic_type of output_reg : constant is 1; - attribute mti_svvh_generic_type of output_aclr : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of extra_multiplier_latency : constant is 1; - attribute mti_svvh_generic_type of extra_accumulator_latency : constant is 1; - attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1; - attribute mti_svvh_generic_type of dsp_block_balancing : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of accum_round_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_round_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_round_pipeline_reg : constant is 1; - attribute mti_svvh_generic_type of accum_round_reg : constant is 1; - attribute mti_svvh_generic_type of accum_saturation_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_saturation_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_saturation_pipeline_reg : constant is 1; - attribute mti_svvh_generic_type of accum_saturation_reg : constant is 1; - attribute mti_svvh_generic_type of accum_sload_upper_data_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_sload_upper_data_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_sload_upper_data_pipeline_reg : constant is 1; - attribute mti_svvh_generic_type of accum_sload_upper_data_reg : constant is 1; - attribute mti_svvh_generic_type of mult_round_aclr : constant is 1; - attribute mti_svvh_generic_type of mult_round_reg : constant is 1; - attribute mti_svvh_generic_type of mult_saturation_aclr : constant is 1; - attribute mti_svvh_generic_type of mult_saturation_reg : constant is 1; - attribute mti_svvh_generic_type of input_source_a : constant is 1; - attribute mti_svvh_generic_type of input_source_b : constant is 1; - attribute mti_svvh_generic_type of width_upper_data : constant is 1; - attribute mti_svvh_generic_type of multiplier_rounding : constant is 1; - attribute mti_svvh_generic_type of multiplier_saturation : constant is 1; - attribute mti_svvh_generic_type of accumulator_rounding : constant is 1; - attribute mti_svvh_generic_type of accumulator_saturation : constant is 1; - attribute mti_svvh_generic_type of port_mult_is_saturated : constant is 1; - attribute mti_svvh_generic_type of port_accum_is_saturated : constant is 1; - attribute mti_svvh_generic_type of int_width_a : constant is 3; - attribute mti_svvh_generic_type of int_width_b : constant is 3; - attribute mti_svvh_generic_type of int_width_result : constant is 3; - attribute mti_svvh_generic_type of int_extra_width : constant is 3; - attribute mti_svvh_generic_type of diff_width_a : constant is 3; - attribute mti_svvh_generic_type of diff_width_b : constant is 3; - attribute mti_svvh_generic_type of sat_for_ini : constant is 3; - attribute mti_svvh_generic_type of mult_round_for_ini : constant is 3; - attribute mti_svvh_generic_type of bits_to_round : constant is 3; - attribute mti_svvh_generic_type of sload_for_limit : constant is 3; - attribute mti_svvh_generic_type of accum_sat_for_limit : constant is 3; - attribute mti_svvh_generic_type of int_width_extra_bit : constant is 3; - attribute mti_svvh_generic_type of preadder_mode : constant is 1; - attribute mti_svvh_generic_type of loadconst_value : constant is 1; - attribute mti_svvh_generic_type of width_coef : constant is 1; - attribute mti_svvh_generic_type of loadconst_control_register : constant is 1; - attribute mti_svvh_generic_type of loadconst_control_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel0_register : constant is 1; - attribute mti_svvh_generic_type of coefsel1_register : constant is 1; - attribute mti_svvh_generic_type of coefsel2_register : constant is 1; - attribute mti_svvh_generic_type of coefsel3_register : constant is 1; - attribute mti_svvh_generic_type of coefsel0_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel1_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel2_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel3_aclr : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1; - attribute mti_svvh_generic_type of systolic_delay1 : constant is 1; - attribute mti_svvh_generic_type of systolic_delay3 : constant is 1; - attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1; - attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1; - attribute mti_svvh_generic_type of coef0_0 : constant is 1; - attribute mti_svvh_generic_type of coef0_1 : constant is 1; - attribute mti_svvh_generic_type of coef0_2 : constant is 1; - attribute mti_svvh_generic_type of coef0_3 : constant is 1; - attribute mti_svvh_generic_type of coef0_4 : constant is 1; - attribute mti_svvh_generic_type of coef0_5 : constant is 1; - attribute mti_svvh_generic_type of coef0_6 : constant is 1; - attribute mti_svvh_generic_type of coef0_7 : constant is 1; - attribute mti_svvh_generic_type of coef1_0 : constant is 1; - attribute mti_svvh_generic_type of coef1_1 : constant is 1; - attribute mti_svvh_generic_type of coef1_2 : constant is 1; - attribute mti_svvh_generic_type of coef1_3 : constant is 1; - attribute mti_svvh_generic_type of coef1_4 : constant is 1; - attribute mti_svvh_generic_type of coef1_5 : constant is 1; - attribute mti_svvh_generic_type of coef1_6 : constant is 1; - attribute mti_svvh_generic_type of coef1_7 : constant is 1; - attribute mti_svvh_generic_type of coef2_0 : constant is 1; - attribute mti_svvh_generic_type of coef2_1 : constant is 1; - attribute mti_svvh_generic_type of coef2_2 : constant is 1; - attribute mti_svvh_generic_type of coef2_3 : constant is 1; - attribute mti_svvh_generic_type of coef2_4 : constant is 1; - attribute mti_svvh_generic_type of coef2_5 : constant is 1; - attribute mti_svvh_generic_type of coef2_6 : constant is 1; - attribute mti_svvh_generic_type of coef2_7 : constant is 1; - attribute mti_svvh_generic_type of coef3_0 : constant is 1; - attribute mti_svvh_generic_type of coef3_1 : constant is 1; - attribute mti_svvh_generic_type of coef3_2 : constant is 1; - attribute mti_svvh_generic_type of coef3_3 : constant is 1; - attribute mti_svvh_generic_type of coef3_4 : constant is 1; - attribute mti_svvh_generic_type of coef3_5 : constant is 1; - attribute mti_svvh_generic_type of coef3_6 : constant is 1; - attribute mti_svvh_generic_type of coef3_7 : constant is 1; -end altmult_accum; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_add/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_add/_primary.dat deleted file mode 100644 index 0712304..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_add/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_add/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_add/_primary.dbs deleted file mode 100644 index 179e1c0..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_add/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_add/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_add/_primary.vhd deleted file mode 100644 index e080486..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altmult_add/_primary.vhd +++ /dev/null @@ -1,569 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altmult_add is - generic( - width_a : integer := 16; - width_b : integer := 16; - width_c : integer := 22; - width_result : integer := 34; - number_of_multipliers: integer := 1; - lpm_type : string := "altmult_add"; - lpm_hint : string := "UNUSED"; - multiplier1_direction: string := "UNUSED"; - multiplier3_direction: string := "UNUSED"; - input_register_a0: string := "CLOCK0"; - input_aclr_a0 : string := "ACLR3"; - input_source_a0 : string := "DATAA"; - input_register_a1: string := "CLOCK0"; - input_aclr_a1 : string := "ACLR3"; - input_source_a1 : string := "DATAA"; - input_register_a2: string := "CLOCK0"; - input_aclr_a2 : string := "ACLR3"; - input_source_a2 : string := "DATAA"; - input_register_a3: string := "CLOCK0"; - input_aclr_a3 : string := "ACLR3"; - input_source_a3 : string := "DATAA"; - port_signa : string := "PORT_CONNECTIVITY"; - representation_a: string := "UNSIGNED"; - signed_register_a: string := "CLOCK0"; - signed_aclr_a : string := "ACLR3"; - signed_pipeline_register_a: string := "CLOCK0"; - signed_pipeline_aclr_a: string := "ACLR3"; - scanouta_register: string := "UNREGISTERED"; - scanouta_aclr : string := "NONE"; - input_register_b0: string := "CLOCK0"; - input_aclr_b0 : string := "ACLR3"; - input_source_b0 : string := "DATAB"; - input_register_b1: string := "CLOCK0"; - input_aclr_b1 : string := "ACLR3"; - input_source_b1 : string := "DATAB"; - input_register_b2: string := "CLOCK0"; - input_aclr_b2 : string := "ACLR3"; - input_source_b2 : string := "DATAB"; - input_register_b3: string := "CLOCK0"; - input_aclr_b3 : string := "ACLR3"; - input_source_b3 : string := "DATAB"; - port_signb : string := "PORT_CONNECTIVITY"; - representation_b: string := "UNSIGNED"; - signed_register_b: string := "CLOCK0"; - signed_aclr_b : string := "ACLR3"; - signed_pipeline_register_b: string := "CLOCK0"; - signed_pipeline_aclr_b: string := "ACLR3"; - input_register_c0: string := "CLOCK0"; - input_aclr_c0 : string := "ACLR0"; - input_register_c1: string := "CLOCK0"; - input_aclr_c1 : string := "ACLR0"; - input_register_c2: string := "CLOCK0"; - input_aclr_c2 : string := "ACLR0"; - input_register_c3: string := "CLOCK0"; - input_aclr_c3 : string := "ACLR0"; - multiplier_register0: string := "CLOCK0"; - multiplier_aclr0: string := "ACLR3"; - multiplier_register1: string := "CLOCK0"; - multiplier_aclr1: string := "ACLR3"; - multiplier_register2: string := "CLOCK0"; - multiplier_aclr2: string := "ACLR3"; - multiplier_register3: string := "CLOCK0"; - multiplier_aclr3: string := "ACLR3"; - port_addnsub1 : string := "PORT_CONNECTIVITY"; - addnsub_multiplier_register1: string := "CLOCK0"; - addnsub_multiplier_aclr1: string := "ACLR3"; - addnsub_multiplier_pipeline_register1: string := "CLOCK0"; - addnsub_multiplier_pipeline_aclr1: string := "ACLR3"; - port_addnsub3 : string := "PORT_CONNECTIVITY"; - addnsub_multiplier_register3: string := "CLOCK0"; - addnsub_multiplier_aclr3: string := "ACLR3"; - addnsub_multiplier_pipeline_register3: string := "CLOCK0"; - addnsub_multiplier_pipeline_aclr3: string := "ACLR3"; - addnsub1_round_aclr: string := "ACLR3"; - addnsub1_round_pipeline_aclr: string := "ACLR3"; - addnsub1_round_register: string := "CLOCK0"; - addnsub1_round_pipeline_register: string := "CLOCK0"; - addnsub3_round_aclr: string := "ACLR3"; - addnsub3_round_pipeline_aclr: string := "ACLR3"; - addnsub3_round_register: string := "CLOCK0"; - addnsub3_round_pipeline_register: string := "CLOCK0"; - mult01_round_aclr: string := "ACLR3"; - mult01_round_register: string := "CLOCK0"; - mult01_saturation_register: string := "CLOCK0"; - mult01_saturation_aclr: string := "ACLR3"; - mult23_round_register: string := "CLOCK0"; - mult23_round_aclr: string := "ACLR3"; - mult23_saturation_register: string := "CLOCK0"; - mult23_saturation_aclr: string := "ACLR3"; - multiplier01_rounding: string := "NO"; - multiplier01_saturation: string := "NO"; - multiplier23_rounding: string := "NO"; - multiplier23_saturation: string := "NO"; - adder1_rounding : string := "NO"; - adder3_rounding : string := "NO"; - port_mult0_is_saturated: string := "UNUSED"; - port_mult1_is_saturated: string := "UNUSED"; - port_mult2_is_saturated: string := "UNUSED"; - port_mult3_is_saturated: string := "UNUSED"; - output_rounding : string := "NO"; - output_round_type: string := "NEAREST_INTEGER"; - width_msb : integer := 17; - output_round_register: string := "UNREGISTERED"; - output_round_aclr: string := "NONE"; - output_round_pipeline_register: string := "UNREGISTERED"; - output_round_pipeline_aclr: string := "NONE"; - chainout_rounding: string := "NO"; - chainout_round_register: string := "UNREGISTERED"; - chainout_round_aclr: string := "NONE"; - chainout_round_pipeline_register: string := "UNREGISTERED"; - chainout_round_pipeline_aclr: string := "NONE"; - chainout_round_output_register: string := "UNREGISTERED"; - chainout_round_output_aclr: string := "NONE"; - port_output_is_overflow: string := "PORT_UNUSED"; - port_chainout_sat_is_overflow: string := "PORT_UNUSED"; - output_saturation: string := "NO"; - output_saturate_type: string := "ASYMMETRIC"; - width_saturate_sign: integer := 1; - output_saturate_register: string := "UNREGISTERED"; - output_saturate_aclr: string := "NONE"; - output_saturate_pipeline_register: string := "UNREGISTERED"; - output_saturate_pipeline_aclr: string := "NONE"; - chainout_saturation: string := "NO"; - chainout_saturate_register: string := "UNREGISTERED"; - chainout_saturate_aclr: string := "NONE"; - chainout_saturate_pipeline_register: string := "UNREGISTERED"; - chainout_saturate_pipeline_aclr: string := "NONE"; - chainout_saturate_output_register: string := "UNREGISTERED"; - chainout_saturate_output_aclr: string := "NONE"; - chainout_adder : string := "NO"; - chainout_register: string := "UNREGISTERED"; - chainout_aclr : string := "ACLR3"; - width_chainin : integer := 1; - zero_chainout_output_register: string := "UNREGISTERED"; - zero_chainout_output_aclr: string := "NONE"; - shift_mode : string := "NO"; - rotate_aclr : string := "NONE"; - rotate_register : string := "UNREGISTERED"; - rotate_pipeline_register: string := "UNREGISTERED"; - rotate_pipeline_aclr: string := "NONE"; - rotate_output_register: string := "UNREGISTERED"; - rotate_output_aclr: string := "NONE"; - shift_right_register: string := "UNREGISTERED"; - shift_right_aclr: string := "NONE"; - shift_right_pipeline_register: string := "UNREGISTERED"; - shift_right_pipeline_aclr: string := "NONE"; - shift_right_output_register: string := "UNREGISTERED"; - shift_right_output_aclr: string := "NONE"; - zero_loopback_register: string := "UNREGISTERED"; - zero_loopback_aclr: string := "NONE"; - zero_loopback_pipeline_register: string := "UNREGISTERED"; - zero_loopback_pipeline_aclr: string := "NONE"; - zero_loopback_output_register: string := "UNREGISTERED"; - zero_loopback_output_aclr: string := "NONE"; - accum_sload_register: string := "UNREGISTERED"; - accum_sload_aclr: string := "NONE"; - accum_sload_pipeline_register: string := "UNREGISTERED"; - accum_sload_pipeline_aclr: string := "NONE"; - accum_direction : string := "ADD"; - accumulator : string := "NO"; - preadder_mode : string := "SIMPLE"; - loadconst_value : integer := 0; - width_coef : integer := 0; - loadconst_control_register: string := "CLOCK0"; - loadconst_control_aclr: string := "ACLR0"; - coefsel0_register: string := "CLOCK0"; - coefsel1_register: string := "CLOCK0"; - coefsel2_register: string := "CLOCK0"; - coefsel3_register: string := "CLOCK0"; - coefsel0_aclr : string := "ACLR0"; - coefsel1_aclr : string := "ACLR0"; - coefsel2_aclr : string := "ACLR0"; - coefsel3_aclr : string := "ACLR0"; - preadder_direction_0: string := "ADD"; - preadder_direction_1: string := "ADD"; - preadder_direction_2: string := "ADD"; - preadder_direction_3: string := "ADD"; - systolic_delay1 : string := "UNREGISTERED"; - systolic_delay3 : string := "UNREGISTERED"; - systolic_aclr1 : string := "NONE"; - systolic_aclr3 : string := "NONE"; - coef0_0 : integer := 0; - coef0_1 : integer := 0; - coef0_2 : integer := 0; - coef0_3 : integer := 0; - coef0_4 : integer := 0; - coef0_5 : integer := 0; - coef0_6 : integer := 0; - coef0_7 : integer := 0; - coef1_0 : integer := 0; - coef1_1 : integer := 0; - coef1_2 : integer := 0; - coef1_3 : integer := 0; - coef1_4 : integer := 0; - coef1_5 : integer := 0; - coef1_6 : integer := 0; - coef1_7 : integer := 0; - coef2_0 : integer := 0; - coef2_1 : integer := 0; - coef2_2 : integer := 0; - coef2_3 : integer := 0; - coef2_4 : integer := 0; - coef2_5 : integer := 0; - coef2_6 : integer := 0; - coef2_7 : integer := 0; - coef3_0 : integer := 0; - coef3_1 : integer := 0; - coef3_2 : integer := 0; - coef3_3 : integer := 0; - coef3_4 : integer := 0; - coef3_5 : integer := 0; - coef3_6 : integer := 0; - coef3_7 : integer := 0; - output_register : string := "CLOCK0"; - output_aclr : string := "ACLR3"; - extra_latency : integer := 0; - dedicated_multiplier_circuitry: string := "AUTO"; - dsp_block_balancing: string := "AUTO"; - intended_device_family: string := "Stratix"; - int_width_c : vl_notype; - int_width_preadder: vl_notype; - int_width_a : vl_notype; - int_width_b : vl_notype; - int_width_multiply_b: vl_notype; - int_width_result: vl_notype; - mult_b_pre_width: vl_notype; - int_mult_diff_bit: vl_notype; - int_mult_diff_bit_loopbk: vl_notype; - sat_ini_value : vl_notype; - round_position : vl_notype; - chainout_round_position: vl_notype; - saturation_position: vl_notype; - chainout_saturation_position: vl_notype; - result_msb_stxiii: vl_notype; - result_msb : vl_notype; - shift_partition : vl_notype; - shift_msb : vl_notype; - sat_msb : vl_notype; - chainout_sat_msb: vl_notype; - chainout_input_a: vl_notype; - chainout_input_b: vl_notype; - mult_res_pad : vl_notype; - result_pad : vl_notype; - result_stxiii_pad: vl_notype; - loopback_input_pad: vl_notype; - loopback_lower_bound: vl_notype; - accum_width : vl_notype; - feedback_width : vl_notype; - lower_range : vl_notype; - addsub1_clr : vl_notype; - addsub3_clr : vl_notype; - lsb_position : vl_notype; - extra_sign_bit_width: vl_notype; - bit_position : vl_notype - ); - port( - dataa : in vl_logic_vector; - datab : in vl_logic_vector; - datac : in vl_logic_vector; - scanina : in vl_logic_vector; - scaninb : in vl_logic_vector; - sourcea : in vl_logic_vector; - sourceb : in vl_logic_vector; - clock3 : in vl_logic; - clock2 : in vl_logic; - clock1 : in vl_logic; - clock0 : in vl_logic; - aclr3 : in vl_logic; - aclr2 : in vl_logic; - aclr1 : in vl_logic; - aclr0 : in vl_logic; - ena3 : in vl_logic; - ena2 : in vl_logic; - ena1 : in vl_logic; - ena0 : in vl_logic; - signa : in vl_logic; - signb : in vl_logic; - addnsub1 : in vl_logic; - addnsub3 : in vl_logic; - result : out vl_logic_vector; - scanouta : out vl_logic_vector; - scanoutb : out vl_logic_vector; - mult01_round : in vl_logic; - mult23_round : in vl_logic; - mult01_saturation: in vl_logic; - mult23_saturation: in vl_logic; - addnsub1_round : in vl_logic; - addnsub3_round : in vl_logic; - mult0_is_saturated: out vl_logic; - mult1_is_saturated: out vl_logic; - mult2_is_saturated: out vl_logic; - mult3_is_saturated: out vl_logic; - output_round : in vl_logic; - chainout_round : in vl_logic; - output_saturate : in vl_logic; - chainout_saturate: in vl_logic; - overflow : out vl_logic; - chainout_sat_overflow: out vl_logic; - chainin : in vl_logic_vector; - zero_chainout : in vl_logic; - rotate : in vl_logic; - shift_right : in vl_logic; - zero_loopback : in vl_logic; - accum_sload : in vl_logic; - coefsel0 : in vl_logic_vector(2 downto 0); - coefsel1 : in vl_logic_vector(2 downto 0); - coefsel2 : in vl_logic_vector(2 downto 0); - coefsel3 : in vl_logic_vector(2 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_a : constant is 1; - attribute mti_svvh_generic_type of width_b : constant is 1; - attribute mti_svvh_generic_type of width_c : constant is 1; - attribute mti_svvh_generic_type of width_result : constant is 1; - attribute mti_svvh_generic_type of number_of_multipliers : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of multiplier1_direction : constant is 1; - attribute mti_svvh_generic_type of multiplier3_direction : constant is 1; - attribute mti_svvh_generic_type of input_register_a0 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_a0 : constant is 1; - attribute mti_svvh_generic_type of input_source_a0 : constant is 1; - attribute mti_svvh_generic_type of input_register_a1 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_a1 : constant is 1; - attribute mti_svvh_generic_type of input_source_a1 : constant is 1; - attribute mti_svvh_generic_type of input_register_a2 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_a2 : constant is 1; - attribute mti_svvh_generic_type of input_source_a2 : constant is 1; - attribute mti_svvh_generic_type of input_register_a3 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_a3 : constant is 1; - attribute mti_svvh_generic_type of input_source_a3 : constant is 1; - attribute mti_svvh_generic_type of port_signa : constant is 1; - attribute mti_svvh_generic_type of representation_a : constant is 1; - attribute mti_svvh_generic_type of signed_register_a : constant is 1; - attribute mti_svvh_generic_type of signed_aclr_a : constant is 1; - attribute mti_svvh_generic_type of signed_pipeline_register_a : constant is 1; - attribute mti_svvh_generic_type of signed_pipeline_aclr_a : constant is 1; - attribute mti_svvh_generic_type of scanouta_register : constant is 1; - attribute mti_svvh_generic_type of scanouta_aclr : constant is 1; - attribute mti_svvh_generic_type of input_register_b0 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_b0 : constant is 1; - attribute mti_svvh_generic_type of input_source_b0 : constant is 1; - attribute mti_svvh_generic_type of input_register_b1 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_b1 : constant is 1; - attribute mti_svvh_generic_type of input_source_b1 : constant is 1; - attribute mti_svvh_generic_type of input_register_b2 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_b2 : constant is 1; - attribute mti_svvh_generic_type of input_source_b2 : constant is 1; - attribute mti_svvh_generic_type of input_register_b3 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_b3 : constant is 1; - attribute mti_svvh_generic_type of input_source_b3 : constant is 1; - attribute mti_svvh_generic_type of port_signb : constant is 1; - attribute mti_svvh_generic_type of representation_b : constant is 1; - attribute mti_svvh_generic_type of signed_register_b : constant is 1; - attribute mti_svvh_generic_type of signed_aclr_b : constant is 1; - attribute mti_svvh_generic_type of signed_pipeline_register_b : constant is 1; - attribute mti_svvh_generic_type of signed_pipeline_aclr_b : constant is 1; - attribute mti_svvh_generic_type of input_register_c0 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_c0 : constant is 1; - attribute mti_svvh_generic_type of input_register_c1 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_c1 : constant is 1; - attribute mti_svvh_generic_type of input_register_c2 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_c2 : constant is 1; - attribute mti_svvh_generic_type of input_register_c3 : constant is 1; - attribute mti_svvh_generic_type of input_aclr_c3 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register0 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register1 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register2 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1; - attribute mti_svvh_generic_type of multiplier_register3 : constant is 1; - attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1; - attribute mti_svvh_generic_type of port_addnsub1 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_register1 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_aclr1 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register1 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr1 : constant is 1; - attribute mti_svvh_generic_type of port_addnsub3 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_register3 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_aclr3 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_register3 : constant is 1; - attribute mti_svvh_generic_type of addnsub_multiplier_pipeline_aclr3 : constant is 1; - attribute mti_svvh_generic_type of addnsub1_round_aclr : constant is 1; - attribute mti_svvh_generic_type of addnsub1_round_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of addnsub1_round_register : constant is 1; - attribute mti_svvh_generic_type of addnsub1_round_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of addnsub3_round_aclr : constant is 1; - attribute mti_svvh_generic_type of addnsub3_round_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of addnsub3_round_register : constant is 1; - attribute mti_svvh_generic_type of addnsub3_round_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of mult01_round_aclr : constant is 1; - attribute mti_svvh_generic_type of mult01_round_register : constant is 1; - attribute mti_svvh_generic_type of mult01_saturation_register : constant is 1; - attribute mti_svvh_generic_type of mult01_saturation_aclr : constant is 1; - attribute mti_svvh_generic_type of mult23_round_register : constant is 1; - attribute mti_svvh_generic_type of mult23_round_aclr : constant is 1; - attribute mti_svvh_generic_type of mult23_saturation_register : constant is 1; - attribute mti_svvh_generic_type of mult23_saturation_aclr : constant is 1; - attribute mti_svvh_generic_type of multiplier01_rounding : constant is 1; - attribute mti_svvh_generic_type of multiplier01_saturation : constant is 1; - attribute mti_svvh_generic_type of multiplier23_rounding : constant is 1; - attribute mti_svvh_generic_type of multiplier23_saturation : constant is 1; - attribute mti_svvh_generic_type of adder1_rounding : constant is 1; - attribute mti_svvh_generic_type of adder3_rounding : constant is 1; - attribute mti_svvh_generic_type of port_mult0_is_saturated : constant is 1; - attribute mti_svvh_generic_type of port_mult1_is_saturated : constant is 1; - attribute mti_svvh_generic_type of port_mult2_is_saturated : constant is 1; - attribute mti_svvh_generic_type of port_mult3_is_saturated : constant is 1; - attribute mti_svvh_generic_type of output_rounding : constant is 1; - attribute mti_svvh_generic_type of output_round_type : constant is 1; - attribute mti_svvh_generic_type of width_msb : constant is 1; - attribute mti_svvh_generic_type of output_round_register : constant is 1; - attribute mti_svvh_generic_type of output_round_aclr : constant is 1; - attribute mti_svvh_generic_type of output_round_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of output_round_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_rounding : constant is 1; - attribute mti_svvh_generic_type of chainout_round_register : constant is 1; - attribute mti_svvh_generic_type of chainout_round_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_round_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of chainout_round_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_round_output_register : constant is 1; - attribute mti_svvh_generic_type of chainout_round_output_aclr : constant is 1; - attribute mti_svvh_generic_type of port_output_is_overflow : constant is 1; - attribute mti_svvh_generic_type of port_chainout_sat_is_overflow : constant is 1; - attribute mti_svvh_generic_type of output_saturation : constant is 1; - attribute mti_svvh_generic_type of output_saturate_type : constant is 1; - attribute mti_svvh_generic_type of width_saturate_sign : constant is 1; - attribute mti_svvh_generic_type of output_saturate_register : constant is 1; - attribute mti_svvh_generic_type of output_saturate_aclr : constant is 1; - attribute mti_svvh_generic_type of output_saturate_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of output_saturate_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_saturation : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_register : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_output_register : constant is 1; - attribute mti_svvh_generic_type of chainout_saturate_output_aclr : constant is 1; - attribute mti_svvh_generic_type of chainout_adder : constant is 1; - attribute mti_svvh_generic_type of chainout_register : constant is 1; - attribute mti_svvh_generic_type of chainout_aclr : constant is 1; - attribute mti_svvh_generic_type of width_chainin : constant is 1; - attribute mti_svvh_generic_type of zero_chainout_output_register : constant is 1; - attribute mti_svvh_generic_type of zero_chainout_output_aclr : constant is 1; - attribute mti_svvh_generic_type of shift_mode : constant is 1; - attribute mti_svvh_generic_type of rotate_aclr : constant is 1; - attribute mti_svvh_generic_type of rotate_register : constant is 1; - attribute mti_svvh_generic_type of rotate_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of rotate_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of rotate_output_register : constant is 1; - attribute mti_svvh_generic_type of rotate_output_aclr : constant is 1; - attribute mti_svvh_generic_type of shift_right_register : constant is 1; - attribute mti_svvh_generic_type of shift_right_aclr : constant is 1; - attribute mti_svvh_generic_type of shift_right_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of shift_right_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of shift_right_output_register : constant is 1; - attribute mti_svvh_generic_type of shift_right_output_aclr : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_register : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_aclr : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_output_register : constant is 1; - attribute mti_svvh_generic_type of zero_loopback_output_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_sload_register : constant is 1; - attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_sload_pipeline_register : constant is 1; - attribute mti_svvh_generic_type of accum_sload_pipeline_aclr : constant is 1; - attribute mti_svvh_generic_type of accum_direction : constant is 1; - attribute mti_svvh_generic_type of accumulator : constant is 1; - attribute mti_svvh_generic_type of preadder_mode : constant is 1; - attribute mti_svvh_generic_type of loadconst_value : constant is 1; - attribute mti_svvh_generic_type of width_coef : constant is 1; - attribute mti_svvh_generic_type of loadconst_control_register : constant is 1; - attribute mti_svvh_generic_type of loadconst_control_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel0_register : constant is 1; - attribute mti_svvh_generic_type of coefsel1_register : constant is 1; - attribute mti_svvh_generic_type of coefsel2_register : constant is 1; - attribute mti_svvh_generic_type of coefsel3_register : constant is 1; - attribute mti_svvh_generic_type of coefsel0_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel1_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel2_aclr : constant is 1; - attribute mti_svvh_generic_type of coefsel3_aclr : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1; - attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1; - attribute mti_svvh_generic_type of systolic_delay1 : constant is 1; - attribute mti_svvh_generic_type of systolic_delay3 : constant is 1; - attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1; - attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1; - attribute mti_svvh_generic_type of coef0_0 : constant is 1; - attribute mti_svvh_generic_type of coef0_1 : constant is 1; - attribute mti_svvh_generic_type of coef0_2 : constant is 1; - attribute mti_svvh_generic_type of coef0_3 : constant is 1; - attribute mti_svvh_generic_type of coef0_4 : constant is 1; - attribute mti_svvh_generic_type of coef0_5 : constant is 1; - attribute mti_svvh_generic_type of coef0_6 : constant is 1; - attribute mti_svvh_generic_type of coef0_7 : constant is 1; - attribute mti_svvh_generic_type of coef1_0 : constant is 1; - attribute mti_svvh_generic_type of coef1_1 : constant is 1; - attribute mti_svvh_generic_type of coef1_2 : constant is 1; - attribute mti_svvh_generic_type of coef1_3 : constant is 1; - attribute mti_svvh_generic_type of coef1_4 : constant is 1; - attribute mti_svvh_generic_type of coef1_5 : constant is 1; - attribute mti_svvh_generic_type of coef1_6 : constant is 1; - attribute mti_svvh_generic_type of coef1_7 : constant is 1; - attribute mti_svvh_generic_type of coef2_0 : constant is 1; - attribute mti_svvh_generic_type of coef2_1 : constant is 1; - attribute mti_svvh_generic_type of coef2_2 : constant is 1; - attribute mti_svvh_generic_type of coef2_3 : constant is 1; - attribute mti_svvh_generic_type of coef2_4 : constant is 1; - attribute mti_svvh_generic_type of coef2_5 : constant is 1; - attribute mti_svvh_generic_type of coef2_6 : constant is 1; - attribute mti_svvh_generic_type of coef2_7 : constant is 1; - attribute mti_svvh_generic_type of coef3_0 : constant is 1; - attribute mti_svvh_generic_type of coef3_1 : constant is 1; - attribute mti_svvh_generic_type of coef3_2 : constant is 1; - attribute mti_svvh_generic_type of coef3_3 : constant is 1; - attribute mti_svvh_generic_type of coef3_4 : constant is 1; - attribute mti_svvh_generic_type of coef3_5 : constant is 1; - attribute mti_svvh_generic_type of coef3_6 : constant is 1; - attribute mti_svvh_generic_type of coef3_7 : constant is 1; - attribute mti_svvh_generic_type of output_register : constant is 1; - attribute mti_svvh_generic_type of output_aclr : constant is 1; - attribute mti_svvh_generic_type of extra_latency : constant is 1; - attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1; - attribute mti_svvh_generic_type of dsp_block_balancing : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of int_width_c : constant is 3; - attribute mti_svvh_generic_type of int_width_preadder : constant is 3; - attribute mti_svvh_generic_type of int_width_a : constant is 3; - attribute mti_svvh_generic_type of int_width_b : constant is 3; - attribute mti_svvh_generic_type of int_width_multiply_b : constant is 3; - attribute mti_svvh_generic_type of int_width_result : constant is 3; - attribute mti_svvh_generic_type of mult_b_pre_width : constant is 3; - attribute mti_svvh_generic_type of int_mult_diff_bit : constant is 3; - attribute mti_svvh_generic_type of int_mult_diff_bit_loopbk : constant is 3; - attribute mti_svvh_generic_type of sat_ini_value : constant is 3; - attribute mti_svvh_generic_type of round_position : constant is 3; - attribute mti_svvh_generic_type of chainout_round_position : constant is 3; - attribute mti_svvh_generic_type of saturation_position : constant is 3; - attribute mti_svvh_generic_type of chainout_saturation_position : constant is 3; - attribute mti_svvh_generic_type of result_msb_stxiii : constant is 3; - attribute mti_svvh_generic_type of result_msb : constant is 3; - attribute mti_svvh_generic_type of shift_partition : constant is 3; - attribute mti_svvh_generic_type of shift_msb : constant is 3; - attribute mti_svvh_generic_type of sat_msb : constant is 3; - attribute mti_svvh_generic_type of chainout_sat_msb : constant is 3; - attribute mti_svvh_generic_type of chainout_input_a : constant is 3; - attribute mti_svvh_generic_type of chainout_input_b : constant is 3; - attribute mti_svvh_generic_type of mult_res_pad : constant is 3; - attribute mti_svvh_generic_type of result_pad : constant is 3; - attribute mti_svvh_generic_type of result_stxiii_pad : constant is 3; - attribute mti_svvh_generic_type of loopback_input_pad : constant is 3; - attribute mti_svvh_generic_type of loopback_lower_bound : constant is 3; - attribute mti_svvh_generic_type of accum_width : constant is 3; - attribute mti_svvh_generic_type of feedback_width : constant is 3; - attribute mti_svvh_generic_type of lower_range : constant is 3; - attribute mti_svvh_generic_type of addsub1_clr : constant is 3; - attribute mti_svvh_generic_type of addsub3_clr : constant is 3; - attribute mti_svvh_generic_type of lsb_position : constant is 3; - attribute mti_svvh_generic_type of extra_sign_bit_width : constant is 3; - attribute mti_svvh_generic_type of bit_position : constant is 3; -end altmult_add; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altparallel_flash_loader/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altparallel_flash_loader/_primary.dat deleted file mode 100644 index 0947b54..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altparallel_flash_loader/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altparallel_flash_loader/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altparallel_flash_loader/_primary.dbs deleted file mode 100644 index 252749a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altparallel_flash_loader/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altparallel_flash_loader/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altparallel_flash_loader/_primary.vhd deleted file mode 100644 index 43f7c62..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altparallel_flash_loader/_primary.vhd +++ /dev/null @@ -1,128 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altparallel_flash_loader is - generic( - EXTRA_ADDR_BYTE : integer := 0; - FEATURES_CFG : integer := 1; - PAGE_CLK_DIVISOR: integer := 1; - BURST_MODE_SPANSION: integer := 0; - ENHANCED_FLASH_PROGRAMMING: integer := 0; - FLASH_ECC_CHECKBOX: integer := 0; - FLASH_NRESET_COUNTER: integer := 1; - PAGE_MODE : integer := 0; - NRB_ADDR : integer := 65667072; - BURST_MODE : integer := 0; - SAFE_MODE_REVERT_ADDR: integer := 0; - US_UNIT_COUNTER : integer := 1; - FIFO_SIZE : integer := 16; - CONF_DATA_WIDTH : integer := 1; - CONF_WAIT_TIMER_WIDTH: integer := 14; - NFLASH_MFC : string := "NUMONYX"; - OPTION_BITS_START_ADDRESS: integer := 0; - SAFE_MODE_RETRY : integer := 1; - DCLK_DIVISOR : integer := 1; - FLASH_TYPE : string := "CFI_FLASH"; - N_FLASH : integer := 1; - TRISTATE_CHECKBOX: integer := 0; - QFLASH_MFC : string := "ALTERA"; - FEATURES_PGM : integer := 1; - DISABLE_CRC_CHECKBOX: integer := 0; - FLASH_DATA_WIDTH: integer := 16; - RSU_WATCHDOG_COUNTER: integer := 100000000; - PFL_RSU_WATCHDOG_ENABLED: integer := 0; - SAFE_MODE_HALT : integer := 0; - ADDR_WIDTH : integer := 20; - NAND_SIZE : integer := 67108864; - NORMAL_MODE : integer := 1; - FLASH_NRESET_CHECKBOX: integer := 0; - SAFE_MODE_REVERT: integer := 0; - LPM_TYPE : string := "ALTPARALLEL_FLASH_LOADER"; - AUTO_RESTART : string := "OFF"; - CLK_DIVISOR : integer := 1; - BURST_MODE_INTEL: integer := 0; - BURST_MODE_NUMONYX: integer := 0; - DECOMPRESSOR_MODE: string := "NONE"; - PFL_QUAD_IO_FLASH_IR_BITS: integer := 8; - PFL_CFI_FLASH_IR_BITS: integer := 5; - PFL_NAND_FLASH_IR_BITS: integer := 4; - N_FLASH_BITS : integer := 4 - ); - port( - flash_nce : out vl_logic_vector; - fpga_data : out vl_logic_vector; - fpga_dclk : out vl_logic; - fpga_nstatus : in vl_logic; - flash_ale : out vl_logic; - pfl_clk : in vl_logic; - fpga_nconfig : out vl_logic; - flash_io2 : inout vl_logic_vector; - flash_sck : out vl_logic_vector; - flash_noe : out vl_logic; - flash_nwe : out vl_logic; - pfl_watchdog_error: out vl_logic; - pfl_reset_watchdog: in vl_logic; - fpga_conf_done : in vl_logic; - flash_rdy : in vl_logic; - pfl_flash_access_granted: in vl_logic; - pfl_nreconfigure: in vl_logic; - flash_cle : out vl_logic; - flash_nreset : out vl_logic; - flash_io0 : inout vl_logic_vector; - pfl_nreset : in vl_logic; - flash_data : inout vl_logic_vector; - flash_io1 : inout vl_logic_vector; - flash_nadv : out vl_logic; - flash_clk : out vl_logic; - flash_io3 : inout vl_logic_vector; - flash_io : inout vl_logic_vector(7 downto 0); - flash_addr : out vl_logic_vector; - pfl_flash_access_request: out vl_logic; - flash_ncs : out vl_logic_vector; - fpga_pgm : in vl_logic_vector(2 downto 0) - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of EXTRA_ADDR_BYTE : constant is 1; - attribute mti_svvh_generic_type of FEATURES_CFG : constant is 1; - attribute mti_svvh_generic_type of PAGE_CLK_DIVISOR : constant is 1; - attribute mti_svvh_generic_type of BURST_MODE_SPANSION : constant is 1; - attribute mti_svvh_generic_type of ENHANCED_FLASH_PROGRAMMING : constant is 1; - attribute mti_svvh_generic_type of FLASH_ECC_CHECKBOX : constant is 1; - attribute mti_svvh_generic_type of FLASH_NRESET_COUNTER : constant is 1; - attribute mti_svvh_generic_type of PAGE_MODE : constant is 1; - attribute mti_svvh_generic_type of NRB_ADDR : constant is 1; - attribute mti_svvh_generic_type of BURST_MODE : constant is 1; - attribute mti_svvh_generic_type of SAFE_MODE_REVERT_ADDR : constant is 1; - attribute mti_svvh_generic_type of US_UNIT_COUNTER : constant is 1; - attribute mti_svvh_generic_type of FIFO_SIZE : constant is 1; - attribute mti_svvh_generic_type of CONF_DATA_WIDTH : constant is 1; - attribute mti_svvh_generic_type of CONF_WAIT_TIMER_WIDTH : constant is 1; - attribute mti_svvh_generic_type of NFLASH_MFC : constant is 1; - attribute mti_svvh_generic_type of OPTION_BITS_START_ADDRESS : constant is 1; - attribute mti_svvh_generic_type of SAFE_MODE_RETRY : constant is 1; - attribute mti_svvh_generic_type of DCLK_DIVISOR : constant is 1; - attribute mti_svvh_generic_type of FLASH_TYPE : constant is 1; - attribute mti_svvh_generic_type of N_FLASH : constant is 1; - attribute mti_svvh_generic_type of TRISTATE_CHECKBOX : constant is 1; - attribute mti_svvh_generic_type of QFLASH_MFC : constant is 1; - attribute mti_svvh_generic_type of FEATURES_PGM : constant is 1; - attribute mti_svvh_generic_type of DISABLE_CRC_CHECKBOX : constant is 1; - attribute mti_svvh_generic_type of FLASH_DATA_WIDTH : constant is 1; - attribute mti_svvh_generic_type of RSU_WATCHDOG_COUNTER : constant is 1; - attribute mti_svvh_generic_type of PFL_RSU_WATCHDOG_ENABLED : constant is 1; - attribute mti_svvh_generic_type of SAFE_MODE_HALT : constant is 1; - attribute mti_svvh_generic_type of ADDR_WIDTH : constant is 1; - attribute mti_svvh_generic_type of NAND_SIZE : constant is 1; - attribute mti_svvh_generic_type of NORMAL_MODE : constant is 1; - attribute mti_svvh_generic_type of FLASH_NRESET_CHECKBOX : constant is 1; - attribute mti_svvh_generic_type of SAFE_MODE_REVERT : constant is 1; - attribute mti_svvh_generic_type of LPM_TYPE : constant is 1; - attribute mti_svvh_generic_type of AUTO_RESTART : constant is 1; - attribute mti_svvh_generic_type of CLK_DIVISOR : constant is 1; - attribute mti_svvh_generic_type of BURST_MODE_INTEL : constant is 1; - attribute mti_svvh_generic_type of BURST_MODE_NUMONYX : constant is 1; - attribute mti_svvh_generic_type of DECOMPRESSOR_MODE : constant is 1; - attribute mti_svvh_generic_type of PFL_QUAD_IO_FLASH_IR_BITS : constant is 1; - attribute mti_svvh_generic_type of PFL_CFI_FLASH_IR_BITS : constant is 1; - attribute mti_svvh_generic_type of PFL_NAND_FLASH_IR_BITS : constant is 1; - attribute mti_svvh_generic_type of N_FLASH_BITS : constant is 1; -end altparallel_flash_loader; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altpll/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altpll/_primary.dat deleted file mode 100644 index 56adf5e..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altpll/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altpll/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altpll/_primary.dbs deleted file mode 100644 index bcde1a3..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altpll/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altpll/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altpll/_primary.vhd deleted file mode 100644 index 6c92578..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altpll/_primary.vhd +++ /dev/null @@ -1,764 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altpll is - generic( - intended_device_family: string := "Stratix"; - operation_mode : string := "NORMAL"; - pll_type : string := "AUTO"; - qualify_conf_done: string := "OFF"; - compensate_clock: string := "CLK0"; - scan_chain : string := "LONG"; - primary_clock : string := "inclk0"; - inclk0_input_frequency: integer := 1000; - inclk1_input_frequency: integer := 0; - gate_lock_signal: string := "NO"; - gate_lock_counter: integer := 0; - lock_high : integer := 1; - lock_low : integer := 0; - valid_lock_multiplier: integer := 1; - invalid_lock_multiplier: integer := 5; - switch_over_type: string := "AUTO"; - switch_over_on_lossclk: string := "OFF"; - switch_over_on_gated_lock: string := "OFF"; - enable_switch_over_counter: string := "OFF"; - switch_over_counter: integer := 0; - feedback_source : string := "EXTCLK0"; - bandwidth : integer := 0; - bandwidth_type : string := "UNUSED"; - lpm_hint : string := "UNUSED"; - spread_frequency: integer := 0; - down_spread : string := "0.0"; - self_reset_on_gated_loss_lock: string := "OFF"; - self_reset_on_loss_lock: string := "OFF"; - lock_window_ui : string := "0.05"; - width_clock : integer := 6; - width_phasecounterselect: integer := 4; - charge_pump_current_bits: integer := 9999; - loop_filter_c_bits: integer := 9999; - loop_filter_r_bits: integer := 9999; - scan_chain_mif_file: string := "UNUSED"; - simulation_type : string := "functional"; - source_is_pll : string := "off"; - skip_vco : string := "off"; - clk9_multiply_by: integer := 1; - clk8_multiply_by: integer := 1; - clk7_multiply_by: integer := 1; - clk6_multiply_by: integer := 1; - clk5_multiply_by: integer := 1; - clk4_multiply_by: integer := 1; - clk3_multiply_by: integer := 1; - clk2_multiply_by: integer := 1; - clk1_multiply_by: integer := 1; - clk0_multiply_by: integer := 1; - clk9_divide_by : integer := 1; - clk8_divide_by : integer := 1; - clk7_divide_by : integer := 1; - clk6_divide_by : integer := 1; - clk5_divide_by : integer := 1; - clk4_divide_by : integer := 1; - clk3_divide_by : integer := 1; - clk2_divide_by : integer := 1; - clk1_divide_by : integer := 1; - clk0_divide_by : integer := 1; - clk9_phase_shift: string := "0"; - clk8_phase_shift: string := "0"; - clk7_phase_shift: string := "0"; - clk6_phase_shift: string := "0"; - clk5_phase_shift: string := "0"; - clk4_phase_shift: string := "0"; - clk3_phase_shift: string := "0"; - clk2_phase_shift: string := "0"; - clk1_phase_shift: string := "0"; - clk0_phase_shift: string := "0"; - clk5_time_delay : string := "0"; - clk4_time_delay : string := "0"; - clk3_time_delay : string := "0"; - clk2_time_delay : string := "0"; - clk1_time_delay : string := "0"; - clk0_time_delay : string := "0"; - clk9_duty_cycle : integer := 50; - clk8_duty_cycle : integer := 50; - clk7_duty_cycle : integer := 50; - clk6_duty_cycle : integer := 50; - clk5_duty_cycle : integer := 50; - clk4_duty_cycle : integer := 50; - clk3_duty_cycle : integer := 50; - clk2_duty_cycle : integer := 50; - clk1_duty_cycle : integer := 50; - clk0_duty_cycle : integer := 50; - clk9_use_even_counter_mode: string := "OFF"; - clk8_use_even_counter_mode: string := "OFF"; - clk7_use_even_counter_mode: string := "OFF"; - clk6_use_even_counter_mode: string := "OFF"; - clk5_use_even_counter_mode: string := "OFF"; - clk4_use_even_counter_mode: string := "OFF"; - clk3_use_even_counter_mode: string := "OFF"; - clk2_use_even_counter_mode: string := "OFF"; - clk1_use_even_counter_mode: string := "OFF"; - clk0_use_even_counter_mode: string := "OFF"; - clk9_use_even_counter_value: string := "OFF"; - clk8_use_even_counter_value: string := "OFF"; - clk7_use_even_counter_value: string := "OFF"; - clk6_use_even_counter_value: string := "OFF"; - clk5_use_even_counter_value: string := "OFF"; - clk4_use_even_counter_value: string := "OFF"; - clk3_use_even_counter_value: string := "OFF"; - clk2_use_even_counter_value: string := "OFF"; - clk1_use_even_counter_value: string := "OFF"; - clk0_use_even_counter_value: string := "OFF"; - clk2_output_frequency: integer := 0; - clk1_output_frequency: integer := 0; - clk0_output_frequency: integer := 0; - extclk3_multiply_by: integer := 1; - extclk2_multiply_by: integer := 1; - extclk1_multiply_by: integer := 1; - extclk0_multiply_by: integer := 1; - extclk3_divide_by: integer := 1; - extclk2_divide_by: integer := 1; - extclk1_divide_by: integer := 1; - extclk0_divide_by: integer := 1; - extclk3_phase_shift: string := "0"; - extclk2_phase_shift: string := "0"; - extclk1_phase_shift: string := "0"; - extclk0_phase_shift: string := "0"; - extclk3_time_delay: string := "0"; - extclk2_time_delay: string := "0"; - extclk1_time_delay: string := "0"; - extclk0_time_delay: string := "0"; - extclk3_duty_cycle: integer := 50; - extclk2_duty_cycle: integer := 50; - extclk1_duty_cycle: integer := 50; - extclk0_duty_cycle: integer := 50; - vco_multiply_by : integer := 0; - vco_divide_by : integer := 0; - sclkout0_phase_shift: string := "0"; - sclkout1_phase_shift: string := "0"; - dpa_multiply_by : integer := 0; - dpa_divide_by : integer := 0; - dpa_divider : integer := 0; - vco_min : integer := 0; - vco_max : integer := 0; - vco_center : integer := 0; - pfd_min : integer := 0; - pfd_max : integer := 0; - m_initial : integer := 1; - m : integer := 0; - n : integer := 1; - m2 : integer := 1; - n2 : integer := 1; - ss : integer := 0; - l0_high : integer := 1; - l1_high : integer := 1; - g0_high : integer := 1; - g1_high : integer := 1; - g2_high : integer := 1; - g3_high : integer := 1; - e0_high : integer := 1; - e1_high : integer := 1; - e2_high : integer := 1; - e3_high : integer := 1; - l0_low : integer := 1; - l1_low : integer := 1; - g0_low : integer := 1; - g1_low : integer := 1; - g2_low : integer := 1; - g3_low : integer := 1; - e0_low : integer := 1; - e1_low : integer := 1; - e2_low : integer := 1; - e3_low : integer := 1; - l0_initial : integer := 1; - l1_initial : integer := 1; - g0_initial : integer := 1; - g1_initial : integer := 1; - g2_initial : integer := 1; - g3_initial : integer := 1; - e0_initial : integer := 1; - e1_initial : integer := 1; - e2_initial : integer := 1; - e3_initial : integer := 1; - l0_mode : string := "bypass"; - l1_mode : string := "bypass"; - g0_mode : string := "bypass"; - g1_mode : string := "bypass"; - g2_mode : string := "bypass"; - g3_mode : string := "bypass"; - e0_mode : string := "bypass"; - e1_mode : string := "bypass"; - e2_mode : string := "bypass"; - e3_mode : string := "bypass"; - l0_ph : integer := 0; - l1_ph : integer := 0; - g0_ph : integer := 0; - g1_ph : integer := 0; - g2_ph : integer := 0; - g3_ph : integer := 0; - e0_ph : integer := 0; - e1_ph : integer := 0; - e2_ph : integer := 0; - e3_ph : integer := 0; - m_ph : integer := 0; - l0_time_delay : integer := 0; - l1_time_delay : integer := 0; - g0_time_delay : integer := 0; - g1_time_delay : integer := 0; - g2_time_delay : integer := 0; - g3_time_delay : integer := 0; - e0_time_delay : integer := 0; - e1_time_delay : integer := 0; - e2_time_delay : integer := 0; - e3_time_delay : integer := 0; - m_time_delay : integer := 0; - n_time_delay : integer := 0; - extclk3_counter : string := "e3"; - extclk2_counter : string := "e2"; - extclk1_counter : string := "e1"; - extclk0_counter : string := "e0"; - clk9_counter : string := "c9"; - clk8_counter : string := "c8"; - clk7_counter : string := "c7"; - clk6_counter : string := "c6"; - clk5_counter : string := "l1"; - clk4_counter : string := "l0"; - clk3_counter : string := "g3"; - clk2_counter : string := "g2"; - clk1_counter : string := "g1"; - clk0_counter : string := "g0"; - enable0_counter : string := "l0"; - enable1_counter : string := "l0"; - charge_pump_current: integer := 2; - loop_filter_r : string := "1.0"; - loop_filter_c : integer := 5; - vco_post_scale : integer := 0; - vco_frequency_control: string := "AUTO"; - vco_phase_shift_step: integer := 0; - lpm_type : string := "altpll"; - port_clkena0 : string := "PORT_CONNECTIVITY"; - port_clkena1 : string := "PORT_CONNECTIVITY"; - port_clkena2 : string := "PORT_CONNECTIVITY"; - port_clkena3 : string := "PORT_CONNECTIVITY"; - port_clkena4 : string := "PORT_CONNECTIVITY"; - port_clkena5 : string := "PORT_CONNECTIVITY"; - port_extclkena0 : string := "PORT_CONNECTIVITY"; - port_extclkena1 : string := "PORT_CONNECTIVITY"; - port_extclkena2 : string := "PORT_CONNECTIVITY"; - port_extclkena3 : string := "PORT_CONNECTIVITY"; - port_extclk0 : string := "PORT_CONNECTIVITY"; - port_extclk1 : string := "PORT_CONNECTIVITY"; - port_extclk2 : string := "PORT_CONNECTIVITY"; - port_extclk3 : string := "PORT_CONNECTIVITY"; - port_clk0 : string := "PORT_CONNECTIVITY"; - port_clk1 : string := "PORT_CONNECTIVITY"; - port_clk2 : string := "PORT_CONNECTIVITY"; - port_clk3 : string := "PORT_CONNECTIVITY"; - port_clk4 : string := "PORT_CONNECTIVITY"; - port_clk5 : string := "PORT_CONNECTIVITY"; - port_clk6 : string := "PORT_CONNECTIVITY"; - port_clk7 : string := "PORT_CONNECTIVITY"; - port_clk8 : string := "PORT_CONNECTIVITY"; - port_clk9 : string := "PORT_CONNECTIVITY"; - port_scandata : string := "PORT_CONNECTIVITY"; - port_scandataout: string := "PORT_CONNECTIVITY"; - port_scandone : string := "PORT_CONNECTIVITY"; - port_sclkout1 : string := "PORT_CONNECTIVITY"; - port_sclkout0 : string := "PORT_CONNECTIVITY"; - port_clkbad0 : string := "PORT_CONNECTIVITY"; - port_clkbad1 : string := "PORT_CONNECTIVITY"; - port_activeclock: string := "PORT_CONNECTIVITY"; - port_clkloss : string := "PORT_CONNECTIVITY"; - port_inclk1 : string := "PORT_CONNECTIVITY"; - port_inclk0 : string := "PORT_CONNECTIVITY"; - port_fbin : string := "PORT_CONNECTIVITY"; - port_fbout : string := "PORT_CONNECTIVITY"; - port_pllena : string := "PORT_CONNECTIVITY"; - port_clkswitch : string := "PORT_CONNECTIVITY"; - port_areset : string := "PORT_CONNECTIVITY"; - port_pfdena : string := "PORT_CONNECTIVITY"; - port_scanclk : string := "PORT_CONNECTIVITY"; - port_scanaclr : string := "PORT_CONNECTIVITY"; - port_scanread : string := "PORT_CONNECTIVITY"; - port_scanwrite : string := "PORT_CONNECTIVITY"; - port_enable0 : string := "PORT_CONNECTIVITY"; - port_enable1 : string := "PORT_CONNECTIVITY"; - port_locked : string := "PORT_CONNECTIVITY"; - port_configupdate: string := "PORT_CONNECTIVITY"; - port_phasecounterselect: string := "PORT_CONNECTIVITY"; - port_phasedone : string := "PORT_CONNECTIVITY"; - port_phasestep : string := "PORT_CONNECTIVITY"; - port_phaseupdown: string := "PORT_CONNECTIVITY"; - port_vcooverrange: string := "PORT_CONNECTIVITY"; - port_vcounderrange: string := "PORT_CONNECTIVITY"; - port_scanclkena : string := "PORT_CONNECTIVITY"; - using_fbmimicbidir_port: string := "ON"; - c0_high : integer := 1; - c1_high : integer := 1; - c2_high : integer := 1; - c3_high : integer := 1; - c4_high : integer := 1; - c5_high : integer := 1; - c6_high : integer := 1; - c7_high : integer := 1; - c8_high : integer := 1; - c9_high : integer := 1; - c0_low : integer := 1; - c1_low : integer := 1; - c2_low : integer := 1; - c3_low : integer := 1; - c4_low : integer := 1; - c5_low : integer := 1; - c6_low : integer := 1; - c7_low : integer := 1; - c8_low : integer := 1; - c9_low : integer := 1; - c0_initial : integer := 1; - c1_initial : integer := 1; - c2_initial : integer := 1; - c3_initial : integer := 1; - c4_initial : integer := 1; - c5_initial : integer := 1; - c6_initial : integer := 1; - c7_initial : integer := 1; - c8_initial : integer := 1; - c9_initial : integer := 1; - c0_mode : string := "bypass"; - c1_mode : string := "bypass"; - c2_mode : string := "bypass"; - c3_mode : string := "bypass"; - c4_mode : string := "bypass"; - c5_mode : string := "bypass"; - c6_mode : string := "bypass"; - c7_mode : string := "bypass"; - c8_mode : string := "bypass"; - c9_mode : string := "bypass"; - c0_ph : integer := 0; - c1_ph : integer := 0; - c2_ph : integer := 0; - c3_ph : integer := 0; - c4_ph : integer := 0; - c5_ph : integer := 0; - c6_ph : integer := 0; - c7_ph : integer := 0; - c8_ph : integer := 0; - c9_ph : integer := 0; - c1_use_casc_in : string := "off"; - c2_use_casc_in : string := "off"; - c3_use_casc_in : string := "off"; - c4_use_casc_in : string := "off"; - c5_use_casc_in : string := "off"; - c6_use_casc_in : string := "off"; - c7_use_casc_in : string := "off"; - c8_use_casc_in : string := "off"; - c9_use_casc_in : string := "off"; - m_test_source : integer := 5; - c0_test_source : integer := 5; - c1_test_source : integer := 5; - c2_test_source : integer := 5; - c3_test_source : integer := 5; - c4_test_source : integer := 5; - c5_test_source : integer := 5; - c6_test_source : integer := 5; - c7_test_source : integer := 5; - c8_test_source : integer := 5; - c9_test_source : integer := 5; - sim_gate_lock_device_behavior: string := "OFF" - ); - port( - inclk : in vl_logic_vector(1 downto 0); - fbin : in vl_logic; - pllena : in vl_logic; - clkswitch : in vl_logic; - areset : in vl_logic; - pfdena : in vl_logic; - clkena : in vl_logic_vector(5 downto 0); - extclkena : in vl_logic_vector(3 downto 0); - scanclk : in vl_logic; - scanaclr : in vl_logic; - scanclkena : in vl_logic; - scanread : in vl_logic; - scanwrite : in vl_logic; - scandata : in vl_logic; - phasecounterselect: in vl_logic_vector; - phaseupdown : in vl_logic; - phasestep : in vl_logic; - configupdate : in vl_logic; - fbmimicbidir : inout vl_logic; - clk : out vl_logic_vector; - extclk : out vl_logic_vector(3 downto 0); - clkbad : out vl_logic_vector(1 downto 0); - enable0 : out vl_logic; - enable1 : out vl_logic; - activeclock : out vl_logic; - clkloss : out vl_logic; - locked : out vl_logic; - scandataout : out vl_logic; - scandone : out vl_logic; - sclkout0 : out vl_logic; - sclkout1 : out vl_logic; - phasedone : out vl_logic; - vcooverrange : out vl_logic; - vcounderrange : out vl_logic; - fbout : out vl_logic; - fref : out vl_logic; - icdrclk : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of pll_type : constant is 1; - attribute mti_svvh_generic_type of qualify_conf_done : constant is 1; - attribute mti_svvh_generic_type of compensate_clock : constant is 1; - attribute mti_svvh_generic_type of scan_chain : constant is 1; - attribute mti_svvh_generic_type of primary_clock : constant is 1; - attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1; - attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1; - attribute mti_svvh_generic_type of gate_lock_signal : constant is 1; - attribute mti_svvh_generic_type of gate_lock_counter : constant is 1; - attribute mti_svvh_generic_type of lock_high : constant is 1; - attribute mti_svvh_generic_type of lock_low : constant is 1; - attribute mti_svvh_generic_type of valid_lock_multiplier : constant is 1; - attribute mti_svvh_generic_type of invalid_lock_multiplier : constant is 1; - attribute mti_svvh_generic_type of switch_over_type : constant is 1; - attribute mti_svvh_generic_type of switch_over_on_lossclk : constant is 1; - attribute mti_svvh_generic_type of switch_over_on_gated_lock : constant is 1; - attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of switch_over_counter : constant is 1; - attribute mti_svvh_generic_type of feedback_source : constant is 1; - attribute mti_svvh_generic_type of bandwidth : constant is 1; - attribute mti_svvh_generic_type of bandwidth_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of spread_frequency : constant is 1; - attribute mti_svvh_generic_type of down_spread : constant is 1; - attribute mti_svvh_generic_type of self_reset_on_gated_loss_lock : constant is 1; - attribute mti_svvh_generic_type of self_reset_on_loss_lock : constant is 1; - attribute mti_svvh_generic_type of lock_window_ui : constant is 1; - attribute mti_svvh_generic_type of width_clock : constant is 1; - attribute mti_svvh_generic_type of width_phasecounterselect : constant is 1; - attribute mti_svvh_generic_type of charge_pump_current_bits : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c_bits : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r_bits : constant is 1; - attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1; - attribute mti_svvh_generic_type of simulation_type : constant is 1; - attribute mti_svvh_generic_type of source_is_pll : constant is 1; - attribute mti_svvh_generic_type of skip_vco : constant is 1; - attribute mti_svvh_generic_type of clk9_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk8_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk7_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk6_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk5_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1; - attribute mti_svvh_generic_type of clk9_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk8_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk7_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk6_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk5_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk4_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk3_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk2_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk1_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk0_divide_by : constant is 1; - attribute mti_svvh_generic_type of clk9_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk8_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk7_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk6_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk5_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of clk5_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk4_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk3_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk2_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk1_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk0_time_delay : constant is 1; - attribute mti_svvh_generic_type of clk9_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk8_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk7_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk6_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk5_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of clk9_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk8_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk7_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk6_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk5_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1; - attribute mti_svvh_generic_type of clk9_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk8_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk7_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk6_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk5_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1; - attribute mti_svvh_generic_type of clk2_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk1_output_frequency : constant is 1; - attribute mti_svvh_generic_type of clk0_output_frequency : constant is 1; - attribute mti_svvh_generic_type of extclk3_multiply_by : constant is 1; - attribute mti_svvh_generic_type of extclk2_multiply_by : constant is 1; - attribute mti_svvh_generic_type of extclk1_multiply_by : constant is 1; - attribute mti_svvh_generic_type of extclk0_multiply_by : constant is 1; - attribute mti_svvh_generic_type of extclk3_divide_by : constant is 1; - attribute mti_svvh_generic_type of extclk2_divide_by : constant is 1; - attribute mti_svvh_generic_type of extclk1_divide_by : constant is 1; - attribute mti_svvh_generic_type of extclk0_divide_by : constant is 1; - attribute mti_svvh_generic_type of extclk3_phase_shift : constant is 1; - attribute mti_svvh_generic_type of extclk2_phase_shift : constant is 1; - attribute mti_svvh_generic_type of extclk1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of extclk0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of extclk3_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk2_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk1_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk0_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk3_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of extclk2_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of extclk1_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of extclk0_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of vco_multiply_by : constant is 1; - attribute mti_svvh_generic_type of vco_divide_by : constant is 1; - attribute mti_svvh_generic_type of sclkout0_phase_shift : constant is 1; - attribute mti_svvh_generic_type of sclkout1_phase_shift : constant is 1; - attribute mti_svvh_generic_type of dpa_multiply_by : constant is 1; - attribute mti_svvh_generic_type of dpa_divide_by : constant is 1; - attribute mti_svvh_generic_type of dpa_divider : constant is 1; - attribute mti_svvh_generic_type of vco_min : constant is 1; - attribute mti_svvh_generic_type of vco_max : constant is 1; - attribute mti_svvh_generic_type of vco_center : constant is 1; - attribute mti_svvh_generic_type of pfd_min : constant is 1; - attribute mti_svvh_generic_type of pfd_max : constant is 1; - attribute mti_svvh_generic_type of m_initial : constant is 1; - attribute mti_svvh_generic_type of m : constant is 1; - attribute mti_svvh_generic_type of n : constant is 1; - attribute mti_svvh_generic_type of m2 : constant is 1; - attribute mti_svvh_generic_type of n2 : constant is 1; - attribute mti_svvh_generic_type of ss : constant is 1; - attribute mti_svvh_generic_type of l0_high : constant is 1; - attribute mti_svvh_generic_type of l1_high : constant is 1; - attribute mti_svvh_generic_type of g0_high : constant is 1; - attribute mti_svvh_generic_type of g1_high : constant is 1; - attribute mti_svvh_generic_type of g2_high : constant is 1; - attribute mti_svvh_generic_type of g3_high : constant is 1; - attribute mti_svvh_generic_type of e0_high : constant is 1; - attribute mti_svvh_generic_type of e1_high : constant is 1; - attribute mti_svvh_generic_type of e2_high : constant is 1; - attribute mti_svvh_generic_type of e3_high : constant is 1; - attribute mti_svvh_generic_type of l0_low : constant is 1; - attribute mti_svvh_generic_type of l1_low : constant is 1; - attribute mti_svvh_generic_type of g0_low : constant is 1; - attribute mti_svvh_generic_type of g1_low : constant is 1; - attribute mti_svvh_generic_type of g2_low : constant is 1; - attribute mti_svvh_generic_type of g3_low : constant is 1; - attribute mti_svvh_generic_type of e0_low : constant is 1; - attribute mti_svvh_generic_type of e1_low : constant is 1; - attribute mti_svvh_generic_type of e2_low : constant is 1; - attribute mti_svvh_generic_type of e3_low : constant is 1; - attribute mti_svvh_generic_type of l0_initial : constant is 1; - attribute mti_svvh_generic_type of l1_initial : constant is 1; - attribute mti_svvh_generic_type of g0_initial : constant is 1; - attribute mti_svvh_generic_type of g1_initial : constant is 1; - attribute mti_svvh_generic_type of g2_initial : constant is 1; - attribute mti_svvh_generic_type of g3_initial : constant is 1; - attribute mti_svvh_generic_type of e0_initial : constant is 1; - attribute mti_svvh_generic_type of e1_initial : constant is 1; - attribute mti_svvh_generic_type of e2_initial : constant is 1; - attribute mti_svvh_generic_type of e3_initial : constant is 1; - attribute mti_svvh_generic_type of l0_mode : constant is 1; - attribute mti_svvh_generic_type of l1_mode : constant is 1; - attribute mti_svvh_generic_type of g0_mode : constant is 1; - attribute mti_svvh_generic_type of g1_mode : constant is 1; - attribute mti_svvh_generic_type of g2_mode : constant is 1; - attribute mti_svvh_generic_type of g3_mode : constant is 1; - attribute mti_svvh_generic_type of e0_mode : constant is 1; - attribute mti_svvh_generic_type of e1_mode : constant is 1; - attribute mti_svvh_generic_type of e2_mode : constant is 1; - attribute mti_svvh_generic_type of e3_mode : constant is 1; - attribute mti_svvh_generic_type of l0_ph : constant is 1; - attribute mti_svvh_generic_type of l1_ph : constant is 1; - attribute mti_svvh_generic_type of g0_ph : constant is 1; - attribute mti_svvh_generic_type of g1_ph : constant is 1; - attribute mti_svvh_generic_type of g2_ph : constant is 1; - attribute mti_svvh_generic_type of g3_ph : constant is 1; - attribute mti_svvh_generic_type of e0_ph : constant is 1; - attribute mti_svvh_generic_type of e1_ph : constant is 1; - attribute mti_svvh_generic_type of e2_ph : constant is 1; - attribute mti_svvh_generic_type of e3_ph : constant is 1; - attribute mti_svvh_generic_type of m_ph : constant is 1; - attribute mti_svvh_generic_type of l0_time_delay : constant is 1; - attribute mti_svvh_generic_type of l1_time_delay : constant is 1; - attribute mti_svvh_generic_type of g0_time_delay : constant is 1; - attribute mti_svvh_generic_type of g1_time_delay : constant is 1; - attribute mti_svvh_generic_type of g2_time_delay : constant is 1; - attribute mti_svvh_generic_type of g3_time_delay : constant is 1; - attribute mti_svvh_generic_type of e0_time_delay : constant is 1; - attribute mti_svvh_generic_type of e1_time_delay : constant is 1; - attribute mti_svvh_generic_type of e2_time_delay : constant is 1; - attribute mti_svvh_generic_type of e3_time_delay : constant is 1; - attribute mti_svvh_generic_type of m_time_delay : constant is 1; - attribute mti_svvh_generic_type of n_time_delay : constant is 1; - attribute mti_svvh_generic_type of extclk3_counter : constant is 1; - attribute mti_svvh_generic_type of extclk2_counter : constant is 1; - attribute mti_svvh_generic_type of extclk1_counter : constant is 1; - attribute mti_svvh_generic_type of extclk0_counter : constant is 1; - attribute mti_svvh_generic_type of clk9_counter : constant is 1; - attribute mti_svvh_generic_type of clk8_counter : constant is 1; - attribute mti_svvh_generic_type of clk7_counter : constant is 1; - attribute mti_svvh_generic_type of clk6_counter : constant is 1; - attribute mti_svvh_generic_type of clk5_counter : constant is 1; - attribute mti_svvh_generic_type of clk4_counter : constant is 1; - attribute mti_svvh_generic_type of clk3_counter : constant is 1; - attribute mti_svvh_generic_type of clk2_counter : constant is 1; - attribute mti_svvh_generic_type of clk1_counter : constant is 1; - attribute mti_svvh_generic_type of clk0_counter : constant is 1; - attribute mti_svvh_generic_type of enable0_counter : constant is 1; - attribute mti_svvh_generic_type of enable1_counter : constant is 1; - attribute mti_svvh_generic_type of charge_pump_current : constant is 1; - attribute mti_svvh_generic_type of loop_filter_r : constant is 1; - attribute mti_svvh_generic_type of loop_filter_c : constant is 1; - attribute mti_svvh_generic_type of vco_post_scale : constant is 1; - attribute mti_svvh_generic_type of vco_frequency_control : constant is 1; - attribute mti_svvh_generic_type of vco_phase_shift_step : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of port_clkena0 : constant is 1; - attribute mti_svvh_generic_type of port_clkena1 : constant is 1; - attribute mti_svvh_generic_type of port_clkena2 : constant is 1; - attribute mti_svvh_generic_type of port_clkena3 : constant is 1; - attribute mti_svvh_generic_type of port_clkena4 : constant is 1; - attribute mti_svvh_generic_type of port_clkena5 : constant is 1; - attribute mti_svvh_generic_type of port_extclkena0 : constant is 1; - attribute mti_svvh_generic_type of port_extclkena1 : constant is 1; - attribute mti_svvh_generic_type of port_extclkena2 : constant is 1; - attribute mti_svvh_generic_type of port_extclkena3 : constant is 1; - attribute mti_svvh_generic_type of port_extclk0 : constant is 1; - attribute mti_svvh_generic_type of port_extclk1 : constant is 1; - attribute mti_svvh_generic_type of port_extclk2 : constant is 1; - attribute mti_svvh_generic_type of port_extclk3 : constant is 1; - attribute mti_svvh_generic_type of port_clk0 : constant is 1; - attribute mti_svvh_generic_type of port_clk1 : constant is 1; - attribute mti_svvh_generic_type of port_clk2 : constant is 1; - attribute mti_svvh_generic_type of port_clk3 : constant is 1; - attribute mti_svvh_generic_type of port_clk4 : constant is 1; - attribute mti_svvh_generic_type of port_clk5 : constant is 1; - attribute mti_svvh_generic_type of port_clk6 : constant is 1; - attribute mti_svvh_generic_type of port_clk7 : constant is 1; - attribute mti_svvh_generic_type of port_clk8 : constant is 1; - attribute mti_svvh_generic_type of port_clk9 : constant is 1; - attribute mti_svvh_generic_type of port_scandata : constant is 1; - attribute mti_svvh_generic_type of port_scandataout : constant is 1; - attribute mti_svvh_generic_type of port_scandone : constant is 1; - attribute mti_svvh_generic_type of port_sclkout1 : constant is 1; - attribute mti_svvh_generic_type of port_sclkout0 : constant is 1; - attribute mti_svvh_generic_type of port_clkbad0 : constant is 1; - attribute mti_svvh_generic_type of port_clkbad1 : constant is 1; - attribute mti_svvh_generic_type of port_activeclock : constant is 1; - attribute mti_svvh_generic_type of port_clkloss : constant is 1; - attribute mti_svvh_generic_type of port_inclk1 : constant is 1; - attribute mti_svvh_generic_type of port_inclk0 : constant is 1; - attribute mti_svvh_generic_type of port_fbin : constant is 1; - attribute mti_svvh_generic_type of port_fbout : constant is 1; - attribute mti_svvh_generic_type of port_pllena : constant is 1; - attribute mti_svvh_generic_type of port_clkswitch : constant is 1; - attribute mti_svvh_generic_type of port_areset : constant is 1; - attribute mti_svvh_generic_type of port_pfdena : constant is 1; - attribute mti_svvh_generic_type of port_scanclk : constant is 1; - attribute mti_svvh_generic_type of port_scanaclr : constant is 1; - attribute mti_svvh_generic_type of port_scanread : constant is 1; - attribute mti_svvh_generic_type of port_scanwrite : constant is 1; - attribute mti_svvh_generic_type of port_enable0 : constant is 1; - attribute mti_svvh_generic_type of port_enable1 : constant is 1; - attribute mti_svvh_generic_type of port_locked : constant is 1; - attribute mti_svvh_generic_type of port_configupdate : constant is 1; - attribute mti_svvh_generic_type of port_phasecounterselect : constant is 1; - attribute mti_svvh_generic_type of port_phasedone : constant is 1; - attribute mti_svvh_generic_type of port_phasestep : constant is 1; - attribute mti_svvh_generic_type of port_phaseupdown : constant is 1; - attribute mti_svvh_generic_type of port_vcooverrange : constant is 1; - attribute mti_svvh_generic_type of port_vcounderrange : constant is 1; - attribute mti_svvh_generic_type of port_scanclkena : constant is 1; - attribute mti_svvh_generic_type of using_fbmimicbidir_port : constant is 1; - attribute mti_svvh_generic_type of c0_high : constant is 1; - attribute mti_svvh_generic_type of c1_high : constant is 1; - attribute mti_svvh_generic_type of c2_high : constant is 1; - attribute mti_svvh_generic_type of c3_high : constant is 1; - attribute mti_svvh_generic_type of c4_high : constant is 1; - attribute mti_svvh_generic_type of c5_high : constant is 1; - attribute mti_svvh_generic_type of c6_high : constant is 1; - attribute mti_svvh_generic_type of c7_high : constant is 1; - attribute mti_svvh_generic_type of c8_high : constant is 1; - attribute mti_svvh_generic_type of c9_high : constant is 1; - attribute mti_svvh_generic_type of c0_low : constant is 1; - attribute mti_svvh_generic_type of c1_low : constant is 1; - attribute mti_svvh_generic_type of c2_low : constant is 1; - attribute mti_svvh_generic_type of c3_low : constant is 1; - attribute mti_svvh_generic_type of c4_low : constant is 1; - attribute mti_svvh_generic_type of c5_low : constant is 1; - attribute mti_svvh_generic_type of c6_low : constant is 1; - attribute mti_svvh_generic_type of c7_low : constant is 1; - attribute mti_svvh_generic_type of c8_low : constant is 1; - attribute mti_svvh_generic_type of c9_low : constant is 1; - attribute mti_svvh_generic_type of c0_initial : constant is 1; - attribute mti_svvh_generic_type of c1_initial : constant is 1; - attribute mti_svvh_generic_type of c2_initial : constant is 1; - attribute mti_svvh_generic_type of c3_initial : constant is 1; - attribute mti_svvh_generic_type of c4_initial : constant is 1; - attribute mti_svvh_generic_type of c5_initial : constant is 1; - attribute mti_svvh_generic_type of c6_initial : constant is 1; - attribute mti_svvh_generic_type of c7_initial : constant is 1; - attribute mti_svvh_generic_type of c8_initial : constant is 1; - attribute mti_svvh_generic_type of c9_initial : constant is 1; - attribute mti_svvh_generic_type of c0_mode : constant is 1; - attribute mti_svvh_generic_type of c1_mode : constant is 1; - attribute mti_svvh_generic_type of c2_mode : constant is 1; - attribute mti_svvh_generic_type of c3_mode : constant is 1; - attribute mti_svvh_generic_type of c4_mode : constant is 1; - attribute mti_svvh_generic_type of c5_mode : constant is 1; - attribute mti_svvh_generic_type of c6_mode : constant is 1; - attribute mti_svvh_generic_type of c7_mode : constant is 1; - attribute mti_svvh_generic_type of c8_mode : constant is 1; - attribute mti_svvh_generic_type of c9_mode : constant is 1; - attribute mti_svvh_generic_type of c0_ph : constant is 1; - attribute mti_svvh_generic_type of c1_ph : constant is 1; - attribute mti_svvh_generic_type of c2_ph : constant is 1; - attribute mti_svvh_generic_type of c3_ph : constant is 1; - attribute mti_svvh_generic_type of c4_ph : constant is 1; - attribute mti_svvh_generic_type of c5_ph : constant is 1; - attribute mti_svvh_generic_type of c6_ph : constant is 1; - attribute mti_svvh_generic_type of c7_ph : constant is 1; - attribute mti_svvh_generic_type of c8_ph : constant is 1; - attribute mti_svvh_generic_type of c9_ph : constant is 1; - attribute mti_svvh_generic_type of c1_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c2_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c3_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c4_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c5_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c6_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c7_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c8_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of c9_use_casc_in : constant is 1; - attribute mti_svvh_generic_type of m_test_source : constant is 1; - attribute mti_svvh_generic_type of c0_test_source : constant is 1; - attribute mti_svvh_generic_type of c1_test_source : constant is 1; - attribute mti_svvh_generic_type of c2_test_source : constant is 1; - attribute mti_svvh_generic_type of c3_test_source : constant is 1; - attribute mti_svvh_generic_type of c4_test_source : constant is 1; - attribute mti_svvh_generic_type of c5_test_source : constant is 1; - attribute mti_svvh_generic_type of c6_test_source : constant is 1; - attribute mti_svvh_generic_type of c7_test_source : constant is 1; - attribute mti_svvh_generic_type of c8_test_source : constant is 1; - attribute mti_svvh_generic_type of c9_test_source : constant is 1; - attribute mti_svvh_generic_type of sim_gate_lock_device_behavior : constant is 1; -end altpll; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altserial_flash_loader/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altserial_flash_loader/_primary.dat deleted file mode 100644 index 646f5fb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altserial_flash_loader/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altserial_flash_loader/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altserial_flash_loader/_primary.dbs deleted file mode 100644 index 4098e07..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altserial_flash_loader/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altserial_flash_loader/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altserial_flash_loader/_primary.vhd deleted file mode 100644 index edc527c..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altserial_flash_loader/_primary.vhd +++ /dev/null @@ -1,29 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altserial_flash_loader is - generic( - enhanced_mode : integer := 0; - intended_device_family: string := "Cyclone"; - enable_shared_access: string := "OFF"; - enable_quad_spi_support: integer := 0; - lpm_type : string := "ALTSERIAL_FLASH_LOADER" - ); - port( - data_in : in vl_logic_vector(3 downto 0); - noe : in vl_logic; - asmi_access_granted: in vl_logic; - data_out : out vl_logic_vector(3 downto 0); - data_oe : in vl_logic_vector(3 downto 0); - sdoin : in vl_logic; - asmi_access_request: out vl_logic; - data0out : out vl_logic; - scein : in vl_logic; - dclkin : in vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of enhanced_mode : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of enable_shared_access : constant is 1; - attribute mti_svvh_generic_type of enable_quad_spi_support : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end altserial_flash_loader; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altshift_taps/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altshift_taps/_primary.dat deleted file mode 100644 index 4f4db2c..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altshift_taps/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altshift_taps/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altshift_taps/_primary.dbs deleted file mode 100644 index 842387f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altshift_taps/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altshift_taps/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altshift_taps/_primary.vhd deleted file mode 100644 index bc24d2d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altshift_taps/_primary.vhd +++ /dev/null @@ -1,33 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altshift_taps is - generic( - number_of_taps : integer := 4; - tap_distance : integer := 3; - width : integer := 8; - power_up_state : string := "CLEARED"; - lpm_type : string := "altshift_taps"; - intended_device_family: string := "Stratix"; - lpm_hint : string := "UNUSED"; - RAM_WIDTH : vl_notype; - TOTAL_TAP_DISTANCE: vl_notype - ); - port( - shiftin : in vl_logic_vector; - clock : in vl_logic; - clken : in vl_logic; - aclr : in vl_logic; - shiftout : out vl_logic_vector; - taps : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_taps : constant is 1; - attribute mti_svvh_generic_type of tap_distance : constant is 1; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of power_up_state : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of RAM_WIDTH : constant is 3; - attribute mti_svvh_generic_type of TOTAL_TAP_DISTANCE : constant is 3; -end altshift_taps; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsource_probe/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsource_probe/_primary.dat deleted file mode 100644 index 290f36e..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsource_probe/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsource_probe/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsource_probe/_primary.dbs deleted file mode 100644 index c12fe57..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsource_probe/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsource_probe/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsource_probe/_primary.vhd deleted file mode 100644 index f7bb4d5..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsource_probe/_primary.vhd +++ /dev/null @@ -1,50 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altsource_probe is - generic( - lpm_hint : string := "UNUSED"; - sld_instance_index: integer := 0; - source_initial_value: string := "0"; - sld_ir_width : integer := 4; - probe_width : integer := 1; - source_width : integer := 1; - instance_id : string := "UNUSED"; - lpm_type : string := "altsource_probe"; - sld_auto_instance_index: string := "YES"; - SLD_NODE_INFO : integer := 4746752; - enable_metastability: string := "NO" - ); - port( - jtag_state_sdr : in vl_logic; - ir_in : in vl_logic_vector; - jtag_state_cir : in vl_logic; - jtag_state_udr : in vl_logic; - jtag_state_e1dr : in vl_logic; - source_clk : in vl_logic; - probe : in vl_logic_vector; - source : out vl_logic_vector; - ir_out : out vl_logic_vector; - jtag_state_cdr : in vl_logic; - jtag_state_tlr : in vl_logic; - tdi : in vl_logic; - jtag_state_uir : in vl_logic; - source_ena : in vl_logic; - tdo : out vl_logic; - clrn : in vl_logic; - raw_tck : in vl_logic; - usr1 : in vl_logic; - ena : in vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of sld_instance_index : constant is 1; - attribute mti_svvh_generic_type of source_initial_value : constant is 1; - attribute mti_svvh_generic_type of sld_ir_width : constant is 1; - attribute mti_svvh_generic_type of probe_width : constant is 1; - attribute mti_svvh_generic_type of source_width : constant is 1; - attribute mti_svvh_generic_type of instance_id : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of sld_auto_instance_index : constant is 1; - attribute mti_svvh_generic_type of SLD_NODE_INFO : constant is 1; - attribute mti_svvh_generic_type of enable_metastability : constant is 1; -end altsource_probe; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsqrt/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsqrt/_primary.dat deleted file mode 100644 index db3c6ff..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsqrt/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsqrt/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsqrt/_primary.dbs deleted file mode 100644 index 18509de..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsqrt/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsqrt/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsqrt/_primary.vhd deleted file mode 100644 index 01922a3..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsqrt/_primary.vhd +++ /dev/null @@ -1,27 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altsqrt is - generic( - q_port_width : integer := 1; - r_port_width : integer := 1; - width : integer := 1; - pipeline : integer := 0; - lpm_hint : string := "UNUSED"; - lpm_type : string := "altsqrt" - ); - port( - radical : in vl_logic_vector; - clk : in vl_logic; - ena : in vl_logic; - aclr : in vl_logic; - q : out vl_logic_vector; - remainder : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of q_port_width : constant is 1; - attribute mti_svvh_generic_type of r_port_width : constant is 1; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of pipeline : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end altsqrt; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsquare/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsquare/_primary.dat deleted file mode 100644 index 408f935..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsquare/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsquare/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsquare/_primary.dbs deleted file mode 100644 index 8948e5b..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsquare/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsquare/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsquare/_primary.vhd deleted file mode 100644 index 216b446..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsquare/_primary.vhd +++ /dev/null @@ -1,28 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altsquare is - generic( - data_width : integer := 1; - result_width : integer := 1; - pipeline : integer := 0; - representation : string := "UNSIGNED"; - result_alignment: string := "LSB"; - lpm_hint : string := "UNUSED"; - lpm_type : string := "altsquare" - ); - port( - data : in vl_logic_vector; - clock : in vl_logic; - ena : in vl_logic; - aclr : in vl_logic; - result : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of data_width : constant is 1; - attribute mti_svvh_generic_type of result_width : constant is 1; - attribute mti_svvh_generic_type of pipeline : constant is 1; - attribute mti_svvh_generic_type of representation : constant is 1; - attribute mti_svvh_generic_type of result_alignment : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end altsquare; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altstratixii_oct/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altstratixii_oct/_primary.dat deleted file mode 100644 index 0bf62b4..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altstratixii_oct/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altstratixii_oct/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altstratixii_oct/_primary.dbs deleted file mode 100644 index c1baa99..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altstratixii_oct/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altstratixii_oct/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altstratixii_oct/_primary.vhd deleted file mode 100644 index 930db03..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altstratixii_oct/_primary.vhd +++ /dev/null @@ -1,15 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altstratixii_oct is - generic( - lpm_type : string := "altstratixii_oct" - ); - port( - terminationenable: in vl_logic; - terminationclock: in vl_logic; - rdn : in vl_logic; - rup : in vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end altstratixii_oct; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsyncram/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsyncram/_primary.dat deleted file mode 100644 index 9c872b3..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsyncram/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsyncram/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsyncram/_primary.dbs deleted file mode 100644 index 6ac6640..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsyncram/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsyncram/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsyncram/_primary.vhd deleted file mode 100644 index 9f33aa9..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/altsyncram/_primary.vhd +++ /dev/null @@ -1,204 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity altsyncram is - generic( - width_a : integer := 1; - widthad_a : integer := 1; - numwords_a : integer := 0; - outdata_reg_a : string := "UNREGISTERED"; - address_aclr_a : string := "NONE"; - outdata_aclr_a : string := "NONE"; - indata_aclr_a : string := "NONE"; - wrcontrol_aclr_a: string := "NONE"; - byteena_aclr_a : string := "NONE"; - width_byteena_a : integer := 1; - width_b : integer := 1; - widthad_b : integer := 1; - numwords_b : integer := 0; - rdcontrol_reg_b : string := "CLOCK1"; - address_reg_b : string := "CLOCK1"; - outdata_reg_b : string := "UNREGISTERED"; - outdata_aclr_b : string := "NONE"; - rdcontrol_aclr_b: string := "NONE"; - indata_reg_b : string := "CLOCK1"; - wrcontrol_wraddress_reg_b: string := "CLOCK1"; - byteena_reg_b : string := "CLOCK1"; - indata_aclr_b : string := "NONE"; - wrcontrol_aclr_b: string := "NONE"; - address_aclr_b : string := "NONE"; - byteena_aclr_b : string := "NONE"; - width_byteena_b : integer := 1; - clock_enable_input_a: string := "NORMAL"; - clock_enable_output_a: string := "NORMAL"; - clock_enable_input_b: string := "NORMAL"; - clock_enable_output_b: string := "NORMAL"; - clock_enable_core_a: string := "USE_INPUT_CLKEN"; - clock_enable_core_b: string := "USE_INPUT_CLKEN"; - read_during_write_mode_port_a: string := "NEW_DATA_NO_NBE_READ"; - read_during_write_mode_port_b: string := "NEW_DATA_NO_NBE_READ"; - enable_ecc : string := "FALSE"; - width_eccstatus : integer := 3; - ecc_pipeline_stage_enabled: string := "FALSE"; - operation_mode : string := "BIDIR_DUAL_PORT"; - byte_size : integer := 0; - read_during_write_mode_mixed_ports: string := "DONT_CARE"; - ram_block_type : string := "AUTO"; - init_file : string := "UNUSED"; - init_file_layout: string := "UNUSED"; - maximum_depth : integer := 0; - intended_device_family: string := "Stratix"; - lpm_hint : string := "UNUSED"; - lpm_type : string := "altsyncram"; - implement_in_les: string := "OFF"; - power_up_uninitialized: string := "FALSE"; - sim_show_memory_data_in_port_b_layout: string := "OFF"; - is_lutram : vl_notype; - is_bidir_and_wrcontrol_addb_clk0: vl_notype; - is_bidir_and_wrcontrol_addb_clk1: vl_notype; - check_simultaneous_read_write: vl_notype; - dual_port_addreg_b_clk0: vl_notype; - dual_port_addreg_b_clk1: vl_notype; - i_byte_size_tmp : vl_notype; - i_lutram_read : vl_notype; - enable_mem_data_b_reading: vl_notype; - family_arriav : vl_notype; - family_stratixv : vl_notype; - family_hardcopyiv: vl_notype; - family_hardcopyiii: vl_notype; - family_hardcopyii: vl_notype; - family_arriaiigz: vl_notype; - family_arriaiigx: vl_notype; - family_stratixiii: vl_notype; - family_cycloneiii: vl_notype; - family_cyclone : vl_notype; - family_base_cycloneii: vl_notype; - family_cycloneii: vl_notype; - family_base_stratix: vl_notype; - family_base_stratixii: vl_notype; - family_has_lutram: vl_notype; - family_has_stratixv_style_ram: vl_notype; - family_has_stratixiii_style_ram: vl_notype; - family_has_m512 : vl_notype; - family_has_megaram: vl_notype; - family_has_stratixi_style_ram: vl_notype; - is_write_on_positive_edge: vl_notype; - lutram_single_port_fast_read: vl_notype; - lutram_dual_port_fast_read: vl_notype; - s3_address_aclr_a: vl_notype; - s3_address_aclr_b: vl_notype; - i_address_aclr_family_a: vl_notype; - i_address_aclr_family_b: vl_notype - ); - port( - wren_a : in vl_logic; - wren_b : in vl_logic; - rden_a : in vl_logic; - rden_b : in vl_logic; - data_a : in vl_logic_vector; - data_b : in vl_logic_vector; - address_a : in vl_logic_vector; - address_b : in vl_logic_vector; - clock0 : in vl_logic; - clock1 : in vl_logic; - clocken0 : in vl_logic; - clocken1 : in vl_logic; - clocken2 : in vl_logic; - clocken3 : in vl_logic; - aclr0 : in vl_logic; - aclr1 : in vl_logic; - byteena_a : in vl_logic_vector; - byteena_b : in vl_logic_vector; - addressstall_a : in vl_logic; - addressstall_b : in vl_logic; - q_a : out vl_logic_vector; - q_b : out vl_logic_vector; - eccstatus : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width_a : constant is 1; - attribute mti_svvh_generic_type of widthad_a : constant is 1; - attribute mti_svvh_generic_type of numwords_a : constant is 1; - attribute mti_svvh_generic_type of outdata_reg_a : constant is 1; - attribute mti_svvh_generic_type of address_aclr_a : constant is 1; - attribute mti_svvh_generic_type of outdata_aclr_a : constant is 1; - attribute mti_svvh_generic_type of indata_aclr_a : constant is 1; - attribute mti_svvh_generic_type of wrcontrol_aclr_a : constant is 1; - attribute mti_svvh_generic_type of byteena_aclr_a : constant is 1; - attribute mti_svvh_generic_type of width_byteena_a : constant is 1; - attribute mti_svvh_generic_type of width_b : constant is 1; - attribute mti_svvh_generic_type of widthad_b : constant is 1; - attribute mti_svvh_generic_type of numwords_b : constant is 1; - attribute mti_svvh_generic_type of rdcontrol_reg_b : constant is 1; - attribute mti_svvh_generic_type of address_reg_b : constant is 1; - attribute mti_svvh_generic_type of outdata_reg_b : constant is 1; - attribute mti_svvh_generic_type of outdata_aclr_b : constant is 1; - attribute mti_svvh_generic_type of rdcontrol_aclr_b : constant is 1; - attribute mti_svvh_generic_type of indata_reg_b : constant is 1; - attribute mti_svvh_generic_type of wrcontrol_wraddress_reg_b : constant is 1; - attribute mti_svvh_generic_type of byteena_reg_b : constant is 1; - attribute mti_svvh_generic_type of indata_aclr_b : constant is 1; - attribute mti_svvh_generic_type of wrcontrol_aclr_b : constant is 1; - attribute mti_svvh_generic_type of address_aclr_b : constant is 1; - attribute mti_svvh_generic_type of byteena_aclr_b : constant is 1; - attribute mti_svvh_generic_type of width_byteena_b : constant is 1; - attribute mti_svvh_generic_type of clock_enable_input_a : constant is 1; - attribute mti_svvh_generic_type of clock_enable_output_a : constant is 1; - attribute mti_svvh_generic_type of clock_enable_input_b : constant is 1; - attribute mti_svvh_generic_type of clock_enable_output_b : constant is 1; - attribute mti_svvh_generic_type of clock_enable_core_a : constant is 1; - attribute mti_svvh_generic_type of clock_enable_core_b : constant is 1; - attribute mti_svvh_generic_type of read_during_write_mode_port_a : constant is 1; - attribute mti_svvh_generic_type of read_during_write_mode_port_b : constant is 1; - attribute mti_svvh_generic_type of enable_ecc : constant is 1; - attribute mti_svvh_generic_type of width_eccstatus : constant is 1; - attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of byte_size : constant is 1; - attribute mti_svvh_generic_type of read_during_write_mode_mixed_ports : constant is 1; - attribute mti_svvh_generic_type of ram_block_type : constant is 1; - attribute mti_svvh_generic_type of init_file : constant is 1; - attribute mti_svvh_generic_type of init_file_layout : constant is 1; - attribute mti_svvh_generic_type of maximum_depth : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of implement_in_les : constant is 1; - attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1; - attribute mti_svvh_generic_type of sim_show_memory_data_in_port_b_layout : constant is 1; - attribute mti_svvh_generic_type of is_lutram : constant is 3; - attribute mti_svvh_generic_type of is_bidir_and_wrcontrol_addb_clk0 : constant is 3; - attribute mti_svvh_generic_type of is_bidir_and_wrcontrol_addb_clk1 : constant is 3; - attribute mti_svvh_generic_type of check_simultaneous_read_write : constant is 3; - attribute mti_svvh_generic_type of dual_port_addreg_b_clk0 : constant is 3; - attribute mti_svvh_generic_type of dual_port_addreg_b_clk1 : constant is 3; - attribute mti_svvh_generic_type of i_byte_size_tmp : constant is 3; - attribute mti_svvh_generic_type of i_lutram_read : constant is 3; - attribute mti_svvh_generic_type of enable_mem_data_b_reading : constant is 3; - attribute mti_svvh_generic_type of family_arriav : constant is 3; - attribute mti_svvh_generic_type of family_stratixv : constant is 3; - attribute mti_svvh_generic_type of family_hardcopyiv : constant is 3; - attribute mti_svvh_generic_type of family_hardcopyiii : constant is 3; - attribute mti_svvh_generic_type of family_hardcopyii : constant is 3; - attribute mti_svvh_generic_type of family_arriaiigz : constant is 3; - attribute mti_svvh_generic_type of family_arriaiigx : constant is 3; - attribute mti_svvh_generic_type of family_stratixiii : constant is 3; - attribute mti_svvh_generic_type of family_cycloneiii : constant is 3; - attribute mti_svvh_generic_type of family_cyclone : constant is 3; - attribute mti_svvh_generic_type of family_base_cycloneii : constant is 3; - attribute mti_svvh_generic_type of family_cycloneii : constant is 3; - attribute mti_svvh_generic_type of family_base_stratix : constant is 3; - attribute mti_svvh_generic_type of family_base_stratixii : constant is 3; - attribute mti_svvh_generic_type of family_has_lutram : constant is 3; - attribute mti_svvh_generic_type of family_has_stratixv_style_ram : constant is 3; - attribute mti_svvh_generic_type of family_has_stratixiii_style_ram : constant is 3; - attribute mti_svvh_generic_type of family_has_m512 : constant is 3; - attribute mti_svvh_generic_type of family_has_megaram : constant is 3; - attribute mti_svvh_generic_type of family_has_stratixi_style_ram : constant is 3; - attribute mti_svvh_generic_type of is_write_on_positive_edge : constant is 3; - attribute mti_svvh_generic_type of lutram_single_port_fast_read : constant is 3; - attribute mti_svvh_generic_type of lutram_dual_port_fast_read : constant is 3; - attribute mti_svvh_generic_type of s3_address_aclr_a : constant is 3; - attribute mti_svvh_generic_type of s3_address_aclr_b : constant is 3; - attribute mti_svvh_generic_type of i_address_aclr_family_a : constant is 3; - attribute mti_svvh_generic_type of i_address_aclr_family_b : constant is 3; -end altsyncram; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_m_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_m_cntr/_primary.dat deleted file mode 100644 index cbe7990..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_m_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_m_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_m_cntr/_primary.dbs deleted file mode 100644 index f89e17a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_m_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_m_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_m_cntr/_primary.vhd deleted file mode 100644 index 6f36990..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_m_cntr/_primary.vhd +++ /dev/null @@ -1,12 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity arm_m_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - initial_value : in vl_logic_vector(31 downto 0); - modulus : in vl_logic_vector(31 downto 0); - time_delay : in vl_logic_vector(31 downto 0) - ); -end arm_m_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_n_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_n_cntr/_primary.dat deleted file mode 100644 index cee68cf..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_n_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_n_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_n_cntr/_primary.dbs deleted file mode 100644 index b673deb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_n_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_n_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_n_cntr/_primary.vhd deleted file mode 100644 index 095f1c9..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_n_cntr/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity arm_n_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - modulus : in vl_logic_vector(31 downto 0) - ); -end arm_n_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_scale_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_scale_cntr/_primary.dat deleted file mode 100644 index 474eec8..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_scale_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_scale_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_scale_cntr/_primary.dbs deleted file mode 100644 index b5337ba..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_scale_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_scale_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_scale_cntr/_primary.vhd deleted file mode 100644 index eb77f21..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/arm_scale_cntr/_primary.vhd +++ /dev/null @@ -1,14 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity arm_scale_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - high : in vl_logic_vector(31 downto 0); - low : in vl_logic_vector(31 downto 0); - initial_value : in vl_logic_vector(31 downto 0); - mode : in vl_logic_vector(48 downto 1); - ph_tap : in vl_logic_vector(31 downto 0) - ); -end arm_scale_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_m_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_m_cntr/_primary.dat deleted file mode 100644 index 2ac9f54..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_m_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_m_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_m_cntr/_primary.dbs deleted file mode 100644 index ca84a95..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_m_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_m_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_m_cntr/_primary.vhd deleted file mode 100644 index ce7c2bc..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_m_cntr/_primary.vhd +++ /dev/null @@ -1,12 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity cda_m_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - initial_value : in vl_logic_vector(31 downto 0); - modulus : in vl_logic_vector(31 downto 0); - time_delay : in vl_logic_vector(31 downto 0) - ); -end cda_m_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_n_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_n_cntr/_primary.dat deleted file mode 100644 index 48b35e2..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_n_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_n_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_n_cntr/_primary.dbs deleted file mode 100644 index bb7e6b9..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_n_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_n_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_n_cntr/_primary.vhd deleted file mode 100644 index dea19f3..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_n_cntr/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity cda_n_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - modulus : in vl_logic_vector(31 downto 0) - ); -end cda_n_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_scale_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_scale_cntr/_primary.dat deleted file mode 100644 index 7ead8ba..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_scale_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_scale_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_scale_cntr/_primary.dbs deleted file mode 100644 index 39df5eb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_scale_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_scale_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_scale_cntr/_primary.vhd deleted file mode 100644 index 4cbbec8..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cda_scale_cntr/_primary.vhd +++ /dev/null @@ -1,14 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity cda_scale_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - high : in vl_logic_vector(31 downto 0); - low : in vl_logic_vector(31 downto 0); - initial_value : in vl_logic_vector(31 downto 0); - mode : in vl_logic_vector(48 downto 1); - ph_tap : in vl_logic_vector(31 downto 0) - ); -end cda_scale_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cycloneiiigl_post_divider/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cycloneiiigl_post_divider/_primary.dat deleted file mode 100644 index 104babf..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cycloneiiigl_post_divider/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cycloneiiigl_post_divider/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cycloneiiigl_post_divider/_primary.dbs deleted file mode 100644 index 2ddf1d8..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cycloneiiigl_post_divider/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cycloneiiigl_post_divider/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cycloneiiigl_post_divider/_primary.vhd deleted file mode 100644 index 38078b3..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/cycloneiiigl_post_divider/_primary.vhd +++ /dev/null @@ -1,14 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity cycloneiiigl_post_divider is - generic( - dpa_divider : integer := 1 - ); - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of dpa_divider : constant is 1; -end cycloneiiigl_post_divider; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo/_primary.dat deleted file mode 100644 index 5c33a1d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo/_primary.dbs deleted file mode 100644 index 13b738c..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo/_primary.vhd deleted file mode 100644 index 832e1ab..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo/_primary.vhd +++ /dev/null @@ -1,62 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity dcfifo is - generic( - lpm_width : integer := 1; - lpm_widthu : integer := 1; - lpm_numwords : integer := 2; - delay_rdusedw : integer := 1; - delay_wrusedw : integer := 1; - rdsync_delaypipe: integer := 0; - wrsync_delaypipe: integer := 0; - intended_device_family: string := "Stratix"; - lpm_showahead : string := "OFF"; - underflow_checking: string := "ON"; - overflow_checking: string := "ON"; - clocks_are_synchronized: string := "FALSE"; - use_eab : string := "ON"; - add_ram_output_register: string := "OFF"; - lpm_hint : string := "USE_EAB=ON"; - lpm_type : string := "dcfifo"; - add_usedw_msb_bit: string := "OFF"; - write_aclr_synch: string := "OFF"; - add_width : integer := 1; - ram_block_type : string := "AUTO" - ); - port( - data : in vl_logic_vector; - rdclk : in vl_logic; - wrclk : in vl_logic; - aclr : in vl_logic; - rdreq : in vl_logic; - wrreq : in vl_logic; - rdfull : out vl_logic; - wrfull : out vl_logic; - rdempty : out vl_logic; - wrempty : out vl_logic; - rdusedw : out vl_logic_vector; - wrusedw : out vl_logic_vector; - q : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_width : constant is 1; - attribute mti_svvh_generic_type of lpm_widthu : constant is 1; - attribute mti_svvh_generic_type of lpm_numwords : constant is 1; - attribute mti_svvh_generic_type of delay_rdusedw : constant is 1; - attribute mti_svvh_generic_type of delay_wrusedw : constant is 1; - attribute mti_svvh_generic_type of rdsync_delaypipe : constant is 1; - attribute mti_svvh_generic_type of wrsync_delaypipe : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_showahead : constant is 1; - attribute mti_svvh_generic_type of underflow_checking : constant is 1; - attribute mti_svvh_generic_type of overflow_checking : constant is 1; - attribute mti_svvh_generic_type of clocks_are_synchronized : constant is 1; - attribute mti_svvh_generic_type of use_eab : constant is 1; - attribute mti_svvh_generic_type of add_ram_output_register : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of add_usedw_msb_bit : constant is 1; - attribute mti_svvh_generic_type of write_aclr_synch : constant is 1; - attribute mti_svvh_generic_type of add_width : constant is 1; - attribute mti_svvh_generic_type of ram_block_type : constant is 1; -end dcfifo; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_async/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_async/_primary.dat deleted file mode 100644 index 102de31..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_async/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_async/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_async/_primary.dbs deleted file mode 100644 index 035f210..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_async/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_async/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_async/_primary.vhd deleted file mode 100644 index 62d1fa1..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_async/_primary.vhd +++ /dev/null @@ -1,48 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity dcfifo_async is - generic( - lpm_width : integer := 1; - lpm_widthu : integer := 1; - lpm_numwords : integer := 2; - delay_rdusedw : integer := 1; - delay_wrusedw : integer := 1; - rdsync_delaypipe: integer := 0; - wrsync_delaypipe: integer := 0; - intended_device_family: string := "Stratix"; - lpm_showahead : string := "OFF"; - underflow_checking: string := "ON"; - overflow_checking: string := "ON"; - use_eab : string := "ON"; - add_ram_output_register: string := "OFF" - ); - port( - data : in vl_logic_vector; - rdclk : in vl_logic; - wrclk : in vl_logic; - aclr : in vl_logic; - rdreq : in vl_logic; - wrreq : in vl_logic; - rdfull : out vl_logic; - wrfull : out vl_logic; - rdempty : out vl_logic; - wrempty : out vl_logic; - rdusedw : out vl_logic_vector; - wrusedw : out vl_logic_vector; - q : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_width : constant is 1; - attribute mti_svvh_generic_type of lpm_widthu : constant is 1; - attribute mti_svvh_generic_type of lpm_numwords : constant is 1; - attribute mti_svvh_generic_type of delay_rdusedw : constant is 1; - attribute mti_svvh_generic_type of delay_wrusedw : constant is 1; - attribute mti_svvh_generic_type of rdsync_delaypipe : constant is 1; - attribute mti_svvh_generic_type of wrsync_delaypipe : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_showahead : constant is 1; - attribute mti_svvh_generic_type of underflow_checking : constant is 1; - attribute mti_svvh_generic_type of overflow_checking : constant is 1; - attribute mti_svvh_generic_type of use_eab : constant is 1; - attribute mti_svvh_generic_type of add_ram_output_register : constant is 1; -end dcfifo_async; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_dffpipe/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_dffpipe/_primary.dat deleted file mode 100644 index 337641c..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_dffpipe/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_dffpipe/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_dffpipe/_primary.dbs deleted file mode 100644 index 39bc4ae..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_dffpipe/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_dffpipe/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_dffpipe/_primary.vhd deleted file mode 100644 index 08d93f8..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_dffpipe/_primary.vhd +++ /dev/null @@ -1,19 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity dcfifo_dffpipe is - generic( - lpm_delay : integer := 1; - lpm_width : integer := 64; - delay : vl_notype - ); - port( - d : in vl_logic_vector; - clock : in vl_logic; - aclr : in vl_logic; - q : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_delay : constant is 1; - attribute mti_svvh_generic_type of lpm_width : constant is 1; - attribute mti_svvh_generic_type of delay : constant is 3; -end dcfifo_dffpipe; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_fefifo/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_fefifo/_primary.dat deleted file mode 100644 index 6160252..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_fefifo/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_fefifo/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_fefifo/_primary.dbs deleted file mode 100644 index 0eb929f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_fefifo/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_fefifo/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_fefifo/_primary.vhd deleted file mode 100644 index d97883c..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_fefifo/_primary.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity dcfifo_fefifo is - generic( - lpm_widthad : integer := 1; - lpm_numwords : integer := 1; - underflow_checking: string := "ON"; - overflow_checking: string := "ON"; - lpm_mode : string := "READ" - ); - port( - usedw_in : in vl_logic_vector; - wreq : in vl_logic; - rreq : in vl_logic; - clock : in vl_logic; - aclr : in vl_logic; - empty : out vl_logic; - full : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_widthad : constant is 1; - attribute mti_svvh_generic_type of lpm_numwords : constant is 1; - attribute mti_svvh_generic_type of underflow_checking : constant is 1; - attribute mti_svvh_generic_type of overflow_checking : constant is 1; - attribute mti_svvh_generic_type of lpm_mode : constant is 1; -end dcfifo_fefifo; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_low_latency/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_low_latency/_primary.dat deleted file mode 100644 index 371b6fb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_low_latency/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_low_latency/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_low_latency/_primary.dbs deleted file mode 100644 index 8346d24..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_low_latency/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_low_latency/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_low_latency/_primary.vhd deleted file mode 100644 index 0ecc286..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_low_latency/_primary.vhd +++ /dev/null @@ -1,64 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity dcfifo_low_latency is - generic( - lpm_width : integer := 1; - lpm_widthu : integer := 1; - lpm_width_r : vl_notype; - lpm_widthu_r : vl_notype; - lpm_numwords : integer := 2; - delay_rdusedw : integer := 2; - delay_wrusedw : integer := 2; - rdsync_delaypipe: integer := 0; - wrsync_delaypipe: integer := 0; - intended_device_family: string := "Stratix"; - lpm_showahead : string := "OFF"; - underflow_checking: string := "ON"; - overflow_checking: string := "ON"; - add_usedw_msb_bit: string := "OFF"; - write_aclr_synch: string := "OFF"; - use_eab : string := "ON"; - clocks_are_synchronized: string := "FALSE"; - add_ram_output_register: string := "OFF"; - lpm_hint : string := "USE_EAB=ON"; - WIDTH_RATIO : vl_notype; - FIFO_DEPTH : vl_notype - ); - port( - data : in vl_logic_vector; - rdclk : in vl_logic; - wrclk : in vl_logic; - aclr : in vl_logic; - rdreq : in vl_logic; - wrreq : in vl_logic; - rdfull : out vl_logic; - wrfull : out vl_logic; - rdempty : out vl_logic; - wrempty : out vl_logic; - rdusedw : out vl_logic_vector; - wrusedw : out vl_logic_vector; - q : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_width : constant is 1; - attribute mti_svvh_generic_type of lpm_widthu : constant is 1; - attribute mti_svvh_generic_type of lpm_width_r : constant is 3; - attribute mti_svvh_generic_type of lpm_widthu_r : constant is 3; - attribute mti_svvh_generic_type of lpm_numwords : constant is 1; - attribute mti_svvh_generic_type of delay_rdusedw : constant is 1; - attribute mti_svvh_generic_type of delay_wrusedw : constant is 1; - attribute mti_svvh_generic_type of rdsync_delaypipe : constant is 1; - attribute mti_svvh_generic_type of wrsync_delaypipe : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_showahead : constant is 1; - attribute mti_svvh_generic_type of underflow_checking : constant is 1; - attribute mti_svvh_generic_type of overflow_checking : constant is 1; - attribute mti_svvh_generic_type of add_usedw_msb_bit : constant is 1; - attribute mti_svvh_generic_type of write_aclr_synch : constant is 1; - attribute mti_svvh_generic_type of use_eab : constant is 1; - attribute mti_svvh_generic_type of clocks_are_synchronized : constant is 1; - attribute mti_svvh_generic_type of add_ram_output_register : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of WIDTH_RATIO : constant is 3; - attribute mti_svvh_generic_type of FIFO_DEPTH : constant is 3; -end dcfifo_low_latency; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_mixed_widths/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_mixed_widths/_primary.dat deleted file mode 100644 index 6177a34..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_mixed_widths/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_mixed_widths/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_mixed_widths/_primary.dbs deleted file mode 100644 index 0f1e73a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_mixed_widths/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_mixed_widths/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_mixed_widths/_primary.vhd deleted file mode 100644 index 9eee90d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_mixed_widths/_primary.vhd +++ /dev/null @@ -1,74 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity dcfifo_mixed_widths is - generic( - lpm_width : integer := 1; - lpm_widthu : integer := 1; - lpm_width_r : vl_notype; - lpm_widthu_r : vl_notype; - lpm_numwords : integer := 2; - delay_rdusedw : integer := 1; - delay_wrusedw : integer := 1; - rdsync_delaypipe: integer := 0; - wrsync_delaypipe: integer := 0; - intended_device_family: string := "Stratix"; - lpm_showahead : string := "OFF"; - underflow_checking: string := "ON"; - overflow_checking: string := "ON"; - clocks_are_synchronized: string := "FALSE"; - use_eab : string := "ON"; - add_ram_output_register: string := "OFF"; - lpm_hint : string := "USE_EAB=ON"; - lpm_type : string := "dcfifo_mixed_widths"; - add_usedw_msb_bit: string := "OFF"; - write_aclr_synch: string := "OFF"; - add_width : integer := 1; - ram_block_type : string := "AUTO"; - FAMILY_HAS_STRATIXII_STYLE_RAM: vl_notype; - FAMILY_HAS_STRATIXIII_STYLE_RAM: vl_notype; - WRITE_SIDE_SYNCHRONIZERS: vl_notype; - READ_SIDE_SYNCHRONIZERS: vl_notype - ); - port( - data : in vl_logic_vector; - rdclk : in vl_logic; - wrclk : in vl_logic; - aclr : in vl_logic; - rdreq : in vl_logic; - wrreq : in vl_logic; - rdfull : out vl_logic; - wrfull : out vl_logic; - rdempty : out vl_logic; - wrempty : out vl_logic; - rdusedw : out vl_logic_vector; - wrusedw : out vl_logic_vector; - q : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_width : constant is 1; - attribute mti_svvh_generic_type of lpm_widthu : constant is 1; - attribute mti_svvh_generic_type of lpm_width_r : constant is 3; - attribute mti_svvh_generic_type of lpm_widthu_r : constant is 3; - attribute mti_svvh_generic_type of lpm_numwords : constant is 1; - attribute mti_svvh_generic_type of delay_rdusedw : constant is 1; - attribute mti_svvh_generic_type of delay_wrusedw : constant is 1; - attribute mti_svvh_generic_type of rdsync_delaypipe : constant is 1; - attribute mti_svvh_generic_type of wrsync_delaypipe : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_showahead : constant is 1; - attribute mti_svvh_generic_type of underflow_checking : constant is 1; - attribute mti_svvh_generic_type of overflow_checking : constant is 1; - attribute mti_svvh_generic_type of clocks_are_synchronized : constant is 1; - attribute mti_svvh_generic_type of use_eab : constant is 1; - attribute mti_svvh_generic_type of add_ram_output_register : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of add_usedw_msb_bit : constant is 1; - attribute mti_svvh_generic_type of write_aclr_synch : constant is 1; - attribute mti_svvh_generic_type of add_width : constant is 1; - attribute mti_svvh_generic_type of ram_block_type : constant is 1; - attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXII_STYLE_RAM : constant is 3; - attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXIII_STYLE_RAM : constant is 3; - attribute mti_svvh_generic_type of WRITE_SIDE_SYNCHRONIZERS : constant is 3; - attribute mti_svvh_generic_type of READ_SIDE_SYNCHRONIZERS : constant is 3; -end dcfifo_mixed_widths; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_sync/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_sync/_primary.dat deleted file mode 100644 index 36f792a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_sync/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_sync/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_sync/_primary.dbs deleted file mode 100644 index d6425a2..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_sync/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_sync/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_sync/_primary.vhd deleted file mode 100644 index 7fbeffa..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dcfifo_sync/_primary.vhd +++ /dev/null @@ -1,40 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity dcfifo_sync is - generic( - lpm_width : integer := 1; - lpm_widthu : integer := 1; - lpm_numwords : integer := 2; - intended_device_family: string := "Stratix"; - lpm_showahead : string := "OFF"; - underflow_checking: string := "ON"; - overflow_checking: string := "ON"; - use_eab : string := "ON"; - add_ram_output_register: string := "OFF" - ); - port( - data : in vl_logic_vector; - rdclk : in vl_logic; - wrclk : in vl_logic; - aclr : in vl_logic; - rdreq : in vl_logic; - wrreq : in vl_logic; - rdfull : out vl_logic; - wrfull : out vl_logic; - rdempty : out vl_logic; - wrempty : out vl_logic; - rdusedw : out vl_logic_vector; - wrusedw : out vl_logic_vector; - q : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_width : constant is 1; - attribute mti_svvh_generic_type of lpm_widthu : constant is 1; - attribute mti_svvh_generic_type of lpm_numwords : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of lpm_showahead : constant is 1; - attribute mti_svvh_generic_type of underflow_checking : constant is 1; - attribute mti_svvh_generic_type of overflow_checking : constant is 1; - attribute mti_svvh_generic_type of use_eab : constant is 1; - attribute mti_svvh_generic_type of add_ram_output_register : constant is 1; -end dcfifo_sync; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dffp/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dffp/_primary.dat deleted file mode 100644 index d07d2f3..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dffp/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dffp/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dffp/_primary.dbs deleted file mode 100644 index 9a7d329..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dffp/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dffp/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dffp/_primary.vhd deleted file mode 100644 index 8af02d1..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dffp/_primary.vhd +++ /dev/null @@ -1,12 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity dffp is - port( - q : out vl_logic; - clk : in vl_logic; - ena : in vl_logic; - d : in vl_logic; - clrn : in vl_logic; - prn : in vl_logic - ); -end dffp; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dummy_hub/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dummy_hub/_primary.dat deleted file mode 100644 index 0fddccd..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dummy_hub/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dummy_hub/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dummy_hub/_primary.dbs deleted file mode 100644 index b685b42..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dummy_hub/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dummy_hub/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dummy_hub/_primary.vhd deleted file mode 100644 index 8e28ffa..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/dummy_hub/_primary.vhd +++ /dev/null @@ -1,62 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity dummy_hub is - generic( - sld_node_ir_width: integer := 16 - ); - port( - jtag_tck : in vl_logic; - jtag_tdi : in vl_logic; - jtag_tms : in vl_logic; - jtag_usr1 : in vl_logic; - jtag_state_tlr : in vl_logic; - jtag_state_rti : in vl_logic; - jtag_state_drs : in vl_logic; - jtag_state_cdr : in vl_logic; - jtag_state_sdr : in vl_logic; - jtag_state_e1dr : in vl_logic; - jtag_state_pdr : in vl_logic; - jtag_state_e2dr : in vl_logic; - jtag_state_udr : in vl_logic; - jtag_state_irs : in vl_logic; - jtag_state_cir : in vl_logic; - jtag_state_sir : in vl_logic; - jtag_state_e1ir : in vl_logic; - jtag_state_pir : in vl_logic; - jtag_state_e2ir : in vl_logic; - jtag_state_uir : in vl_logic; - dummy_tdo : in vl_logic; - virtual_ir_out : in vl_logic_vector; - jtag_tdo : out vl_logic; - dummy_tck : out vl_logic; - dummy_tdi : out vl_logic; - dummy_tms : out vl_logic; - dummy_state_tlr : out vl_logic; - dummy_state_rti : out vl_logic; - dummy_state_drs : out vl_logic; - dummy_state_cdr : out vl_logic; - dummy_state_sdr : out vl_logic; - dummy_state_e1dr: out vl_logic; - dummy_state_pdr : out vl_logic; - dummy_state_e2dr: out vl_logic; - dummy_state_udr : out vl_logic; - dummy_state_irs : out vl_logic; - dummy_state_cir : out vl_logic; - dummy_state_sir : out vl_logic; - dummy_state_e1ir: out vl_logic; - dummy_state_pir : out vl_logic; - dummy_state_e2ir: out vl_logic; - dummy_state_uir : out vl_logic; - virtual_state_cdr: out vl_logic; - virtual_state_sdr: out vl_logic; - virtual_state_e1dr: out vl_logic; - virtual_state_pdr: out vl_logic; - virtual_state_e2dr: out vl_logic; - virtual_state_udr: out vl_logic; - virtual_state_cir: out vl_logic; - virtual_state_uir: out vl_logic; - virtual_ir_in : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of sld_node_ir_width : constant is 1; -end dummy_hub; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_rx/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_rx/_primary.dat deleted file mode 100644 index 25872b5..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_rx/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_rx/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_rx/_primary.dbs deleted file mode 100644 index 1ef7cf5..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_rx/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_rx/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_rx/_primary.vhd deleted file mode 100644 index 89ea937..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_rx/_primary.vhd +++ /dev/null @@ -1,42 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity flexible_lvds_rx is - generic( - number_of_channels: integer := 1; - deserialization_factor: integer := 4; - use_extra_ddio_register: string := "YES"; - use_extra_pll_clk: string := "NO"; - buffer_implementation: string := "RAM"; - registered_data_align_input: string := "OFF"; - use_external_pll: string := "OFF"; - registered_output: string := "ON"; - add_latency : string := "YES"; - REGISTER_WIDTH : vl_notype; - LATENCY : vl_notype; - NUM_OF_SYNC_STAGES: vl_notype - ); - port( - rx_in : in vl_logic_vector; - rx_fastclk : in vl_logic; - rx_slowclk : in vl_logic; - rx_syncclk : in vl_logic; - pll_areset : in vl_logic; - rx_data_align : in vl_logic_vector; - rx_cda_reset : in vl_logic_vector; - rx_locked : in vl_logic; - rx_out : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of use_extra_ddio_register : constant is 1; - attribute mti_svvh_generic_type of use_extra_pll_clk : constant is 1; - attribute mti_svvh_generic_type of buffer_implementation : constant is 1; - attribute mti_svvh_generic_type of registered_data_align_input : constant is 1; - attribute mti_svvh_generic_type of use_external_pll : constant is 1; - attribute mti_svvh_generic_type of registered_output : constant is 1; - attribute mti_svvh_generic_type of add_latency : constant is 1; - attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3; - attribute mti_svvh_generic_type of LATENCY : constant is 3; - attribute mti_svvh_generic_type of NUM_OF_SYNC_STAGES : constant is 3; -end flexible_lvds_rx; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_tx/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_tx/_primary.dat deleted file mode 100644 index 30bf15a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_tx/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_tx/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_tx/_primary.dbs deleted file mode 100644 index 0d7ef10..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_tx/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_tx/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_tx/_primary.vhd deleted file mode 100644 index 1c8bc90..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/flexible_lvds_tx/_primary.vhd +++ /dev/null @@ -1,40 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity flexible_lvds_tx is - generic( - number_of_channels: integer := 1; - deserialization_factor: integer := 4; - registered_input: string := "ON"; - use_new_coreclk_ckt: string := "FALSE"; - outclock_multiply_by: integer := 1; - outclock_duty_cycle: integer := 50; - outclock_divide_by: integer := 1; - use_self_generated_outclock: string := "FALSE"; - REGISTER_WIDTH : vl_notype; - DOUBLE_DESER : vl_notype; - LOAD_CNTR_MODULUS: vl_notype - ); - port( - tx_in : in vl_logic_vector; - tx_fastclk : in vl_logic; - tx_slowclk : in vl_logic; - tx_regclk : in vl_logic; - tx_locked : in vl_logic; - pll_areset : in vl_logic; - pll_outclock : in vl_logic; - tx_out : out vl_logic_vector; - tx_outclock : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of registered_input : constant is 1; - attribute mti_svvh_generic_type of use_new_coreclk_ckt : constant is 1; - attribute mti_svvh_generic_type of outclock_multiply_by : constant is 1; - attribute mti_svvh_generic_type of outclock_duty_cycle : constant is 1; - attribute mti_svvh_generic_type of outclock_divide_by : constant is 1; - attribute mti_svvh_generic_type of use_self_generated_outclock : constant is 1; - attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3; - attribute mti_svvh_generic_type of DOUBLE_DESER : constant is 3; - attribute mti_svvh_generic_type of LOAD_CNTR_MODULUS : constant is 3; -end flexible_lvds_tx; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/jtag_tap_controller/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/jtag_tap_controller/_primary.dat deleted file mode 100644 index 9a8dcf8..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/jtag_tap_controller/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/jtag_tap_controller/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/jtag_tap_controller/_primary.dbs deleted file mode 100644 index 39f8d0e..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/jtag_tap_controller/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/jtag_tap_controller/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/jtag_tap_controller/_primary.vhd deleted file mode 100644 index cb6388d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/jtag_tap_controller/_primary.vhd +++ /dev/null @@ -1,36 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity jtag_tap_controller is - generic( - ir_register_width: integer := 16 - ); - port( - tck : in vl_logic; - tms : in vl_logic; - tdi : in vl_logic; - jtag_tdo : in vl_logic; - tdo : out vl_logic; - jtag_tck : out vl_logic; - jtag_tms : out vl_logic; - jtag_tdi : out vl_logic; - jtag_state_tlr : out vl_logic; - jtag_state_rti : out vl_logic; - jtag_state_drs : out vl_logic; - jtag_state_cdr : out vl_logic; - jtag_state_sdr : out vl_logic; - jtag_state_e1dr : out vl_logic; - jtag_state_pdr : out vl_logic; - jtag_state_e2dr : out vl_logic; - jtag_state_udr : out vl_logic; - jtag_state_irs : out vl_logic; - jtag_state_cir : out vl_logic; - jtag_state_sir : out vl_logic; - jtag_state_e1ir : out vl_logic; - jtag_state_pir : out vl_logic; - jtag_state_e2ir : out vl_logic; - jtag_state_uir : out vl_logic; - jtag_usr1 : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of ir_register_width : constant is 1; -end jtag_tap_controller; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/lcell/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/lcell/_primary.dat deleted file mode 100644 index 1bf6eb3..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/lcell/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/lcell/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/lcell/_primary.dbs deleted file mode 100644 index c92f27a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/lcell/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/lcell/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/lcell/_primary.vhd deleted file mode 100644 index 56351ca..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/lcell/_primary.vhd +++ /dev/null @@ -1,8 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity lcell is - port( - \in\ : in vl_logic; - \out\ : out vl_logic - ); -end lcell; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/parallel_add/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/parallel_add/_primary.dat deleted file mode 100644 index 7082523..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/parallel_add/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/parallel_add/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/parallel_add/_primary.dbs deleted file mode 100644 index 1c71a6f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/parallel_add/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/parallel_add/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/parallel_add/_primary.vhd deleted file mode 100644 index e4c4ccc..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/parallel_add/_primary.vhd +++ /dev/null @@ -1,34 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity parallel_add is - generic( - width : integer := 4; - size : integer := 2; - widthr : integer := 4; - shift : integer := 0; - msw_subtract : string := "NO"; - representation : string := "UNSIGNED"; - pipeline : integer := 0; - result_alignment: string := "LSB"; - lpm_type : string := "parallel_add"; - lpm_hint : string := "UNUSED" - ); - port( - data : in vl_logic_vector; - clock : in vl_logic; - aclr : in vl_logic; - clken : in vl_logic; - result : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of width : constant is 1; - attribute mti_svvh_generic_type of size : constant is 1; - attribute mti_svvh_generic_type of widthr : constant is 1; - attribute mti_svvh_generic_type of shift : constant is 1; - attribute mti_svvh_generic_type of msw_subtract : constant is 1; - attribute mti_svvh_generic_type of representation : constant is 1; - attribute mti_svvh_generic_type of pipeline : constant is 1; - attribute mti_svvh_generic_type of result_alignment : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; -end parallel_add; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/pll_iobuf/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/pll_iobuf/_primary.dat deleted file mode 100644 index 4af700a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/pll_iobuf/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/pll_iobuf/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/pll_iobuf/_primary.dbs deleted file mode 100644 index 57da369..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/pll_iobuf/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/pll_iobuf/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/pll_iobuf/_primary.vhd deleted file mode 100644 index 0e7fc0e..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/pll_iobuf/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity pll_iobuf is - port( - i : in vl_logic; - oe : in vl_logic; - io : inout vl_logic; - o : out vl_logic - ); -end pll_iobuf; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/scfifo/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/scfifo/_primary.dat deleted file mode 100644 index 6cda20f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/scfifo/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/scfifo/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/scfifo/_primary.dbs deleted file mode 100644 index 9281df6..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/scfifo/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/scfifo/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/scfifo/_primary.vhd deleted file mode 100644 index dd0289b..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/scfifo/_primary.vhd +++ /dev/null @@ -1,57 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity scfifo is - generic( - lpm_width : integer := 1; - lpm_widthu : integer := 1; - lpm_numwords : integer := 2; - lpm_showahead : string := "OFF"; - lpm_type : string := "scfifo"; - lpm_hint : string := "USE_EAB=ON"; - intended_device_family: string := "Stratix"; - underflow_checking: string := "ON"; - overflow_checking: string := "ON"; - allow_rwcycle_when_full: string := "OFF"; - use_eab : string := "ON"; - add_ram_output_register: string := "OFF"; - almost_full_value: integer := 0; - almost_empty_value: integer := 0; - maximum_depth : integer := 0; - showahead_area : vl_notype; - showahead_speed : vl_notype; - legacy_speed : vl_notype - ); - port( - data : in vl_logic_vector; - clock : in vl_logic; - wrreq : in vl_logic; - rdreq : in vl_logic; - aclr : in vl_logic; - sclr : in vl_logic; - q : out vl_logic_vector; - usedw : out vl_logic_vector; - full : out vl_logic; - empty : out vl_logic; - almost_full : out vl_logic; - almost_empty : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_width : constant is 1; - attribute mti_svvh_generic_type of lpm_widthu : constant is 1; - attribute mti_svvh_generic_type of lpm_numwords : constant is 1; - attribute mti_svvh_generic_type of lpm_showahead : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of intended_device_family : constant is 1; - attribute mti_svvh_generic_type of underflow_checking : constant is 1; - attribute mti_svvh_generic_type of overflow_checking : constant is 1; - attribute mti_svvh_generic_type of allow_rwcycle_when_full : constant is 1; - attribute mti_svvh_generic_type of use_eab : constant is 1; - attribute mti_svvh_generic_type of add_ram_output_register : constant is 1; - attribute mti_svvh_generic_type of almost_full_value : constant is 1; - attribute mti_svvh_generic_type of almost_empty_value : constant is 1; - attribute mti_svvh_generic_type of maximum_depth : constant is 1; - attribute mti_svvh_generic_type of showahead_area : constant is 3; - attribute mti_svvh_generic_type of showahead_speed : constant is 3; - attribute mti_svvh_generic_type of legacy_speed : constant is 3; -end scfifo; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/signal_gen/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/signal_gen/_primary.dat deleted file mode 100644 index 5fa892e..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/signal_gen/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/signal_gen/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/signal_gen/_primary.dbs deleted file mode 100644 index 5058edc..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/signal_gen/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/signal_gen/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/signal_gen/_primary.vhd deleted file mode 100644 index d7a6d40..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/signal_gen/_primary.vhd +++ /dev/null @@ -1,22 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity signal_gen is - generic( - sld_node_ir_width: integer := 1; - sld_node_n_scan : integer := 0; - sld_node_total_length: integer := 0; - sld_node_sim_action: string := "()" - ); - port( - tck : out vl_logic; - tms : out vl_logic; - tdi : out vl_logic; - jtag_usr1 : in vl_logic; - tdo : in vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of sld_node_ir_width : constant is 1; - attribute mti_svvh_generic_type of sld_node_n_scan : constant is 1; - attribute mti_svvh_generic_type of sld_node_total_length : constant is 1; - attribute mti_svvh_generic_type of sld_node_sim_action : constant is 1; -end signal_gen; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_signaltap/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_signaltap/_primary.dat deleted file mode 100644 index c7a1cdc..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_signaltap/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_signaltap/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_signaltap/_primary.dbs deleted file mode 100644 index eb628a5..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_signaltap/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_signaltap/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_signaltap/_primary.vhd deleted file mode 100644 index 17c4a22..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_signaltap/_primary.vhd +++ /dev/null @@ -1,129 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity sld_signaltap is - generic( - SLD_CURRENT_RESOURCE_WIDTH: integer := 0; - SLD_INVERSION_MASK: string := "0"; - SLD_POWER_UP_TRIGGER: integer := 0; - SLD_ADVANCED_TRIGGER_6: string := "NONE"; - SLD_ADVANCED_TRIGGER_9: string := "NONE"; - SLD_ADVANCED_TRIGGER_7: string := "NONE"; - SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY: string := "basic"; - SLD_STORAGE_QUALIFIER_GAP_RECORD: integer := 0; - SLD_INCREMENTAL_ROUTING: integer := 0; - SLD_STORAGE_QUALIFIER_PIPELINE: integer := 0; - SLD_TRIGGER_IN_ENABLED: integer := 0; - SLD_STATE_BITS : integer := 11; - SLD_STATE_FLOW_USE_GENERATED: integer := 0; - SLD_INVERSION_MASK_LENGTH: integer := 1; - SLD_DATA_BITS : integer := 1; - SLD_BUFFER_FULL_STOP: integer := 1; - SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH: integer := 0; - SLD_ATTRIBUTE_MEM_MODE: string := "OFF"; - SLD_STORAGE_QUALIFIER_MODE: string := "OFF"; - SLD_STATE_FLOW_MGR_ENTITY: string := "state_flow_mgr_entity.vhd"; - SLD_NODE_CRC_LOWORD: integer := 50132; - SLD_ADVANCED_TRIGGER_5: string := "NONE"; - SLD_TRIGGER_BITS: integer := 1; - SLD_STORAGE_QUALIFIER_BITS: integer := 1; - SLD_ADVANCED_TRIGGER_10: string := "NONE"; - SLD_MEM_ADDRESS_BITS: integer := 7; - SLD_ADVANCED_TRIGGER_ENTITY: string := "basic"; - SLD_ADVANCED_TRIGGER_4: string := "NONE"; - SLD_TRIGGER_LEVEL: integer := 10; - SLD_ADVANCED_TRIGGER_8: string := "NONE"; - SLD_RAM_BLOCK_TYPE: string := "AUTO"; - SLD_ADVANCED_TRIGGER_2: string := "NONE"; - SLD_ADVANCED_TRIGGER_1: string := "NONE"; - SLD_DATA_BIT_CNTR_BITS: integer := 4; - lpm_type : string := "sld_signaltap"; - SLD_NODE_CRC_BITS: integer := 32; - SLD_SAMPLE_DEPTH: integer := 16; - SLD_ENABLE_ADVANCED_TRIGGER: integer := 0; - SLD_SEGMENT_SIZE: integer := 0; - SLD_NODE_INFO : integer := 0; - SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION: integer := 0; - SLD_NODE_CRC_HIWORD: integer := 41394; - SLD_TRIGGER_LEVEL_PIPELINE: integer := 1; - SLD_ADVANCED_TRIGGER_3: string := "NONE"; - ELA_STATUS_BITS : integer := 4; - N_ELA_INSTRS : integer := 8; - SLD_IR_BITS : vl_notype - ); - port( - jtag_state_sdr : in vl_logic; - ir_out : out vl_logic_vector; - jtag_state_cdr : in vl_logic; - ir_in : in vl_logic_vector; - tdi : in vl_logic; - acq_trigger_out : out vl_logic_vector; - jtag_state_uir : in vl_logic; - acq_trigger_in : in vl_logic_vector; - trigger_out : out vl_logic; - storage_enable : in vl_logic; - acq_data_out : out vl_logic_vector; - acq_data_in : in vl_logic_vector; - acq_storage_qualifier_in: in vl_logic_vector; - jtag_state_udr : in vl_logic; - tdo : out vl_logic; - crc : in vl_logic_vector; - jtag_state_e1dr : in vl_logic; - raw_tck : in vl_logic; - usr1 : in vl_logic; - acq_clk : in vl_logic; - shift : in vl_logic; - ena : in vl_logic; - clr : in vl_logic; - trigger_in : in vl_logic; - update : in vl_logic; - rti : in vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of SLD_CURRENT_RESOURCE_WIDTH : constant is 1; - attribute mti_svvh_generic_type of SLD_INVERSION_MASK : constant is 1; - attribute mti_svvh_generic_type of SLD_POWER_UP_TRIGGER : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_6 : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_9 : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_7 : constant is 1; - attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY : constant is 1; - attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_GAP_RECORD : constant is 1; - attribute mti_svvh_generic_type of SLD_INCREMENTAL_ROUTING : constant is 1; - attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_PIPELINE : constant is 1; - attribute mti_svvh_generic_type of SLD_TRIGGER_IN_ENABLED : constant is 1; - attribute mti_svvh_generic_type of SLD_STATE_BITS : constant is 1; - attribute mti_svvh_generic_type of SLD_STATE_FLOW_USE_GENERATED : constant is 1; - attribute mti_svvh_generic_type of SLD_INVERSION_MASK_LENGTH : constant is 1; - attribute mti_svvh_generic_type of SLD_DATA_BITS : constant is 1; - attribute mti_svvh_generic_type of SLD_BUFFER_FULL_STOP : constant is 1; - attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH : constant is 1; - attribute mti_svvh_generic_type of SLD_ATTRIBUTE_MEM_MODE : constant is 1; - attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_MODE : constant is 1; - attribute mti_svvh_generic_type of SLD_STATE_FLOW_MGR_ENTITY : constant is 1; - attribute mti_svvh_generic_type of SLD_NODE_CRC_LOWORD : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_5 : constant is 1; - attribute mti_svvh_generic_type of SLD_TRIGGER_BITS : constant is 1; - attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_BITS : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_10 : constant is 1; - attribute mti_svvh_generic_type of SLD_MEM_ADDRESS_BITS : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_ENTITY : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_4 : constant is 1; - attribute mti_svvh_generic_type of SLD_TRIGGER_LEVEL : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_8 : constant is 1; - attribute mti_svvh_generic_type of SLD_RAM_BLOCK_TYPE : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_2 : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_1 : constant is 1; - attribute mti_svvh_generic_type of SLD_DATA_BIT_CNTR_BITS : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of SLD_NODE_CRC_BITS : constant is 1; - attribute mti_svvh_generic_type of SLD_SAMPLE_DEPTH : constant is 1; - attribute mti_svvh_generic_type of SLD_ENABLE_ADVANCED_TRIGGER : constant is 1; - attribute mti_svvh_generic_type of SLD_SEGMENT_SIZE : constant is 1; - attribute mti_svvh_generic_type of SLD_NODE_INFO : constant is 1; - attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION : constant is 1; - attribute mti_svvh_generic_type of SLD_NODE_CRC_HIWORD : constant is 1; - attribute mti_svvh_generic_type of SLD_TRIGGER_LEVEL_PIPELINE : constant is 1; - attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_3 : constant is 1; - attribute mti_svvh_generic_type of ELA_STATUS_BITS : constant is 1; - attribute mti_svvh_generic_type of N_ELA_INSTRS : constant is 1; - attribute mti_svvh_generic_type of SLD_IR_BITS : constant is 3; -end sld_signaltap; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag/_primary.dat deleted file mode 100644 index 8fb487d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag/_primary.dbs deleted file mode 100644 index 3450b67..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag/_primary.vhd deleted file mode 100644 index deaf996..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag/_primary.vhd +++ /dev/null @@ -1,55 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity sld_virtual_jtag is - generic( - lpm_type : string := "SLD_VIRTUAL_JTAG"; - lpm_hint : string := "SLD_VIRTUAL_JTAG"; - sld_auto_instance_index: string := "NO"; - sld_instance_index: integer := 0; - sld_ir_width : integer := 1; - sld_sim_n_scan : integer := 0; - sld_sim_total_length: integer := 0; - sld_sim_action : string := "" - ); - port( - tdo : in vl_logic; - ir_out : in vl_logic_vector; - tck : out vl_logic; - tdi : out vl_logic; - ir_in : out vl_logic_vector; - virtual_state_cdr: out vl_logic; - virtual_state_sdr: out vl_logic; - virtual_state_e1dr: out vl_logic; - virtual_state_pdr: out vl_logic; - virtual_state_e2dr: out vl_logic; - virtual_state_udr: out vl_logic; - virtual_state_cir: out vl_logic; - virtual_state_uir: out vl_logic; - jtag_state_tlr : out vl_logic; - jtag_state_rti : out vl_logic; - jtag_state_sdrs : out vl_logic; - jtag_state_cdr : out vl_logic; - jtag_state_sdr : out vl_logic; - jtag_state_e1dr : out vl_logic; - jtag_state_pdr : out vl_logic; - jtag_state_e2dr : out vl_logic; - jtag_state_udr : out vl_logic; - jtag_state_sirs : out vl_logic; - jtag_state_cir : out vl_logic; - jtag_state_sir : out vl_logic; - jtag_state_e1ir : out vl_logic; - jtag_state_pir : out vl_logic; - jtag_state_e2ir : out vl_logic; - jtag_state_uir : out vl_logic; - tms : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of sld_auto_instance_index : constant is 1; - attribute mti_svvh_generic_type of sld_instance_index : constant is 1; - attribute mti_svvh_generic_type of sld_ir_width : constant is 1; - attribute mti_svvh_generic_type of sld_sim_n_scan : constant is 1; - attribute mti_svvh_generic_type of sld_sim_total_length : constant is 1; - attribute mti_svvh_generic_type of sld_sim_action : constant is 1; -end sld_virtual_jtag; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag_basic/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag_basic/_primary.dat deleted file mode 100644 index 24781b7..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag_basic/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag_basic/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag_basic/_primary.dbs deleted file mode 100644 index d09c857..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag_basic/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag_basic/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag_basic/_primary.vhd deleted file mode 100644 index 4a6866d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/sld_virtual_jtag_basic/_primary.vhd +++ /dev/null @@ -1,61 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity sld_virtual_jtag_basic is - generic( - lpm_hint : string := "UNUSED"; - sld_sim_action : string := "UNUSED"; - sld_instance_index: integer := 0; - sld_ir_width : integer := 1; - sld_sim_n_scan : integer := 0; - sld_mfg_id : integer := 0; - sld_version : integer := 0; - sld_type_id : integer := 0; - lpm_type : string := "sld_virtual_jtag_basic"; - sld_auto_instance_index: string := "NO"; - sld_sim_total_length: integer := 0 - ); - port( - jtag_state_sdr : out vl_logic; - jtag_state_sirs : out vl_logic; - ir_out : in vl_logic_vector; - jtag_state_sir : out vl_logic; - jtag_state_cdr : out vl_logic; - jtag_state_e2dr : out vl_logic; - tms : out vl_logic; - jtag_state_sdrs : out vl_logic; - jtag_state_tlr : out vl_logic; - ir_in : out vl_logic_vector; - virtual_state_sdr: out vl_logic; - tdi : out vl_logic; - jtag_state_uir : out vl_logic; - jtag_state_cir : out vl_logic; - virtual_state_cdr: out vl_logic; - virtual_state_uir: out vl_logic; - virtual_state_e2dr: out vl_logic; - jtag_state_e2ir : out vl_logic; - virtual_state_cir: out vl_logic; - jtag_state_pir : out vl_logic; - jtag_state_udr : out vl_logic; - virtual_state_udr: out vl_logic; - tdo : in vl_logic; - jtag_state_e1dr : out vl_logic; - jtag_state_rti : out vl_logic; - virtual_state_pdr: out vl_logic; - virtual_state_e1dr: out vl_logic; - jtag_state_e1ir : out vl_logic; - jtag_state_pdr : out vl_logic; - tck : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_hint : constant is 1; - attribute mti_svvh_generic_type of sld_sim_action : constant is 1; - attribute mti_svvh_generic_type of sld_instance_index : constant is 1; - attribute mti_svvh_generic_type of sld_ir_width : constant is 1; - attribute mti_svvh_generic_type of sld_sim_n_scan : constant is 1; - attribute mti_svvh_generic_type of sld_mfg_id : constant is 1; - attribute mti_svvh_generic_type of sld_version : constant is 1; - attribute mti_svvh_generic_type of sld_type_id : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of sld_auto_instance_index : constant is 1; - attribute mti_svvh_generic_type of sld_sim_total_length : constant is 1; -end sld_virtual_jtag_basic; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_lvds_rx/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_lvds_rx/_primary.dat deleted file mode 100644 index 2d1ef47..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_lvds_rx/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_lvds_rx/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_lvds_rx/_primary.dbs deleted file mode 100644 index 0050703..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_lvds_rx/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_lvds_rx/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_lvds_rx/_primary.vhd deleted file mode 100644 index d4b8de5..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_lvds_rx/_primary.vhd +++ /dev/null @@ -1,20 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stratix_lvds_rx is - generic( - number_of_channels: integer := 1; - deserialization_factor: integer := 4; - REGISTER_WIDTH : vl_notype - ); - port( - rx_in : in vl_logic_vector; - rx_fastclk : in vl_logic; - rx_enable0 : in vl_logic; - rx_enable1 : in vl_logic; - rx_out : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3; -end stratix_lvds_rx; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_tx_outclk/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_tx_outclk/_primary.dat deleted file mode 100644 index 113c56f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_tx_outclk/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_tx_outclk/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_tx_outclk/_primary.dbs deleted file mode 100644 index d10c7d0..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_tx_outclk/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_tx_outclk/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_tx_outclk/_primary.vhd deleted file mode 100644 index a4a3253..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratix_tx_outclk/_primary.vhd +++ /dev/null @@ -1,21 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stratix_tx_outclk is - generic( - deserialization_factor: integer := 4; - bypass_serializer: string := "FALSE"; - invert_clock : string := "FALSE"; - use_falling_clock_edge: string := "FALSE" - ); - port( - tx_in : in vl_logic_vector(9 downto 0); - tx_fastclk : in vl_logic; - tx_enable : in vl_logic; - tx_out : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of bypass_serializer : constant is 1; - attribute mti_svvh_generic_type of invert_clock : constant is 1; - attribute mti_svvh_generic_type of use_falling_clock_edge : constant is 1; -end stratix_tx_outclk; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixgx_dpa_lvds_rx/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixgx_dpa_lvds_rx/_primary.dat deleted file mode 100644 index 0e0d8ce..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixgx_dpa_lvds_rx/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixgx_dpa_lvds_rx/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixgx_dpa_lvds_rx/_primary.dbs deleted file mode 100644 index d82c19c..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixgx_dpa_lvds_rx/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixgx_dpa_lvds_rx/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixgx_dpa_lvds_rx/_primary.vhd deleted file mode 100644 index 9e3bece..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixgx_dpa_lvds_rx/_primary.vhd +++ /dev/null @@ -1,31 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stratixgx_dpa_lvds_rx is - generic( - number_of_channels: integer := 1; - deserialization_factor: integer := 4; - use_coreclock_input: string := "OFF"; - enable_dpa_fifo : string := "ON"; - registered_output: string := "ON"; - REGISTER_WIDTH : vl_notype - ); - port( - rx_in : in vl_logic_vector; - rx_fastclk : in vl_logic; - rx_slowclk : in vl_logic; - rx_locked : in vl_logic; - rx_coreclk : in vl_logic_vector; - rx_reset : in vl_logic_vector; - rx_dpll_reset : in vl_logic_vector; - rx_channel_data_align: in vl_logic_vector; - rx_out : out vl_logic_vector; - rx_dpa_locked : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of use_coreclock_input : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_fifo : constant is 1; - attribute mti_svvh_generic_type of registered_output : constant is 1; - attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3; -end stratixgx_dpa_lvds_rx; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_lvds_rx/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_lvds_rx/_primary.dat deleted file mode 100644 index bda8257..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_lvds_rx/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_lvds_rx/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_lvds_rx/_primary.dbs deleted file mode 100644 index 62829ae..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_lvds_rx/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_lvds_rx/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_lvds_rx/_primary.vhd deleted file mode 100644 index 4fd6526..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_lvds_rx/_primary.vhd +++ /dev/null @@ -1,45 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stratixii_lvds_rx is - generic( - number_of_channels: integer := 1; - deserialization_factor: integer := 4; - enable_dpa_mode : string := "OFF"; - data_align_rollover: vl_notype; - lose_lock_on_one_change: string := "OFF"; - reset_fifo_at_first_lock: string := "ON"; - x_on_bitslip : string := "ON"; - show_warning : string := "OFF"; - REGISTER_WIDTH : vl_notype; - MUX_WIDTH : integer := 12; - RAM_WIDTH : integer := 6 - ); - port( - rx_in : in vl_logic_vector; - rx_reset : in vl_logic_vector; - rx_fastclk : in vl_logic; - rx_enable : in vl_logic; - rx_locked : in vl_logic; - rx_dpll_reset : in vl_logic_vector; - rx_dpll_hold : in vl_logic_vector; - rx_dpll_enable : in vl_logic_vector; - rx_fifo_reset : in vl_logic_vector; - rx_channel_data_align: in vl_logic_vector; - rx_cda_reset : in vl_logic_vector; - rx_out : out vl_logic_vector; - rx_dpa_locked : out vl_logic_vector; - rx_cda_max : out vl_logic_vector - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_mode : constant is 1; - attribute mti_svvh_generic_type of data_align_rollover : constant is 3; - attribute mti_svvh_generic_type of lose_lock_on_one_change : constant is 1; - attribute mti_svvh_generic_type of reset_fifo_at_first_lock : constant is 1; - attribute mti_svvh_generic_type of x_on_bitslip : constant is 1; - attribute mti_svvh_generic_type of show_warning : constant is 1; - attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3; - attribute mti_svvh_generic_type of MUX_WIDTH : constant is 1; - attribute mti_svvh_generic_type of RAM_WIDTH : constant is 1; -end stratixii_lvds_rx; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_tx_outclk/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_tx_outclk/_primary.dat deleted file mode 100644 index bdfb93f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_tx_outclk/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_tx_outclk/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_tx_outclk/_primary.dbs deleted file mode 100644 index b7ce748..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_tx_outclk/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_tx_outclk/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_tx_outclk/_primary.vhd deleted file mode 100644 index b359a99..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixii_tx_outclk/_primary.vhd +++ /dev/null @@ -1,21 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stratixii_tx_outclk is - generic( - deserialization_factor: integer := 4; - bypass_serializer: string := "FALSE"; - invert_clock : string := "FALSE"; - use_falling_clock_edge: string := "FALSE" - ); - port( - tx_in : in vl_logic_vector(9 downto 0); - tx_fastclk : in vl_logic; - tx_enable : in vl_logic; - tx_out : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of bypass_serializer : constant is 1; - attribute mti_svvh_generic_type of invert_clock : constant is 1; - attribute mti_svvh_generic_type of use_falling_clock_edge : constant is 1; -end stratixii_tx_outclk; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx/_primary.dat deleted file mode 100644 index 2735e1e..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx/_primary.dbs deleted file mode 100644 index 913e3e1..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx/_primary.vhd deleted file mode 100644 index cf4da55..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx/_primary.vhd +++ /dev/null @@ -1,69 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stratixiii_lvds_rx is - generic( - number_of_channels: integer := 1; - deserialization_factor: integer := 4; - enable_dpa_mode : string := "OFF"; - data_align_rollover: vl_notype; - lose_lock_on_one_change: string := "OFF"; - reset_fifo_at_first_lock: string := "ON"; - x_on_bitslip : string := "ON"; - rx_align_data_reg: string := "RISING_EDGE"; - enable_soft_cdr_mode: string := "OFF"; - sim_dpa_output_clock_phase_shift: integer := 0; - sim_dpa_is_negative_ppm_drift: string := "OFF"; - sim_dpa_net_ppm_variation: integer := 0; - enable_dpa_align_to_rising_edge_only: string := "OFF"; - enable_dpa_initial_phase_selection: string := "OFF"; - dpa_initial_phase_value: integer := 0; - registered_output: string := "ON"; - use_external_pll: string := "OFF"; - use_dpa_calibration: integer := 0; - ARRIAII_RX_STYLE: integer := 0; - STRATIXV_RX_STYLE: integer := 0; - REGISTER_WIDTH : vl_notype - ); - port( - rx_in : in vl_logic_vector; - rx_reset : in vl_logic_vector; - rx_fastclk : in vl_logic; - rx_slowclk : in vl_logic; - rx_enable : in vl_logic; - rx_dpll_reset : in vl_logic_vector; - rx_dpll_hold : in vl_logic_vector; - rx_dpll_enable : in vl_logic_vector; - rx_fifo_reset : in vl_logic_vector; - rx_channel_data_align: in vl_logic_vector; - rx_cda_reset : in vl_logic_vector; - rx_out : out vl_logic_vector; - rx_dpa_locked : out vl_logic_vector; - rx_cda_max : out vl_logic_vector; - rx_divfwdclk : out vl_logic_vector; - rx_locked : in vl_logic; - rx_dpa_lock_reset: in vl_logic_vector; - rx_dpaclock : in vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of number_of_channels : constant is 1; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_mode : constant is 1; - attribute mti_svvh_generic_type of data_align_rollover : constant is 3; - attribute mti_svvh_generic_type of lose_lock_on_one_change : constant is 1; - attribute mti_svvh_generic_type of reset_fifo_at_first_lock : constant is 1; - attribute mti_svvh_generic_type of x_on_bitslip : constant is 1; - attribute mti_svvh_generic_type of rx_align_data_reg : constant is 1; - attribute mti_svvh_generic_type of enable_soft_cdr_mode : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_output_clock_phase_shift : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_is_negative_ppm_drift : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_net_ppm_variation : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_align_to_rising_edge_only : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_initial_phase_selection : constant is 1; - attribute mti_svvh_generic_type of dpa_initial_phase_value : constant is 1; - attribute mti_svvh_generic_type of registered_output : constant is 1; - attribute mti_svvh_generic_type of use_external_pll : constant is 1; - attribute mti_svvh_generic_type of use_dpa_calibration : constant is 1; - attribute mti_svvh_generic_type of ARRIAII_RX_STYLE : constant is 1; - attribute mti_svvh_generic_type of STRATIXV_RX_STYLE : constant is 1; - attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3; -end stratixiii_lvds_rx; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_channel/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_channel/_primary.dat deleted file mode 100644 index e81bbd1..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_channel/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_channel/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_channel/_primary.dbs deleted file mode 100644 index d712ad3..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_channel/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_channel/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_channel/_primary.vhd deleted file mode 100644 index 939d640..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_channel/_primary.vhd +++ /dev/null @@ -1,69 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stratixiii_lvds_rx_channel is - generic( - deserialization_factor: integer := 4; - enable_dpa_mode : string := "OFF"; - data_align_rollover: vl_notype; - lose_lock_on_one_change: string := "OFF"; - reset_fifo_at_first_lock: string := "ON"; - x_on_bitslip : string := "ON"; - rx_align_data_reg: string := "RISING_EDGE"; - enable_soft_cdr_mode: string := "OFF"; - sim_dpa_output_clock_phase_shift: integer := 0; - sim_dpa_is_negative_ppm_drift: string := "OFF"; - sim_dpa_net_ppm_variation: integer := 0; - enable_dpa_align_to_rising_edge_only: string := "OFF"; - enable_dpa_initial_phase_selection: string := "OFF"; - dpa_initial_phase_value: integer := 0; - registered_output: string := "ON"; - use_external_pll: string := "OFF"; - use_dpa_calibration: integer := 0; - ARRIAII_RX_STYLE: integer := 0; - STRATIXV_RX_STYLE: integer := 0; - MUX_WIDTH : integer := 12; - RAM_WIDTH : integer := 6 - ); - port( - rx_in : in vl_logic; - rx_reset : in vl_logic; - rx_fastclk : in vl_logic; - rx_slowclk : in vl_logic; - rx_enable : in vl_logic; - rx_dpll_reset : in vl_logic; - rx_dpll_hold : in vl_logic; - rx_dpll_enable : in vl_logic; - rx_fifo_reset : in vl_logic; - rx_channel_data_align: in vl_logic; - rx_cda_reset : in vl_logic; - rx_out : out vl_logic_vector; - rx_dpa_locked : out vl_logic; - rx_cda_max : out vl_logic; - rx_divfwdclk : out vl_logic; - rx_dpa_lock_reset: in vl_logic; - rx_locked : in vl_logic; - rx_dpaclock : in vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of deserialization_factor : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_mode : constant is 1; - attribute mti_svvh_generic_type of data_align_rollover : constant is 3; - attribute mti_svvh_generic_type of lose_lock_on_one_change : constant is 1; - attribute mti_svvh_generic_type of reset_fifo_at_first_lock : constant is 1; - attribute mti_svvh_generic_type of x_on_bitslip : constant is 1; - attribute mti_svvh_generic_type of rx_align_data_reg : constant is 1; - attribute mti_svvh_generic_type of enable_soft_cdr_mode : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_output_clock_phase_shift : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_is_negative_ppm_drift : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_net_ppm_variation : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_align_to_rising_edge_only : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_initial_phase_selection : constant is 1; - attribute mti_svvh_generic_type of dpa_initial_phase_value : constant is 1; - attribute mti_svvh_generic_type of registered_output : constant is 1; - attribute mti_svvh_generic_type of use_external_pll : constant is 1; - attribute mti_svvh_generic_type of use_dpa_calibration : constant is 1; - attribute mti_svvh_generic_type of ARRIAII_RX_STYLE : constant is 1; - attribute mti_svvh_generic_type of STRATIXV_RX_STYLE : constant is 1; - attribute mti_svvh_generic_type of MUX_WIDTH : constant is 1; - attribute mti_svvh_generic_type of RAM_WIDTH : constant is 1; -end stratixiii_lvds_rx_channel; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_dpa/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_dpa/_primary.dat deleted file mode 100644 index bc632cd..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_dpa/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_dpa/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_dpa/_primary.dbs deleted file mode 100644 index 493f484..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_dpa/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_dpa/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_dpa/_primary.vhd deleted file mode 100644 index 9918aa7..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stratixiii_lvds_rx_dpa/_primary.vhd +++ /dev/null @@ -1,34 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stratixiii_lvds_rx_dpa is - generic( - enable_soft_cdr_mode: string := "OFF"; - sim_dpa_is_negative_ppm_drift: string := "OFF"; - sim_dpa_net_ppm_variation: integer := 0; - enable_dpa_align_to_rising_edge_only: string := "OFF"; - enable_dpa_initial_phase_selection: string := "OFF"; - dpa_initial_phase_value: integer := 0; - INITIAL_PHASE_SELECT: vl_notype; - PHASE_NUM : integer := 8 - ); - port( - rx_in : in vl_logic; - rx_fastclk : in vl_logic; - rx_enable : in vl_logic; - rx_dpa_reset : in vl_logic; - rx_dpa_hold : in vl_logic; - rx_out : out vl_logic; - rx_dpa_clk : out vl_logic; - rx_dpa_loaden : out vl_logic; - rx_dpa_locked : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of enable_soft_cdr_mode : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_is_negative_ppm_drift : constant is 1; - attribute mti_svvh_generic_type of sim_dpa_net_ppm_variation : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_align_to_rising_edge_only : constant is 1; - attribute mti_svvh_generic_type of enable_dpa_initial_phase_selection : constant is 1; - attribute mti_svvh_generic_type of dpa_initial_phase_value : constant is 1; - attribute mti_svvh_generic_type of INITIAL_PHASE_SELECT : constant is 3; - attribute mti_svvh_generic_type of PHASE_NUM : constant is 1; -end stratixiii_lvds_rx_dpa; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_m_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_m_cntr/_primary.dat deleted file mode 100644 index 514b11d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_m_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_m_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_m_cntr/_primary.dbs deleted file mode 100644 index 91ad6bc..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_m_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_m_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_m_cntr/_primary.vhd deleted file mode 100644 index 79d2ad2..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_m_cntr/_primary.vhd +++ /dev/null @@ -1,12 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stx_m_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - initial_value : in vl_logic_vector(31 downto 0); - modulus : in vl_logic_vector(31 downto 0); - time_delay : in vl_logic_vector(31 downto 0) - ); -end stx_m_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_n_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_n_cntr/_primary.dat deleted file mode 100644 index 289ae4d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_n_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_n_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_n_cntr/_primary.dbs deleted file mode 100644 index b1e393e..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_n_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_n_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_n_cntr/_primary.vhd deleted file mode 100644 index 834f17e..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_n_cntr/_primary.vhd +++ /dev/null @@ -1,11 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stx_n_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - modulus : in vl_logic_vector(31 downto 0); - time_delay : in vl_logic_vector(31 downto 0) - ); -end stx_n_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_scale_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_scale_cntr/_primary.dat deleted file mode 100644 index c3ef3d2..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_scale_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_scale_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_scale_cntr/_primary.dbs deleted file mode 100644 index 61ffda4..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_scale_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_scale_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_scale_cntr/_primary.vhd deleted file mode 100644 index f93982b..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/stx_scale_cntr/_primary.vhd +++ /dev/null @@ -1,15 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity stx_scale_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - high : in vl_logic_vector(31 downto 0); - low : in vl_logic_vector(31 downto 0); - initial_value : in vl_logic_vector(31 downto 0); - mode : in vl_logic_vector(48 downto 1); - time_delay : in vl_logic_vector(31 downto 0); - ph_tap : in vl_logic_vector(31 downto 0) - ); -end stx_scale_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_m_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_m_cntr/_primary.dat deleted file mode 100644 index edcc8b8..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_m_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_m_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_m_cntr/_primary.dbs deleted file mode 100644 index eacd6d7..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_m_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_m_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_m_cntr/_primary.vhd deleted file mode 100644 index b9035de..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_m_cntr/_primary.vhd +++ /dev/null @@ -1,12 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ttn_m_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - initial_value : in vl_logic_vector(31 downto 0); - modulus : in vl_logic_vector(31 downto 0); - time_delay : in vl_logic_vector(31 downto 0) - ); -end ttn_m_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_n_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_n_cntr/_primary.dat deleted file mode 100644 index 7f7e878..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_n_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_n_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_n_cntr/_primary.dbs deleted file mode 100644 index fc34d52..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_n_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_n_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_n_cntr/_primary.vhd deleted file mode 100644 index 85fbf41..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_n_cntr/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ttn_n_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - modulus : in vl_logic_vector(31 downto 0) - ); -end ttn_n_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_scale_cntr/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_scale_cntr/_primary.dat deleted file mode 100644 index 98f1ecc..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_scale_cntr/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_scale_cntr/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_scale_cntr/_primary.dbs deleted file mode 100644 index e76c057..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_scale_cntr/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_scale_cntr/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_scale_cntr/_primary.vhd deleted file mode 100644 index 5dd30f8..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_mf_ver/ttn_scale_cntr/_primary.vhd +++ /dev/null @@ -1,14 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity ttn_scale_cntr is - port( - clk : in vl_logic; - reset : in vl_logic; - cout : out vl_logic; - high : in vl_logic_vector(31 downto 0); - low : in vl_logic_vector(31 downto 0); - initial_value : in vl_logic_vector(31 downto 0); - mode : in vl_logic_vector(48 downto 1); - ph_tap : in vl_logic_vector(31 downto 0) - ); -end ttn_scale_cntr; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@h@i@g@h/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@h@i@g@h/_primary.dat deleted file mode 100644 index 6068dff..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@h@i@g@h/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@h@i@g@h/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@h@i@g@h/_primary.dbs deleted file mode 100644 index 234f88b..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@h@i@g@h/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@h@i@g@h/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@h@i@g@h/_primary.vhd deleted file mode 100644 index 35a33b8..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@h@i@g@h/_primary.vhd +++ /dev/null @@ -1,6 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity PRIM_GDFF_HIGH is - -- This module cannot be connected to from - -- VHDL because it has unnamed ports. -end PRIM_GDFF_HIGH; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@l@o@w/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@l@o@w/_primary.dat deleted file mode 100644 index 6da6faf..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@l@o@w/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@l@o@w/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@l@o@w/_primary.dbs deleted file mode 100644 index 12e5242..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@l@o@w/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@l@o@w/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@l@o@w/_primary.vhd deleted file mode 100644 index d01a32c..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_ver/@p@r@i@m_@g@d@f@f_@l@o@w/_primary.vhd +++ /dev/null @@ -1,6 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity PRIM_GDFF_LOW is - -- This module cannot be connected to from - -- VHDL because it has unnamed ports. -end PRIM_GDFF_LOW; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/@t@r@i/_primary.dat b/firmware/simulation/modelsim/verilog_libs/altera_ver/@t@r@i/_primary.dat deleted file mode 100644 index 9225f43..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_ver/@t@r@i/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/@t@r@i/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/altera_ver/@t@r@i/_primary.dbs deleted file mode 100644 index 4f72dd9..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/altera_ver/@t@r@i/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/@t@r@i/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/altera_ver/@t@r@i/_primary.vhd deleted file mode 100644 index 65c3b90..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_ver/@t@r@i/_primary.vhd +++ /dev/null @@ -1,9 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity TRI is - port( - \in\ : in vl_logic; - oe : in vl_logic; - \out\ : out vl_logic - ); -end TRI; diff --git a/firmware/simulation/modelsim/verilog_libs/altera_ver/_info b/firmware/simulation/modelsim/verilog_libs/altera_ver/_info deleted file mode 100644 index 4e853ed..0000000 --- a/firmware/simulation/modelsim/verilog_libs/altera_ver/_info +++ /dev/null @@ -1,688 +0,0 @@ -m255 -K3 -13 -cModel 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deleted file mode 100644 index 8caebe7..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and1/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and1/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and1/_primary.vhd deleted file mode 100644 index e175233..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and1/_primary.vhd +++ /dev/null @@ -1,8 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_and1 is - port( - Y : out vl_logic; - IN1 : in vl_logic - ); -end maxii_and1; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and16/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and16/_primary.dat deleted file mode 100644 index d98e248..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and16/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and16/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and16/_primary.dbs deleted file mode 100644 index cbf221c..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and16/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and16/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and16/_primary.vhd deleted file mode 100644 index f7c4dde..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_and16/_primary.vhd +++ /dev/null @@ -1,8 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_and16 is - port( - Y : out vl_logic_vector(15 downto 0); - IN1 : in vl_logic_vector(15 downto 0) - ); -end maxii_and16; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_asynch_lcell/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_asynch_lcell/_primary.dat deleted file mode 100644 index a558ab2..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_asynch_lcell/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_asynch_lcell/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_asynch_lcell/_primary.dbs deleted file mode 100644 index 36c8dee..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_asynch_lcell/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_asynch_lcell/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_asynch_lcell/_primary.vhd deleted file mode 100644 index 8a630de..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_asynch_lcell/_primary.vhd +++ /dev/null @@ -1,35 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_asynch_lcell is - generic( - operation_mode : string := "normal"; - sum_lutc_input : string := "datac"; - lut_mask : string := "ffff"; - cin_used : string := "false"; - cin0_used : string := "false"; - cin1_used : string := "false" - ); - port( - dataa : in vl_logic; - datab : in vl_logic; - datac : in vl_logic; - datad : in vl_logic; - cin : in vl_logic; - cin0 : in vl_logic; - cin1 : in vl_logic; - inverta : in vl_logic; - qfbkin : in vl_logic; - regin : out vl_logic; - combout : out vl_logic; - cout : out vl_logic; - cout0 : out vl_logic; - cout1 : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of sum_lutc_input : constant is 1; - attribute mti_svvh_generic_type of lut_mask : constant is 1; - attribute mti_svvh_generic_type of cin_used : constant is 1; - attribute mti_svvh_generic_type of cin0_used : constant is 1; - attribute mti_svvh_generic_type of cin1_used : constant is 1; -end maxii_asynch_lcell; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b17mux21/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b17mux21/_primary.dat deleted file mode 100644 index 3f6d2bd..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b17mux21/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b17mux21/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b17mux21/_primary.dbs deleted file mode 100644 index 4991902..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b17mux21/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b17mux21/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b17mux21/_primary.vhd deleted file mode 100644 index 53cfae7..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b17mux21/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_b17mux21 is - port( - MO : out vl_logic_vector(16 downto 0); - A : in vl_logic_vector(16 downto 0); - B : in vl_logic_vector(16 downto 0); - S : in vl_logic - ); -end maxii_b17mux21; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b5mux21/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b5mux21/_primary.dat deleted file mode 100644 index 3eb75aa..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b5mux21/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b5mux21/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b5mux21/_primary.dbs deleted file mode 100644 index 48311d1..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b5mux21/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b5mux21/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b5mux21/_primary.vhd deleted file mode 100644 index 63de60d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_b5mux21/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_b5mux21 is - port( - MO : out vl_logic_vector(4 downto 0); - A : in vl_logic_vector(4 downto 0); - B : in vl_logic_vector(4 downto 0); - S : in vl_logic - ); -end maxii_b5mux21; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_bmux21/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_bmux21/_primary.dat deleted file mode 100644 index d36dcdd..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_bmux21/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_bmux21/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_bmux21/_primary.dbs deleted file mode 100644 index 2e068d9..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_bmux21/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_bmux21/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_bmux21/_primary.vhd deleted file mode 100644 index d428009..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_bmux21/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_bmux21 is - port( - MO : out vl_logic_vector(15 downto 0); - A : in vl_logic_vector(15 downto 0); - B : in vl_logic_vector(15 downto 0); - S : in vl_logic - ); -end maxii_bmux21; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_crcblock/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_crcblock/_primary.dat deleted file mode 100644 index 240b8bb..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_crcblock/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_crcblock/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_crcblock/_primary.dbs deleted file mode 100644 index 094694a..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_crcblock/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_crcblock/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_crcblock/_primary.vhd deleted file mode 100644 index 470f83d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_crcblock/_primary.vhd +++ /dev/null @@ -1,17 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_crcblock is - generic( - oscillator_divider: integer := 1; - lpm_type : string := "maxii_crcblock" - ); - port( - clk : in vl_logic; - shiftnld : in vl_logic; - crcerror : out vl_logic; - regout : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of oscillator_divider : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end maxii_crcblock; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_dffe/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_dffe/_primary.dat deleted file mode 100644 index 11aa013..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_dffe/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_dffe/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_dffe/_primary.dbs deleted file mode 100644 index fbacfde..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_dffe/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_dffe/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_dffe/_primary.vhd deleted file mode 100644 index aa767b4..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_dffe/_primary.vhd +++ /dev/null @@ -1,12 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_dffe is - port( - Q : out vl_logic; - CLK : in vl_logic; - ENA : in vl_logic; - D : in vl_logic; - CLRN : in vl_logic; - PRN : in vl_logic - ); -end maxii_dffe; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_io/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_io/_primary.dat deleted file mode 100644 index 5b21bda..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_io/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_io/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_io/_primary.dbs deleted file mode 100644 index 0e03142..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_io/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_io/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_io/_primary.vhd deleted file mode 100644 index 47e49ed..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_io/_primary.vhd +++ /dev/null @@ -1,21 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_io is - generic( - operation_mode : string := "input"; - bus_hold : string := "false"; - open_drain_output: string := "false"; - lpm_type : string := "maxii_io" - ); - port( - datain : in vl_logic; - oe : in vl_logic; - padio : inout vl_logic; - combout : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of bus_hold : constant is 1; - attribute mti_svvh_generic_type of open_drain_output : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end maxii_io; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_jtag/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_jtag/_primary.dat deleted file mode 100644 index ae7e9d7..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_jtag/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_jtag/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_jtag/_primary.dbs deleted file mode 100644 index 2ca351d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_jtag/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_jtag/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_jtag/_primary.vhd deleted file mode 100644 index e87cfad..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_jtag/_primary.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_jtag is - generic( - lpm_type : string := "maxii_jtag" - ); - port( - tms : in vl_logic; - tck : in vl_logic; - tdi : in vl_logic; - ntrst : in vl_logic; - tdoutap : in vl_logic; - tdouser : in vl_logic; - tdo : out vl_logic; - tmsutap : out vl_logic; - tckutap : out vl_logic; - tdiutap : out vl_logic; - shiftuser : out vl_logic; - clkdruser : out vl_logic; - updateuser : out vl_logic; - runidleuser : out vl_logic; - usr1user : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of lpm_type : constant is 1; -end maxii_jtag; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell/_primary.dat deleted file mode 100644 index 8e792c1..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell/_primary.dbs deleted file mode 100644 index 17b27b6..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell/_primary.vhd deleted file mode 100644 index 5056db4..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell/_primary.vhd +++ /dev/null @@ -1,55 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_lcell is - generic( - operation_mode : string := "normal"; - synch_mode : string := "off"; - register_cascade_mode: string := "off"; - sum_lutc_input : string := "datac"; - lut_mask : string := "ffff"; - power_up : string := "low"; - cin_used : string := "false"; - cin0_used : string := "false"; - cin1_used : string := "false"; - output_mode : string := "reg_and_comb"; - lpm_type : string := "maxii_lcell"; - x_on_violation : string := "on" - ); - port( - clk : in vl_logic; - dataa : in vl_logic; - datab : in vl_logic; - datac : in vl_logic; - datad : in vl_logic; - aclr : in vl_logic; - aload : in vl_logic; - sclr : in vl_logic; - sload : in vl_logic; - ena : in vl_logic; - cin : in vl_logic; - cin0 : in vl_logic; - cin1 : in vl_logic; - inverta : in vl_logic; - regcascin : in vl_logic; - devclrn : in vl_logic; - devpor : in vl_logic; - combout : out vl_logic; - regout : out vl_logic; - cout : out vl_logic; - cout0 : out vl_logic; - cout1 : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of operation_mode : constant is 1; - attribute mti_svvh_generic_type of synch_mode : constant is 1; - attribute mti_svvh_generic_type of register_cascade_mode : constant is 1; - attribute mti_svvh_generic_type of sum_lutc_input : constant is 1; - attribute mti_svvh_generic_type of lut_mask : constant is 1; - attribute mti_svvh_generic_type of power_up : constant is 1; - attribute mti_svvh_generic_type of cin_used : constant is 1; - attribute mti_svvh_generic_type of cin0_used : constant is 1; - attribute mti_svvh_generic_type of cin1_used : constant is 1; - attribute mti_svvh_generic_type of output_mode : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of x_on_violation : constant is 1; -end maxii_lcell; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell_register/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell_register/_primary.dat deleted file mode 100644 index bb84ba8..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell_register/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell_register/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell_register/_primary.dbs deleted file mode 100644 index 3897ee8..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell_register/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell_register/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell_register/_primary.vhd deleted file mode 100644 index afd3085..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_lcell_register/_primary.vhd +++ /dev/null @@ -1,30 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_lcell_register is - generic( - synch_mode : string := "off"; - register_cascade_mode: string := "off"; - power_up : string := "low"; - x_on_violation : string := "on" - ); - port( - clk : in vl_logic; - aclr : in vl_logic; - aload : in vl_logic; - sclr : in vl_logic; - sload : in vl_logic; - ena : in vl_logic; - datain : in vl_logic; - datac : in vl_logic; - regcascin : in vl_logic; - devclrn : in vl_logic; - devpor : in vl_logic; - regout : out vl_logic; - qfbkout : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of synch_mode : constant is 1; - attribute mti_svvh_generic_type of register_cascade_mode : constant is 1; - attribute mti_svvh_generic_type of power_up : constant is 1; - attribute mti_svvh_generic_type of x_on_violation : constant is 1; -end maxii_lcell_register; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux21/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux21/_primary.dat deleted file mode 100644 index fa63559..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux21/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux21/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux21/_primary.dbs deleted file mode 100644 index fc80a7d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux21/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux21/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux21/_primary.vhd deleted file mode 100644 index 9469160..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux21/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_mux21 is - port( - MO : out vl_logic; - A : in vl_logic; - B : in vl_logic; - S : in vl_logic - ); -end maxii_mux21; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux41/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux41/_primary.dat deleted file mode 100644 index ba39003..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux41/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux41/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux41/_primary.dbs deleted file mode 100644 index 26d9a9e..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux41/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux41/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux41/_primary.vhd deleted file mode 100644 index 658a8c0..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_mux41/_primary.vhd +++ /dev/null @@ -1,12 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_mux41 is - port( - MO : out vl_logic; - IN0 : in vl_logic; - IN1 : in vl_logic; - IN2 : in vl_logic; - IN3 : in vl_logic; - S : in vl_logic_vector(1 downto 0) - ); -end maxii_mux41; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_nmux21/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_nmux21/_primary.dat deleted file mode 100644 index 7c3b393..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_nmux21/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_nmux21/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_nmux21/_primary.dbs deleted file mode 100644 index c6c898f..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_nmux21/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_nmux21/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_nmux21/_primary.vhd deleted file mode 100644 index e28ce6f..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_nmux21/_primary.vhd +++ /dev/null @@ -1,10 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_nmux21 is - port( - MO : out vl_logic; - A : in vl_logic; - B : in vl_logic; - S : in vl_logic - ); -end maxii_nmux21; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_routing_wire/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_routing_wire/_primary.dat deleted file mode 100644 index a31bb76..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_routing_wire/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_routing_wire/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_routing_wire/_primary.dbs deleted file mode 100644 index e8a836c..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_routing_wire/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_routing_wire/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_routing_wire/_primary.vhd deleted file mode 100644 index 677a9f4..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_routing_wire/_primary.vhd +++ /dev/null @@ -1,8 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_routing_wire is - port( - datain : in vl_logic; - dataout : out vl_logic - ); -end maxii_routing_wire; diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_ufm/_primary.dat b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_ufm/_primary.dat deleted file mode 100644 index e1dd44d..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_ufm/_primary.dat and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_ufm/_primary.dbs b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_ufm/_primary.dbs deleted file mode 100644 index 6e2adfe..0000000 Binary files a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_ufm/_primary.dbs and /dev/null differ diff --git a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_ufm/_primary.vhd b/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_ufm/_primary.vhd deleted file mode 100644 index 200d25d..0000000 --- a/firmware/simulation/modelsim/verilog_libs/maxii_ver/maxii_ufm/_primary.vhd +++ /dev/null @@ -1,83 +0,0 @@ -library verilog; -use verilog.vl_types.all; -entity maxii_ufm is - generic( - address_width : integer := 9; - init_file : string := "none"; - lpm_type : string := "maxii_ufm"; - mem1 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem2 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem3 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem4 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem5 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem6 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem7 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem8 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem9 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem10 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem11 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem12 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem13 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem14 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem15 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - mem16 : vl_logic_vector(511 downto 0) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); - osc_sim_setting : integer := 180000; - program_time : integer := 1600000; - erase_time : integer := 500000000; - widthdata : integer := 16; - widthadd : integer := 9; - sector0_range : vl_notype; - TOSCMN_PW : vl_notype; - TPPMX : vl_notype; - TEPMX : vl_notype - ); - port( - program : in vl_logic; - erase : in vl_logic; - oscena : in vl_logic; - arclk : in vl_logic; - arshft : in vl_logic; - ardin : in vl_logic; - drclk : in vl_logic; - drshft : in vl_logic; - drdin : in vl_logic; - sbdin : in vl_logic; - devclrn : in vl_logic; - devpor : in vl_logic; - ctrl_bgpbusy : in vl_logic; - busy : out vl_logic; - osc : out vl_logic; - drdout : out vl_logic; - sbdout : out vl_logic; - bgpbusy : out vl_logic - ); - attribute mti_svvh_generic_type : integer; - attribute mti_svvh_generic_type of address_width : constant is 1; - attribute mti_svvh_generic_type of init_file : constant is 1; - attribute mti_svvh_generic_type of lpm_type : constant is 1; - attribute mti_svvh_generic_type of mem1 : constant is 1; - attribute mti_svvh_generic_type of mem2 : constant is 1; - attribute mti_svvh_generic_type of mem3 : constant is 1; - attribute mti_svvh_generic_type of mem4 : constant is 1; - attribute mti_svvh_generic_type of mem5 : constant is 1; - attribute mti_svvh_generic_type of mem6 : constant is 1; - attribute mti_svvh_generic_type of mem7 : constant is 1; - attribute mti_svvh_generic_type of mem8 : constant is 1; - attribute mti_svvh_generic_type of mem9 : constant is 1; - attribute mti_svvh_generic_type of mem10 : constant is 1; - attribute mti_svvh_generic_type of mem11 : constant is 1; - attribute mti_svvh_generic_type of mem12 : constant is 1; - attribute mti_svvh_generic_type of mem13 : constant is 1; - attribute mti_svvh_generic_type of mem14 : constant is 1; - attribute mti_svvh_generic_type of mem15 : constant is 1; - attribute mti_svvh_generic_type of mem16 : constant is 1; - attribute mti_svvh_generic_type of osc_sim_setting : constant is 1; - attribute mti_svvh_generic_type of program_time : constant is 1; - attribute mti_svvh_generic_type of erase_time : constant is 1; - attribute mti_svvh_generic_type of widthdata : constant is 1; - attribute mti_svvh_generic_type of widthadd : constant is 1; - attribute mti_svvh_generic_type of sector0_range : constant is 3; - attribute mti_svvh_generic_type of TOSCMN_PW : constant is 3; - attribute mti_svvh_generic_type of TPPMX : constant is 3; - attribute mti_svvh_generic_type of TEPMX : constant is 3; -end maxii_ufm; diff --git a/firmware/simulation/modelsim/verilog_libs/sgate_ver/_info b/firmware/simulation/modelsim/verilog_libs/sgate_ver/_info deleted file mode 100644 index 32d725e..0000000 --- a/firmware/simulation/modelsim/verilog_libs/sgate_ver/_info +++ /dev/null @@ -1,328 +0,0 @@ -m255 -K3 -13 -cModel Technology -Z0 dC:\Users\3304\Desktop\codes\codes from HY\PF_old bottom\PF_DS0401\PF_DS\simulation\modelsim -vio_buf_opdrn -!s100 G1bzEZ?V9[_a95RTI25XO0 -IWA;[oA4e5SAdK7`hSLH8Y1 -V]SIJ;5S`0Wkj=inABn;b=0 -Z1 dC:\Users\3304\Desktop\codes\codes from HY\PF_old bottom\PF_DS0401\PF_DS\simulation\modelsim -Z2 w1303981772 -Z3 8d:/altera/11.0/quartus/eda/sim_lib/sgate.v -Z4 Fd:/altera/11.0/quartus/eda/sim_lib/sgate.v -L0 248 -Z5 OL;L;10.0c;49 -r1 -!s85 0 -31 -Z6 !s108 1386757420.614000 -Z7 !s107 d:/altera/11.0/quartus/eda/sim_lib/sgate.v| -Z8 !s90 -reportprogress|300|-vlog01compat|-work|sgate_ver|d:/altera/11.0/quartus/eda/sim_lib/sgate.v| -Z9 o-vlog01compat -work sgate_ver -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF -vio_buf_tri -!s100 j>NJ1LoFoLTQH4dLOMbb91 -IQ;a18z249XE][F?GdMEf1I29?AK[3 -V5PC^09V70V21o7H@P495X2 -R1 -R2 -R3 -R4 -L0 18 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -voper_addsub -!s100 oNK8;>_YGY`C9_[K;CP@i1 -IKl91_TmdRPNGc[1HAkAh`3 -Vamkg7<]og=GB4I>1^PbO90 -R1 -R2 -R3 -R4 -L0 95 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -voper_bus_mux -!s100 `c^Ik<:Gb>G0<=KHhj4WY[W063 -R1 -R2 -R3 -R4 -L0 1036 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -voper_div -!s100 Sd9Q3j>2^K?@d@RD`83NW2 -Ii5^;FoV]K@IZ35Y^`Q]_A0 -VT7]BQk@80IZSCk2540R;@0 -R1 -R2 -R3 -R4 -L0 394 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -voper_latch -!s100 XPJ]h^`L806:1ALnEAFfbkz;^iA3 -I[Yj@AGKF5AadCDCkcAH2<2 -V?4NgTNVZBo721RbXNOnCL1 -R1 -R2 -R3 -R4 -L0 572 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -voper_less_than -!s100 B3IEbfjXj^ihMkTU1e@Bb6ng19n2 -I35^8oF=S8AfaDfGMAcACF2 -V6NUa[=2[QSB0 -VcIOAHb8_LbDQX4XElONW2 -R1 -R2 -R3 -R4 -L0 732 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -voper_rotate_right -!s100 `EiXNz>W:3ca;0z2L2kM81 -IHzH7i5I4f0I?fenSPH@fk2 -VJkXU8I1V>E7i09h]8hd0 -R1 -R2 -R3 -R4 -L0 991 -R5 -r1 -!s85 0 -31 -R6 -R7 -R8 -R9 -vtri_bus -!s100 i2TR3Czi50b;b@Mza[aUe3 -IbCi' -# 42 0x7689ed6c: '' -# 43 0x77c1377b: '' -# 44 0x77c1374e: '' -StackWalk failed 487 -# End of Stack Trace - -# Current time Wed Apr 11 12:55:14 2012 -# ModelSim Stack Trace -# Program = vish -# Id = "6.6d" -# Version = "2010.11" -# Date = "Nov 2 2010" -# Platform = win32pe - -Exception c0000005 has occurred at address 1025b6d5. Traceback: -# 0 0x1025b6d5: 'Tk_FreeColor + 0x85' -# 1 0x10223fe5: 'TkpFreeBorder + 0x25' -# 2 0x1023c248: 'Tk_Free3DBorder + 0x28' -# 3 0x10288b7e: 'Tk_FreeOptions + 0x8e' -# 4 0x0046929c: '' -# 5 0x10052666: 'Tcl_EventuallyFree + 0x66' -# 6 0x00469903: '' -# 7 0x102633e4: 'Tk_HandleEvent + 0x444' -# 8 0x102a9fe6: 'Tk_DestroyWindow + 0x1d6' -# 9 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 10 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 11 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 12 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 13 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 14 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 15 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 16 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 17 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 18 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 19 0x102aa38c: 'Tk_MapWindow + 0xfc' -# 20 0x1002b0b0: 'Tcl_FinalizeThread + 0x50' -# 21 0x10011ca6: 'Tcl_ExitObjCmd + 0x66' -# 22 0x1000c770: 'TclEvalObjvInternal + 0x230' -# 23 0x1002d7bb: 'TclExprFloatError + 0x10eb' -# 24 0x1002bc79: 'TclCompEvalObj + 0xd9' -# 25 0x1005391f: 'TclObjInterpProc + 0x23f' -# 26 0x1000c770: 'TclEvalObjvInternal + 0x230' -# 27 0x1000dd77: 'Tcl_EvalEx + 0x167' -# 28 0x1000e0d6: 'Tcl_Eval + 0x16' -# 29 0x00498b33: 'Mtirpc_Init + 0xe7f3' -# 30 0x0049d4ba: 'Mtirpc_Init + 0x1317a' -# 31 0x004a0c75: 'Mtirpc_Init + 0x16935' -# 32 0x0072edba: '' -# 33 0x7689ed6c: '' -# 34 0x77c1377b: '' -# 35 0x77c1374e: '' -StackWalk failed 487 -# End of Stack Trace - -# Current time Wed Apr 11 12:55:14 2012 -# ModelSim Stack Trace -# Program = vish -# Id = "6.6d" -# Version = "2010.11" -# Date = "Nov 2 2010" -# Platform = win32pe - -Exception c0000005 has occurred at address 1025b6d5. Traceback: -# 0 0x1025b6d5: 'Tk_FreeColor + 0x85' -# 1 0x10223fe5: 'TkpFreeBorder + 0x25' -# 2 0x1023c248: 'Tk_Free3DBorder + 0x28' -# 3 0x10288b7e: 'Tk_FreeOptions + 0x8e' -# 4 0x0046929c: '' -# 5 0x10052666: 'Tcl_EventuallyFree + 0x66' -# 6 0x00469903: '' -# 7 0x102633e4: 'Tk_HandleEvent + 0x444' -# 8 0x102a9fe6: 'Tk_DestroyWindow + 0x1d6' -# 9 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 10 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 11 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 12 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 13 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 14 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 15 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 16 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 17 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 18 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 19 0x102aa38c: 'Tk_MapWindow + 0xfc' -# 20 0x1002b0b0: 'Tcl_FinalizeThread + 0x50' -# 21 0x10011ca6: 'Tcl_ExitObjCmd + 0x66' -# 22 0x1000c770: 'TclEvalObjvInternal + 0x230' -# 23 0x1002d7bb: 'TclExprFloatError + 0x10eb' -# 24 0x1002bc79: 'TclCompEvalObj + 0xd9' -# 25 0x1005391f: 'TclObjInterpProc + 0x23f' -# 26 0x1000c770: 'TclEvalObjvInternal + 0x230' -# 27 0x1000dd77: 'Tcl_EvalEx + 0x167' -# 28 0x1000e0d6: 'Tcl_Eval + 0x16' -# 29 0x00498b33: 'Mtirpc_Init + 0xe7f3' -# 30 0x0049d4ba: 'Mtirpc_Init + 0x1317a' -# 31 0x004a0c75: 'Mtirpc_Init + 0x16935' -# 32 0x0072edba: '' -# 33 0x7689ed6c: '' -# 34 0x77c1377b: '' -# 35 0x77c1374e: '' -StackWalk failed 487 -# End of Stack Trace - -# Current time Wed Apr 11 12:55:14 2012 -# ModelSim Stack Trace -# Program = vish -# Id = "6.6d" -# Version = "2010.11" -# Date = "Nov 2 2010" -# Platform = win32pe - -Exception c0000005 has occurred at address 1025b6d5. Traceback: -# 0 0x1025b6d5: 'Tk_FreeColor + 0x85' -# 1 0x10223fe5: 'TkpFreeBorder + 0x25' -# 2 0x1023c248: 'Tk_Free3DBorder + 0x28' -# 3 0x10288b7e: 'Tk_FreeOptions + 0x8e' -# 4 0x0046929c: '' -# 5 0x10052666: 'Tcl_EventuallyFree + 0x66' -# 6 0x00469903: '' -# 7 0x102633e4: 'Tk_HandleEvent + 0x444' -# 8 0x102a9fe6: 'Tk_DestroyWindow + 0x1d6' -# 9 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 10 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 11 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 12 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 13 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 14 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 15 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 16 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 17 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 18 0x102a9f40: 'Tk_DestroyWindow + 0x130' -# 19 0x102aa38c: 'Tk_MapWindow + 0xfc' -# 20 0x1002b0b0: 'Tcl_FinalizeThread + 0x50' -# 21 0x10011ca6: 'Tcl_ExitObjCmd + 0x66' -# 22 0x1000c770: 'TclEvalObjvInternal + 0x230' -# 23 0x1002d7bb: 'TclExprFloatError + 0x10eb' -# 24 0x1002bc79: 'TclCompEvalObj + 0xd9' -# 25 0x1005391f: 'TclObjInterpProc + 0x23f' -# 26 0x1000c770: 'TclEvalObjvInternal + 0x230' -# 27 0x1000dd77: 'Tcl_EvalEx + 0x167' -# 28 0x1000e0d6: 'Tcl_Eval + 0x16' -# 29 0x00498b33: 'Mtirpc_Init + 0xe7f3' -# 30 0x0049d4ba: 'Mtirpc_Init + 0x1317a' -# 31 0x004a0c75: 'Mtirpc_Init + 0x16935' -# 32 0x0072edba: '' -# 33 0x7689ed6c: '' -# 34 0x77c1377b: '' -# 35 0x77c1374e: '' -StackWalk failed 487 -# End of Stack Trace - diff --git a/firmware/simulation/modelsim/vsim.wlf b/firmware/simulation/modelsim/vsim.wlf deleted file mode 100644 index 7533640..0000000 Binary files a/firmware/simulation/modelsim/vsim.wlf and /dev/null differ diff --git a/firmware/simulation/modelsim/wlfteik4dn b/firmware/simulation/modelsim/wlfteik4dn deleted file mode 100644 index 7c269da..0000000 Binary files a/firmware/simulation/modelsim/wlfteik4dn and /dev/null differ diff --git a/firmware/simulation/modelsim/wlftyh13a8 b/firmware/simulation/modelsim/wlftyh13a8 deleted file mode 100644 index 8aefd7f..0000000 Binary files a/firmware/simulation/modelsim/wlftyh13a8 and /dev/null differ diff --git a/firmware/tb_PF1.v b/firmware/tb_valveboard_firmware.v similarity index 92% rename from firmware/tb_PF1.v rename to firmware/tb_valveboard_firmware.v index 5ce3e18..316ef47 100644 --- a/firmware/tb_PF1.v +++ b/firmware/tb_valveboard_firmware.v @@ -1,5 +1,5 @@ `timescale 1ns / 100ps -module tb_PF1(); +module tb_valveboard_firmware(); reg sys_clk; reg rst_n; reg line_sclk; @@ -9,7 +9,7 @@ module tb_PF1(); wire [48:0] signal_high_voltage; wire [48:0] signal_low_voltage; - PF1 inst_PF1( + valveboard_firmware inst_valveboard_firmware( .sys_clk (sys_clk), .rst_n (rst_n), .line_sclk (line_sclk), diff --git a/firmware/valveboard_firmware.qpf b/firmware/valveboard_firmware.qpf new file mode 100644 index 0000000..4706ab4 --- /dev/null +++ b/firmware/valveboard_firmware.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition +# Date created = 16:15:48 December 24, 2021 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "16:15:48 December 24, 2021" + +# Revisions + +PROJECT_REVISION = "valveboard_firmware" diff --git a/firmware/PF1.qsf b/firmware/valveboard_firmware.qsf similarity index 69% rename from firmware/PF1.qsf rename to firmware/valveboard_firmware.qsf index feb657e..87f7fb6 100644 --- a/firmware/PF1.qsf +++ b/firmware/valveboard_firmware.qsf @@ -1,36 +1,37 @@ # -------------------------------------------------------------------------- # # -# Copyright (C) 1991-2010 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. # # -------------------------------------------------------------------------- # # -# Quartus II -# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version -# Date created = 13:42:56 December 10, 2011 +# Quartus Prime +# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition +# Date created = 16:15:48 December 24, 2021 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: -# PF1_assignment_defaults.qdf +# valveboard_firmware_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software +# file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # @@ -38,29 +39,19 @@ set_global_assignment -name FAMILY "MAX II" set_global_assignment -name DEVICE EPM1270T144C5 -set_global_assignment -name TOP_LEVEL_ENTITY PF1 -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:42:56 DECEMBER 10, 2011" +set_global_assignment -name TOP_LEVEL_ENTITY valveboard_firmware +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:15:48 DECEMBER 24, 2021" set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" -set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name VERILOG_FILE valveboard_firmware.v +set_global_assignment -name VERILOG_FILE tb_valveboard_firmware.v +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_location_assignment PIN_37 -to rst_n -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation -set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_PF1 -section_id eda_simulation -set_global_assignment -name EDA_TEST_BENCH_NAME PF1 -section_id eda_simulation -set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id PF1 -set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME PF1_vlg_tst -section_id PF1 -set_global_assignment -name USE_CONFIGURATION_DEVICE ON -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" set_location_assignment PIN_14 -to signal_high_voltage[46] set_location_assignment PIN_15 -to signal_high_voltage[47] set_location_assignment PIN_12 -to signal_high_voltage[44] @@ -158,15 +149,6 @@ set_location_assignment PIN_51 -to signal_low_voltage[2] set_location_assignment PIN_50 -to signal_low_voltage[1] set_location_assignment PIN_49 -to signal_low_voltage[0] set_location_assignment PIN_18 -to sys_clk -set_location_assignment PIN_40 -to line_sclk -set_location_assignment PIN_41 -to line_sdata -set_location_assignment PIN_39 -to line_sen -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name EDA_TEST_BENCH_NAME tb_PF1 -section_id eda_simulation -set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_PF1 -set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "5 ms" -section_id tb_PF1 -set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_PF1 -section_id tb_PF1 -set_global_assignment -name VERILOG_FILE tb_PF1.v -set_global_assignment -name VERILOG_FILE PF1.v -set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/PF1.vt -section_id PF1 -set_global_assignment -name EDA_TEST_BENCH_FILE tb_PF1.v -section_id tb_PF1 \ No newline at end of file +set_location_assignment PIN_41 -to line_sclk +set_location_assignment PIN_39 -to line_sdata +set_location_assignment PIN_40 -to line_sen \ No newline at end of file diff --git a/firmware/valveboard_firmware.qsf.bak b/firmware/valveboard_firmware.qsf.bak new file mode 100644 index 0000000..4ff9bd6 --- /dev/null +++ b/firmware/valveboard_firmware.qsf.bak @@ -0,0 +1,53 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition +# Date created = 16:15:48 December 24, 2021 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# valveboard_firmware_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX II" +set_global_assignment -name DEVICE EPM1270T144C5 +set_global_assignment -name TOP_LEVEL_ENTITY valveboard_firmware +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:15:48 DECEMBER 24, 2021" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name VERILOG_FILE valveboard_firmware.v +set_global_assignment -name VERILOG_FILE tb_valveboard_firmware.v +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V \ No newline at end of file diff --git a/firmware/PF1.qws b/firmware/valveboard_firmware.qws similarity index 72% rename from firmware/PF1.qws rename to firmware/valveboard_firmware.qws index 07dac5d..963a6ff 100644 Binary files a/firmware/PF1.qws and b/firmware/valveboard_firmware.qws differ diff --git a/firmware/valveboard_firmware.v b/firmware/valveboard_firmware.v new file mode 100644 index 0000000..71304ce --- /dev/null +++ b/firmware/valveboard_firmware.v @@ -0,0 +1,305 @@ +/* +丁坤的阀板程序 2021/12/26 +对应原理图ValveBoard Kun v1.1.pdf +将b01-h1.1-p1.1-f1.1中的高压时间改为0.37ms +使用的是合肥的阀，1A电流需0.37ms的100V(阀标称100V，现场供电为96V)高电压 +*/ + +module valveboard_firmware( + input sys_clk, // 20MHz + input rst_n, + input line_sclk, + input line_sen, + input line_sdata, + + output reg [47:0] signal_high_voltage, + output reg [47:0] signal_low_voltage + + ); + + parameter CHANNEL_NUM = 48; + parameter CHANNEL_NUM_MINUS_1 = CHANNEL_NUM - 1; + parameter HIGH_VOLTAGE_TIME = 32'd7400; // 高压时间HIGH_VOLTAGE_TIME / 20MHz = 0.37ms + parameter HIGH_VOLTAGE_TIME_MINUS_1 = HIGH_VOLTAGE_TIME - 1; // 高压时间HIGH_VOLTAGE_TIME / 20MHz = 2ms + parameter FAULT_COUNTER_THRESHOLD = 32'd20_000_000; // 通讯中断超过FAULT_COUNTER_THRESHOLD / 20MHz = 1s，就关所有阀 + parameter FAULT_COUNTER_THRESHOLD_MINUS_1 = FAULT_COUNTER_THRESHOLD - 1; + parameter FAULT_COUNTER_THRESHOLD_PLUS_1 = FAULT_COUNTER_THRESHOLD + 1; + + + + reg [CHANNEL_NUM_MINUS_1:0] cache_signal_high_voltage; + reg [31:0] i; + reg [31:0] fault_counter; + reg [0:0] fault_flag [0:7]; // fault_flag支持8类错误信号 + + /** + * 维护错误信号 + */ + wire total_fault_flag = fault_flag[7] | fault_flag[6] | fault_flag[5] | fault_flag[4] | fault_flag[3] | fault_flag[2] | fault_flag[1] | fault_flag[0]; + integer j; + initial begin + for (j = 0; j < 8; j = j + 1) begin + fault_flag[j] = 1'b0; + end + end +// /** +// * 产生周期为100kHz的posedge_100khz信号，信号高电平持续1个sys_clk +// */ +// reg[7:0] cnt_for_posedge_100khz; +// reg posedge_100khz; +// always @(posedge sys_clk or negedge rst_n) begin +// if(!rst_n) begin +// cnt_for_posedge_100khz <= 0; +// end +// else if(cnt_for_posedge_100khz == 199) begin +// posedge_100khz <= 1; +// cnt_for_posedge_100khz <= 0; +// end +// else begin +// cnt_for_posedge_100khz <= cnt_for_posedge_100khz + 1; +// posedge_100khz <= 0; +// end +// end + + /** + * 在输入的line_sclk信号上升沿产生1个sys_clk时长高电平的脉冲信号posedge_line_sclk，比原信号延迟(4,5]个sys_clk + */ + reg [4:0] cache_line_sclk; + reg posedge_line_sclk; + always@(posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + cache_line_sclk <= 0; + posedge_line_sclk <= 0; + end + else begin + cache_line_sclk <= {cache_line_sclk[3:0], line_sclk}; + if ({cache_line_sclk, line_sclk} == 6'b011111) + posedge_line_sclk <= 1; + else + posedge_line_sclk <= 0; + end + end + + /** + * filter_line_sdata比原信号延迟(4,5]个sys_clk + */ + reg [4:0] tmp_cache_line_sdata; + reg fiter_line_sdata; + always@(posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + tmp_cache_line_sdata <= ~0; + end + else begin + tmp_cache_line_sdata <= {tmp_cache_line_sdata[3:0], line_sdata}; + fiter_line_sdata <= tmp_cache_line_sdata[4]; + end + end + + /** + * 在输入的line_sen信号上升沿产生1个sys_clk时长高电平的脉冲信号posedge_line_sen，比原信号延迟(4,5]个sys_clk + * 在输入的line_sen信号下降沿产生1个sys_clk时长高电平的脉冲信号negedge_line_sen，比原信号延迟(4,5]个sys_clk + * 缓存和整理line_sen信号得filter_line_sen，比原信号延迟(4,5]个sys_clk + */ + reg [4:0] cache_line_sen; +// reg posedge_line_sen; + reg filter_line_sen; + reg negedge_line_sen; + always@(posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + cache_line_sen <= 0; + filter_line_sen <= 0; +// posedge_line_sen <= 0; + end + else begin + cache_line_sen <= {cache_line_sen[3:0], line_sen}; + if ({cache_line_sen, line_sen} == 6'b011111) begin +// posedge_line_sen <= 1; + filter_line_sen <= 1; + negedge_line_sen <= 0; + end + else if ({cache_line_sen, line_sen} == 6'b100000) begin +// posedge_line_sen <= 0; + filter_line_sen <= 0; + negedge_line_sen <= 1; + end + else begin +// posedge_line_sen <= 0; + filter_line_sen <= filter_line_sen; + negedge_line_sen <= 0; + end + end + end + + /** + * line_clk上升沿采样line_sdata，采样时刻与posedge_line_sclk下降沿对齐 + * total_fault_flag会相对line_clk异步结束本次通信 + * recv_complete指示是否接收完成，单sys_clk周期宽度，与negedge_line_sen信号对齐 + */ + reg [CHANNEL_NUM_MINUS_1:0] cache_line_sdata; + wire recv_complete = negedge_line_sen && (i == CHANNEL_NUM); + always @ (posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + i <= 0; + cache_line_sdata <= ~0; + end + else if (total_fault_flag) begin + i <= 0; + cache_line_sdata <= ~0; + end + else if (filter_line_sen && posedge_line_sclk) begin + cache_line_sdata[i] <= fiter_line_sdata; + i <= i + 1; + end + else if (negedge_line_sen) begin + i <= 0; + end + end + + /** + * 若接收超过CHANNEL_NUM个数据，产生错误信号fault_flag[0]；fault_flag[0]将在posedge_line_sen上升沿时刻清楚 + */ + always @ (posedge sys_clk or negedge rst_n) begin + if (!rst_n) + fault_flag[0] <= 0; + else if (i > CHANNEL_NUM) + fault_flag[0] <= 1; + else if ({cache_line_sen, line_sen} == 6'b011111) + fault_flag[0] <= 0; + else + fault_flag[0] <= fault_flag[0]; + end + + /** + * 若通讯中断，超过FAULT_COUNTER_THRESHOLD个csys_clk就置位fault_flag[1] + * fault_flag[1]在posedge_line_sclk上升沿时刻清楚 + */ + always @(posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + fault_counter <= 0; + fault_flag[1] <= 0; + end + else if ({cache_line_sclk, line_sclk} == 6'b011111) begin + fault_counter <= 0; + fault_flag[1] <= 0; + end + else begin + if (fault_counter >= FAULT_COUNTER_THRESHOLD_PLUS_1) + fault_flag[1] <= 1; + else if (fault_counter >= FAULT_COUNTER_THRESHOLD_MINUS_1) begin + fault_counter <= fault_counter + 1; + fault_flag[1] <= 1; + end + else begin + fault_counter <= fault_counter + 1; + fault_flag[1] <= 0; + end + end + end + + + /** + * 得到enable_count_high_voltage_time的上升沿脉冲posedge_enable_count_high_voltage_time + * enable_count_high_voltage_time是用于开启高电压计时的信号，在其上升沿开启计时 + */ + reg [1:0] cache_enable_count_high_voltage_time; + reg enable_count_high_voltage_time; + wire posedge_enable_count_high_voltage_time = cache_enable_count_high_voltage_time[0] & ~cache_enable_count_high_voltage_time[1]; + always @(posedge sys_clk or negedge rst_n) begin + if (!rst_n) + cache_enable_count_high_voltage_time <= 0; + else begin + cache_enable_count_high_voltage_time[0] <= enable_count_high_voltage_time; + cache_enable_count_high_voltage_time[1] <= cache_enable_count_high_voltage_time[0]; + end + end + + /** + * posedge_enable_count_high_voltage_time下降沿开始从HIGH_VOLTAGE_TIME-1向下计数，count_high_voltage_time_end上升沿与到0瞬间对齐 + * is_high_voltage_time表示当前是否需要输出高电平，其宽度为HIGH_VOLTAGE_TIME + * posedge_count_high_voltage_time_complete脉冲时长为一个sys_clk + */ + reg [31:0] cnt_for_high_voltage_time; +// reg high_voltage_time_end; + reg is_high_voltage_time; + always @(posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + cnt_for_high_voltage_time <= 0; +// high_voltage_time_end <= 0; + is_high_voltage_time <= 0; + end + else if (total_fault_flag) begin + cnt_for_high_voltage_time <= 0; +// high_voltage_time_end <= 0; + is_high_voltage_time <= 0; + end + else if (posedge_enable_count_high_voltage_time) begin + cnt_for_high_voltage_time <= HIGH_VOLTAGE_TIME_MINUS_1; +// high_voltage_time_end <= 0; + is_high_voltage_time <= 1; + end + else if (cnt_for_high_voltage_time > 1) begin + cnt_for_high_voltage_time <= cnt_for_high_voltage_time - 1; +// high_voltage_time_end <= 0; + is_high_voltage_time <= 1; + end + else if (cnt_for_high_voltage_time == 1) begin + cnt_for_high_voltage_time <= cnt_for_high_voltage_time - 1; +// high_voltage_time_end <= 1; + is_high_voltage_time <= 1; + end + else begin +// high_voltage_time_end <= 0; + is_high_voltage_time <= 0; + end + + end + + /** + * recv_complete下降沿缓存cache_line_sdata数据到cache2_line_sdata并开始高电压时间计时 + */ + reg [CHANNEL_NUM_MINUS_1:0] cache2_line_sdata; + always @(posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + enable_count_high_voltage_time <= 0; + cache2_line_sdata <= ~0; + end + else if (total_fault_flag) begin + enable_count_high_voltage_time <= 0; + cache2_line_sdata <= ~0; + end + else if (recv_complete) begin + enable_count_high_voltage_time <= 1; + cache2_line_sdata <= cache_line_sdata; + end + else begin + enable_count_high_voltage_time <= 0; + end + + end + + /** + * 高电压时间内(is_high_voltage_time高电平时)，按cache2_line_sdata打开所需高电压；高电压时间后关闭 + * 按cache2_line_sdata打开低电压 + * total_fault_flag会关闭所有喷阀 + */ + always @ (posedge sys_clk or negedge rst_n) begin + if (!rst_n) begin + signal_low_voltage <= ~0; + signal_high_voltage <= ~0; + end + else if (total_fault_flag) begin + signal_low_voltage <= ~0; + signal_high_voltage <= ~0; + end + else if (is_high_voltage_time) begin + signal_high_voltage <= cache2_line_sdata; + signal_low_voltage <= cache2_line_sdata; + end + else begin + signal_high_voltage <= ~0; + signal_low_voltage <= cache2_line_sdata; + end + end + +endmodule + \ No newline at end of file diff --git a/firmware/PF1.v b/firmware/valveboard_firmware.v.bak similarity index 100% rename from firmware/PF1.v rename to firmware/valveboard_firmware.v.bak diff --git a/hardware/README.assets/image-20211226143651047.png b/hardware/README.assets/image-20211226143651047.png new file mode 100644 index 0000000..95e1fcb Binary files /dev/null and b/hardware/README.assets/image-20211226143651047.png differ diff --git a/hardware/README.md b/hardware/README.md index 95c4be5..534a775 100644 --- a/hardware/README.md +++ b/hardware/README.md @@ -1,16 +1,22 @@ # 阀板硬件 -这是48路阀板的原理图和PCB，是Altium Designer工程，原理图抄袭改进了老倪的老板子，老板子据他说是抄的德国的板子 +这个文件夹下是丁坤画的48路阀板的原理图和PCB，然而**这次烟梗分选机用的板子是汪学良师兄画的，和这个文件夹下的板子不是同一块**，这次据老倪说板子是安徽生产的。整个机器用了六块48路阀板，驱动200路喷嘴，阀的型号是合肥旭伟电子气动有限公司的XW-F16，这个阀一个可以连接并控制16个喷嘴。 + +![image-20211226143651047](README.assets/image-20211226143651047.png) + +**下面的说明仅针对丁坤画的阀板v1.1，并不是烟梗分选机用到的，丁坤的阀板简化了供电，添加了不同的接口，但总体思路是一样的**，此外丁坤和汪学良的阀板引脚分配并不相同，具体见阀板程序`../firmware`。 ## 概述 +**汪学良的板子供电数量和标号与下面所述的丁坤阀板v1.1稍有不同，非粗体字体是对丁坤板子的说明，请留意。** + 48个电磁阀连接在顶部的12个接口上，当接口上有电压时电流流过电磁阀，电磁阀打开。由于电磁阀工作需要大电流大电压且为感性器件，容易影响发出控制信号的CPLD芯片，因此需要独立且隔离的电源，这个电源标为`LOW`，参考为`PGND`。为加快电磁阀开启，在开启瞬间会输出一个高电压，这是另一个独立的电源，标为`HIGH`，参考也为`PGND`。这个高电压会在电磁阀开启后被断开，随后施加标号为`LOW`的保持电压，用来保持电磁阀的打开状态。需要电磁阀关闭切断保持电压。 上面的过程由光耦隔离驱动端MOS和控制芯片CPLD，提供给光耦输出端的电压标号为`+12V`，参考为`PGND`。 -**上述提及的`LOW`、`HIGH`、`PGND`、`+12V`仅为板子的丝印上的称呼，都在右上角电源接口输入。** +上述提及的`LOW`、`HIGH`、`PGND`、`+12V`仅为板子的丝印上的称呼，都在右上角电源接口输入。 -CPLD为控制芯片，接收外部信号并将控制信号输出到板上的光耦，数字电路部分和光耦输入端的电源标号为`DGND`、`+12V`，**仅为板子的丝印上的称呼，都在右下角电源接口输入**，当然，输入的12V会转换为3.3V提供给数字电路。 +CPLD为控制芯片，接收外部信号并将控制信号输出到板上的光耦，数字电路部分和光耦输入端的电源标号为`DGND`、`+12V`，仅为板子的丝印上的称呼，都在右下角电源接口输入，当然，输入的12V会转换为3.3V提供给数字电路。 设计时是按照下表电压来做的 @@ -23,12 +29,16 @@ CPLD为控制芯片，接收外部信号并将控制信号输出到板上的光 | DGND | 0V | | +12V | 12V | +**本次所用汪学良的阀板加速开启用的高电压为直流100V、保持用的低电压为直流12V，另有光耦、CPLD等的弱电供电。** + 下面是阀板正面视图。 ![image-20211121221859923](README.assets/image-20211121221859923.png) ## 通信接口 +**下面非粗体字体是丁坤的阀板v1.1说明，本次烟梗分选机的汪学良师兄阀板只有`LVDS`接口，请注意** + 分3种，共4个，分别为`TTL`接口、`ISO`LATE接口、`LVDS`接口 用相应接口时应断开其他接口的跳线，焊接要启用的接口的跳线，跳线位置在接口或接口芯片旁边，大概长这个样子 @@ -41,13 +51,13 @@ CPLD为控制芯片，接收外部信号并将控制信号输出到板上的光 ## 版号 - +**下面非粗体字体是丁坤的阀板v1.1说明，本次用的汪学良板子大同小异，需要注意的是，版号没有意义，CPLD中程序目前不识别** ## 调试 **版号** -在`MB VER.`丝印标志的区域有`S1`、`S2`、`S3`、`S4`标注的0欧电阻焊接位，按`0`、`1`标注焊接即可，注意0和1不能都焊。这个设置是为阀板级联做的冗余 +在`MB VER.`丝印标志的区域有`S1`、`S2`、`S3`、`S4`标注的0欧电阻焊接位，按`0`、`1`标注焊接即可，注意0和1不能都焊。这个设置是为阀板级联做的冗余。 **烧录** @@ -71,5 +81,5 @@ CPLD烧录口为没有标出来的那个简牛口，用USB Blaster烧录的， 板子上标有CE、FC、WEEE等认证，甚至在背面写上了苹果制造的小字，这些都是随手放上去的，完全没有进行过这些认证，当然也不是作者在苹果公司的时候画的。如果要了解板子工作原理，自行看原理图，原理图内的标号命名来自于老阀板，很让人不知所措，要有耐心才能看下去 -**作者是丁坤，2019年9月入学、丁坤QQ1091546069、丁坤电话17761700156**，他刚入学时就被师兄叫去焊接老阀板，后来接替师兄做了这个仓库里的阀板，无论有没有毕业，都很乐意解答关于板子的所有问题 +**本次用的阀板作者不是丁坤，丁坤的阀板就是从本次用的汪学良的阀板基础上改进的，由于还在调试没来得及生产，且已有生产了的汪学良的阀板，所以本次使用汪学良的阀板。**丁坤2019年9月入学、丁坤QQ1091546069、丁坤电话17761700156，他刚入学时就被师兄叫去焊接汪学良的阀板，后来接替师兄做了这个仓库里的阀板，无论有没有毕业，都很乐意解答关于板子的所有问题 diff --git a/protocol/README.md b/protocol/README.md index e6aa7ad..a19b681 100644 --- a/protocol/README.md +++ b/protocol/README.md @@ -14,9 +14,7 @@ - LVDS差分 -- 100欧姆双绞线 - -*电磁兼容、信号衰减什么的统统没测过，杜邦线、软排线、双绞线随便乱用即可 +- 灰色排线 ## 数据链路层 @@ -34,6 +32,8 @@ | t2 | Data output access time | - | 250 | 280 | ns | | t3 | SEN hold time | 250 | 500 | 750 | ns | | t4 | Data output disable time | - | 250 | 280 | ns | + + *Condition at SCLK=1MHz 下面是每一位数据的具体时序 @@ -46,6 +46,8 @@ | ------ | ---------------------- | ---- | ---- | ---- | ---- | | t5 | Data output valid time | 50** | 500 | 750 | ns | | t6 | Data output hold time | 250 | 500 | 750 | ns | + + *Condition at SCLK=1MHz **Limit value diff --git a/protocol/阀板通信协议.pdf b/protocol/阀板通信协议.pdf index e8c44a4..92ecc94 100644 Binary files a/protocol/阀板通信协议.pdf and b/protocol/阀板通信协议.pdf differ