mirror of
https://github.com/NanjingForestryUniversity/valveboard.git
synced 2025-11-09 14:54:12 +00:00
a8e54608b3
add epc9600 example Co-Authored-By: Suhandong <80463329+Suhandong@users.noreply.github.com> Co-Authored-By: FGR-cmd <80112392+FGR-cmd@users.noreply.github.com>
53 lines
2.5 KiB
Plaintext
53 lines
2.5 KiB
Plaintext
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
|
# Your use of Intel Corporation's design tools, logic functions
|
|
# and other software and tools, and any partner logic
|
|
# functions, and any output files from any of the foregoing
|
|
# (including device programming or simulation files), and any
|
|
# associated documentation or information are expressly subject
|
|
# to the terms and conditions of the Intel Program License
|
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
# the Intel FPGA IP License Agreement, or other applicable license
|
|
# agreement, including, without limitation, that your use is for
|
|
# the sole purpose of programming logic devices manufactured by
|
|
# Intel and sold by Intel or its authorized distributors. Please
|
|
# refer to the applicable agreement for further details, at
|
|
# https://fpgasoftware.intel.com/eula.
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Quartus Prime
|
|
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
|
|
# Date created = 16:15:48 December 24, 2021
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Notes:
|
|
#
|
|
# 1) The default values for assignments are stored in the file:
|
|
# valveboard_firmware_assignment_defaults.qdf
|
|
# If this file doesn't exist, see file:
|
|
# assignment_defaults.qdf
|
|
#
|
|
# 2) Altera recommends that you do not modify this file. This
|
|
# file is updated automatically by the Quartus Prime software
|
|
# and any changes you make may be lost or overwritten.
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
|
|
|
|
set_global_assignment -name FAMILY "MAX II"
|
|
set_global_assignment -name DEVICE EPM1270T144C5
|
|
set_global_assignment -name TOP_LEVEL_ENTITY valveboard_firmware
|
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
|
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:15:48 DECEMBER 24, 2021"
|
|
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
|
|
set_global_assignment -name VERILOG_FILE valveboard_firmware.v
|
|
set_global_assignment -name VERILOG_FILE tb_valveboard_firmware.v
|
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
|
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
|
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V |