original version

hardware/epc9600ioextend/xme0724ioextend.PrjPcb

@@ -0,0 +1,993 @@
+[Design]
+Version=1.0
+HierarchyMode=0
+ChannelRoomNamingStyle=0
+ReleasesFolder=
+ChannelDesignatorFormatString=$Component_$RoomName
+ChannelRoomLevelSeperator=_
+OpenOutputs=1
+ArchiveProject=0
+TimestampOutput=0
+SeparateFolders=0
+TemplateLocationPath=
+PinSwapBy_Netlabel=1
+PinSwapBy_Pin=1
+AllowPortNetNames=0
+AllowSheetEntryNetNames=1
+AppendSheetNumberToLocalNets=0
+NetlistSinglePinNets=0
+DefaultConfiguration=Sources
+UserID=0xFFFFFFFF
+DefaultPcbProtel=1
+DefaultPcbPcad=0
+ReorderDocumentsOnCompile=1
+NameNetsHierarchically=0
+PowerPortNamesTakePriority=0
+AutoSheetNumbering=1
+AutoCrossReferences=0
+NewIndexingOfSheetSymbols=0
+PushECOToAnnotationFile=1
+DItemRevisionGUID=
+ReportSuppressedErrorsInMessages=0
+FSMCodingStyle=eFMSDropDownList_OneProcess
+FSMEncodingStyle=eFMSDropDownList_OneHot
+IsProjectConflictPreventionWarningsEnabled=0
+IsVirtualBomDocumentRemoved=0
+OutputPath=
+LogFolderPath=
+ManagedProjectGUID=
+IncludeDesignInRelease=0
+
+[Preferences]
+PrefsVaultGUID=
+PrefsRevisionGUID=
+
+[Document1]
+DocumentPath=Sheet.SchDoc
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=0
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=EQLVNOON
+
+[Document2]
+DocumentPath=PCB.PcbDoc
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=LIDASSEV
+
+[Document3]
+DocumentPath=lib\mw.PcbLib
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=MSKNGCIS
+
+[Document4]
+DocumentPath=lib\mw.SchLib
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=SPCOHXLI
+
+[Document5]
+DocumentPath=xme0724ioextend.PCBDwf
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=
+
+[Document6]
+DocumentPath=Sheet1.SchDoc
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+DocumentUniqueId=GDOGKSRJ
+
+[Configuration1]
+Name=Sources
+ParameterCount=0
+ConstraintFileCount=0
+ReleaseItemId=
+Variant=[No Variations]
+OutputJobsCount=0
+ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2
+ConfigurationType=Source
+
+[OutputGroup1]
+Name=Netlist Outputs
+Description=
+TargetPrinter=HP LaserJet Professional M1136 MFP
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=PADSNetlist
+OutputName1=PADS ASCII Netlist
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+OutputType2=PCADNetlist
+OutputName2=PCAD Netlist
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+
+[OutputGroup2]
+Name=Simulator Outputs
+Description=
+TargetPrinter=HP LaserJet Professional M1136 MFP
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+
+[OutputGroup3]
+Name=Documentation Outputs
+Description=
+TargetPrinter=Virtual Printer
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Composite
+OutputName1=Composite Drawing
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=PCB 3D Print
+OutputName2=PCB 3D Print
+OutputDocumentPath2=
+OutputVariantName2=[No Variations]
+OutputDefault2=0
+PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType3=PCB 3D Video
+OutputName3=PCB 3D Video
+OutputDocumentPath3=
+OutputVariantName3=[No Variations]
+OutputDefault3=0
+PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType4=PCB Print
+OutputName4=PCB Prints
+OutputDocumentPath4=
+OutputVariantName4=
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=PCBDrawing
+OutputName5=Draftsman
+OutputDocumentPath5=
+OutputVariantName5=[No Variations]
+OutputDefault5=0
+PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType6=PCBLIB Print
+OutputName6=PCBLIB Prints
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType7=Report Print
+OutputName7=Report Prints
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType8=Schematic Print
+OutputName8=Schematic Prints
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType9=SimView Print
+OutputName9=SimView Prints
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+
+[OutputGroup4]
+Name=Assembly Outputs
+Description=
+TargetPrinter=HP LaserJet Professional M1136 MFP
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Assembly
+OutputName1=Assembly Drawings
+OutputDocumentPath1=
+OutputVariantName1=[No Variations]
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=Pick Place
+OutputName2=Generates pick and place files
+OutputDocumentPath2=
+OutputVariantName2=[No Variations]
+OutputDefault2=0
+OutputType3=Test Points For Assembly
+OutputName3=Test Point Report
+OutputDocumentPath3=
+OutputVariantName3=[No Variations]
+OutputDefault3=0
+
+[OutputGroup5]
+Name=Fabrication Outputs
+Description=
+TargetPrinter=HP LaserJet Professional M1136 MFP
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=CompositeDrill
+OutputName1=Composite Drill Drawing
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=Drill
+OutputName2=Drill Drawing/Guides
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType3=Board Stack Report
+OutputName3=Report Board Stack
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType4=Final
+OutputName4=Final Artwork Prints
+OutputDocumentPath4=
+OutputVariantName4=[No Variations]
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=Gerber X2
+OutputName5=Gerber X2 Files
+OutputDocumentPath5=
+OutputVariantName5=
+OutputDefault5=0
+OutputType6=ODB
+OutputName6=ODB++ Files
+OutputDocumentPath6=
+OutputVariantName6=[No Variations]
+OutputDefault6=0
+OutputType7=Mask
+OutputName7=Solder/Paste Mask Prints
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType8=NC Drill
+OutputName8=NC Drill Files
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+Configuration8_Name1=ForceUpdateSettings
+Configuration8_Item1=False
+Configuration8_Name2=OutputConfigurationParameter1
+Configuration8_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|GenerateSeparateViaTypeFiles=False|NumberOfDecimals=5|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=SuppressTrailingZeroes|DocumentPath=E:\guoyiren\xme0724ioextend\PCB.PcbDoc
+OutputType9=IPC2581
+OutputName9=IPC-2581 Files
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+OutputType10=Plane
+OutputName10=Power-Plane Prints
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType11=Test Points
+OutputName11=Test Point Report
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+OutputType12=Gerber
+OutputName12=Gerber Files
+OutputDocumentPath12=
+OutputVariantName12=[No Variations]
+OutputDefault12=0
+Configuration12_Name1=ForceUpdateSettings
+Configuration12_Item1=False
+Configuration12_Name2=OutputConfigurationParameter1
+Configuration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=False|GenerateDRCRulesFile=False|GenerateReliefShapes=True|GenerateReports=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=50|MinusApertureTolerance=50|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=5|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16842753~1,16842754~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=50|PlusApertureTolerance=50|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=E:\guoyiren\xme0724ioextend\PCB.PcbDoc
+
+[OutputGroup6]
+Name=Report Outputs
+Description=
+TargetPrinter=HP LaserJet Professional M1136 MFP
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=BOM_PartType
+OutputName1=Bill of Materials
+OutputDocumentPath1=
+OutputVariantName1=[No Variations]
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=BOM_ReportCompare
+OutputName2=BOM Compare
+OutputDocumentPath2=
+OutputVariantName2=[No Variations]
+OutputDefault2=0
+PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType3=ComponentCrossReference
+OutputName3=Component Cross Reference Report
+OutputDocumentPath3=
+OutputVariantName3=[No Variations]
+OutputDefault3=0
+OutputType4=Export Comments
+OutputName4=Export Comments
+OutputDocumentPath4=
+OutputVariantName4=[No Variations]
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=ReportHierarchy
+OutputName5=Report Project Hierarchy
+OutputDocumentPath5=
+OutputVariantName5=[No Variations]
+OutputDefault5=0
+OutputType6=Script
+OutputName6=Script Output
+OutputDocumentPath6=
+OutputVariantName6=[No Variations]
+OutputDefault6=0
+OutputType7=SimpleBOM
+OutputName7=Simple BOM
+OutputDocumentPath7=
+OutputVariantName7=[No Variations]
+OutputDefault7=0
+OutputType8=SinglePinNetReporter
+OutputName8=Report Single Pin Nets
+OutputDocumentPath8=
+OutputVariantName8=[No Variations]
+OutputDefault8=0
+
+[OutputGroup7]
+Name=Other Outputs
+Description=
+TargetPrinter=HP LaserJet Professional M1136 MFP
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Text Print
+OutputName1=Text Print
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType2=Text Print
+OutputName2=Text Print
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType3=Text Print
+OutputName3=Text Print
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType4=Text Print
+OutputName4=Text Print
+OutputDocumentPath4=
+OutputVariantName4=
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=Text Print
+OutputName5=Text Print
+OutputDocumentPath5=
+OutputVariantName5=
+OutputDefault5=0
+PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType6=Text Print
+OutputName6=Text Print
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType7=Text Print
+OutputName7=Text Print
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType8=Text Print
+OutputName8=Text Print
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType9=Text Print
+OutputName9=Text Print
+OutputDocumentPath9=
+OutputVariantName9=
+OutputDefault9=0
+PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType10=Text Print
+OutputName10=Text Print
+OutputDocumentPath10=
+OutputVariantName10=
+OutputDefault10=0
+PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType11=Text Print
+OutputName11=Text Print
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType12=Text Print
+OutputName12=Text Print
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
+PageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType13=Text Print
+OutputName13=Text Print
+OutputDocumentPath13=
+OutputVariantName13=
+OutputDefault13=0
+PageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType14=Text Print
+OutputName14=Text Print
+OutputDocumentPath14=
+OutputVariantName14=
+OutputDefault14=0
+PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType15=Text Print
+OutputName15=Text Print
+OutputDocumentPath15=
+OutputVariantName15=
+OutputDefault15=0
+PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType16=Text Print
+OutputName16=Text Print
+OutputDocumentPath16=
+OutputVariantName16=
+OutputDefault16=0
+PageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType17=Text Print
+OutputName17=Text Print
+OutputDocumentPath17=
+OutputVariantName17=
+OutputDefault17=0
+PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+
+[OutputGroup8]
+Name=Validation Outputs
+Description=
+TargetPrinter=HP LaserJet Professional M1136 MFP
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=BOM_Violations
+OutputName1=BOM Checks Report
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+OutputType2=Component states check
+OutputName2=Server's components states check
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+OutputType3=Configuration compliance
+OutputName3=Environment configuration compliance check
+OutputDocumentPath3=
+OutputVariantName3=
+OutputDefault3=0
+OutputType4=Design Rules Check
+OutputName4=Design Rules Check
+OutputDocumentPath4=
+OutputVariantName4=
+OutputDefault4=0
+PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType5=Differences Report
+OutputName5=Differences Report
+OutputDocumentPath5=
+OutputVariantName5=
+OutputDefault5=0
+PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType6=Electrical Rules Check
+OutputName6=Electrical Rules Check
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType7=Footprint Comparison Report
+OutputName7=Footprint Comparison Report
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+
+[OutputGroup9]
+Name=Export Outputs
+Description=
+TargetPrinter=HP LaserJet Professional M1136 MFP
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=AutoCAD dwg/dxf PCB
+OutputName1=AutoCAD dwg/dxf File PCB
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+OutputType2=AutoCAD dwg/dxf Schematic
+OutputName2=AutoCAD dwg/dxf File Schematic
+OutputDocumentPath2=
+OutputVariantName2=
+OutputDefault2=0
+OutputType3=ExportPARASOLID
+OutputName3=Export PARASOLID
+OutputDocumentPath3=
+OutputVariantName3=[No Variations]
+OutputDefault3=0
+OutputType4=ExportSTEP
+OutputName4=Export STEP
+OutputDocumentPath4=
+OutputVariantName4=[No Variations]
+OutputDefault4=0
+OutputType5=ExportVRML
+OutputName5=Export VRML
+OutputDocumentPath5=
+OutputVariantName5=[No Variations]
+OutputDefault5=0
+OutputType6=Save As/Export PCB
+OutputName6=Save As/Export PCB
+OutputDocumentPath6=
+OutputVariantName6=
+OutputDefault6=0
+OutputType7=Save As/Export Schematic
+OutputName7=Save As/Export Schematic
+OutputDocumentPath7=
+OutputVariantName7=
+OutputDefault7=0
+OutputType8=Specctra Design PCB
+OutputName8=Specctra Design PCB
+OutputDocumentPath8=
+OutputVariantName8=
+OutputDefault8=0
+
+[OutputGroup10]
+Name=PostProcess Outputs
+Description=
+TargetPrinter=HP LaserJet Professional M1136 MFP
+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
+OutputType1=Copy Files
+OutputName1=Copy Files
+OutputDocumentPath1=
+OutputVariantName1=
+OutputDefault1=0
+
+[Modification Levels]
+Type1=1
+Type2=1
+Type3=1
+Type4=1
+Type5=1
+Type6=1
+Type7=1
+Type8=1
+Type9=1
+Type10=1
+Type11=1
+Type12=1
+Type13=1
+Type14=1
+Type15=1
+Type16=1
+Type17=1
+Type18=1
+Type19=1
+Type20=1
+Type21=1
+Type22=1
+Type23=1
+Type24=1
+Type25=1
+Type26=1
+Type27=1
+Type28=1
+Type29=1
+Type30=1
+Type31=1
+Type32=1
+Type33=1
+Type34=1
+Type35=1
+Type36=1
+Type37=1
+Type38=1
+Type39=1
+Type40=1
+Type41=1
+Type42=1
+Type43=1
+Type44=1
+Type45=1
+Type46=1
+Type47=1
+Type48=1
+Type49=1
+Type50=1
+Type51=1
+Type52=1
+Type53=1
+Type54=1
+Type55=1
+Type56=1
+Type57=1
+Type58=1
+Type59=1
+Type60=1
+Type61=1
+Type62=1
+Type63=1
+Type64=1
+Type65=1
+Type66=1
+Type67=1
+Type68=1
+Type69=1
+Type70=1
+Type71=1
+Type72=1
+Type73=1
+Type74=1
+Type75=1
+Type76=1
+Type77=1
+Type78=1
+Type79=1
+Type80=1
+Type81=1
+Type82=1
+Type83=1
+Type84=1
+Type85=1
+Type86=1
+Type87=1
+Type88=1
+Type89=1
+Type90=1
+Type91=1
+Type92=1
+Type93=1
+Type94=1
+Type95=1
+Type96=1
+Type97=1
+Type98=1
+Type99=1
+Type100=1
+Type101=1
+Type102=1
+Type103=1
+Type104=1
+Type105=1
+Type106=1
+Type107=1
+Type108=1
+Type109=1
+Type110=1
+Type111=1
+Type112=1
+Type113=1
+Type114=1
+Type115=1
+Type116=1
+Type117=1
+Type118=1
+Type119=1
+
+[Difference Levels]
+Type1=1
+Type2=1
+Type3=1
+Type4=1
+Type5=1
+Type6=1
+Type7=1
+Type8=1
+Type9=1
+Type10=1
+Type11=1
+Type12=1
+Type13=1
+Type14=1
+Type15=1
+Type16=1
+Type17=1
+Type18=1
+Type19=1
+Type20=1
+Type21=1
+Type22=1
+Type23=1
+Type24=1
+Type25=1
+Type26=1
+Type27=1
+Type28=1
+Type29=1
+Type30=1
+Type31=1
+Type32=1
+Type33=1
+Type34=1
+Type35=1
+Type36=1
+Type37=1
+Type38=1
+Type39=1
+Type40=1
+Type41=1
+Type42=1
+Type43=1
+Type44=1
+Type45=1
+Type46=1
+Type47=1
+Type48=1
+Type49=1
+Type50=1
+Type51=1
+Type52=1
+Type53=1
+Type54=1
+Type55=1
+Type56=1
+Type57=1
+Type58=1
+Type59=1
+Type60=1
+Type61=1
+Type62=1
+Type63=1
+Type64=1
+Type65=1
+Type66=1
+Type67=1
+Type68=1
+
+[Electrical Rules Check]
+Type1=1
+Type2=1
+Type3=2
+Type4=1
+Type5=2
+Type6=2
+Type7=0
+Type8=1
+Type9=1
+Type10=1
+Type11=2
+Type12=2
+Type13=2
+Type14=1
+Type15=1
+Type16=1
+Type17=1
+Type18=1
+Type19=1
+Type20=0
+Type21=0
+Type22=0
+Type23=0
+Type24=1
+Type25=2
+Type26=0
+Type27=2
+Type28=1
+Type29=1
+Type30=1
+Type31=1
+Type32=2
+Type33=0
+Type34=2
+Type35=1
+Type36=2
+Type37=1
+Type38=2
+Type39=2
+Type40=2
+Type41=0
+Type42=2
+Type43=1
+Type44=0
+Type45=0
+Type46=0
+Type47=0
+Type48=0
+Type49=0
+Type50=2
+Type51=0
+Type52=0
+Type53=1
+Type54=1
+Type55=1
+Type56=2
+Type57=1
+Type58=1
+Type59=1
+Type60=0
+Type61=0
+Type62=0
+Type63=0
+Type64=0
+Type65=2
+Type66=3
+Type67=2
+Type68=2
+Type69=0
+Type70=2
+Type71=2
+Type72=2
+Type73=2
+Type74=1
+Type75=2
+Type76=1
+Type77=1
+Type78=1
+Type79=1
+Type80=2
+Type81=3
+Type82=3
+Type83=3
+Type84=3
+Type85=3
+Type86=2
+Type87=2
+Type88=2
+Type89=1
+Type90=1
+Type91=3
+Type92=3
+Type93=2
+Type94=2
+Type95=2
+Type96=2
+Type97=2
+Type98=0
+Type99=1
+Type100=2
+Type101=0
+Type102=2
+Type103=2
+Type104=1
+Type105=2
+Type106=2
+Type107=2
+Type108=2
+Type109=1
+Type110=1
+Type111=1
+Type112=1
+Type113=1
+Type114=2
+Type115=2
+Type116=2
+Type117=3
+Type118=3
+Type119=3
+MultiChannelAlternate=2
+AlternateItemFail=3
+Type122=2
+Type123=1
+Type124=1
+Type125=1
+Type126=1
+
+[ERC Connection Matrix]
+L1=NNNNNNNNNNNWNNNWW
+L2=NNWNNNNWWWNWNWNWN
+L3=NWEENEEEENEWNEEWN
+L4=NNENNNWEENNWNENWN
+L5=NNNNNNNNNNNNNNNNN
+L6=NNENNNNEENNWNENWN
+L7=NNEWNNWEENNWNENWN
+L8=NWEENEENEEENNEENN
+L9=NWEENEEEENEWNEEWW
+L10=NWNNNNNENNEWNNEWN
+L11=NNENNNNEEENWNENWN
+L12=WWWWNWWNWWWNWWWNN
+L13=NNNNNNNNNNNWNNNWW
+L14=NWEENEEEENEWNEEWW
+L15=NNENNNNEEENWNENWW
+L16=WWWWNWWNWWWNWWWNW
+L17=WNNNNNNNWNNNWWWWN
+
+[Annotate]
+SortOrder=3
+SortLocation=0
+ReplaceSubparts=0
+MatchParameter1=Comment
+MatchStrictly1=1
+MatchParameter2=Library Reference
+MatchStrictly2=1
+PhysicalNamingFormat=$Component_$RoomName
+GlobalIndexSortOrder=3
+GlobalIndexSortLocation=0
+
+[PrjClassGen]
+CompClassManualEnabled=0
+CompClassManualRoomEnabled=0
+NetClassAutoBusEnabled=1
+NetClassAutoCompEnabled=0
+NetClassAutoNamedHarnessEnabled=0
+NetClassManualEnabled=1
+NetClassSeparateForBusSections=0
+
+[LibraryUpdateOptions]
+SelectedOnly=0
+UpdateVariants=1
+UpdateToLatestRevision=1
+PartTypes=0
+FullReplace=1
+UpdateDesignatorLock=1
+UpdatePartIDLock=1
+PreserveParameterLocations=1
+PreserveParameterVisibility=1
+DoGraphics=1
+DoParameters=1
+DoModels=1
+AddParameters=0
+RemoveParameters=0
+AddModels=1
+RemoveModels=1
+UpdateCurrentModels=1
+
+[DatabaseUpdateOptions]
+SelectedOnly=0
+UpdateVariants=1
+UpdateToLatestRevision=1
+PartTypes=0
+
+[Comparison Options]
+ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0
+ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0
+
+[SmartPDF]
+PageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+

hardware/epc9600ioextend/xme0724ioextend.PrjPcbStructure

@@ -0,0 +1,2 @@
+Record=TopLevelDocument|FileName=Sheet.SchDoc|SheetNumber=1
+Record=NoMainPathDocument|SourceDocument=Sheet.SchDoc|FileName=Sheet1.SchDoc|SheetNumber=2

hardware/test_lower_machine/ip_upgrade.log

@@ -0,0 +1,555 @@
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 22:01:10 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 23) to (Rev. 24)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 21:22:43 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 22) to (Rev. 23)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 21:17:10 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 21) to (Rev. 22)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 20:54:40 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 20) to (Rev. 21)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 14:00:19 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+CAUTION (success, with warnings) in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 19) to (Rev. 20)
+
+After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
+
+2. Connection Warnings
+----------------------
+
+Detected external port differences while upgrading 'system_ip_fifo_0_0'. These changes may impact your design.
+
+
+-Upgraded port 'data_count' width 12 differs from original width 14
+
+-Upgrade has added port 'fifo_valid'
+
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 13:32:41 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+CAUTION (success, with warnings) in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 18) to (Rev. 19)
+
+After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
+
+2. Connection Warnings
+----------------------
+
+Detected external port differences while upgrading 'system_ip_fifo_0_0'. These changes may impact your design.
+
+
+-Upgraded port 'data_count' width 14 differs from original width 10
+
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 13:30:55 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 17) to (Rev. 18)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 13:26:18 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 16) to (Rev. 17)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 13:13:41 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 15) to (Rev. 16)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 13:02:46 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'valve_interface_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of valve_interface_0 (user.org:user:valve_interface:1.0) from (Rev. 2) to (Rev. 3)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Thu Apr 21 12:52:37 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 14) to (Rev. 15)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Wed Apr 20 20:51:39 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_encoder_0_1'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_encoder_0_1 (user.org:user:ip_encoder:1.0) from (Rev. 2) to (Rev. 3)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Wed Apr 20 16:50:39 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_encoder_0_0'
+
+1. Summary
+----------
+
+CAUTION (success, with warnings) in the upgrade of system_ip_encoder_0_0 (user.org:user:ip_encoder:1.0) from (Rev. 1) to (Rev. 3)
+
+After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
+
+2. Connection Warnings
+----------------------
+
+Detected external port differences while upgrading 'system_ip_encoder_0_0'. These changes may impact your design.
+
+
+-Upgrade has removed port 'out_signal'
+
+-Upgrade has removed port 'out_signal_posedge'
+
+-Upgrade has added port 'out_signal_camera'
+
+-Upgrade has added port 'out_signal_camera_posedge'
+
+-Upgrade has added port 'out_signal_valve'
+
+-Upgrade has added port 'out_signal_valve_posedge'
+
+
+3. Customization warnings
+-------------------------
+
+Parameter 'DIVIDER' is no longer present on the upgraded IP 'system_ip_encoder_0_0', and cannot be set to '10'
+
+
+4. Debug Commands
+-----------------
+
+  The following debug information can be passed to Vivado as Tcl commands,
+in order to validate or debug the output of the upgrade flow.
+  You may consult any warnings from within this upgrade, and alter or remove
+the configuration parameter(s) which caused the warning; then execute the Tcl
+commands, and use the IP Customization GUI to verify the IP configuration.
+
+create_ip -vlnv user.org:user:ip_encoder:1.0 -user_name system_ip_encoder_0_0
+set_property -dict "\
+  CONFIG.Component_Name {system_ip_encoder_0_0} \
+  CONFIG.rst_n.INSERT_VIP {0} \
+  CONFIG.rst_n.POLARITY {ACTIVE_LOW} \
+  CONFIG.sys_clk.ASSOCIATED_BUSIF {} \
+  CONFIG.sys_clk.ASSOCIATED_PORT {} \
+  CONFIG.sys_clk.ASSOCIATED_RESET {} \
+  CONFIG.sys_clk.CLK_DOMAIN {} \
+  CONFIG.sys_clk.FREQ_HZ {100000000} \
+  CONFIG.sys_clk.FREQ_TOLERANCE_HZ {0} \
+  CONFIG.sys_clk.INSERT_VIP {0} \
+  CONFIG.sys_clk.PHASE {0.0} " [get_ips system_ip_encoder_0_0]
+
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Tue Apr 19 17:23:51 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+CAUTION (success, with warnings) in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 13) to (Rev. 14)
+
+After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
+
+2. Connection Warnings
+----------------------
+
+Detected external port differences while upgrading 'system_ip_fifo_0_0'. These changes may impact your design.
+
+
+-Upgrade has added port 'almost_empty'
+
+-Upgrade has added port 'almost_full'
+
+-Upgrade has added port 'data_count'
+
+-Upgrade has added port 'dout'
+
+-Upgrade has added port 'empty'
+
+-Upgrade has added port 'full'
+
+-Upgrade has added port 'rd_en'
+
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Mon Apr 18 20:50:40 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 12) to (Rev. 13)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Mon Apr 18 20:31:17 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 11) to (Rev. 12)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Mon Apr 18 20:02:55 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 10) to (Rev. 11)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Mon Apr 18 17:08:30 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 6) to (Rev. 10)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Mon Apr 18 16:46:01 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 5) to (Rev. 6)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Tue Apr  5 20:36:21 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 4) to (Rev. 5)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Tue Apr  5 20:28:59 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 3) to (Rev. 4)
+
+
+
+
+
+
+Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+| Date         : Tue Apr  5 18:58:47 2022
+| Host         : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+| Command      : upgrade_ip
+| Device       : xc7z010clg400-1
+------------------------------------------------------------------------------------
+
+Upgrade Log for IP 'system_ip_fifo_0_0'
+
+1. Summary
+----------
+
+SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 2) to (Rev. 3)
+

hardware/test_lower_machine/test_lower_machine.gen/sources_1/bd/mref/valve_interfaces/component.xml

@@ -0,0 +1,286 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>module_ref</spirit:library>
+  <spirit:name>valve_interfaces</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST_N.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sys_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sys_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>Verilog</spirit:language>
+        <spirit:modelName>valve_interfaces</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>52d9f4f7</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>Verilog</spirit:language>
+        <spirit:modelName>valve_interfaces</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>52d9f4f7</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>total_valve_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH&apos;)) - 1)">383</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sys_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rst_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>valve_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>empty</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.VALVE_PORT_NUM&apos;)) - 1)">5</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sen</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.VALVE_PORT_NUM&apos;)) - 1)">5</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.VALVE_PORT_NUM&apos;)) - 1)">5</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>VALVE_PORT_NUM</spirit:name>
+        <spirit:displayName>Valve Port Num</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VALVE_PORT_NUM">6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>TOTAL_VALVE_DATA_WIDTH</spirit:name>
+        <spirit:displayName>Total Valve Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VALVE_DATA_WIDTH</spirit:name>
+        <spirit:displayName>Valve Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_74b5137e</spirit:name>
+      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/valve_interfaces_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_a55fb5f0</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>xilinx.com:module_ref:valve_interfaces:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>VALVE_PORT_NUM</spirit:name>
+      <spirit:displayName>Valve Port Num</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VALVE_PORT_NUM">6</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TOTAL_VALVE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Total Valve Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VALVE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Valve Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">valve_interfaces_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/UserIP</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>valve_interfaces_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+      <xilinx:supportsAutoXDC>dynamic_params</xilinx:supportsAutoXDC>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:designToolContexts>
+        <xilinx:designToolContext>IPI</xilinx:designToolContext>
+      </xilinx:designToolContexts>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2022-04-21T12:40:59Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2021.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

hardware/test_lower_machine/test_lower_machine.gen/sources_1/bd/mref/valve_interfaces/xgui/valve_interfaces_v1_0.tcl

@@ -0,0 +1,55 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "TOTAL_VALVE_DATA_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "VALVE_DATA_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "VALVE_PORT_NUM" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH { PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH } {
+	# Procedure called to update TOTAL_VALVE_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH { PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH } {
+	# Procedure called to validate TOTAL_VALVE_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.VALVE_DATA_WIDTH { PARAM_VALUE.VALVE_DATA_WIDTH } {
+	# Procedure called to update VALVE_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.VALVE_DATA_WIDTH { PARAM_VALUE.VALVE_DATA_WIDTH } {
+	# Procedure called to validate VALVE_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.VALVE_PORT_NUM { PARAM_VALUE.VALVE_PORT_NUM } {
+	# Procedure called to update VALVE_PORT_NUM when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.VALVE_PORT_NUM { PARAM_VALUE.VALVE_PORT_NUM } {
+	# Procedure called to validate VALVE_PORT_NUM
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.VALVE_PORT_NUM { MODELPARAM_VALUE.VALVE_PORT_NUM PARAM_VALUE.VALVE_PORT_NUM } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.VALVE_PORT_NUM}] ${MODELPARAM_VALUE.VALVE_PORT_NUM}
+}
+
+proc update_MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH { MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH}] ${MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.VALVE_DATA_WIDTH { MODELPARAM_VALUE.VALVE_DATA_WIDTH PARAM_VALUE.VALVE_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.VALVE_DATA_WIDTH}] ${MODELPARAM_VALUE.VALVE_DATA_WIDTH}
+}
+

hardware/test_lower_machine/test_lower_machine.gen/sources_1/bd/system/hdl/system_wrapper.v

@@ -0,0 +1,120 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
+//Date        : Thu Apr 21 22:01:23 2022
+//Host        : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
+//Command     : generate_target system_wrapper.bd
+//Design      : system_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module system_wrapper
+   (DDR_addr,
+    DDR_ba,
+    DDR_cas_n,
+    DDR_ck_n,
+    DDR_ck_p,
+    DDR_cke,
+    DDR_cs_n,
+    DDR_dm,
+    DDR_dq,
+    DDR_dqs_n,
+    DDR_dqs_p,
+    DDR_odt,
+    DDR_ras_n,
+    DDR_reset_n,
+    DDR_we_n,
+    FIXED_IO_ddr_vrn,
+    FIXED_IO_ddr_vrp,
+    FIXED_IO_mio,
+    FIXED_IO_ps_clk,
+    FIXED_IO_ps_porb,
+    FIXED_IO_ps_srstb,
+    encoder_signal,
+    out_signal_camera_0,
+    sclk_0,
+    sdata_0,
+    sen_0);
+  inout [14:0]DDR_addr;
+  inout [2:0]DDR_ba;
+  inout DDR_cas_n;
+  inout DDR_ck_n;
+  inout DDR_ck_p;
+  inout DDR_cke;
+  inout DDR_cs_n;
+  inout [3:0]DDR_dm;
+  inout [31:0]DDR_dq;
+  inout [3:0]DDR_dqs_n;
+  inout [3:0]DDR_dqs_p;
+  inout DDR_odt;
+  inout DDR_ras_n;
+  inout DDR_reset_n;
+  inout DDR_we_n;
+  inout FIXED_IO_ddr_vrn;
+  inout FIXED_IO_ddr_vrp;
+  inout [53:0]FIXED_IO_mio;
+  inout FIXED_IO_ps_clk;
+  inout FIXED_IO_ps_porb;
+  inout FIXED_IO_ps_srstb;
+  input encoder_signal;
+  output out_signal_camera_0;
+  output [5:0]sclk_0;
+  output [5:0]sdata_0;
+  output [5:0]sen_0;
+
+  wire [14:0]DDR_addr;
+  wire [2:0]DDR_ba;
+  wire DDR_cas_n;
+  wire DDR_ck_n;
+  wire DDR_ck_p;
+  wire DDR_cke;
+  wire DDR_cs_n;
+  wire [3:0]DDR_dm;
+  wire [31:0]DDR_dq;
+  wire [3:0]DDR_dqs_n;
+  wire [3:0]DDR_dqs_p;
+  wire DDR_odt;
+  wire DDR_ras_n;
+  wire DDR_reset_n;
+  wire DDR_we_n;
+  wire FIXED_IO_ddr_vrn;
+  wire FIXED_IO_ddr_vrp;
+  wire [53:0]FIXED_IO_mio;
+  wire FIXED_IO_ps_clk;
+  wire FIXED_IO_ps_porb;
+  wire FIXED_IO_ps_srstb;
+  wire encoder_signal;
+  wire out_signal_camera_0;
+  wire [5:0]sclk_0;
+  wire [5:0]sdata_0;
+  wire [5:0]sen_0;
+
+  system system_i
+       (.DDR_addr(DDR_addr),
+        .DDR_ba(DDR_ba),
+        .DDR_cas_n(DDR_cas_n),
+        .DDR_ck_n(DDR_ck_n),
+        .DDR_ck_p(DDR_ck_p),
+        .DDR_cke(DDR_cke),
+        .DDR_cs_n(DDR_cs_n),
+        .DDR_dm(DDR_dm),
+        .DDR_dq(DDR_dq),
+        .DDR_dqs_n(DDR_dqs_n),
+        .DDR_dqs_p(DDR_dqs_p),
+        .DDR_odt(DDR_odt),
+        .DDR_ras_n(DDR_ras_n),
+        .DDR_reset_n(DDR_reset_n),
+        .DDR_we_n(DDR_we_n),
+        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
+        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
+        .FIXED_IO_mio(FIXED_IO_mio),
+        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
+        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
+        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
+        .encoder_signal(encoder_signal),
+        .out_signal_camera_0(out_signal_camera_0),
+        .sclk_0(sclk_0),
+        .sdata_0(sdata_0),
+        .sen_0(sen_0));
+endmodule

hardware/test_lower_machine/test_lower_machine.gen/sources_1/bd/system/ip/system_processing_system7_0_0/ps7_parameters.xml

@@ -0,0 +1,643 @@
+<?xml version="1.0" encoding="UTF-8" ?> 
+<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
+<designInfo version="1.0" >
+  <MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
+    <PARAMETERS >
+      <PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
+      <PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666" />
+      <PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
+      <PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
+      <PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
+      <PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
+      <PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
+      <PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
+      <PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
+      <PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
+      <PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
+      <PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
+      <PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
+      <PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
+      <PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
+      <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
+      <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
+      <PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
+      <PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
+      <PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
+      <PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
+      <PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
+      <PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
+      <PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
+      <PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
+      <PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
+      <PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
+      <PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
+      <PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
+      <PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
+      <PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
+      <PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
+      <PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
+      <PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
+      <PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
+      <PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" />
+      <PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
+      <PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
+      <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="4" />
+      <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
+      <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
+      <PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
+      <PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
+      <PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
+      <PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
+      <PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="200" />
+      <PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50" />
+      <PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
+      <PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
+      <PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
+      <PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
+      <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
+      <PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="" />
+      <PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
+      <PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
+      <PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="48" />
+      <PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1600.000" />
+      <PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
+      <PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="in" />
+      <PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="out" />
+      <PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
+      <PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
+      <PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="" />
+      <PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
+      <PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
+      <PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
+      <PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
+      <PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="8" />
+      <PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
+      <PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
+      <PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 3.3V" />
+      <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
+      <PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
+      <PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
+      <PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="" />
+      <PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
+      <PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
+      <PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
+      <PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
+      <PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
+      <PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
+      <PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
+      <PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
+      <PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
+      <PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
+      <PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
+      <PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 14 .. 15" />
+      <PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
+      <PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
+      <PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
+      <PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="16" />
+      <PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="54.563" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="54.563" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="54.563" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="54.563" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="2048 MBits" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="101.239" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="79.5025" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="60.536" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="71.7715" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="104.5365" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="70.676" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="59.1615" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="81.319" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41J128M16 HA-125" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="14" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
+      <PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
+      <PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
+      <PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="" />
+      <PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
+      <PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
+      <PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
+      <PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="" />
+      <PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
+      <PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" />
+      <PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
+      <PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
+      <PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
+      <PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
+      <PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
+      <PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
+      <PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
+      <PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
+    </PARAMETERS>
+    <BUSINTERFACES >
+      <BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
+      <BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
+      <BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
+    </BUSINTERFACES>
+    <CLOCKOUTS >
+      <CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="200.000000" />
+      <CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="10.000000" />
+      <CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
+      <CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
+    </CLOCKOUTS>
+  </MODULE>
+</designInfo>

hardware/test_lower_machine/test_lower_machine.gen/sources_1/bd/system/ip/system_rst_ps7_0_200M_0/system_rst_ps7_0_200M_0.xml

@@ -0,0 +1,700 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>system_rst_ps7_0_200M_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>clock</spirit:name>
+      <spirit:displayName>Clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>slowest_sync_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
+          <spirit:description>Slowest Synchronous clock frequency</spirit:description>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">2e+08</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_PORT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ext_reset</spirit:name>
+      <spirit:displayName>Ext_Reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ext_reset_in</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
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+          <spirit:name>INSERT_VIP</spirit:name>
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+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
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+          <spirit:name>INSERT_VIP</spirit:name>
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+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
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+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
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+      <spirit:displayName>peripheral_low_rst</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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+            <spirit:name>peripheral_aresetn</spirit:name>
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+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>TYPE</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE">PERIPHERAL</spirit:value>
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+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:value>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>ext_reset_in</spirit:name>
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+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>aux_reset_in</spirit:name>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>mb_debug_sys_rst</spirit:name>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:wire>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+        <spirit:name>mb_reset</spirit:name>
+        <spirit:wire>
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+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
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+        <spirit:name>bus_struct_reset</spirit:name>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+      <spirit:port>
+        <spirit:name>peripheral_reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_RST&apos;)) - 1)">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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+      <spirit:port>
+        <spirit:name>interconnect_aresetn</spirit:name>
+        <spirit:wire>
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+          <spirit:vector>
+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN&apos;)) - 1)">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
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+      <spirit:port>
+        <spirit:name>peripheral_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+            <spirit:left spirit:format="long">0</spirit:left>
+            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_NUM_PERP_ARESETN&apos;)) - 1)">0</spirit:right>
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+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
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+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
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+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+        <spirit:name>C_FAMILY</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:value>
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+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+        <spirit:displayName>Ext Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+        <spirit:displayName>Aux Rst Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
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+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+        <spirit:displayName>Ext Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="std_logic">
+        <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+        <spirit:displayName>Aux Reset High</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_BUS_RST</spirit:name>
+        <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_RST</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+        <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+        <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
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+    <spirit:choice>
+      <spirit:name>choice_list_ac75ef1e</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>Processor Reset System</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_ARESETN</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
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+    <spirit:parameter>
+      <spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
+      <spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_PERP_RST</spirit:name>
+      <spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_NUM_BUS_RST</spirit:name>
+      <spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RESET_HIGH</spirit:name>
+      <spirit:displayName>Aux Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RESET_HIGH</spirit:name>
+      <spirit:displayName>Ext Reset High</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_AUX_RST_WIDTH</spirit:name>
+      <spirit:displayName>Aux Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_EXT_RST_WIDTH</spirit:name>
+      <spirit:displayName>Ext Rst Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_rst_ps7_0_200M_0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Processor System Reset</xilinx:displayName>
+      <xilinx:coreRevision>13</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2021.2</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

hardware/test_lower_machine/test_lower_machine.gen/sources_1/bd/system/ip/system_valve_interfaces_0_0/system_valve_interfaces_0_0.xml

@@ -0,0 +1,312 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>system_valve_interfaces_0_0</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>rst_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>rst_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST_N.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST_N.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sys_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sys_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.FREQ_HZ">2e+08</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.PHASE">0.0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_PORT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_PORT"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>total_valve_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH&apos;)) - 1)">383</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sys_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>rst_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>valve_en</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>empty</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.VALVE_PORT_NUM&apos;)) - 1)">5</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sen</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.VALVE_PORT_NUM&apos;)) - 1)">5</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>sdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.VALVE_PORT_NUM&apos;)) - 1)">5</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>VALVE_PORT_NUM</spirit:name>
+        <spirit:displayName>Valve Port Num</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VALVE_PORT_NUM">6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>TOTAL_VALVE_DATA_WIDTH</spirit:name>
+        <spirit:displayName>Total Valve Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>VALVE_DATA_WIDTH</spirit:name>
+        <spirit:displayName>Valve Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_9d8b0d81</spirit:name>
+      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:description>xilinx.com:module_ref:valve_interfaces:1.0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>VALVE_PORT_NUM</spirit:name>
+      <spirit:displayName>Valve Port Num</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VALVE_PORT_NUM">6</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>TOTAL_VALVE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Total Valve Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>VALVE_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Valve Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_valve_interfaces_0_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>valve_interfaces_v1_0</xilinx:displayName>
+      <xilinx:definitionSource>module_ref</xilinx:definitionSource>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST_N.POLARITY" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2021.2</xilinx:xilinxVersion>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

hardware/test_lower_machine/test_lower_machine.gen/sources_1/bd/system/system.bxml

@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Root MajorVersion="0" MinorVersion="39">
+  <CompositeFile CompositeFileTopName="system" CanBeSetAsTop="false" CanDisplayChildGraph="true">
+    <Description>Composite Fileset</Description>
+    <Generation Name="SYNTHESIS" State="RESET" Timestamp="1652624652"/>
+    <Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1652624652"/>
+    <Generation Name="SIMULATION" State="RESET" Timestamp="1652624652"/>
+    <Generation Name="HW_HANDOFF" State="RESET" Timestamp="1652624652"/>
+    <FileCollection Name="SOURCES" Type="SOURCES"/>
+  </CompositeFile>
+</Root>

hardware/test_lower_machine/test_lower_machine.srcs/constrs_1/new/test_lower_machine.xdc

@@ -0,0 +1,59 @@
+set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[0]}]
+set_property PACKAGE_PIN E17 [get_ports {sclk_0[0]}]
+set_property PACKAGE_PIN J18 [get_ports {sclk_0[1]}]
+set_property PACKAGE_PIN B20 [get_ports {sclk_0[2]}]
+set_property PACKAGE_PIN B19 [get_ports {sclk_0[3]}]
+set_property PACKAGE_PIN H15 [get_ports {sclk_0[4]}]
+set_property PACKAGE_PIN L17 [get_ports {sclk_0[5]}]
+set_property SLEW FAST [get_ports {sclk_0[5]}]
+set_property SLEW FAST [get_ports {sclk_0[4]}]
+set_property SLEW FAST [get_ports {sclk_0[3]}]
+set_property SLEW FAST [get_ports {sclk_0[2]}]
+set_property SLEW FAST [get_ports {sclk_0[1]}]
+set_property SLEW FAST [get_ports {sclk_0[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[0]}]
+set_property SLEW FAST [get_ports {sdata_0[5]}]
+set_property SLEW FAST [get_ports {sdata_0[4]}]
+set_property SLEW FAST [get_ports {sdata_0[3]}]
+set_property SLEW FAST [get_ports {sdata_0[2]}]
+set_property SLEW FAST [get_ports {sdata_0[1]}]
+set_property SLEW FAST [get_ports {sdata_0[0]}]
+set_property PACKAGE_PIN H18 [get_ports {sdata_0[0]}]
+set_property PACKAGE_PIN E18 [get_ports {sdata_0[1]}]
+set_property PACKAGE_PIN C20 [get_ports {sdata_0[2]}]
+set_property PACKAGE_PIN K14 [get_ports {sdata_0[3]}]
+set_property PACKAGE_PIN G15 [get_ports {sdata_0[4]}]
+set_property PACKAGE_PIN D20 [get_ports {sdata_0[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[0]}]
+set_property SLEW FAST [get_ports {sen_0[5]}]
+set_property SLEW FAST [get_ports {sen_0[4]}]
+set_property SLEW FAST [get_ports {sen_0[3]}]
+set_property SLEW FAST [get_ports {sen_0[2]}]
+set_property SLEW FAST [get_ports {sen_0[1]}]
+set_property SLEW FAST [get_ports {sen_0[0]}]
+set_property PACKAGE_PIN D18 [get_ports {sen_0[0]}]
+set_property PACKAGE_PIN E19 [get_ports {sen_0[1]}]
+set_property PACKAGE_PIN J14 [get_ports {sen_0[2]}]
+set_property PACKAGE_PIN A20 [get_ports {sen_0[3]}]
+set_property PACKAGE_PIN D19 [get_ports {sen_0[4]}]
+set_property PACKAGE_PIN L16 [get_ports {sen_0[5]}]
+set_property PACKAGE_PIN W19 [get_ports encoder_signal]
+set_property IOSTANDARD LVCMOS33 [get_ports encoder_signal]
+set_property IOSTANDARD LVCMOS33 [get_ports out_signal_camera_0]
+set_property PACKAGE_PIN T10 [get_ports out_signal_camera_0]
+set_property SLEW FAST [get_ports out_signal_camera_0]

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0.xci

@@ -0,0 +1,260 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:library>xci</spirit:library>
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+  <spirit:version>1.0</spirit:version>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">12</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IGNORE_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_PROTOCOL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_PROTOCOL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRANSLATION_MODE">2</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_auto_pc_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SI_PROTOCOL">AXI3</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../test_lower_machine.gen/sources_1/bd/system/ip/system_auto_pc_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL">rtl</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;aresetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_araddr&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_arprot&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_arready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_arvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_awaddr&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_awprot&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_awready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_awvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_br
+eady&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_bresp&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_bvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_rdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_rready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_rresp&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_rvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_wdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_wready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_wstrb&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_wvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physic
+al_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_araddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arburst&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arcache&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arlen&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arlock&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arqos&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_arsize&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;
+is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_awaddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awburst&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awcache&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awlen&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awlock&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awqos&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_awsize&quot;
+:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_bid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_bready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_bresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_bvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_rdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_rid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_rlast&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_rready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_rresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_lef
+t&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_rvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_wdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_wid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_wlast&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_wready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_wstrb&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_wvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI:M_AXI&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;
+usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;ARESETN&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inf
+erred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;M_AXI&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:aximm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:aximm_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ARUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;
+:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;AWUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;BUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generat
+ed&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_CACHE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_LOCK&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_PROT&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulat
+ion.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_QOS&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_REGION&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_RRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_WSTRB&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_
+object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MAX_BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_THREADS&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:
+false}],&quot;NUM_WRITE_THREADS&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;AXI4LITE&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:fa
+lse}],&quot;RUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;SUPPORTS_NARROW_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ARADDR&quot;:[{&quot;physical_name&quot;:&quot;m_axi_araddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARBURST&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arb
+urst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARCACHE&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arid&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLEN&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLOCK&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARPROT&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARQOS&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AR
+READY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREGION&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arregion&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARSIZE&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_aruser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWADDR&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awaddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWBURST&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,
+&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWCACHE&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awid&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLEN&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLOCK&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWPROT&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWQOS&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;phys
+ical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREGION&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awregion&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWSIZE&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_bid&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_bready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BRESP&quot;:[{&quot;physical_name&quot;:&quot;m
+_axi_bresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_buser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_bvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rid&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;
+RRESP&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_ruser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wid&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,
+&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;RST&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCON
+NECT&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXI&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:aximm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:aximm_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ARUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;AWUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is
+_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;BUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simu
+lation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BURST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_CACHE&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_LOCK&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_PROT&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_QOS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_stat
+ic_object&quot;:false}],&quot;HAS_REGION&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_RRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_WSTRB&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ID_WIDTH&quot;:[{&quot;value&quot;:&quot;12&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MAX_BURST_LENGTH&quot;:[{&quot;value&quot;
+:&quot;16&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_THREADS&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_THREADS&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;
+:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;AXI3&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;,&quot;value_src&quot;:&quot;auto_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;SUPPORTS_NARR
+OW_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ARADDR&quot;:[{&quot;physical_name&quot;:&quot;s_axi_araddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARBURST&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARCACHE&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_lef
+t&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arid&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLEN&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arlen&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLOCK&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arlock&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARPROT&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARQOS&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREGION&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arregion&quot;,&quot;physical_left&quot;:
+&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARSIZE&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axi_aruser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWADDR&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awaddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWBURST&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWCACHE&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWID&quot;:[{&quot;phy
+sical_name&quot;:&quot;s_axi_awid&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLEN&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awlen&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLOCK&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awlock&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWPROT&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWQOS&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREGION&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awregion&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;p
+ort_maps_used&quot;:&quot;none&quot;}],&quot;AWSIZE&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bid&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;11&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BRESP&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axi_buser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_l
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+</spirit:design>

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/bd/system/ip/system_ip_encoder_0_1/system_ip_encoder_0_1.xci

@@ -0,0 +1,138 @@
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.PHASE" xilinx:valuePermission="bd"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;in_signal&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;out_signal_camera&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;out_signal_camera_posedge&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;out_signal_valve&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;out_signal_valve_posedge&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_araddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_aresetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_arprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_arready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;ph
+ysical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_arvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_awaddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_awprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_awready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_awvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_bready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_bresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_bvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_rdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_rready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_
+right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_rresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_rvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_wdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_wready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_wstrb&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_wvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;S00_AXI&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:aximm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:aximm_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;memory_map_ref&quot;:&quot;S00_AXI&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ARUSER_WIDTH&quot;:[{&quot;
+value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;AWUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;BUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_pe
+rmission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_CACHE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_LOCK&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_PROT&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,
+&quot;is_static_object&quot;:false}],&quot;HAS_QOS&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_REGION&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_RRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_WSTRB&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;
+user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MAX_BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;ip_propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;2&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_THREADS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;2&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_THREADS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,
+&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;AXI4LITE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_st
+atic_object&quot;:false}],&quot;SUPPORTS_NARROW_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;WIZ_DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;WIZ_NUM_REG&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;WUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ARADDR&quot;:[{&quot;physical_name&quot;:&quot;s00
+_axi_araddr&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARPROT&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_arprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_arready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_arvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWADDR&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_awaddr&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWPROT&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_awprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_awready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,
+&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_awvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_bready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BRESP&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_bresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_bvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RDATA&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_rdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_rready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RRESP&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_rresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_r
+ight&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_rvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WDATA&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_wdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_wready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WSTRB&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_wstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_wvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S00_AXI_CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S00_AXI&quot;,&quot;
+value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s00_axi_aresetn&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src
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+RITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}},&quot;memory_maps&quot;:{&quot;S00_AXI&quot;:{&quot;address_blocks&quot;:{&quot;S00_AXI_reg&quot;:[{&quot;base_address&quot;:&quot;0&quot;,&quot;range&quot;:&quot;4096&quot;,&quot;display_name&quot;:&quot;&quot;,&quot;description&quot;:&quot;&quot;,&quot;usage&quot;:&quot;register&quot;,&quot;access&quot;:&quot;&quot;}]}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/bd/system/ip/system_ip_fifo_0_0/system_ip_fifo_0_0.xci

@@ -0,0 +1,138 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
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+      <spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="ip_fifo" spirit:version="1.0"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_BASEADDR">0xFFFFFFFF</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_HIGHADDR">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_ip_fifo_0_0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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+      <spirit:vendorExtensions>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.PHASE" xilinx:valuePermission="bd"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;almost_empty&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;almost_full&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;data_count&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;11&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;dout&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;383&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;empty&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;fifo_valid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;full&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rd_en&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_araddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_aresetn&quot;:[{&quot;direction
+&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_arprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_arready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_arvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_awaddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_awprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_awready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_awvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_bready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_bresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_bvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;
+,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_rdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_rready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_rresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_rvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_wdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_wready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s00_axi_wstrb&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s00_axi_wvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;S00_AXI&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:aximm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:aximm_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;memory_
+map_ref&quot;:&quot;S00_AXI&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;6&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ARUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;AWUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;BUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH
+&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_CACHE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_LOCK&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;form
+at&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_PROT&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_QOS&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_REGION&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_RRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_WSTRB&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ID_WIDTH&quot;:[{&quot;value&quot;
+:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MAX_BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;ip_propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;2&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_THREADS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;2&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_per
+mission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_THREADS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;AXI4LITE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long
+&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;SUPPORTS_NARROW_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;WIZ_DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;WIZ_NUM_REG&quot;:[{&quot;value&quot;:&quot;15&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;WUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}
+],&quot;WUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ARADDR&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_araddr&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;5&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARPROT&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_arprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_arready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_arvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWADDR&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_awaddr&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;5&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWPROT&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_awprot&quot;,&quot;p
+hysical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_awready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_awvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_bready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BRESP&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_bresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_bvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RDATA&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_rdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;n
+one&quot;}],&quot;RREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_rready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RRESP&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_rresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_rvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WDATA&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_wdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WREADY&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_wready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WSTRB&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_wstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WVALID&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_wvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_le
+ft&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S00_AXI_CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S00_AXI&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;s00_axi_aresetn&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}
+],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S00_AXI_RST&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_r
+tl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;s00_axi_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}},&quot;memory_maps&quot;:{&quot;S00_AXI&quot;:{&quot;address_blocks&quot;:{&quot;S00_AXI_reg&quot;:[{&quot;base_address&quot;:&quot;0&quot;,&quot;range&quot;:&quot;4096&quot;,&quot;display_name&quot;:&quot;&quot;,&quot;description&quot;:&quot;&quot;,&quot;usage&quot;:&quot;register&quot;,&quot;access&quot;:&quot;&quot;}]}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/bd/system/ip/system_ps7_0_axi_periph_0/system_ps7_0_axi_periph_0.xci

@@ -0,0 +1,362 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_ps7_0_axi_periph_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_interconnect" spirit:version="2.1"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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+</spirit:design>

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/bd/system/ip/system_rst_ps7_0_200M_0/system_rst_ps7_0_200M_0.xci

@@ -0,0 +1,101 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;aux_reset_in&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;bus_struct_reset&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;dcm_locked&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;ext_reset_in&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;interconnect_aresetn&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;mb_debug_sys_rst&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;mb_reset&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;peripheral_aresetn&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;peripheral_reset&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;slowest_sync_clk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;
+is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;aux_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;aux_reset_in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;bus_struct_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_i
+nferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;bus_struct_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;clock&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;gen
+erated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;def
+ault&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;slowest_sync_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;dbg_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:tru
+e}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;mb_debug_sys_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;ext_reset&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;ext_reset_in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_
+left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;interconnect_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;interconnect_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;mb_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_t
+ype&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PROCESSOR&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;mb_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;peripheral_high_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permissio
+n&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;peripheral_reset&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;peripheral_low_rst&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:false}],&quot;P
+OLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;PERIPHERAL&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;peripheral_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/bd/system/ip/system_s00_data_fifo_0/system_s00_data_fifo_0.xci

@@ -0,0 +1,264 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_s00_data_fifo_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_data_fifo" spirit:version="2.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">ARESETN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">2e+08</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">2e+08</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_FIFO_DELAY" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_FIFO_DEPTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WRITE_FIFO_DELAY" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WRITE_FIFO_DEPTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;aclk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;aresetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_araddr&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_arprot&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_arready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_arvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_awaddr&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_awprot&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_awready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_awvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_br
+eady&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_bresp&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_bvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_rdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_rready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_rresp&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_rvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_wdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_wready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;m_axi_wstrb&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;m_axi_wvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physic
+al_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_araddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_arready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_arvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_awaddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_awready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_awvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_bready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_bresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_ri
+ght&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_bvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_rdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_rready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_rresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_rvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_wdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_wready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;s_axi_wstrb&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;s_axi_wvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:
+clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;S_AXI:M_AXI&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;ARESETN&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:fa
+lse,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;aclk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;M_AXI&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:aximm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:aximm_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;
+:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ARUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;AWUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;BUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;l
+ong&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_CACHE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_LOCK&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;
+is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_PROT&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_QOS&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_REGION&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_RRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_WSTRB&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_sta
+tic_object&quot;:false}],&quot;ID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MAX_BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_THREADS&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]
+,&quot;NUM_WRITE_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_THREADS&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;AXI4LITE&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}
+],&quot;RUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;SUPPORTS_NARROW_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port
+_maps&quot;:{&quot;ARADDR&quot;:[{&quot;physical_name&quot;:&quot;m_axi_araddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARBURST&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARCACHE&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLEN&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLOCK&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARPROT&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;
+logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARQOS&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREGION&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arregion&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARSIZE&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_aruser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_arvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWADDR&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awaddr&quot;,&quot;physical_left&quot;:&quot;3
+1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWBURST&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWCACHE&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLEN&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLOCK&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWPROT&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWQOS&quot;:[{&quot;physical_nam
+e&quot;:&quot;m_axi_awqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREGION&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awregion&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWSIZE&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_awvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_bid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_u
+sed&quot;:&quot;none&quot;}],&quot;BREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_bready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BRESP&quot;:[{&quot;physical_name&quot;:&quot;m_axi_bresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_buser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_bvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logica
+l_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RRESP&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_ruser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_rvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WDATA&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WLAST&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;
+logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WREADY&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WSTRB&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WUSER&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WVALID&quot;:[{&quot;physical_name&quot;:&quot;m_axi_wvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;RST&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LO
+W&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;TYPE&quot;:[{&quot;value&quot;:&quot;INTERCONNECT&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;S_AXI&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:aximm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:aximm_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ARUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred
+&quot;:true,&quot;is_static_object&quot;:false}],&quot;AWUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;BUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation
+.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_CACHE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_LOCK&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_PROT&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_sta
+tic_object&quot;:false}],&quot;HAS_QOS&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_REGION&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_RRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_WSTRB&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ID_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;ip_propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;valu
+e&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MAX_BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;ip_propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_THREADS&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_THREADS&quot;:[{&quot;va
+lue&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;AXI4LITE&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;
+,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;SUPPORTS_NARROW_BURST&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;ip_propagated&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant_prop&quot;,&quot;value_permission&quot;:&quot;bd&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ARADDR&quot;:[{&quot;physical_name&quot;:&quot;s_axi_araddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARBURST&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arburst&quot;,&quot;physical_left
+&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARCACHE&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLEN&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLOCK&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARPROT&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARQOS&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREADY&quot;:[{&quot;physical_nam
+e&quot;:&quot;s_axi_arready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREGION&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arregion&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARSIZE&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axi_aruser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_arvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWADDR&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awaddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWBURST&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;p
+ort_maps_used&quot;:&quot;none&quot;}],&quot;AWCACHE&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLEN&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLOCK&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWPROT&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWQOS&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical
+_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREGION&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awregion&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWSIZE&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_awvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BRESP&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bresp&quot;,&quot;physical_left
+&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axi_buser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_bvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axi_rdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_rid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RLAST&quot;:[{&quot;physical_name&quot;:&quot;s_axi_rlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_rready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RRESP&quot;:[{&quot;physical_name&quot;:&quot;s_
+axi_rresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axi_ruser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_rvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WDATA&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wdata&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WLAST&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WREADY&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WST
+RB&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wstrb&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WUSER&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WVALID&quot;:[{&quot;physical_name&quot;:&quot;s_axi_wvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/bd/system/ip/system_valve_interfaces_0_0/system_valve_interfaces_0_0.xci

@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_valve_interfaces_0_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="module_ref" spirit:name="valve_interfaces" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_PORT"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_HZ">2e+08</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.PHASE">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VALVE_PORT_NUM">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_valve_interfaces_0_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALVE_PORT_NUM">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
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+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+          <xilinx:boundaryDescriptionInfo>
+            <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;empty&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;rst_n&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;sclk&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;sdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;sen&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;5&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;sys_clk&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;total_valve_data&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;383&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;valve_en&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;rst_n&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,
+&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;bd_and_user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;rst_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;sys_clk&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd_and_user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_PORT&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd_and_user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;&quot;,
+&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd_and_user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;system_processing_system7_0_0_FCLK_CLK0&quot;,&quot;value_src&quot;:&quot;default_prop&quot;,&quot;value_permission&quot;:&quot;bd_and_user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;2e+08&quot;,&quot;value_src&quot;:&quot;user_prop&quot;,&quot;value_permission&quot;:&quot;bd_and_user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd_and_user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.
+0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;bd_and_user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;sys_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}}}}"/>
+          </xilinx:boundaryDescriptionInfo>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/bd/system/system.bda

@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="utf-8"?>
+<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
+  <key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
+  <key id="BP" for="node" attr.name="base_param" attr.type="string"/>
+  <key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
+  <key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
+  <key id="HP" for="node" attr.name="high_param" attr.type="string"/>
+  <key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
+  <key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
+  <key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
+  <key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
+  <key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
+  <key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
+  <key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
+  <key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
+  <key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
+  <key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
+  <key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
+  <key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
+  <key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
+  <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
+  <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
+    <node id="n0">
+      <data key="BA">0x43C10000</data>
+      <data key="BP">C_S00_AXI_BASEADDR</data>
+      <data key="HA">0x43C1FFFF</data>
+      <data key="HP">C_S00_AXI_HIGHADDR</data>
+      <data key="MA">Data</data>
+      <data key="MX">/processing_system7_0</data>
+      <data key="MI">M_AXI_GP0</data>
+      <data key="MS">SEG_ip_encoder_0_S00_AXI_reg</data>
+      <data key="MV">xilinx.com:ip:processing_system7:5.5</data>
+      <data key="TM">both</data>
+      <data key="SX">/ip_encoder_0</data>
+      <data key="SI">S00_AXI</data>
+      <data key="SS">S00_AXI_reg</data>
+      <data key="SV">user.org:user:ip_encoder:1.0</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <node id="n1">
+      <data key="VH">2</data>
+      <data key="VM">system</data>
+      <data key="VT">VR</data>
+    </node>
+    <node id="n2">
+      <data key="TU">active</data>
+      <data key="VH">2</data>
+      <data key="VT">PM</data>
+    </node>
+    <node id="n3">
+      <data key="VM">system</data>
+      <data key="VT">BC</data>
+    </node>
+    <node id="n4">
+      <data key="BA">0x43C00000</data>
+      <data key="BP">C_S00_AXI_BASEADDR</data>
+      <data key="HA">0x43C0FFFF</data>
+      <data key="HP">C_S00_AXI_HIGHADDR</data>
+      <data key="MA">Data</data>
+      <data key="MX">/processing_system7_0</data>
+      <data key="MI">M_AXI_GP0</data>
+      <data key="MS">SEG_ip_fifo_0_S00_AXI_reg</data>
+      <data key="MV">xilinx.com:ip:processing_system7:5.5</data>
+      <data key="TM">both</data>
+      <data key="SX">/ip_fifo_0</data>
+      <data key="SI">S00_AXI</data>
+      <data key="SS">S00_AXI_reg</data>
+      <data key="SV">user.org:user:ip_fifo:1.0</data>
+      <data key="TU">register</data>
+      <data key="VT">AC</data>
+    </node>
+    <edge id="e0" source="n3" target="n1"/>
+    <edge id="e1" source="n1" target="n2"/>
+    <edge id="e2" source="n0" target="n2">
+      <data key="EH">2</data>
+    </edge>
+    <edge id="e3" source="n4" target="n2">
+      <data key="EH">2</data>
+    </edge>
+  </graph>
+</graphml>

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/bd/system/ui/bd_c954508f.ui

@@ -0,0 +1,49 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"0.926657",
+   "Default View_TopLeft":"-156,-150",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
+#  -string -flagsOSRD
+preplace port DDR -pg 1 -lvl 5 -x 1620 -y 320 -defaultsOSRD
+preplace port FIXED_IO -pg 1 -lvl 5 -x 1620 -y 340 -defaultsOSRD
+preplace port port-id_encoder_signal -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD
+preplace port port-id_out_signal_camera_0 -pg 1 -lvl 5 -x 1620 -y 520 -defaultsOSRD
+preplace portBus sen_0 -pg 1 -lvl 5 -x 1620 -y 120 -defaultsOSRD
+preplace portBus sclk_0 -pg 1 -lvl 5 -x 1620 -y 100 -defaultsOSRD
+preplace portBus sdata_0 -pg 1 -lvl 5 -x 1620 -y 140 -defaultsOSRD
+preplace inst processing_system7_0 -pg 1 -lvl 1 -x 230 -y 360 -defaultsOSRD
+preplace inst ps7_0_axi_periph -pg 1 -lvl 2 -x 640 -y 140 -defaultsOSRD
+preplace inst rst_ps7_0_200M -pg 1 -lvl 1 -x 230 -y 160 -defaultsOSRD
+preplace inst ip_encoder_0 -pg 1 -lvl 3 -x 1010 -y 430 -defaultsOSRD
+preplace inst ila_0 -pg 1 -lvl 4 -x 1410 -y 430 -defaultsOSRD
+preplace inst valve_interfaces_0 -pg 1 -lvl 4 -x 1410 -y 120 -defaultsOSRD
+preplace inst ip_fifo_0 -pg 1 -lvl 3 -x 1010 -y 160 -defaultsOSRD
+preplace netloc in_signal_0_1 1 0 3 NJ 260 470J 420 NJ
+preplace netloc ip_encoder_0_out_signal_camera 1 3 2 1230J 300 1590J
+preplace netloc ip_fifo_0_dout 1 3 1 1220 80n
+preplace netloc ip_fifo_0_empty 1 3 1 N 160
+preplace netloc processing_system7_0_FCLK_CLK0 1 0 4 20 60 440 290 820 280 1240
+preplace netloc rst_ps7_0_200M_peripheral_aresetn 1 1 2 430 280 800
+preplace netloc valve_interfaces_0_sclk 1 4 1 NJ 100
+preplace netloc valve_interfaces_0_sdata 1 4 1 NJ 140
+preplace netloc valve_interfaces_0_sen 1 4 1 NJ 120
+preplace netloc ip_encoder_0_out_signal_valve_posedge 1 3 1 1210 140n
+preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 4 30 460 490 330 790J 40 1230J
+preplace netloc ip_encoder_0_out_signal_camera_posedge 1 2 2 830 520 1200
+preplace netloc ip_encoder_0_out_signal_valve 1 3 1 1190 420n
+preplace netloc processing_system7_0_DDR 1 1 4 460J 310 NJ 310 NJ 310 1600J
+preplace netloc processing_system7_0_FIXED_IO 1 1 4 480J 320 NJ 320 NJ 320 1580J
+preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 450 60n
+preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 N 130
+preplace netloc ps7_0_axi_periph_M01_AXI 1 2 1 810 150n
+levelinfo -pg 1 0 230 640 1010 1410 1620
+pagesize -pg 1 -db -bbox -sgen -160 0 1820 540
+"
+}
+{
+   "da_axi4_cnt":"2",
+   "da_board_cnt":"1",
+   "da_clkrst_cnt":"2",
+   "da_ps7_cnt":"1"
+}

hardware/test_lower_machine/test_lower_machine.srcs/sources_1/new/valve_interfaces.v

@@ -0,0 +1,46 @@
+module valve_interfaces#(
+      parameter VALVE_PORT_NUM = 6,
+      parameter TOTAL_VALVE_DATA_WIDTH = 384,
+      parameter VALVE_DATA_WIDTH = 48
+    )(
+      input [TOTAL_VALVE_DATA_WIDTH - 1:0] total_valve_data,
+      input sys_clk,
+      input rst_n,
+      input valve_en,
+      input empty,
+      output [VALVE_PORT_NUM - 1:0] sclk,
+      output [VALVE_PORT_NUM - 1:0] sen,
+      output [VALVE_PORT_NUM - 1:0] sdata
+    );
+ 
+    reg [1:0] valve_en_buf;
+    wire [TOTAL_VALVE_DATA_WIDTH - 1:0] total_valve_data_safe = empty ? 'b0 : total_valve_data;
+    wire valve_en_delayed = valve_en_buf[1];
+    always @(posedge sys_clk) begin
+      if (!rst_n) begin
+        valve_en_buf <= 0;
+      end
+      else begin
+        valve_en_buf[0] <= valve_en;
+        valve_en_buf[1] <= valve_en_buf[0];
+      end
+    end
+  
+    generate
+      genvar i;
+      for(i=0; i<VALVE_PORT_NUM; i=i+1) begin: valve_interface_inst
+          valve_interface_0 valve_interface_inst (
+            .input_data(total_valve_data_safe[i * VALVE_DATA_WIDTH + : VALVE_DATA_WIDTH]),  // input wire [47 : 0] input_data
+            .sys_clk(sys_clk),        // input wire sys_clk
+            .rst_n(rst_n),            // input wire rst_n
+            .valve_en(valve_en_delayed),      // input wire valve_en
+            .sclk(sclk[i]),              // output wire sclk
+            .sen(sen[i]),                // output wire sen
+            .sdata(sdata[i])            // output wire sdata
+          );
+      end
+    endgenerate
+
+    
+    
+endmodule

hardware/test_lower_machine/test_lower_machine.tmp/ip_encoder_v1_0_project/ip_encoder_v1_0_project.cache/wt/project.wpc

@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:3
+eof:

hardware/test_lower_machine/test_lower_machine.tmp/ip_encoder_v1_0_project/ip_encoder_v1_0_project.hw/ip_encoder_v1_0_project.lpr

@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2021.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>

hardware/test_lower_machine/test_lower_machine.tmp/ip_encoder_v1_0_project/ip_encoder_v1_0_project.xpr

@@ -0,0 +1,233 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2021.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="56" Path="/home/miaow/zynq/test_lower_machine/test_lower_machine.tmp/ip_encoder_v1_0_project/ip_encoder_v1_0_project.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="be1d97afcb2144ffb3f5d0c96ef1bebc"/>
+    <Option Name="Part" Val="xc7z010clg400-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2021.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2020.4"/>
+    <Option Name="SimulatorVersionQuesta" Val="2020.4"/>
+    <Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
+    <Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
+    <Option Name="SimulatorVersionRiviera" Val="2020.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
+    <Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../../../ip_repo"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../../ip_repo/ip_encoder_1.0/src/encoder.v">
+        <FileInfo>
+          <Attr Name="Library" Val=""/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../ip_repo/ip_encoder_1.0/hdl/ip_encoder_v1_0_S00_AXI.v">
+        <FileInfo>
+          <Attr Name="Library" Val=""/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../ip_repo/ip_encoder_1.0/hdl/ip_encoder_v1_0.v">
+        <FileInfo>
+          <Attr Name="Library" Val=""/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../ip_repo/ip_encoder_1.0/component.xml">
+        <FileInfo SFType="IPXACT"/>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ip_encoder_v1_0"/>
+        <Option Name="TopRTLFile" Val="$PPRDIR/../../../ip_repo/ip_encoder_1.0/hdl/ip_encoder_v1_0.v"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ip_encoder_v1_0"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="15">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

hardware/test_lower_machine/test_lower_machine.xpr

@@ -0,0 +1,361 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2021.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="56" Path="/home/miaow/zynq/test_lower_machine/test_lower_machine.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="25b0c33abe3a4dd19f352e7b795735b7"/>
+    <Option Name="Part" Val="xc7z010clg400-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2021.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2020.4"/>
+    <Option Name="SimulatorVersionQuesta" Val="2020.4"/>
+    <Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
+    <Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
+    <Option Name="SimulatorVersionRiviera" Val="2020.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
+    <Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../ip_repo"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="39"/>
+    <Option Name="WTModelSimExportSim" Val="39"/>
+    <Option Name="WTQuestaExportSim" Val="39"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="39"/>
+    <Option Name="WTRivieraExportSim" Val="39"/>
+    <Option Name="WTActivehdlExportSim" Val="39"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/ip/valve_interface_0.xcix">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/ip/valve_interface_0/valve_interface_0.xci">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/valve_interface_0/valve_interface_0.xci"/>
+          <Attr Name="ImportTime" Val="1650517366"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/valve_interfaces.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/bd/system/system.bd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+        <CompFileExtendedInfo CompFileName="system.bd" FileRelPathName="ip/system_ila_0_0/system_ila_0_0.xci">
+          <Proxy FileSetName="system_ila_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system.bd" FileRelPathName="ip/system_valve_interfaces_0_0/system_valve_interfaces_0_0.xci">
+          <Proxy FileSetName="system_valve_interfaces_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system.bd" FileRelPathName="ip/system_ip_fifo_0_0/system_ip_fifo_0_0.xci">
+          <Proxy FileSetName="system_ip_fifo_0_0"/>
+        </CompFileExtendedInfo>
+      </File>
+      <File Path="$PGENDIR/sources_1/bd/system/hdl/system_wrapper.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="system_wrapper"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/new/test_lower_machine.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/test_lower_machine.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="system_wrapper"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/system_wrapper.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_valve_interfaces_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_valve_interfaces_0_0" RelGenDir="$PGENDIR/system_valve_interfaces_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_valve_interfaces_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ila_0_0" RelGenDir="$PGENDIR/system_ila_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_ila_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_ip_fifo_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ip_fifo_0_0" RelGenDir="$PGENDIR/system_ip_fifo_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_ip_fifo_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="15">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/system_wrapper.dcp" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_valve_interfaces_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_valve_interfaces_0_0" Part="xc7z010clg400-1" ConstrsSet="system_valve_interfaces_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_valve_interfaces_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ila_0_0" Part="xc7z010clg400-1" ConstrsSet="system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ila_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_ip_fifo_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ip_fifo_0_0" Part="xc7z010clg400-1" ConstrsSet="system_ip_fifo_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ip_fifo_0_0_synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_valve_interfaces_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="system_valve_interfaces_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_valve_interfaces_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_valve_interfaces_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ila_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_ip_fifo_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="system_ip_fifo_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ip_fifo_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ip_fifo_0_0_impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

script/README.md

@@ -0,0 +1,2 @@
+待补充
+

source/.gitignore

@@ -1,66 +0,0 @@
-# Prerequisites
-*.d
-
-.vscode/*
-!.vscode/settings.json
-!.vscode/tasks.json
-!.vscode/launch.json
-!.vscode/extensions.json
-!.vscode/c_cpp_properties.json
-!.vscode/*.code-snippets
-build/
-
-# Local History for Visual Studio Code
-.history/
-
-# Built Visual Studio Code Extensions
-*.vsix
-# Object files
-*.o
-*.ko
-*.obj
-*.elf
-
-# Linker output
-*.ilk
-*.map
-*.exp
-
-# Precompiled Headers
-*.gch
-*.pch
-
-# Libraries
-*.lib
-*.a
-*.la
-*.lo
-
-# Shared objects (inc. Windows DLLs)
-*.dll
-*.so
-*.so.*
-*.dylib
-
-# Executables
-*.exe
-*.out
-*.app
-*.i*86
-*.x86_64
-*.hex
-
-# Debug files
-*.dSYM/
-*.su
-*.idb
-*.pdb
-
-# Kernel Module Compile Results
-*.mod*
-*.cmd
-.tmp_versions/
-modules.order
-Module.symvers
-Mkfile.old
-dkms.conf

source/.vscode/c_cpp_properties.json

@@ -1,24 +0,0 @@
-{
-    "configurations": [
-        {
-            "name": "ARM",
-            "includePath": [
-                "${workspaceFolder}/**",
-                "/home/miaow/software/arm-2011.03/lib/gcc/arm-none-linux-gnueabi/4.5.2/include/**"
-            ],
-            "defines": [],
-            "compilerPath": "/home/miaow/software/arm-2011.03/bin/arm-none-linux-gnueabi-gcc",
-            "cStandard": "gnu99",
-            "cppStandard": "gnu++17",
-            "intelliSenseMode": "linux-gcc-arm",
-            "configurationProvider": "ms-vscode.makefile-tools",
-            "browse": {
-                "path": [
-                    "${workspaceFolder}",
-                    "/home/miaow/software/arm-2011.03/lib/gcc/arm-none-linux-gnueabi/4.5.2/include"
-                ]
-            }
-        }
-    ],
-    "version": 4
-}

source/.vscode/settings.json

@@ -1,76 +0,0 @@
-{
-    "files.associations": {
-        "stdlib.h": "c",
-        "assert.h": "c",
-        "valve_init.h": "c",
-        "gpio.h": "c",
-        "type_traits": "c",
-        "gpio_common.h": "c",
-        "unistd.h": "c",
-        "stdint.h": "c",
-        "stat.h": "c",
-        "types.h": "c",
-        "pthread.h": "c",
-        "pthreadtypes.h": "c",
-        "valve.h": "c",
-        "queue.h": "c",
-        "stdio.h": "c",
-        "encoder.h": "c",
-        "semaphore.h": "c"
-    },
-    "makefile.launchConfigurations": [
-        {
-            "cwd": "/home/miaow/zlg/epc9600",
-            "binaryPath": "/home/miaow/zlg/epc9600",
-            "binaryArgs": []
-        }
-    ],
-
-
-     // Doxygen documentation generator set
-    // 文件注释：版权信息模板
-    "doxdocgen.file.copyrightTag": [
-        "@copyright Copyright (c) {year}  miaow"
-    ],
-    // 文件注释：自定义模块，这里我添加一个修改日志
-    "doxdocgen.file.customTag": [
-        "@par Changelog:",
-        "<table>",
-        "<tr><th>Date       <th>Version <th>Author  <th>Description",
-        "<tr><td>{date} <td>1.0     <td>miaow     <td>内容",
-        "</table>",
-    ],
-    // 文件注释的组成及其排序
-    "doxdocgen.file.fileOrder": [
-        "file",		// @file
-        "brief",	// @brief 简介
-        "author",	// 作者
-        "version",	// 版本
-        "date",		// 日期
-        "empty",	// 空行
-        "copyright",// 版权
-        "empty",
-        "custom"	// 自定义
-    ],
-    // 下面时设置上面标签tag的具体信息
-    "doxdocgen.file.fileTemplate": "@file {name}",
-    "doxdocgen.file.versionTag": "@version 1.0",
-    "doxdocgen.generic.authorEmail": "3703781@qq.com",
-    "doxdocgen.generic.authorName": "miaow",
-    "doxdocgen.generic.authorTag": "@author {author} ({email})",
-    // 日期格式与模板
-    "doxdocgen.generic.dateFormat": "YYYY/MM/DD",
-    "doxdocgen.generic.dateTemplate": "@date {date}",
-	
-    // 根据自动生成的注释模板（目前主要体现在函数注释上）
-    "doxdocgen.generic.order": [
-        "brief",
-        "tparam",
-        "param",
-        "return"
-    ],
-    "doxdocgen.generic.paramTemplate": "@param {param}",
-    "doxdocgen.generic.returnTemplate": "@return {type} ",
-    "doxdocgen.generic.splitCasingSmartText": true
-}
-   

source/Makefile

@@ -1,86 +0,0 @@
-#makefile for file_ioctl
-CROSS_COMPILE ?= /home/miaow/software/arm-2011.03/bin/arm-none-linux-gnueabi-
-TARGET := target
-BUILD_DIR := build
-
-ifeq ("$(origin V)", "command line")
-  KBUILD_VERBOSE = $(V)
-endif
-ifndef KBUILD_VERBOSE
-  KBUILD_VERBOSE = 0
-endif
-
-ifeq ($(KBUILD_VERBOSE),1)
-  quiet =
-  Q =
-else
-  quiet=quiet_
-  Q = @
-endif
-
-ifneq ($(filter 4.%,$(MAKE_VERSION)),)	# make-4
-ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
-  quiet=silent_
-endif
-else					# make-3.8x
-ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
-  quiet=silent_
-endif
-endif
-
-
-SRC := $(wildcard *.c)
-ASM_SRC := $(wildcard *.s)
-OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.o)))
-ASM_OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.o)))
-DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.dis)))
-ASM_DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.dis)))
-
-_TARGET := $(BUILD_DIR)/$(TARGET)
-TARGET_DIS := $(BUILD_DIR)/$(TARGET).dis
-
-LD		= $(CROSS_COMPILE)ld
-CC		= $(CROSS_COMPILE)gcc
-CPP		= $(CC) -E
-AR		= $(CROSS_COMPILE)ar
-LDR		= $(CROSS_COMPILE)ldr
-STRIP		= $(CROSS_COMPILE)strip
-OBJCOPY		= $(CROSS_COMPILE)objcopy
-OBJDUMP		= $(CROSS_COMPILE)objdump
-CFLAGS = -g -std=gnu99 -Wall -I.
-LDFLAGS = -lpthread -lc -lm -lrt -marmelf_linux_eabi
-
-.SECONDARY:
-
-.PHONY:all
-all: $(_TARGET) $(DIS) $(ASM_DIS) $(TARGET_DIS)
-
-$(BUILD_DIR)/%.i:%.c %.h Makefile | $(BUILD_DIR)
-	$(Q)$(CC) -E $(CFLAGS) $< -o $@
-$(BUILD_DIR)/%.s:$(BUILD_DIR)/%.i Makefile | $(BUILD_DIR)
-	$(Q)$(CC) -S $(CFLAGS) $< -o $@
-$(BUILD_DIR)/%.o:$(BUILD_DIR)/%.s Makefile | $(BUILD_DIR)
-	$(Q)$(CC) -c $(CFLAGS) $< -o $@
-$(BUILD_DIR)/%.o:%.s Makefile | $(BUILD_DIR)
-	$(Q)$(CC) -c $(CFLAGS) $< -o $@
-$(BUILD_DIR)/%.dis:$(BUILD_DIR)/%.o Makefile | $(BUILD_DIR)
-	$(Q)$(OBJDUMP) -s -d $< > $@
-$(TARGET_DIS):$(_TARGET) Makefile | $(BUILD_DIR)
-	$(Q)$(OBJDUMP) -s -d $< > $@
-$(_TARGET):$(OBJ) $(ASM_OBJ) Makefile | $(BUILD_DIR)
-	$(Q)$(CC) $(OBJ) $(ASM_OBJ) $(LDFLAGS) -o $@
-
-
-.PHONY:clean
-clean:
-	$(Q)$(RM) $(BUILD_DIR)/* -f
-
-.PHONY:install
-install:$(TARGET)
-	$(Q)chmod 777 $(TARGET)
-
-.PHONY:$(BUILD_DIR)
-$(BUILD_DIR):
-	$(Q)if [ ! -d $(BUILD_DIR) ]; then mkdir -p $@; fi
-	
-	

source/camera_trigger.c

@@ -1,141 +0,0 @@
-/**
- * @file camera_trigger.c
- * @brief Control the camera to grab frames
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2022/01/09
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/09 <td>1.0     <td>miaow     <td>Write this file
- * </table>
- */
-#include <camera_trigger.h>
-#include <gpio_common.h>
-#include <pthread.h>
-#include <unistd.h>
-#include <semaphore.h>
-#include <time.h>
-
-// Write to the file desc (global variable `gpo_value_fd` in gpio_common.c) to operate a gpio.
-// So gpo_value_fd should be initialized in valve_init with great care.
-// Also, gpo_value_fd/gpi_value_fd is used in other .c files (read pluse of encoder, etc).
-#define __GPO_SET_BIT(pin_t) __GPO_SET(pin_t, GPIO_VALUE_HIGH)
-#define __GPO_CLR_BIT(pin_t) __GPO_SET(pin_t, GPIO_VALUE_LOW)
-#define __GPO_SET(pin_t, value_t) write(gpo_value_fd[GPIO_PINDEF_TO_INDEX(pin_t)], gpio_pin_value_str[GPIO_VALUEDEF_TO_INDEX(value_t)], gpio_pin_value_str_len[GPIO_VALUEDEF_TO_INDEX(value_t)])
-
-/**
- * @brief Variables definition used in this module
- */
-typedef struct
-{
-    sem_t need_send;  // Value >= 0 will cause a the camera grabbing one frame
-    sem_t is_sending; // value >= 0 means the last trigger signal is sent
-    pthread_mutex_t loop_thread_mutex;
-    int need_exit;         // loop_thread joins to parent-thread at need_exit==1
-    pthread_t loop_thread; // The sending thread
-} cameratrigger_global_t;
-
-static cameratrigger_global_t _global_structure;
-
-static void *loop_thread_func(void *param);
-
-/**
- * @brief Initialize camera trigger gpo and start loop_thread which keeps listening the trig signal
- * @return 0 - success, -1 - error
- */
-int cameratrigger_init()
-{
-    int trig_line_index = GPIO_PINDEF_TO_INDEX(TRIG_LINE);
-    // export the trigger line
-    int fd_export = open(GPIO_EXPORT_PATH, O_WRONLY);
-    ON_ERROR_RET(fd_export, GPIO_EXPORT_PATH, "export in cameratrigger_init()", -1);
-
-    if (!is_file_exist(gpio_value_file_gpo_list[trig_line_index]))
-    {
-        int ret = write(fd_export, gpo_pin_str[trig_line_index], gpo_pin_str_len[trig_line_index]);
-        ON_ERROR_RET(ret, gpo_pin_str[trig_line_index], "open value file in cameratrigger_init()", -1);
-    }
-    close(fd_export);
-
-    gpo_value_fd[trig_line_index] = open(gpio_value_file_gpo_list[trig_line_index], O_RDWR);
-    ON_ERROR_RET(gpo_value_fd[trig_line_index], gpio_value_file_gpo_list[trig_line_index], "open value file in cameratrigger_init()", -1);
-    __GPO_SET_BIT(TRIG_LINE);
-
-    sem_init(&_global_structure.need_send, 0, 0);
-    sem_init(&_global_structure.is_sending, 0, 1);
-    pthread_mutex_init(&_global_structure.loop_thread_mutex, NULL);
-
-    int ret = pthread_create(&_global_structure.loop_thread, NULL, loop_thread_func, NULL);
-    ON_ERROR_RET(ret, "thread create error in cameratrigger_init()", "", -1);
-
-    return 0;
-}
-
-/**
- * @brief This function runs in child thread and triggles the camera to grab one frame
- */
-void *loop_thread_func(void *param)
-{
-    printf("loop_thread in %s start\r\n", __FILE__);
-    int need_exit = 0;
-    struct timespec ts;
-    int ret = 0;
-    while (!need_exit)
-    {
-
-        clock_gettime(CLOCK_REALTIME, &ts);
-        ts.tv_sec += 1;
-        ret = sem_timedwait(&_global_structure.need_send, &ts);
-        if (ret == 0)
-        {
-            __GPO_CLR_BIT(TRIG_LINE);
-            usleep(200);
-            __GPO_SET_BIT(TRIG_LINE);
-            sem_post(&_global_structure.is_sending);
-        }
-        pthread_mutex_lock(&_global_structure.loop_thread_mutex);
-        need_exit = _global_structure.need_exit;
-        pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
-    }
-    printf("loop_thread in %s exit\r\n", __FILE__);
-    return NULL;
-}
-
-/**
- * @brief Trigger a frame grabbing of the camera
- * @note This function will wait until last grabbing accomplished
- * @return 0 - success
- */
-int cameratrigger_trig()
-{
-    sem_wait(&_global_structure.is_sending);
-    sem_post(&_global_structure.need_send);
-    return 0;
-}
-
-/**
- * @brief Deinitialize and release all resources of this module
- * @note This function DOES BLOCKS 1s at most and DOES NOT UNEXPORT gpo
- * @return 0 - success, -1 - error
- */
-int cameratrigger_deinit()
-{
-    sem_wait(&_global_structure.is_sending);
-    pthread_mutex_lock(&_global_structure.loop_thread_mutex);
-    _global_structure.need_exit = 1;
-    pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
-    pthread_join(_global_structure.loop_thread, NULL);
-    pthread_mutex_destroy(&_global_structure.loop_thread_mutex);
-    sem_destroy(&_global_structure.is_sending);
-    sem_destroy(&_global_structure.need_send);
-    _global_structure.need_exit = 0;
-
-    int ret = close(gpo_value_fd[GPIO_PINDEF_TO_INDEX(TRIG_LINE)]);
-    ON_ERROR_RET(ret, "close value file in cameratrigger_deinit()", "", -1);
-
-    return 0;
-}

source/camera_trigger.h

@@ -1,29 +0,0 @@
-/**
- * @file camera_trigger.c
- * @brief Control the camera to grab frames
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2022/01/09
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/09 <td>1.0     <td>miaow     <td>Write this file
- * </table>
- */
-#ifndef __CAMERA_TRIGGER_H
-#define __CAMERA_TRIGGER_H
-#include <gpio_common.h>
-
-typedef enum
-{
-    TRIG_LINE=GPIO_PINDEF_TO_INDEX(GPO6)
-}cameratrigger_pin_enum_t;
-
-int cameratrigger_init(void);
-int cameratrigger_trig(void);
-int cameratrigger_deinit(void);
-
-#endif

source/delay.s

@@ -1,18 +0,0 @@
-.global delay_us
-.func delay_us
-delay_us:
-    cmp r0, #0
-    moveq pc, lr
-    stmfd	sp!, {r1, r2, fp, lr}
-    mov r1, r0
-    big_loop:
-        ldr r2, =266
-        loop:
-            sub r2, r2, #1
-            cmp r2, #0
-            bne loop
-        sub r1, r1, #1
-        cmp r1, #0
-        bne big_loop
-    ldmfd	sp!, {r1, r2, fp, pc}
-.endfunc

source/encoder.c

@@ -1,130 +0,0 @@
-/**
- * @file encoder.c
- * @brief Manage the encoder and realize a callback function
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2022/01/09
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/09 <td>1.0     <td>Miaow     <td>Write this module
- * </table>
- */
-#include <poll.h>
-#include <stdlib.h>
-#include <encoder.h>
-#include <pthread.h>
-#include <stdint.h>
-#include <gpio_common.h>
-
-
-#define __GPI_GET(pin_t) read(gpi_value_fd[GPIO_PINDEF_TO_INDEX(pin_t)], _global_structure.buf, sizeof(_global_structure.buf))
-
-/**
- * @brief Variables definition used in this module
- */
-typedef struct
-{
-    int need_exit;  // loop_thread joins to parent-thread at need_exit==1
-    pthread_t loop_thread;  // The main deamon thread
-    encoder_callback callback_func;  // Restore the pointer to callback function
-    pthread_mutex_t loop_thread_mutex;  // Used in the main deamon thread and deinit function, surrounding the need_exit variable
-    char buf[1];  // Buffer for reading the file descripter
-} encoder_global_t;
-
-
-static encoder_global_t _global_structure;  //! the global variables used in this file (module)
-
-static void *loop_thread_func(void *param);
-
-/**
- * @brief Initialize the encoder related gpio and thread 
- * @param func The callback function, which is called at rising edge of the encoder
- * @return 0-success, -1 - failed
- */
-int encoder_init(encoder_callback func)
-{
-
-    int phase_b_index = GPIO_PINDEF_TO_INDEX(ENCODER_PHASEB);
-    // export
-    int fd_export = open(GPIO_EXPORT_PATH, O_WRONLY);
-    ON_ERROR_RET(fd_export, GPIO_EXPORT_PATH, "export in encoder_init()", -1);
-
-    if (!is_file_exist(gpio_value_file_gpi_list[phase_b_index]))  // do not export if value file exist
-    {
-        int ret = write(fd_export, gpi_pin_str[phase_b_index], gpi_pin_str_len[phase_b_index]);
-        ON_ERROR_RET(ret, gpi_pin_str[phase_b_index], "open value file in encoder_init()", -1);
-    }
-    close(fd_export);
-
-    // open edge file
-    int edge_fd = open(gpio_edge_file_gpi_list[phase_b_index], O_RDWR);
-    ON_ERROR_RET(edge_fd, gpio_edge_file_gpi_list[phase_b_index], "open edge file in encoder_init()", -1);
-    write(edge_fd, "rising", 7);
-    close(edge_fd);
-
-    // open value file
-    gpi_value_fd[phase_b_index] = open(gpio_value_file_gpi_list[phase_b_index], O_RDWR);
-    ON_ERROR_RET(gpi_value_fd[phase_b_index], gpio_value_file_gpi_list[phase_b_index], "open value file in encoder_init()", -1);
-
-    _global_structure.callback_func = func;
-
-    // start loop thread
-    pthread_create(&_global_structure.loop_thread, NULL, loop_thread_func, NULL);
-
-    return 0;
-}
-
-/**
- * @brief Deinitialize the encoder module, stop the thread and release resources
- * @return 0-success, -1 - failed
- */
-int encoder_deinit()
-{
-    // stop loop_thread
-    pthread_mutex_lock(&_global_structure.loop_thread_mutex);
-    _global_structure.need_exit = 1;
-    pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
-    // wait loop_thread to stop
-    pthread_join(_global_structure.loop_thread, NULL);
-    pthread_mutex_destroy(&_global_structure.loop_thread_mutex);
-    _global_structure.need_exit = 0;
-    // close value file
-    int ret = close(gpi_value_fd[GPIO_PINDEF_TO_INDEX(ENCODER_PHASEB)]);
-    ON_ERROR_RET(ret, "close value file in encoder_init()", "", -1);
-    gpi_value_fd[GPIO_PINDEF_TO_INDEX(ENCODER_PHASEB)] = 0;
-    return 0;
-}
-
-/**
- * @brief Call the callback function set when initialization at rising edge of the encoder pulse
- * @param param Not used
- * @return 0
- */
-static void *loop_thread_func(void *param)
-{
-    // 调用一次encoder_callback func
-    printf("loop thread in %s start\r\n", __FILE__);
-    struct pollfd fds[1];
-    fds[0].fd = gpi_value_fd[GPIO_PINDEF_TO_INDEX(ENCODER_PHASEB)];
-    fds[0].events = POLLPRI;
-    int need_exit = 0;
-    
-    while (!need_exit)
-    {
-        if (poll(fds, 1, 1000) && (fds[0].revents & POLLPRI))
-        {
-            __GPI_GET(ENCODER_PHASEB);
-            _global_structure.callback_func();
-        }
-        pthread_mutex_lock(&_global_structure.loop_thread_mutex);
-        need_exit = _global_structure.need_exit;
-        pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
-    }
-    printf("loop thread in %s exit\r\n", __FILE__);
-    return (void *)NULL;
-}
-

source/encoder.h

@@ -1,35 +0,0 @@
-/**
- * @file encoder.h
- * @brief Manage the encoder and realize a callback function
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2022/01/09
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/09 <td>1.0     <td>Miaow     <td>Write this module
- * </table>
- */
-#ifndef __ENCODER_H
-#define __ENCODER_H
-#include <gpio_common.h>
-
-/**
- * @brief Pin definition
- * @note Actually, only ENCODER_PHASEB is used
- */
-typedef enum
-{
-    ENCODER_PHASEA=GPIO_PINDEF_TO_INDEX(GPI0),
-    ENCODER_PHASEB=GPIO_PINDEF_TO_INDEX(GPI2)
-}encoder_pin_enum_t;
-
-typedef void (*encoder_callback)(void);  // Callback funtion prototype.
-
-int encoder_init(encoder_callback func);
-int encoder_deinit(void);
-
-#endif

source/gpio_common.c

@@ -1,73 +0,0 @@
-/**
- * @file gpio_common.c
- * @brief Operate the GPIO port of Zhou Ligong linux industrial control board
- * @details is_file_exist(const char *file_path) determine whether the specified file exists
- *          print_array(int *array, int count) used to print out the value of the queue buffer, easy to debug and use
- * @mainpage github.com/NanjingForestryUniversity
- * @author miaow
- * @email 3703781@qq.com
- * @version v0.9.0
- * @date 2021/12/25 merry christmas
- */
-#include <gpio_common.h>
-
-char perror_buffer[1024] = {0};
-
-char *gpio_value_file_gpo_list[8] = {GPIO_GET_VALUE_FILE(52), GPIO_GET_VALUE_FILE(53),
-                                     GPIO_GET_VALUE_FILE(54), GPIO_GET_VALUE_FILE(55),
-                                     GPIO_GET_VALUE_FILE(56), GPIO_GET_VALUE_FILE(57),
-                                     GPIO_GET_VALUE_FILE(58), GPIO_GET_VALUE_FILE(59)};
-
-char *gpio_value_file_gpi_list[8] = {GPIO_GET_VALUE_FILE(44), GPIO_GET_VALUE_FILE(45),
-                                     GPIO_GET_VALUE_FILE(46), GPIO_GET_VALUE_FILE(47),
-                                     GPIO_GET_VALUE_FILE(48), GPIO_GET_VALUE_FILE(49),
-                                     GPIO_GET_VALUE_FILE(50), GPIO_GET_VALUE_FILE(51)};
-
-char *gpio_edge_file_gpi_list[8] = {GPIO_GET_EDGE_FILE(44), GPIO_GET_EDGE_FILE(45),
-                                     GPIO_GET_EDGE_FILE(46), GPIO_GET_EDGE_FILE(47),
-                                     GPIO_GET_EDGE_FILE(48), GPIO_GET_EDGE_FILE(49),
-                                     GPIO_GET_EDGE_FILE(50), GPIO_GET_EDGE_FILE(51)};
-
-char *gpo_pin_str[8] = {"52", "53", "54", "55", "56", "57", "58", "59"};
-int gpo_pin_str_len[8] = {2, 2, 2, 2, 2, 2, 2, 2};
-char *gpi_pin_str[8] = {"44", "45", "46", "47", "48", "49", "50", "51"};
-int gpi_pin_str_len[8] = {2, 2, 2, 2, 2, 2, 2, 2};
-char *gpio_pin_value_str[2] = {"0", "1"};
-int gpio_pin_value_str_len[2] = {1, 1};
-int gpo_value_fd[8] = {0};
-int gpi_value_fd[8] = {0};
-
-/**
- * @brief determine whether the specified file exists
- * @param file_path file path
- * @return 1 - success, -1 - error
- */
-int is_file_exist(const char *file_path)
-{
-    if (file_path == NULL)
-        return -1;
-    if (access(file_path, F_OK) == 0)
-        return 1;
-    return -1;
-}
-
-/**
- * @brief Put the processed host computer data into the queue
- * @param array Buffer pointer in the queue
- * @param count The number of data in the buffer
- */
-void print_array(int *array, int count)
-{
-    if (count == 0)
-    {
-        printf("[]\r\n");
-        return;
-    }
-    printf("[");
-    int i;
-    for (i = 0; i < count - 1; i++)
-    {
-        printf("%d,", array[i]);
-    }
-    printf("%d]\r\n", array[i]);
-}

source/gpio_common.h

@@ -1,90 +0,0 @@
-#ifndef __GPIO_COMMON_H
-#define __GPIO_COMMON_H
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <stdint.h>
-#include <fcntl.h>
-#include <termios.h>
-#include <errno.h>
-#include <string.h>
-#include <assert.h>
-#include <sys/types.h>
-
-#define GPIO_EXPORT_PATH "/sys/class/gpio/export"
-#define GPIO_GET_PIN_STR(pin) #pin
-#define GPIO_GET_VALUE_FILE(pin) "/sys/class/gpio/gpio" #pin "/value"
-#define GPIO_GET_EDGE_FILE(pin) "/sys/class/gpio/gpio" #pin "/edge"
-#define GPIO_PINDEF_TO_INDEX(pin_t) ((int)pin_t)
-#define GPIO_VALUEDEF_TO_INDEX(value_t) ((int)value_t)
-
-#define ON_ERROR(res, message1, message2)                                                                 \
-    if (res < 0)                                                                                          \
-    {                                                                                                     \
-        sprintf(perror_buffer, "error %d at %s:%d, %s, %s", res, __FILE__, __LINE__, message1, message2); \
-        perror(perror_buffer);                                                                            \
-    }
-
-#define ON_ERROR_RET_VOID(res, message1, message2) \
-    ON_ERROR(res, message1, message2);             \
-    if (res < 0)                                   \
-    {                                              \
-        res = 0;                                   \
-        return;                                    \
-    }
-
-#define ON_ERROR_RET(res, message1, message2, retval) \
-    ON_ERROR(res, message1, message2);                \
-    if (res < 0)                                      \
-    {                                                 \
-        res = 0;                                      \
-        return retval;                                \
-    }
-
-typedef enum
-{
-    GPO0 = 0,
-    GPO1 = 1,
-    GPO2 = 2,
-    GPO3 = 3,
-    GPO4 = 4,
-    GPO5 = 5,
-    GPO6 = 6,
-    GPO7 = 7
-} gpo_pin_enum_t;
-
-typedef enum
-{
-    GPI0 = 0,
-    GPI1 = 1,
-    GPI2 = 2,
-    GPI3 = 3,
-    GPI4 = 4,
-    GPI5 = 5,
-    GPI6 = 6,
-    GPI7 = 7
-} gpi_pin_enum_t;
-
-typedef enum
-{
-    GPIO_VALUE_LOW = 0,
-    GPIO_VALUE_HIGH = 1
-} gpio_value_enum_t;
-
-int is_file_exist(const char *file_path);
-extern char perror_buffer[];
-extern char *gpio_value_file_gpo_list[];
-extern char *gpio_value_file_gpi_list[];
-extern char *gpio_edge_file_gpi_list[];
-extern char *gpo_pin_str[];
-extern char *gpi_pin_str[];
-extern int gpo_pin_str_len[];
-extern int gpi_pin_str_len[];
-extern char *gpio_pin_value_str[];
-extern int gpo_value_fd[];
-extern int gpi_value_fd[];
-extern int gpio_pin_value_str_len[];
-void print_array(int *array, int count);
-
-#endif

source/host_computer.c

@@ -1,293 +0,0 @@
-/**
- * @file host_computer.c
- * @brief Commnunicate with host computer. Protocal is described in hostcomputer通信协议.md
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2022/01/16
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/16 <td>1.0     <td>miaow     <td>Write this file
- * </table>
- */
-#include <host_computer.h>
-#include <sys/socket.h>
-#include <netinet/in.h>
-#include <arpa/inet.h>
-#include <netinet/tcp.h>
-#include <sys/ioctl.h>
-#include <stdlib.h>
-#include <pthread.h>
-#include <gpio_common.h>
-
-/**
- * @brief Queue handle structure
- */
-typedef struct
-{
-    queue_uint64_msg_t *data_q;        // A pointer to the queue for valve data
-    queue_uint64_msg_t *cmd_q;         // A pointer to the queue for commands
-    int socket_fd;                     // The socket fd for receiving commands and data
-    int need_exit;                     // The flag variable to indicate whether to exit the loop_thread in this file
-    pthread_t loop_thread;             // The main routine of this module, which parses commands and data from host, puts them into the queue
-    pthread_mutex_t loop_thread_mutex; // The mutex for loop_thread
-} hostcomputer_t;
-
-static hostcomputer_t _global_structure;
-void *loop_thread_func(void *param);
-
-/**
- * @brief Pre initialize host computer module
- * @param data_q A pointer to the queue storing the valve data from host computer
- * @param cmd_q A pointer to the queue storing the cmd from host computer
- * @return 0 - success 
- */
-int hostcomputer_init(queue_uint64_msg_t *data_q, queue_uint64_msg_t *cmd_q)
-{
-    _global_structure.data_q = data_q;
-    _global_structure.cmd_q = cmd_q;
-
-    pthread_mutex_init(&_global_structure.loop_thread_mutex, NULL);
-    pthread_create(&_global_structure.loop_thread, NULL, loop_thread_func, NULL);
-
-    return 0;
-}
-
-/**
- * @brief Receive `size` bytes from a socket. If no more bytes are available at the socket, this function return -1 when timeout reaches.
- * @param fd The socket fd
- * @param buf Received bytes
- * @param size Number of bytes to receive
- * @return  These calls return the number of bytes received, or -1 if time out occurred
- */
-static int recvn(int fd, char *buf, int size)
-{
-    char *pt = buf;
-    int count = size;
-    while (count > 0)
-    {
-        int len = recv(fd, pt, count, 0);
-        // if (len == -1 && (errno == EAGAIN || errno == EWOULDBLOCK))
-        // {
-        //     // printf("recv timeout\r\n");
-        // }
-        if (len == -1)
-            return -1;
-        else if (len == 0)
-            return size - count;
-        pt += len;
-        count -= len;
-    }
-    return size;
-}
-
-/**
- * @brief To inspect the status of TCP connection
- * @param sock_fd The socket
- * @return 0 - Not connected, 1 - connected
- */
-static int is_connected(int sock_fd)
-{
-    struct tcp_info info;
-    int len = sizeof(info);
-    getsockopt(sock_fd, IPPROTO_TCP, TCP_INFO, &info, (socklen_t *)&len);
-    return info.tcpi_state == TCP_ESTABLISHED;
-}
-
-/**
- * @brief This function runs in child thread and handles communication with host computer
- * @param param NULL
- * @return NULL
- */
-void *loop_thread_func(void *param)
-{
-    printf("loop thread in %s start\r\n", __FILE__);
-    int need_exit = 0;
-    char pre;
-    uint16_t n_bytes;
-    char type[2];
-    char data[99999];
-    char check[2];
-    while (!need_exit)
-    {
-        pthread_mutex_lock(&_global_structure.loop_thread_mutex);
-        need_exit = _global_structure.need_exit;
-        pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
-        // reconnect if not connected
-        if (!is_connected(_global_structure.socket_fd))
-        {
-            _global_structure.socket_fd = socket(AF_INET, SOCK_STREAM, 0);
-            struct timeval timeout = {.tv_sec = 10, .tv_usec = 0};
-            setsockopt(_global_structure.socket_fd, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout));
-            ON_ERROR_RET(_global_structure.socket_fd, "hostcomputer_init", "", NULL);
-            struct sockaddr_in serAddr;
-            serAddr.sin_family = AF_INET;
-            serAddr.sin_addr.s_addr = inet_addr(HOST_COMPUTER_IP);
-            serAddr.sin_port = htons(HOST_COMPUTER_PORT);
-            printf("Connecting host computer...");
-            fflush(stdout);
-            if (connect(_global_structure.socket_fd, (struct sockaddr *)&serAddr, sizeof(struct sockaddr_in)) == -1)
-            {
-                sleep(2);
-                close(_global_structure.socket_fd);
-                printf("FAILED\r\n");
-                continue;
-            }
-            printf("OK\r\n");
-        }
-
-        // =======================parse the protocal=========================================
-
-        if (recvn(_global_structure.socket_fd, (char *)&pre, 1) > 1)
-        {
-            // close(_global_structure.socket_fd);
-            printf("pre_len!=1\r\n");
-            continue;
-        }
-        if (pre != 0xAA)
-        {
-            // close(_global_structure.socket_fd);
-            // printf("%X ", (int)pre);
-            fflush(stdout);
-            continue;
-        }
-        if (recvn(_global_structure.socket_fd, (char *)&n_bytes, 2) != 2)
-        {
-            // close(_global_structure.socket_fd);
-            printf("n_bytes_len!=2\r\n");
-            continue;
-        }
-        n_bytes = ntohs(n_bytes);
-        if (n_bytes > 4096 || n_bytes < 2)
-        {
-            // close(_global_structure.socket_fd);
-            printf("n_bytes>4096 or n_bytes<2\r\n");
-            continue;
-        }
-        if (recvn(_global_structure.socket_fd, (char *)type, 2) != 2)
-        {
-            // close(_global_structure.socket_fd);
-            printf("type!=2\r\n");
-            continue;
-        }
-        if (recvn(_global_structure.socket_fd, (char *)data, n_bytes - 2) != n_bytes - 2)
-        {
-            // close(_global_structure.socket_fd);
-            printf("data_len!=n_bytes-2\r\n");
-            continue;
-        }
-
-        data[n_bytes - 2] = 0;
-        if (recvn(_global_structure.socket_fd, (char *)check, 2) != 2)
-        {
-            // close(_global_structure.socket_fd);
-            printf("check_len!=2\r\n");
-            continue;
-        }
-        if (recvn(_global_structure.socket_fd, (char *)&pre, 1) != 1)
-        {
-            // close(_global_structure.socket_fd);
-            printf("end_len!=1\r\n");
-            continue;
-        }
-        if (pre != 0xBB)
-        {
-            // close(_global_structure.socket_fd);
-            printf("end!=0xBB\r\n");
-            continue;
-        }
-
-        // =======================parse the commands=========================================
-        // commands are reformed as an uint64_t, 0x--------xxxxxxxx, where `-` refers its paramter and `x` is HOSTCOMPUTER_CMD
-        if (type[0] == 'd' && type[1] == 'a')
-        {
-            // printf("%dbytes of data put to data queue\r\n", (int)n_bytes - 2);
-            if (n_bytes - 2 != 6 * HOST_COMPUTER_PICTURE_ROW_NUM)
-            {
-                printf("n_bytes-2!=%d\r\n", 6 * HOST_COMPUTER_PICTURE_ROW_NUM);
-                continue;
-            }
-            int data_index = 0;
-            uint64_t tmp_one_line_data = 0;
-            // valve arange(nth in rank)       6th     5th     4th     3th     2th     1th
-            // byte arange(nth received)       (6*x)th (5*x)th (4*x)th (3*x)th (2*x)th xth
-            //                                 where x in range(500)
-            //
-
-            for (int i = 0; i < HOST_COMPUTER_PICTURE_ROW_NUM; i++)
-            {
-                tmp_one_line_data = 0ul;
-                for (int j = 0; j < 6; j++)
-                {
-                    tmp_one_line_data <<= 8;
-                    tmp_one_line_data |= data[data_index++];
-                }
-                queue_uint64_put(_global_structure.data_q, tmp_one_line_data);
-            }
-        }
-        else if (type[0] == 's' && type[1] == 't')
-        {
-            // printf("Start put to cmd queue, param:%d\r\n", (int)atoll(data));
-            queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_START);
-        }
-        else if (type[0] == 's' && type[1] == 'p')
-        {
-            // printf("Stop put to cmd queue, param:%d\r\n", (int)atoll(data));
-            queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_STOP);
-        }
-        else if (type[0] == 't' && type[1] == 'e')
-        {
-            // printf("Test put to cmd queue, param:%d\r\n", (int)atoll(data));
-            queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_TEST);
-        }
-        else if (type[0] == 'p' && type[1] == 'o')
-        {
-            // printf("Power on put to cmd queue, param:%d\r\n", (int)atoll(data));
-            queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_POWERON);
-        }
-        else if (type[0] == 's' && type[1] == 'c')
-        {
-            // printf("Set camera triggle pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
-            queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT);
-        }
-        else if (type[0] == 's' && type[1] == 'v')
-        {
-            // printf("Set valve pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
-            queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETVALVETRIGPULSECOUNT);
-        }
-        else if (type[0] == 's' && type[1] == 'd')
-        {
-            // printf("Set camera to valve pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
-            queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETCAMERATOVALVEPULSECOUNT);
-        }
-        else
-        {
-            printf("Unknown command received");
-        }
-    }
-    printf("loop thread in %s exit\r\n", __FILE__);
-    return NULL;
-}
-
-/**
- * @brief Deinitialize and release resources used by host computer module
- * @return int 
- */
-int hostcomputer_deinit()
-{
-    pthread_mutex_lock(&_global_structure.loop_thread_mutex);
-    _global_structure.need_exit = 1;
-    pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
-    pthread_join(_global_structure.loop_thread, NULL);
-    pthread_mutex_destroy(&_global_structure.loop_thread_mutex);
-
-    close(_global_structure.socket_fd);
-    _global_structure.socket_fd = 0;
-    _global_structure.need_exit = 0;
-    _global_structure.cmd_q = NULL;
-    _global_structure.data_q = NULL;
-    return 0;
-}

source/host_computer.h

@@ -1,45 +0,0 @@
-/**
- * @file host_computer.h
- * @brief Commnunicate with host computer. Protocal is described in hostcomputer通信协议.md
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2022/01/16
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/16 <td>1.0     <td>miaow     <td>Write this file
- * </table>
- */
-#ifndef __HOST_COMPUTER_H
-#define __HOST_COMPUTER_H
-
-#include <queue_uint64.h>
-#include <pthread.h>
-#include <stdint.h>
-
-#define HOST_COMPUTER_IP "192.168.2.10"
-#define HOST_COMPUTER_PORT 13452
-#define HOST_COMPUTER_PICTURE_ROW_NUM 500
-
-/**
- * @brief The commonds, ref hostcomputer通信协议.md
- */
-enum HOSTCOMPUTER_CMD
-{
-    HOSTCOMPUTER_CMD_START = 2,
-    HOSTCOMPUTER_CMD_STOP = 3,
-    HOSTCOMPUTER_CMD_TEST = 4,
-    HOSTCOMPUTER_CMD_POWERON = 5,
-    HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT = 6,
-    HOSTCOMPUTER_CMD_SETVALVETRIGPULSECOUNT = 7,
-    HOSTCOMPUTER_CMD_SETCAMERATOVALVEPULSECOUNT = 8
-    
-};
-
-int hostcomputer_init(queue_uint64_msg_t *data_q, queue_uint64_msg_t *cmd_q);
-int hostcomputer_deinit(void);
-
-#endif

source/main.c

@@ -1,244 +0,0 @@
-#include <valve.h>
-#include <sys/socket.h>
-#include <arpa/inet.h>
-#include <math.h>
-#include <queue_uint64.h>
-#include <camera_trigger.h>
-#include <encoder.h>
-#include <host_computer.h>
-
-/**
- * @brief Value of state machine
- */
-typedef enum
-{
-    NOT_INITIALIZED = 0,
-    INITIALIZED = 1,
-    RUNNING = 2,
-    SLEEPING = 3,
-    STOPPED = 4
-} status_enum_t;
-
-valvedata_t valvedata = {0};
-queue_uint64_msg_t data_queue = {0};
-queue_uint64_msg_t cmd_queue = {0};
-
-static int count_valve = 1, count_camera = 0, count_valve_should_be = 2;
-static uint64_t count_continues = 0UL, count_valve_continues = 0UL, count_camera_continues = 0UL;
-static status_enum_t status = NOT_INITIALIZED;
-static int camera_trigger_pulse_count = 0;
-static int valve_should_trigger_pulse_count = 0;
-static int valve_trigger_pulse_count = 0;
-static int camera_to_valve_pulse_count = 0;
-
-#define ROTATE_UINT64_RIGHT(x, n) ((x) >> (n)) | ((x) << ((64) - (n)))
-#define ROTATE_UINT64_LEFT(x, n) ((x) << (n)) | ((x) >> ((64) - (n)))
-
-void on_encoder(void);
-void valve_test(float ms_for_each_channel);
-void valve_test2(float ms_for_each_channel, int which_channel);
-void valve_test3(float ms_for_each_channel);
-void process_cmd(uint64_t *cmd);
-
-int main(int argc, char *argv[])
-{
-    queue_uint64_init(&data_queue, 99999);
-    queue_uint64_init(&cmd_queue, 99999);
-
-    // valve_init();
-    // printf("testing valve.....");
-    // fflush(stdout);
-    // valve_test3(100.0f);
-    // valve_test2(200.0f, 0);
-    // valve_test(200.0f);
-    // printf("OK\r\n");
-    // valve_deinit();
-
-    hostcomputer_init(&data_queue, &cmd_queue);
-    uint64_t cmd;
-    int TRUE = 1;
-    while (TRUE)
-    {
-        if (queue_uint64_get(&cmd_queue, &cmd) == 0)
-        {
-            process_cmd(&cmd);
-            usleep(100000);
-        }
-    }
-    hostcomputer_deinit();
-    queue_uint64_deinit(&data_queue);
-    queue_uint64_deinit(&cmd_queue);
-    return 0;
-}
-
-void process_cmd(uint64_t *cmd)
-{
-    int tmp_cmd = (int)*cmd;
-    int tmp_data = (int)(*cmd >> 32);
-    if (status == SLEEPING)
-    {
-        if (tmp_cmd == HOSTCOMPUTER_CMD_START)
-        {
-            valve_should_trigger_pulse_count = camera_trigger_pulse_count / HOST_COMPUTER_PICTURE_ROW_NUM;
-            for (int i = 0; i < camera_to_valve_pulse_count * HOST_COMPUTER_PICTURE_ROW_NUM / camera_trigger_pulse_count; i++)
-                queue_uint64_put(&data_queue, 0);
-            valve_init();
-            cameratrigger_init();
-            encoder_init(on_encoder);
-            status = RUNNING;
-            printf("\r\n>>>>>\r\nstatus==RUNNING\r\n<<<<<\r\n\r\n");
-        }
-        else if (tmp_cmd == HOSTCOMPUTER_CMD_TEST)
-        {
-            valve_init();
-            valve_test(500.0f);
-            valve_deinit();
-        }
-    }
-    else if (status == NOT_INITIALIZED)
-    {
-        if (tmp_cmd == HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT)
-        {
-            camera_trigger_pulse_count = tmp_data;
-        }
-        else if (tmp_cmd == HOSTCOMPUTER_CMD_SETVALVETRIGPULSECOUNT)
-        {
-            valve_trigger_pulse_count = tmp_data;
-        }
-        else if (tmp_cmd == HOSTCOMPUTER_CMD_SETCAMERATOVALVEPULSECOUNT)
-        {
-            camera_to_valve_pulse_count = tmp_data;
-        }
-        else if (tmp_cmd == HOSTCOMPUTER_CMD_TEST)
-        {
-            valve_init();
-            valve_test(500.0f);
-            valve_deinit();
-        }
-        if (camera_trigger_pulse_count != 0 && valve_trigger_pulse_count != 0 && camera_to_valve_pulse_count != 0)
-        {
-            status = INITIALIZED;
-            printf("\r\n>>>>>\r\nstatus==INITIALIZED\r\ncamera_trigger_pulse_count=%d\r\nvalve_trigger_pulse_count=%d\r\ncamera_to_valve_pulse_count=%d\r\n<<<<<\r\n\r\n", camera_trigger_pulse_count, valve_trigger_pulse_count, camera_to_valve_pulse_count);
-        }
-    }
-    else if (status == INITIALIZED)
-    {
-        if (tmp_cmd == HOSTCOMPUTER_CMD_START)
-        {
-            valve_should_trigger_pulse_count = camera_trigger_pulse_count / HOST_COMPUTER_PICTURE_ROW_NUM;
-            printf("valve_should_trigger_pulse_count=%d", valve_should_trigger_pulse_count);
-            for (int i = 0; i < camera_to_valve_pulse_count * HOST_COMPUTER_PICTURE_ROW_NUM / camera_trigger_pulse_count; i++)
-                queue_uint64_put(&data_queue, 0);
-            valve_init();
-            cameratrigger_init();
-            encoder_init(on_encoder);
-            status = RUNNING;
-            printf("\r\n>>>>>\r\nstatus==RUNNING\r\n<<<<<\r\n\r\n");
-        }
-        else if (tmp_cmd == HOSTCOMPUTER_CMD_TEST)
-        {
-            valve_init();
-            valve_test(500.0f);
-            valve_deinit();
-        }
-    }
-    else if (status == RUNNING)
-    {
-        if (tmp_cmd == HOSTCOMPUTER_CMD_STOP)
-        {
-            encoder_deinit();
-            cameratrigger_deinit();
-            valve_deinit();
-            queue_uint64_clear(&data_queue);
-            status = SLEEPING;
-            printf("\r\n>>>>>\r\nstatus==SLEEPING\r\n<<<<<\r\n\r\n");
-        }
-    }
-}
-
-void valve_test(float ms_for_each_channel)
-{
-    uint64_t valve_data = 1ul;
-    for (int i = 0; i < 48; i++)
-    {
-        usleep((useconds_t)(ms_for_each_channel * 500.0f));
-        valvedata.valvedata_1 = valve_data << i;
-        valve_sendmsg(&valvedata);
-        usleep((useconds_t)(ms_for_each_channel * 500.0f));
-        valvedata.valvedata_1 = 0;
-        valve_sendmsg(&valvedata);
-    }
-}
-
-void valve_test2(float ms_for_each_channel, int which_channel)
-{
-    uint64_t valve_data = 1ul;
-    for (int i = 0; i < 10; i++)
-    {
-        usleep((useconds_t)(ms_for_each_channel * 500.0f));
-        valvedata.valvedata_1 = valve_data << which_channel;
-        valve_sendmsg(&valvedata);
-        usleep((useconds_t)(ms_for_each_channel * 500.0f));
-        valvedata.valvedata_1 = 0;
-        valve_sendmsg(&valvedata);
-    }
-}
-
-void valve_test3(float ms_for_each_channel)
-{
-    valvedata.valvedata_1 = 0x5555555555555555ul;
-    for (int i = 0; i < 9999; i++)
-    {
-        usleep((useconds_t)(ms_for_each_channel * 250.0f));
-        valvedata.valvedata_1 = 0x5555555555555555ul;
-        valve_sendmsg(&valvedata);
-        usleep((useconds_t)(ms_for_each_channel * 250.0f));
-
-        valvedata.valvedata_1 = 0;
-        valve_sendmsg(&valvedata);
-        usleep((useconds_t)(ms_for_each_channel * 250.0f));
-
-        valvedata.valvedata_1 = 0xaaaaaaaaaaaaaaaaul;
-        valve_sendmsg(&valvedata);
-        usleep((useconds_t)(ms_for_each_channel * 250.0f));
-
-        valvedata.valvedata_1 = 0;
-        valve_sendmsg(&valvedata);
-        usleep((useconds_t)(ms_for_each_channel * 250.0f));
-    }
-}
-
-void on_encoder()
-{
-    count_continues++;
-
-    if (++count_valve == valve_trigger_pulse_count + 1)
-    {
-        count_valve = 1;
-        count_valve_continues++;
-        valve_sendmsg(&valvedata);
-
-        // printf("data:%llx send to valve, queue length is %d\r\n", valvedata.valvedata_1, data_queue.nData);
-        // printf("%016llx ", valvedata.valvedata_1);
-        fflush(stdout);
-    }
-
-    if (++count_valve_should_be == valve_should_trigger_pulse_count + 2)
-    {
-        count_valve_should_be = 2;
-        valvedata.valvedata_1 = 0;
-        queue_uint64_get(&data_queue, &(valvedata.valvedata_1));
-        // if (data_queue.nData == 0)
-        // {
-        //     printf("sb\r\n");
-        // }
-    }
-
-    if (++count_camera == camera_trigger_pulse_count)
-    {
-        // printf("camera triggled\r\n");
-        count_camera = 0;
-        count_camera_continues++;
-        cameratrigger_trig();
-    }
-}

source/main.h

@@ -1,6 +0,0 @@
-#ifndef __MAIN_H
-#define __MAIN_H
-
-
-
-#endif

source/queue_reference.c

@@ -1,167 +0,0 @@
-/**
- * @file queue_reference.c
- * @brief Thread safe queue, which stores void* pointers
- * @details Call queue_init(queue_reference_msg_t *q, int max_count) paired with queue_deinit(queue_reference_msg_t *q) as their names imply, queue_initstruct(queue_reference_msg_t *q)Initialize the message queue structure,*queue_get(queue_reference_msg_t *q) and queue_put(queue_reference_msg_t *q, void *data) In and out of the team operation
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2021/12/25 merry christmas
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/09 <td>1.0     <td>miaow     <td>Write this file
- * </table>
- */
-
-#include <pthread.h>
-#include <queue_reference.h>
-#ifdef QUEUE_REFERENCE_DEBUG
-#include <stdio.h>
-#include <stdint.h>
-#endif
-#include <stdlib.h>
-
-/**
- * @brief Take out the first item from the circular queue
- * @param q The queue handler
- * @return A pointer to the item
- */
-void *queue_reference_get(queue_reference_msg_t *q)
-{
-    void *data = NULL;
-    pthread_mutex_lock(&q->_mux);
-    // while (q->lget == q->lput && 0 == q->nData)
-    // {
-    //     // The reason program goes here: assuming there are 2 consmer threads block in this function
-    //     // One wakes first and consumes 2 data quickly before another wakes
-    //     // In the circumstances that the queue contains 2 items formerly, the second thread should not get data from an empty queue
-    //     // This may happen when 2 queue_puts was called by producers and at that moment 2 consmer threads have been blocked
-
-    //     // It is designed as a circular queue, where lget==lput means:
-    //     // 1：nData!=0，a full queue
-    //     // 2：nData为0，an empty queue
-    //     q->nEmptyThread++;
-    //     pthread_cond_wait(&q->_cond_get, &q->_mux);
-    //     q->nEmptyThread--;
-    // }
-    if (q->nData == 0)
-    {
-        pthread_mutex_unlock(&q->_mux);
-        return NULL;
-    }
-#ifdef QUEUE_REFERENCE_DEBUG
-    printf("get data! lget:%d, ", q->lget);
-#endif
-    data = (q->buffer)[q->lget++];
-#ifdef QUEUE_REFERENCE_DEBUG
-    printf("data:% lld", *((uint64_t *)data));
-#endif
-    if (q->lget == q->size)
-    {
-        // this is a circular queue
-        q->lget = 0;
-    }
-    q->nData--;
-#ifdef QUEUE_REFERENCE_DEBUG
-    printf(", nData:%d\r\n", q->nData);
-#endif
-    // if (q->nFullThread)
-    // {
-    //     // call pthread_cond_signal only when necessary, enter the kernel state as little as possible
-    //     pthread_cond_signal(&q->_cond_put);
-    // }
-    pthread_mutex_unlock(&q->_mux);
-    return data;
-}
-
-/**
- * @brief Initialize the queue with a size (maximum count of items) specified in q->size
- * @param q The queue hander to be initialized
- * @return 0 - success, -1 - failed
- * @note q->size should be set before calling this function
- */
-int queue_reference_initstruct(queue_reference_msg_t *q)
-{
-    q->buffer = malloc(q->size * sizeof(void *));
-    if (q->buffer == NULL)
-        return -1;
-    pthread_mutex_init(&q->_mux, NULL);
-    // pthread_cond_init(&q->_cond_get, NULL);
-    // pthread_cond_init(&q->_cond_put, NULL);
-    return 0;
-}
-
-/**
- * @brief Initialize the queue
- * @param q The queue hander to be initialized
- * @param max_count Maximum count of items in the queue
- * @return 0 - success, -1 - failed
- */
-int queue_reference_init(queue_reference_msg_t *q, int max_count)
-{
-    q->size = max_count;
-    return queue_reference_initstruct(q);
-}
-
-/**
- * @brief Deinitialize the queue
- * @param q The queue handle
- * @return 0 - success
- */
-int queue_reference_deinit(queue_reference_msg_t *q)
-{
-    free(q->buffer);
-    q->buffer = NULL;
-    pthread_mutex_destroy(&q->_mux);
-    // pthread_cond_destroy(&q->_cond_get);
-    // pthread_cond_destroy(&q->_cond_put);
-    q->size = 0;
-    q->nData = 0;
-    q->lget = 0;
-    q->lput = 0;
-    // q->nEmptyThread = 0;
-    // q->nFullThread = 0;
-    return 0;
-}
-
-/**
- * @brief Put one item into the circular queue
- * @param q The queue handle
- * @param data A pointer to the item
- * @return 0 - success, -1 - failed
- */
-int queue_reference_put(queue_reference_msg_t *q, void *data)
-{
-    pthread_mutex_lock(&q->_mux);
-    // while (q->lget == q->lput && q->nData)
-    // {
-    //     q->nFullThread++;
-    //     pthread_cond_wait(&q->_cond_put, &q->_mux);
-    //     q->nFullThread--;
-    // }
-    if (q->lget == q->lput && q->nData)
-    {
-        pthread_mutex_unlock(&q->_mux);
-        return -1;
-    }
-#ifdef QUEUE_REFERENCE_DEBUG
-    printf("put data! lput:%d, data:%lld", q->lput, *((uint64_t *)data));
-#endif
-    (q->buffer)[q->lput++] = data;
-    if (q->lput == q->size)
-    {
-        q->lput = 0;
-    }
-    q->nData++;
-#ifdef QUEUE_REFERENCE_DEBUG
-    printf(" nData:%d\n", q->nData);
-#endif
-    // if (q->nEmptyThread)
-    // {
-    //     pthread_cond_signal(&q->_cond_get);
-    // }
-    pthread_mutex_unlock(&q->_mux);
-    return 0;
-}

source/queue_reference.h

@@ -1,46 +0,0 @@
-/**
- * @file queue_reference.h
- * @brief Thread safe queue, which stores void pointers
- * @details Call queue_init(queue_reference_msg_t *q, int max_count) paired with queue_deinit(queue_reference_msg_t *q) as their names imply, queue_initstruct(queue_reference_msg_t *q)Initialize the message queue structure,*queue_get(queue_reference_msg_t *q) and queue_put(queue_reference_msg_t *q, void *data) In and out of the team operation
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2021/12/25 merry christmas
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/09 <td>1.0     <td>miaow     <td>Write this file
- * </table>
- */
-#if !defined(__QUEUE_REFERENCE_H)
-#define __QUEUE_REFERENCE_H
-
-#include <pthread.h>
-
-/**
- * @brief Queue handle structure
- */
-typedef struct
-{
-    void **buffer;    // 缓冲数据, .buffer = msg
-    int size;         // 队列大小，使用的时候给出稍大的size，可以减少进入内核态的操作
-    int lget;         // 取队列数据的偏移量
-    int lput;         // 放队列数据的偏移量
-    int nData;        // 队列中数据的个数,用来判断队列满/空
-    // int nFullThread;  // 由于队列满而阻塞在put_queue的线程个数
-    // int nEmptyThread; // 由于队列空而阻塞在get_queue的线程个数
-    pthread_mutex_t _mux;
-    // pthread_cond_t _cond_get, _cond_put;
-} queue_reference_msg_t;
-
-// #define QUEUE_REFERENCE_DEBUG
-
-void *queue_reference_get(queue_reference_msg_t *q);
-int queue_reference_put(queue_reference_msg_t *q, void *data);
-int queue_reference_initstruct(queue_reference_msg_t *q);
-int queue_reference_init(queue_reference_msg_t *q, int max_count);
-int queue_reference_deinit(queue_reference_msg_t *q);
-
-#endif // __QUEUE_REFERENCE_H

source/queue_uint64.c

@@ -1,195 +0,0 @@
-
-/**
- * @file queue_uint64.c
- * @brief Thread safe queue, which stores uint64_t
- * @details Call queue_init(queue_uint64_msg_t *q, int max_count) paired with queue_deinit(queue_uint64_msg_t *q) as their names imply, queue_initstruct(queue_uint64_msg_t *q)Initialize the message queue structure,*queue_get(queue_uint64_msg_t *q) and queue_put(queue_uint64_msg_t *q, void *data) In and out of the team operation
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2021/01/10
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/09 <td>1.0     <td>miaow     <td>Write this file
- * </table>
- */
-
-#include <pthread.h>
-#include <queue_uint64.h>
-#ifdef QUEUE_UINT64_DEBUG
-#include <stdio.h>
-#include <stdint.h>
-#endif
-#include <stdlib.h>
-
-/**
- * @brief Take out the first item from the circular queue
- * @param q The queue handler
- * @param data A buffer of uint64_t[1] to store the data taken out
- * @return 0 - success, -1 - failed
- */
-int queue_uint64_get(queue_uint64_msg_t *q, uint64_t *data)
-{
-    pthread_mutex_lock(&q->_mux);
-    // while (q->lget == q->lput && 0 == q->nData)
-    // {
-    //     // The reason program goes here: assuming there are 2 consmer threads block in this function
-    //     // One wakes first and consumes 2 data quickly before another wakes
-    //     // In the circumstances that the queue contains 2 items formerly, the second thread should not get data from an empty queue
-    //     // This may happen when 2 queue_puts was called by producers and at that moment 2 consmer threads have been blocked
-
-    //     // It is designed as a circular queue, where lget==lput means:
-    //     // 1：nData!=0，a full queue
-    //     // 2：nData为0，an empty queue
-    //     q->nEmptyThread++;
-    //     pthread_cond_wait(&q->_cond_get, &q->_mux);
-    //     q->nEmptyThread--;
-    // }
-    if (q->nData == 0)
-    {
-        pthread_mutex_unlock(&q->_mux);
-        return -1;
-    }
-#ifdef QUEUE_UINT64_DEBUG
-    printf("get data! lget:%d, ", q->lget);
-#endif
-    *data = (q->buffer)[q->lget++];
-#ifdef QUEUE_UINT64_DEBUG
-    printf("data:% lld", *data);
-#endif
-    if (q->lget == q->size)
-    {
-        // this is a circular queue
-        q->lget = 0;
-    }
-    q->nData--;
-#ifdef QUEUE_UINT64_DEBUG
-    printf(", nData:%d\r\n", q->nData);
-#endif
-    // if (q->nFullThread)
-    // {
-    //     // call pthread_cond_signal only when necessary, enter the kernel state as little as possible
-    //     pthread_cond_signal(&q->_cond_put);
-    // }
-    pthread_mutex_unlock(&q->_mux);
-    return 0;
-}
-
-/**
- * @brief Initialize the queue with a size (maximum count of items) specified in q->size
- * @param q The queue hander to be initialized
- * @return 0 - success, -1 - failed
- * @note q->size should be set before calling this function
- */
-int queue_uint64_initstruct(queue_uint64_msg_t *q)
-{
-    q->buffer = malloc(q->size * sizeof(uint64_t));
-    if (q->buffer == NULL)
-        return -1;
-    pthread_mutex_init(&q->_mux, NULL);
-    // pthread_cond_init(&q->_cond_get, NULL);
-    // pthread_cond_init(&q->_cond_put, NULL);
-    return 0;
-}
-
-/**
- * @brief Initialize the queue
- * @param q The queue hander to be initialized
- * @param max_count Maximum count of items in the queue
- * @return 0 - success, -1 - failed
- */
-int queue_uint64_init(queue_uint64_msg_t *q, int max_count)
-{
-    q->size = max_count;
-    return queue_uint64_initstruct(q);
-}
-
-/**
- * @brief Deinitialize the queue
- * @param q The queue handle
- * @return 0 - success
- */
-int queue_uint64_deinit(queue_uint64_msg_t *q)
-{
-    free(q->buffer);
-    q->buffer = NULL;
-    pthread_mutex_destroy(&q->_mux);
-    // pthread_cond_destroy(&q->_cond_get);
-    // pthread_cond_destroy(&q->_cond_put);
-    q->size = 0;
-    q->nData = 0;
-    q->lget = 0;
-    q->lput = 0;
-    // q->nEmptyThread = 0;
-    // q->nFullThread = 0;
-    return 0;
-}
-
-/**
- * @brief Put one item into the circular queue
- * @param q The queue handle
- * @param data The item to put
- * @return 0 - success, -1 - failed
- */
-int queue_uint64_put(queue_uint64_msg_t *q, uint64_t data)
-{
-    pthread_mutex_lock(&q->_mux);
-    // while (q->lget == q->lput && q->nData)
-    // {
-    //     q->nFullThread++;
-    //     pthread_cond_wait(&q->_cond_put, &q->_mux);
-    //     q->nFullThread--;
-    // }
-    if (q->lget == q->lput && q->nData)
-    {
-        pthread_mutex_unlock(&q->_mux);
-        return -1;
-    }
-#ifdef QUEUE_UINT64_DEBUG
-    printf("put data! lput:%d, data:%lld", q->lput, data);
-#endif
-    (q->buffer)[q->lput++] = data;
-    if (q->lput == q->size)
-    {
-        q->lput = 0;
-    }
-    q->nData++;
-#ifdef QUEUE_UINT64_DEBUG
-    printf(" nData:%d\n", q->nData);
-#endif
-    // if (q->nEmptyThread)
-    // {
-    //     pthread_cond_signal(&q->_cond_get);
-    // }
-    pthread_mutex_unlock(&q->_mux);
-    return 0;
-}
-
-/**
- * @brief Clear the circular queue
- * @param q The queue handle
- * @return 0 - success, -1 - failed
- */
-int queue_uint64_clear(queue_uint64_msg_t *q)
-{
-    pthread_mutex_lock(&q->_mux);
-    // while (q->lget == q->lput && q->nData)
-    // {
-    //     q->nFullThread++;
-    //     pthread_cond_wait(&q->_cond_put, &q->_mux);
-    //     q->nFullThread--;
-    // }
-    q->lget = q->lput = q->nData = 0;
-#ifdef QUEUE_UINT64_DEBUG
-    printf("clear!\r\n");
-#endif
-
-    // if (q->nEmptyThread)
-    // {
-    //     pthread_cond_signal(&q->_cond_get);
-    // }
-    pthread_mutex_unlock(&q->_mux);
-    return 0;
-}

source/queue_uint64.h

@@ -1,48 +0,0 @@
-/**
- * @file queue_uint64.h
- * @brief Thread safe queue, which stores uint64_t
- * @details Call queue_init(queue_uint64_msg_t *q, int max_count) paired with queue_deinit(queue_uint64_msg_t *q) as their names imply, queue_initstruct(queue_uint64_msg_t *q)Initialize the message queue structure,*queue_get(queue_uint64_msg_t *q) and queue_put(queue_uint64_msg_t *q, void *data) In and out of the team operation
- * @author miaow (3703781@qq.com)
- * @version 1.0
- * @date 2021/01/10
- * 
- * @copyright Copyright (c) 2022  miaow
- * 
- * @par Changelog:
- * <table>
- * <tr><th>Date       <th>Version <th>Author  <th>Description
- * <tr><td>2022/01/09 <td>1.0     <td>miaow     <td>Write this file
- * </table>
- */
-#if !defined(__QUEUE_UINT64_H)
-#define __QUEUE_UINT64_H
-
-#include <pthread.h>
-#include <stdint.h>
-
-/**
- * @brief Queue handle structure
- */
-typedef struct
-{
-    uint64_t *buffer; // 缓冲数据, .buffer = msg
-    int size;         // 队列大小，使用的时候给出稍大的size，可以减少进入内核态的操作
-    int lget;         // 取队列数据的偏移量
-    int lput;         // 放队列数据的偏移量
-    int nData;        // 队列中数据的个数,用来判断队列满/空
-    // int nFullThread;  // 由于队列满而阻塞在put_queue的线程个数
-    // int nEmptyThread; // 由于队列空而阻塞在get_queue的线程个数
-    pthread_mutex_t _mux;
-    // pthread_cond_t _cond_get, _cond_put;
-} queue_uint64_msg_t;
-
-// #define QUEUE_UINT64_DEBUG
-
-int queue_uint64_get(queue_uint64_msg_t *q, uint64_t *data);
-int queue_uint64_put(queue_uint64_msg_t *q, uint64_t data);
-int queue_uint64_initstruct(queue_uint64_msg_t *q);
-int queue_uint64_init(queue_uint64_msg_t *q, int max_count);
-int queue_uint64_clear(queue_uint64_msg_t *q);
-int queue_uint64_deinit(queue_uint64_msg_t *q);
-
-#endif // __QUEUE_UINT64_H

source/test_lower_machine/.cproject

@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="org.eclipse.cdt.core.default.config.2070356241">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.2070356241" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+                				
+                <externalSettings/>
+                				
+                <extensions/>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    
+</cproject>

source/test_lower_machine/.gitignore

@@ -0,0 +1,3 @@
+/export/
+*.o
+*.d

source/test_lower_machine/.log/test_lower_machine_.build.ui.log

@@ -0,0 +1,72 @@
+2022-05-15T22:17:26.94189600255-22:17:26 **** Clean-only build of project test_lower_machine ****
+000-buildplatform.sh 36625 test_lower_machine clean 
+000-XSDB Server Channel: tcfchan#5
+000-Cleaning the zynq_fsbl application.
+000-rm -rf  pcap.o  qspi.o  nor.o  rsa.o  main.o  fsbl_hooks.o  md5.o  image_mover.o  ps7_init.o  nand.o  sd.o  fsbl_handoff.o  zyn
+000-q_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a fsbl.elf *.o
+000-
+000-Cleaning the zynq_fsbl application, bsp
+000-make -C ps7_cortexa9_0/libsrc/ip_encoder_v1_0/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/ip_fifo_v1_0/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s clean 
+000-
+000-rm -f ps7_cortexa9_0/lib/libxil.a
+000-
+000-Cleaning the BSP for domain  - standalone_domain
+000-make -C ps7_cortexa9_0/libsrc/ip_encoder_v1_0/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/ip_fifo_v1_0/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s clean 
+000-
+000-make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s clean 
+000-
+000-rm -f ps7_cortexa9_0/lib/libxil.a
+000-
+00255-
+22:17:32 Build Finished (took 5s.534ms)
+

source/test_lower_machine/.project

@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>test_lower_machine</name>
+	<comment>Created by Vitis v2021.2</comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.xilinx.sdx.scw.PlatformProjectBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.xilinx.sdx.scw.platformProject</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+	</natures>
+</projectDescription>

source/test_lower_machine/hw/drivers/ip_encoder_v1_0/data/ip_encoder.mdd

@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER ip_encoder
+	OPTION supported_peripherals = (ip_encoder);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = ip_encoder;
+END DRIVER

source/test_lower_machine/hw/drivers/ip_encoder_v1_0/data/ip_encoder.tcl

@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "ip_encoder" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}

source/test_lower_machine/hw/drivers/ip_encoder_v1_0/src/Makefile

@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling ip_encoder..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}

source/test_lower_machine/hw/drivers/ip_encoder_v1_0/src/ip_encoder.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "ip_encoder.h"
+
+/************************** Function Definitions ***************************/

source/test_lower_machine/hw/drivers/ip_encoder_v1_0/src/ip_encoder.h

@@ -0,0 +1,79 @@
+
+#ifndef IP_ENCODER_H
+#define IP_ENCODER_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define IP_ENCODER_S00_AXI_SLV_REG0_OFFSET 0
+#define IP_ENCODER_S00_AXI_SLV_REG1_OFFSET 4
+#define IP_ENCODER_S00_AXI_SLV_REG2_OFFSET 8
+#define IP_ENCODER_S00_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a IP_ENCODER register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the IP_ENCODERdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void IP_ENCODER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define IP_ENCODER_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a IP_ENCODER register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the IP_ENCODER device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 IP_ENCODER_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define IP_ENCODER_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the IP_ENCODER instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus IP_ENCODER_Reg_SelfTest(void * baseaddr_p);
+
+#endif // IP_ENCODER_H

source/test_lower_machine/hw/drivers/ip_encoder_v1_0/src/ip_encoder_selftest.c

@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "ip_encoder.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the IP_ENCODERinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus IP_ENCODER_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  IP_ENCODER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( IP_ENCODER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}

source/test_lower_machine/hw/drivers/ip_fifo_v1_0/data/ip_fifo.mdd

@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER ip_fifo
+	OPTION supported_peripherals = (ip_fifo);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = ip_fifo;
+END DRIVER

source/test_lower_machine/hw/drivers/ip_fifo_v1_0/data/ip_fifo.tcl

@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "ip_fifo" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}

source/test_lower_machine/hw/drivers/ip_fifo_v1_0/src/Makefile

@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling ip_fifo..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}

source/test_lower_machine/hw/drivers/ip_fifo_v1_0/src/ip_fifo.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "ip_fifo.h"
+
+/************************** Function Definitions ***************************/

source/test_lower_machine/hw/drivers/ip_fifo_v1_0/src/ip_fifo.h

@@ -0,0 +1,90 @@
+
+#ifndef IP_FIFO_H
+#define IP_FIFO_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define IP_FIFO_S00_AXI_SLV_REG0_OFFSET 0
+#define IP_FIFO_S00_AXI_SLV_REG1_OFFSET 4
+#define IP_FIFO_S00_AXI_SLV_REG2_OFFSET 8
+#define IP_FIFO_S00_AXI_SLV_REG3_OFFSET 12
+#define IP_FIFO_S00_AXI_SLV_REG4_OFFSET 16
+#define IP_FIFO_S00_AXI_SLV_REG5_OFFSET 20
+#define IP_FIFO_S00_AXI_SLV_REG6_OFFSET 24
+#define IP_FIFO_S00_AXI_SLV_REG7_OFFSET 28
+#define IP_FIFO_S00_AXI_SLV_REG8_OFFSET 32
+#define IP_FIFO_S00_AXI_SLV_REG9_OFFSET 36
+#define IP_FIFO_S00_AXI_SLV_REG10_OFFSET 40
+#define IP_FIFO_S00_AXI_SLV_REG11_OFFSET 44
+#define IP_FIFO_S00_AXI_SLV_REG12_OFFSET 48
+#define IP_FIFO_S00_AXI_SLV_REG13_OFFSET 52
+#define IP_FIFO_S00_AXI_SLV_REG14_OFFSET 56
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a IP_FIFO register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the IP_FIFOdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void IP_FIFO_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define IP_FIFO_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a IP_FIFO register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the IP_FIFO device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 IP_FIFO_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define IP_FIFO_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the IP_FIFO instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus IP_FIFO_Reg_SelfTest(void * baseaddr_p);
+
+#endif // IP_FIFO_H

source/test_lower_machine/hw/drivers/ip_fifo_v1_0/src/ip_fifo_selftest.c

@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "ip_fifo.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the IP_FIFOinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus IP_FIFO_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  IP_FIFO_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( IP_FIFO_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}

source/test_lower_machine/hw/ps7_init.h

@@ -0,0 +1,117 @@
+/******************************************************************************
+*
+* Copyright (C) 2010-2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158730
+#define QSPI_FREQ  10000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  10000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  10000000
+#define UART_FREQ  100000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  200000000
+#define FPGA1_FREQ  10000000
+#define FPGA2_FREQ  10000000
+#define FPGA3_FREQ  10000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+

source/test_lower_machine/hw/ps7_init.tcl

@@ -0,0 +1,643 @@
+proc ps7_pll_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x000FA240
+    mask_write 0XF8000108 0x0007F000 0x00030000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000154 0x00003F33 0x00001001
+    mask_write 0XF8000168 0x00003F31 0x00000801
+    mask_write 0XF8000170 0x03F03F30 0x00200400
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x015C000D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_3_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x0007FFFF 0x00001082
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004159B
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+    mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+    mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
+    mask_write 0XF8006024 0x0FFFFFC3 0x00000000
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00000003 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
+    mask_write 0XF8006048 0x0003F03F 0x0003C008
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x00010000 0x00000000
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x00000200 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFCF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFCF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0x6FFFFEFE 0x00040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000703FF 0x000003FF
+    mask_write 0XF800620C 0x000703FF 0x000003FF
+    mask_write 0XF8006210 0x000703FF 0x000003FF
+    mask_write 0XF8006214 0x000703FF 0x000003FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF5 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000001 0x00000001
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FEFFFF 0x00000823
+    mask_write 0XF8000738 0x00003FFF 0x000016E1
+    mask_write 0XF800073C 0x00003FFF 0x000016E0
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0000034 0x000000FF 0x00000006
+    mask_write 0XE0000018 0x0000FFFF 0x0000007C
+    mask_write 0XE0000000 0x000001FF 0x00000017
+    mask_write 0XE0000004 0x000003FF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+}
+proc ps7_post_config_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_3_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x000FA240
+    mask_write 0XF8000108 0x0007F000 0x00030000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000154 0x00003F33 0x00001001
+    mask_write 0XF8000168 0x00003F31 0x00000801
+    mask_write 0XF8000170 0x03F03F30 0x00200400
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x015C000D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_2_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004159B
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+    mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000738 0x00003FFF 0x000016E1
+    mask_write 0XF800073C 0x00003FFF 0x000016E0
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0000034 0x000000FF 0x00000006
+    mask_write 0XE0000018 0x0000FFFF 0x0000007C
+    mask_write 0XE0000000 0x000001FF 0x00000017
+    mask_write 0XE0000004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+}
+proc ps7_post_config_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_2_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x000FA240
+    mask_write 0XF8000108 0x0007F000 0x00030000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000154 0x00003F33 0x00001001
+    mask_write 0XF8000168 0x00003F31 0x00000801
+    mask_write 0XF8000170 0x03F03F30 0x00200400
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x015C000D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_1_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081082
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004159B
+    mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
+    mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
+    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x00029000
+    mask_write 0XF8006130 0x000FFFFF 0x00029000
+    mask_write 0XF8006134 0x000FFFFF 0x00029000
+    mask_write 0XF8006138 0x000FFFFF 0x00029000
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x00000080
+    mask_write 0XF8006158 0x000FFFFF 0x00000080
+    mask_write 0XF800615C 0x000FFFFF 0x00000080
+    mask_write 0XF8006160 0x000FFFFF 0x00000080
+    mask_write 0XF8006168 0x001FFFFF 0x000000F9
+    mask_write 0XF800616C 0x001FFFFF 0x000000F9
+    mask_write 0XF8006170 0x001FFFFF 0x000000F9
+    mask_write 0XF8006174 0x001FFFFF 0x000000F9
+    mask_write 0XF800617C 0x000FFFFF 0x000000C0
+    mask_write 0XF8006180 0x000FFFFF 0x000000C0
+    mask_write 0XF8006184 0x000FFFFF 0x000000C0
+    mask_write 0XF8006188 0x000FFFFF 0x000000C0
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x000073FF 0x00000260
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000738 0x00003FFF 0x000016E1
+    mask_write 0XF800073C 0x00003FFF 0x000016E0
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0000034 0x000000FF 0x00000006
+    mask_write 0XE0000018 0x0000FFFF 0x0000007C
+    mask_write 0XE0000000 0x000001FF 0x00000017
+    mask_write 0XE0000004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+}
+proc ps7_post_config_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_1_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+set PCW_SILICON_VER_1_0 "0x0"
+set PCW_SILICON_VER_2_0 "0x1"
+set PCW_SILICON_VER_3_0 "0x2"
+set APU_FREQ  666666666
+
+
+
+proc mask_poll { addr mask } {
+    set count 1
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    while { $maskedval == 0 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval & $mask}]
+        set count [ expr { $count + 1 } ]
+        if { $count == 100000000 } {
+          puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+          break
+        }
+    }
+}
+
+
+
+proc mask_delay { addr val } {
+    set delay  [ get_number_of_cycles_for_delay $val ]
+    perf_reset_and_start_timer
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval < $delay}]
+    while { $maskedval == 1 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval < $delay}]
+    }
+    perf_reset_clock 
+}
+
+proc ps_version { } {
+    set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
+    set mask_sil_ver "0x[expr {$si_ver >> 28}]"
+    return $mask_sil_ver;
+}
+
+proc ps7_post_config {} {
+    set saved_mode [configparams force-mem-accesses]                  
+    configparams force-mem-accesses 1 
+    
+	variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_post_config_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_post_config_2_0   
+    } else {
+        ps7_post_config_3_0   
+    }
+	configparams force-mem-accesses $saved_mode                                       
+}
+
+proc ps7_debug {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_debug_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_debug_2_0   
+    } else {
+        ps7_debug_3_0   
+    }
+}
+proc ps7_init {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+            ps7_mio_init_data_1_0
+            ps7_pll_init_data_1_0
+            ps7_clock_init_data_1_0
+            ps7_ddr_init_data_1_0
+            ps7_peripherals_init_data_1_0
+            #puts "PCW Silicon Version : 1.0"
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+            ps7_mio_init_data_2_0
+            ps7_pll_init_data_2_0
+            ps7_clock_init_data_2_0
+            ps7_ddr_init_data_2_0
+            ps7_peripherals_init_data_2_0
+            #puts "PCW Silicon Version : 2.0"
+    } else {
+            ps7_mio_init_data_3_0
+            ps7_pll_init_data_3_0
+            ps7_clock_init_data_3_0
+            ps7_ddr_init_data_3_0
+            ps7_peripherals_init_data_3_0
+            #puts "PCW Silicon Version : 3.0"
+    }
+}
+
+
+# For delay calculation using global timer 
+
+# start timer 
+ proc perf_start_clock { } {
+
+    #writing SCU_GLOBAL_TIMER_CONTROL register
+
+    mask_write 0xF8F00208 0x00000109 0x00000009
+}
+
+# stop timer and reset timer count regs 
+ proc perf_reset_clock { } {
+	perf_disable_clock
+    mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
+    mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
+}
+
+# Compute mask for given delay in miliseconds
+proc get_number_of_cycles_for_delay { delay } {
+
+  # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  variable APU_FREQ
+  return [ expr ($delay * $APU_FREQ /(2 * 1000))]
+}
+
+
+# stop timer 
+proc perf_disable_clock {} {
+    mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 
+}
+
+proc perf_reset_and_start_timer {} {
+  	    perf_reset_clock 
+	    perf_start_clock 
+}
+
+