2356 lines
254 KiB
Plaintext
2356 lines
254 KiB
Plaintext
/Matrox Electronic Systems Ltd.
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/Copyright 2013.
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/
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/no name DCF template.
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[CAMERA_NAME]
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no name
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[CONFIG_FILE]
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50CF
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ODYSSEY
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Mon Dec 16 12:30:58 2024
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[INFO_FILE_REV]
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0010.0019.0000
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RADIENT/eVCL/DUAL
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[GENERAL_PARAMETERS]
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GEN_MATCH_HW 0x1
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GEN_SAVED_W_ERR 0x0
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CT_LS 0x1
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CT_FS 0x0
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CT_CONV_INVERTED 0x0
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CT_TAPS 0x0
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CT_CAMERA 0x0
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CT_BAYER_DISABLE 0x1
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CT_BAYER_BG 0x0
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CT_BAYER_GB 0x0
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CT_BAYER_GR 0x0
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CT_BAYER_RG 0x0
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VDC_DIG 0x1
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VDC_ANA 0x0
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VDC_MONO 0x0
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VDC_C_COLOR 0x0
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VDC_RGB_COL 0x1
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VDC_RGB_PACK 0x0
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VDC_RGB_ALPHA 0x0
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VDC_SVID 0x0
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VDC_YUVVID 0x0
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VDC_TTL 0x0
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VDC_422 0x0
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VDC_OPTO 0x0
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VDC_LVDS 0x1
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VDC_WD8 0x1
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VDC_WD16 0x0
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VDC_WD24 0x0
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VDC_WD32 0x0
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VDC_WD64 0x0
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VDC_ALT_GRAB 0x0
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VDC_FROM_VCR 0x0
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VDC_IN_CH0 0x0
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VDC_IN_CH1 0x0
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VDC_IN_CH2 0x0
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VDC_IN_CH3 0x0
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VDC_IN_CH_C 0x0
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VDC_DIGITIZER 0x1
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VDC_PSG_MODE_1_CHECK 0x1
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VDC_PSG_MODE_2_CHECKS 0x0
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VDC_PSG_MODE_3_CHECKS 0x0
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VDC_PSG_MODE_4_CHECKS 0x0
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VDC_PSG_MODE_1_3_CHECKS 0x0
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VDC_PSG_MODE_ANY_CHECKS 0x0
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VDC_MIL_CHANNEL 0x0
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VDC_USE_PSG_0 0x1
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VDC_USE_PSG_1 0x0
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VDC_USE_PSG_2 0x0
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VDC_USE_PSG_3 0x0
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VDC_0_AC_WITH_DC 0x0
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VDC_0_DC_WITH_DC 0x0
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VDC_0_DC_WITHOUT_DC 0x0
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VDC_0_NO_FILTER 0x0
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VDC_0_FILTER_0 0x0
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VDC_0_FILTER_1 0x0
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VDC_1_AC_WITH_DC 0x0
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VDC_1_DC_WITH_DC 0x0
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VDC_1_DC_WITHOUT_DC 0x0
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VDC_1_NO_FILTER 0x0
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VDC_1_FILTER_0 0x0
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VDC_1_FILTER_1 0x0
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VDC_2_AC_WITH_DC 0x0
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VDC_2_DC_WITH_DC 0x0
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VDC_2_DC_WITHOUT_DC 0x0
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VDC_2_NO_FILTER 0x0
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VDC_2_FILTER_0 0x0
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VDC_2_FILTER_1 0x0
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VDC_3_AC_WITH_DC 0x0
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VDC_3_DC_WITH_DC 0x0
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VDC_3_DC_WITHOUT_DC 0x0
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VDC_3_NO_FILTER 0x0
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VDC_3_FILTER_0 0x0
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VDC_3_FILTER_1 0x0
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VDT_USE_HLOCK 0x0
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VDT_USE_VLOCK 0x0
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VDT_STD_170 0x0
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VDT_STD_330 0x0
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VDT_STD_CCIR 0x0
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VDT_STD_NTSC 0x0
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VDT_STD_PAL 0x0
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VDT_STD_CL 0x0
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VDT_STD_DIGITAL 0x0
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VDT_NOVERT 0x1
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VDT_HSYNC 0x0
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VDT_HBPORCH 0x10
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VDT_HFPORCH 0x0
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VDT_HACTIVE 0x1000
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VDT_HTOTAL 0x1010
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VDT_HSYNC_FREQ 0x4bff
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VDT_VSYNC 0x0
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VDT_VBPORCH 0x0
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VDT_VFPORCH 0x0
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VDT_VACTIVE 0x200
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VDT_VTOTAL 0x200
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VDT_VSYNC_FREQ 0x0
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VDT_CL_IMAGE_SIZE_X 0x0
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VDT_CL_IMAGE_SIZE_Y 0x0
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VDT_CL_CROPPING_X 0x0
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VDT_CL_CROPPING_Y 0x0
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VDT_INTERL 0x0
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VDT_NINTRL 0x1
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VDT_SER 0x0
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VDT_EQU 0x0
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VDT_CLP_SYN 0x0
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VDT_CLP_BPO 0x0
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VDT_CLP_FPO 0x0
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PCK_CAM_GEN 0x0
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PCK_CAM_REC 0x0
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PCK_CAM_R&G 0x0
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PCK_OTH_REC 0x0
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PCK_USE_OUT 0x0
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PCK_CAM_XCHG 0x0
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PCK_ITTL 0x0
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PCK_I422 0x0
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PCK_IOPTO 0x0
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PCK_ILVDS 0x0
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PCK_IPOS 0x0
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PCK_INEG 0x0
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PCK_FREQ 0x4c4b400
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PCK_INTDVED 0x0
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PCK_INTDIVF 0x0
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PCK_ODVED 0x0
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PCK_ODIVF 0x0
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PCK_OFREQDV 0x4c4b400
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PCK_OTTL 0x0
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PCK_O422 0x0
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PCK_OOPTO 0x0
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PCK_OLVDS 0x0
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PCK_OPOS 0x0
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PCK_ONEG 0x0
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PCK_IDELAY 0x0
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SYC_DIG 0x1
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SYC_ANA 0x0
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SYC_CAM_GEN 0x1
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SYC_CAM_R&G 0x0
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SYC_CAM_LATENCY 0x0
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SYC_MD_CSYN 0x0
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SYC_MD_HVSY 0x0
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SYC_MD_VSYN 0x0
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SYC_MD_HSYN 0x1
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SYC_EXT_VSY 0x0
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SYC_H_IN 0x1
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SYC_H_OUT 0x0
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SYC_H_ITTL 0x0
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SYC_H_I422 0x0
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SYC_H_IOPTO 0x0
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SYC_H_ILVDS 0x1
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SYC_H_IPOS 0x1
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SYC_H_INEG 0x0
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SYC_H_OTTL 0x0
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SYC_H_O422 0x0
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SYC_H_OOPTO 0x0
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SYC_H_OLVDS 0x0
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SYC_H_OPOS 0x0
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SYC_H_ONEG 0x0
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SYC_V_IN 0x0
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SYC_V_OUT 0x0
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SYC_V_ITTL 0x0
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SYC_V_I422 0x0
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SYC_V_IOPTO 0x0
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SYC_V_ILVDS 0x0
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SYC_V_IPOS 0x0
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SYC_V_INEG 0x0
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SYC_V_OTTL 0x0
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SYC_V_O422 0x0
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SYC_V_OOPTO 0x0
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SYC_V_OLVDS 0x0
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SYC_V_OPOS 0x0
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SYC_V_ONEG 0x0
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SYC_C_IN 0x0
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SYC_C_OUT 0x0
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SYC_C_ITTL 0x0
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SYC_C_I422 0x0
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SYC_C_IOPTO 0x0
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SYC_C_ILVDS 0x0
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SYC_C_IPOS 0x0
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SYC_C_INEG 0x0
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SYC_C_OTTL 0x0
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SYC_C_O422 0x0
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SYC_C_OOPTO 0x0
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SYC_C_OLVDS 0x0
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SYC_C_OPOS 0x0
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SYC_C_ONEG 0x0
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SYC_BLK 0x0
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SYC_COMP 0x0
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SYC_SEP 0x0
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SYC_IN_CH 0x0
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EXP_SYN_CLK 0x0
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EXP_ASY_CLK 0x0
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EXP_CLK_FREQ 0x4c4b400
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EXP_CLK_DVED 0x0
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EXP_CLK_DIVF 0x0
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EXP_MD_PERD 0x0
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EXP_MD_W_TRG 0x0
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EXP_MD_EXT 0x0
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EXP_MD_HSY 0x0
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EXP_MD_VSY 0x0
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EXP_MD_SW 0x0
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EXP_TRG_TTL 0x1
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EXP_TRG_422 0x0
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EXP_TRG_OPTO 0x0
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EXP_TRG_LVDS 0x0
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EXP_TRG_DEFAULT 0x0
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EXP_TRG_POS 0x0
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EXP_TRG_NEG 0x0
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EXP_OUT_DLYD 0x0
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EXP_OUT_T0 0x0
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EXP_OUT_T1 0x0
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EXP_OUT_T2 0x0
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EXP_OUT_T3 0x0
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EXP_OUT_TTL 0x0
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EXP_OUT_422 0x0
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EXP_OUT_OPTO 0x0
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EXP_OUT_LVDS 0x0
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EXP_OUT_DEFAULT 0x0
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EXP_OUT_POS 0x0
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EXP_OUT_NEG 0x0
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EXP_ARM_ENABLE 0x0
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EXP_ARM_DISABLE 0x0
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EXP_ARM_TTL 0x1
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EXP_ARM_422 0x0
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EXP_ARM_OPTO 0x0
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EXP_ARM_LVDS 0x0
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EXP_ARM_DEFAULT 0x0
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EXP_ARM_POS 0x1
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EXP_ARM_NEG 0x0
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GRB_MD_CONT 0x1
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GRB_MD_SW_TRG 0x0
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GRB_MD_HW_TRG 0x0
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GRB_START_ODD 0x0
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GRB_START_EVEN 0x0
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GRB_START_ANY 0x0
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GRB_ACT_NXT_FRM 0x0
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GRB_ACT_IMMEDIATE 0x0
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GRB_ACT_IMM_SKP_NFR 0x0
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GRB_TRG_TTL 0x0
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GRB_TRG_422 0x0
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GRB_TRG_OPTO 0x0
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GRB_TRG_LVDS 0x0
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GRB_TRG_DEFAULT 0x0
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GRB_TRG_POS 0x0
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GRB_TRG_NEG 0x0
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GRB_LS_FREE_RUN 0x1
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GRB_LS_FIXED_LINE 0x0
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GRB_LS_VARIABLE_LINE 0x0
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GRB_LS_FRMFIX_LINEFIX 0x0
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GRB_LS_FRMFIX_LINEVAR 0x0
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GRB_LS_FRMVAR_LINEFIX 0x0
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GRB_LS_FRMVAR_LINEVAR 0x0
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GRB_TRG_ARM_TTL 0x0
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GRB_TRG_ARM_422 0x0
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GRB_TRG_ARM_OPTO 0x0
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GRB_TRG_ARM_LVDS 0x0
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GRB_TRG_ARM_DEFAULT 0x0
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GRB_TRG_ARM_POS 0x0
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GRB_TRG_ARM_NEG 0x0
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VDL_USE_DEFVAL 0x1
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VDL_POS_SWG 0x1
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VDL_NEG_SWG 0x0
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VDL_BTH_SWG 0x0
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VDL_AMPL 0x2bc
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VDL_PEDEST 0x0
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VDL_PED_AMP 0x32
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VDL_GAIN_IND 0x2
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VDL_GAIN 0xaf0
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VDL_BRGHT 0x32
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VDL_CONTR 0x32
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VDL_SATUR 0x32
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VDL_HUE 0x32
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DCF_IS_VIRTUAL 0x0
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DAT_INFOFILE_REV_MAJOR 0xa
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DAT_INFOFILE_REV_MINOR 0x12
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DAT_INFOFILE_REV_BUILD 0x0
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EXP_SYN_CLK_2 0x0
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EXP_ASY_CLK_2 0x0
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EXP_CLK_FREQ_2 0x0
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EXP_CLK_DVED_2 0x0
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EXP_CLK_DIVF_2 0x0
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EXP_MD_PERD_2 0x0
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EXP_MD_W_TRG_2 0x0
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EXP_MD_EXT_2 0x0
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EXP_MD_HSY_2 0x0
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EXP_MD_VSY_2 0x0
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EXP_MD_SW_2 0x0
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EXP_TRG_TTL_2 0x1
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EXP_TRG_422_2 0x0
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EXP_TRG_OPTO_2 0x0
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EXP_TRG_LVDS_2 0x0
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EXP_TRG_DEFAULT_2 0x0
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EXP_TRG_POS_2 0x0
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EXP_TRG_NEG_2 0x0
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EXP_OUT_DLYD_2 0x0
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EXP_OUT_T0_2 0x0
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EXP_OUT_T1_2 0x0
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EXP_OUT_T2_2 0x0
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EXP_OUT_T3_2 0x0
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EXP_OUT_TTL_2 0x0
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EXP_OUT_422_2 0x0
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EXP_OUT_OPTO_2 0x0
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EXP_OUT_LVDS_2 0x0
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EXP_OUT_DEFAULT_2 0x0
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EXP_OUT_POS_2 0x0
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EXP_OUT_NEG_2 0x0
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EXP_ARM_ENABLE_2 0x0
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EXP_ARM_DISABLE_2 0x0
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EXP_ARM_TTL_2 0x0
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EXP_ARM_422_2 0x0
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EXP_ARM_OPTO_2 0x0
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EXP_ARM_LVDS_2 0x0
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EXP_ARM_DEFAULT_2 0x0
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EXP_ARM_POS_2 0x1
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EXP_ARM_NEG_2 0x0
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TAP_MULTIPLEX_X 0x1
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TAP_MULTIPLEX_Y 0x1
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TAP_ORDERS 0x343efcea
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REGION_DIRECTIONS 0x0
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TAP_REGIONSX 0x1
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TAP_REGIONSY 0x1
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TAP_PIXADJX 0x1
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TAP_PIXADJY 0x1
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CLC_MODE 0x0
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CLC_MODE_INIT_WIDTH_10_16 0x0
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CLC_ACTIVE_CH0 0x1
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VDT_CL_USE_CAMERA_VALID 0x4
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CL_MODE_BITMAP 0x6
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CLC_MODE_CH0 0x5
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CLC_SYNC_SOURCE 0x0
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CLC_VSYNC_SEL 0x0
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CLC_VSYNC_POL 0x0
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CLC_HSYNC_SEL 0x0
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CLC_HSYNC_POL 0x0
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CLB_CC1 0x0
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CLB_CC2 0x0
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CLB_CC3 0x0
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CLB_CC4 0x0
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CLB_CCOUTEN1 0x0
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CLB_CCOUTEN2 0x0
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USR_IENABLE 0x0
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USR_ITTL 0x0
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USR_ILVDS 0x0
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USR_IOPTO 0x0
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USR_OENABLE 0x0
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USR_OTTL 0x0
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USR_OLVDS 0x0
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USR_BIT_0_OTH0 0x0
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USR_BIT_1_OTH0 0x0
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USR_BIT_2_OTH0 0x0
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USR_BIT_3_OTH0 0x0
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USR_BIT_4_OTH0 0x0
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USR_BIT_5_OTH0 0x0
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USR_BIT_6_OTH0 0x0
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TM_ENABLE 0x0
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TM_LINENUMBER 0x0
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TM_PIXELMODE 0x0
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CT_BAYER_GGBR 0x0
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CT_BAYER_GGRB 0x0
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CT_BAYER_BRGG 0x0
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CT_BAYER_RBGG 0x0
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VDC_VID_WIDTH_10 0x0
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VDC_VID_WIDTH_12 0x0
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VDC_VID_WIDTH_14 0x0
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VDC_VID_WIDTH_16 0x0
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VDC_ODYSSEY_ANA_FILTER 0x0
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GRB_DIG_DESCTL0L 0xc0c0001
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GRB_DIG_DESCTL0H 0xc0c
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GRB_DIG_DESCTL1L 0xc0c0001
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GRB_DIG_DESCTL1H 0xc0c
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GRB_DIG_DESCTL2L 0xc0c0001
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GRB_DIG_DESCTL2H 0xc0c
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VDT_HCNT_LD_ARM_TRG_OPTO 0x0
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VDT_HCNT_LD_ARM_TRG_TTL 0x0
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VDT_HCNT_LD_ARM_TRG_LVDS 0x0
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VDT_HCNT_LD_ARM_DIS 0x0
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VDT_HCNT_LD_ARM_QUADTIMERSTART 0x0
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VDT_HCNT_LD_ARM_TIMER0 0x0
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VDT_HCNT_LD_ARM_TIMER1 0x0
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VDT_HCNT_LD_ARM_TRG_2_AC01_OPTO_CL 0x0
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VDT_HCNT_LD_ARM_TRG_3_AC01_OPTO_CL 0x0
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VDT_HCNT_LD_ARM_TRG_0_AC0_OPTO_CL_SOL_BASE 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC0_OPTO_CL_SOL_BASE 0x0
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VDT_HCNT_LD_ARM_TRG_0_AC1_OPTO_CL 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC1_OPTO_CL 0x0
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VDT_HCNT_LD_ARM_TRG_0_AC0_TTL_CL_SOL_BASE 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC0_TTL_CL_SOL_BASE 0x0
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VDT_HCNT_LD_ARM_TRG_2_AC01_TTL_CL 0x0
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VDT_HCNT_LD_ARM_TRG_3_AC01_TTL_CL 0x0
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VDT_HCNT_LD_ARM_TRG_2_AC01_LVDS_CL 0x0
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VDT_HCNT_LD_ARM_TRG_3_AC01_LVDS_CL 0x0
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VDT_HCNT_LD_ARM_TRG_0_AC0_LVDS_CL_SOL_BASE 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC0_LVDS_CL_SOL_BASE 0x0
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VDT_HCNT_LD_ARM_TRG_0_AC1_LVDS_CL 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC1_LVDS_CL 0x0
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VDT_HCNT_LD_ARM_TRG_0_AC0_OPTO_CL 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC0_OPTO_CL 0x0
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VDT_HCNT_LD_ARM_TRG_0_AC0_TTL_CL 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC0_TTL_CL 0x0
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VDT_HCNT_LD_ARM_TRG_0_AC1_TTL_CL 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC1_TTL_CL 0x0
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VDT_HCNT_LD_ARM_TRG_0_AC0_LVDS_CL 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC0_LVDS_CL 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC0_OPTO_ANA 0x0
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VDT_HCNT_LD_ARM_TRG_1_AC1_OPTO_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC2_OPTO_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC3_OPTO_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC0_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC1_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC2_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC3_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_4AC_AUX0_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_4AC_AUX1_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_4AC_AUX2_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_4AC_AUX3_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_4AC_AUX4_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_4AC_AUX5_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_4AC_AUX6_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_4AC_AUX7_TTL_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_4AC_AUX0_LVDS_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_4AC_AUX1_LVDS_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_4AC_AUX2_LVDS_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_4AC_AUX3_LVDS_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_4AC_AUX4_LVDS_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_4AC_AUX5_LVDS_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_4AC_AUX6_LVDS_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_4AC_AUX7_LVDS_ANA 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC0_OPTO_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC0_OPTO_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC1_OPTO_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC1_OPTO_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC2_OPTO_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC2_OPTO_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC3_OPTO_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC3_OPTO_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC0_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC1_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC2_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_1_AC3_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC0_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC1_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC2_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_0_AC3_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_AC0_AUX1_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_AC0_AUX2_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_AC1_AUX1_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_AC1_AUX2_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_AC2_AUX1_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_AC2_AUX2_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_AC3_AUX1_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_AC3_AUX2_TTL_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_AC0_AUX1_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_AC0_AUX2_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_AC1_AUX1_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_AC1_AUX2_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_AC2_AUX1_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_AC2_AUX2_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_2_AC3_AUX1_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_3_AC3_AUX2_LVDS_DIG 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC0_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC0_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC1_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC1_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
VDT_HCNT_LD_ARM_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
SLOW_SCAN_PLL_HREFSEL_DEFAULT 0x1
|
|
SLOW_SCAN_PLL_HREFSEL_NONE 0x0
|
|
SLOW_SCAN_PLL_HREFSEL_DVI 0x0
|
|
SLOW_SCAN_PLL_HREFSEL_AUX 0x0
|
|
SLOW_SCAN_PLL_HREFSEL_VIDEO 0x0
|
|
SLOW_SCAN_PLL_HREFSEL_DVI_OTHERAC 0x0
|
|
SLOW_SCAN_PLL_HREFSEL_DVI_AC1 0x0
|
|
SLOW_SCAN_PLL_PCKSEL_DEFAULT 0x1
|
|
SLOW_SCAN_PLL_PCKSEL_NONE 0x0
|
|
SLOW_SCAN_PLL_PCKSEL_DVI 0x0
|
|
SLOW_SCAN_PLL_PCKSEL_AUX 0x0
|
|
SLOW_SCAN_PLL_PCKSEL_VIDEO 0x0
|
|
SLOW_SCAN_PLL_PCKSEL_DVI_OTHERAC 0x0
|
|
SLOW_SCAN_PLL_PCKSEL_DVI_AC1 0x0
|
|
GRB_TRG_HS_PSG 0x0
|
|
GRB_TRG_VS_PSG 0x0
|
|
GRB_TRG_TIMER0 0x0
|
|
GRB_TRG_TIMER1 0x0
|
|
GRB_TRG_TIMER2 0x0
|
|
GRB_TRG_TIMER3 0x0
|
|
GRB_TRG_2_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
GRB_TRG_3_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
GRB_TRG_2_AC01_OPTO_CL 0x0
|
|
GRB_TRG_3_AC01_OPTO_CL 0x0
|
|
GRB_TRG_0_AC0_OPTO_CL_SOL_BASE 0x0
|
|
GRB_TRG_1_AC0_OPTO_CL_SOL_BASE 0x0
|
|
GRB_TRG_0_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
GRB_TRG_1_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
GRB_TRG_0_AC0_OPTO_CL 0x0
|
|
GRB_TRG_1_AC0_OPTO_CL 0x0
|
|
GRB_TRG_0_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
GRB_TRG_1_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
GRB_TRG_0_AC1_OPTO_CL 0x0
|
|
GRB_TRG_1_AC1_OPTO_CL 0x0
|
|
GRB_TRG_0_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
GRB_TRG_1_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
GRB_TRG_0_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
GRB_TRG_1_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
GRB_TRG_2_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
GRB_TRG_3_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
GRB_TRG_2_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
GRB_TRG_3_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
GRB_TRG_0_AC0_TTL_CL_SOL_BASE 0x0
|
|
GRB_TRG_1_AC0_TTL_CL_SOL_BASE 0x0
|
|
GRB_TRG_0_AC0_TTL_CL_SOL_EVCL 0x0
|
|
GRB_TRG_1_AC0_TTL_CL_SOL_EVCL 0x0
|
|
GRB_TRG_0_AC0_TTL_CL 0x0
|
|
GRB_TRG_1_AC0_TTL_CL 0x0
|
|
GRB_TRG_0_AC1_TTL_CL_SOL_EVCL 0x0
|
|
GRB_TRG_1_AC1_TTL_CL_SOL_EVCL 0x0
|
|
GRB_TRG_0_AC1_TTL_CL 0x0
|
|
GRB_TRG_1_AC1_TTL_CL 0x0
|
|
GRB_TRG_2_AC01_TTL_CL_SOL_EVCL 0x0
|
|
GRB_TRG_3_AC01_TTL_CL_SOL_EVCL 0x0
|
|
GRB_TRG_2_AC01_TTL_CL 0x0
|
|
GRB_TRG_3_AC01_TTL_CL 0x0
|
|
GRB_TRG_0_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_1_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_0_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_1_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_0_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_1_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_0_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_1_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_2_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_3_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_2_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_3_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
GRB_TRG_0_AC0_LVDS_CL_SOL_BASE 0x0
|
|
GRB_TRG_1_AC0_LVDS_CL_SOL_BASE 0x0
|
|
GRB_TRG_0_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
GRB_TRG_1_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
GRB_TRG_0_AC0_LVDS_CL 0x0
|
|
GRB_TRG_1_AC0_LVDS_CL 0x0
|
|
GRB_TRG_0_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
GRB_TRG_1_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
GRB_TRG_0_AC1_LVDS_CL 0x0
|
|
GRB_TRG_1_AC1_LVDS_CL 0x0
|
|
GRB_TRG_2_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
GRB_TRG_3_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
GRB_TRG_2_AC01_LVDS_CL 0x0
|
|
GRB_TRG_3_AC01_LVDS_CL 0x0
|
|
GRB_TRG_0_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
GRB_TRG_1_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
GRB_TRG_0_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
GRB_TRG_1_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
GRB_TRG_2_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
GRB_TRG_3_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
GRB_TRG_2_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
GRB_TRG_3_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
GRB_TRG_1_AC0_OPTO_ANA 0x0
|
|
GRB_TRG_1_AC1_OPTO_ANA 0x0
|
|
GRB_TRG_1_AC2_OPTO_ANA 0x0
|
|
GRB_TRG_1_AC3_OPTO_ANA 0x0
|
|
GRB_TRG_0_AC0_TTL_ANA 0x0
|
|
GRB_TRG_0_AC1_TTL_ANA 0x0
|
|
GRB_TRG_0_AC2_TTL_ANA 0x0
|
|
GRB_TRG_0_AC3_TTL_ANA 0x0
|
|
GRB_TRG_2_4AC_AUX0_TTL_ANA 0x0
|
|
GRB_TRG_3_4AC_AUX1_TTL_ANA 0x0
|
|
GRB_TRG_2_4AC_AUX2_TTL_ANA 0x0
|
|
GRB_TRG_3_4AC_AUX3_TTL_ANA 0x0
|
|
GRB_TRG_2_4AC_AUX4_TTL_ANA 0x0
|
|
GRB_TRG_3_4AC_AUX5_TTL_ANA 0x0
|
|
GRB_TRG_2_4AC_AUX6_TTL_ANA 0x0
|
|
GRB_TRG_3_4AC_AUX7_TTL_ANA 0x0
|
|
GRB_TRG_2_4AC_AUX0_LVDS_ANA 0x0
|
|
GRB_TRG_3_4AC_AUX1_LVDS_ANA 0x0
|
|
GRB_TRG_2_4AC_AUX2_LVDS_ANA 0x0
|
|
GRB_TRG_3_4AC_AUX3_LVDS_ANA 0x0
|
|
GRB_TRG_2_4AC_AUX4_LVDS_ANA 0x0
|
|
GRB_TRG_3_4AC_AUX5_LVDS_ANA 0x0
|
|
GRB_TRG_2_4AC_AUX6_LVDS_ANA 0x0
|
|
GRB_TRG_3_4AC_AUX7_LVDS_ANA 0x0
|
|
GRB_TRG_0_AC0_OPTO_DIG 0x0
|
|
GRB_TRG_1_AC0_OPTO_DIG 0x0
|
|
GRB_TRG_0_AC1_OPTO_DIG 0x0
|
|
GRB_TRG_1_AC1_OPTO_DIG 0x0
|
|
GRB_TRG_0_AC2_OPTO_DIG 0x0
|
|
GRB_TRG_1_AC2_OPTO_DIG 0x0
|
|
GRB_TRG_0_AC3_OPTO_DIG 0x0
|
|
GRB_TRG_1_AC3_OPTO_DIG 0x0
|
|
GRB_TRG_1_AC0_TTL_DIG 0x0
|
|
GRB_TRG_1_AC1_TTL_DIG 0x0
|
|
GRB_TRG_1_AC2_TTL_DIG 0x0
|
|
GRB_TRG_1_AC3_TTL_DIG 0x0
|
|
GRB_TRG_0_AC0_LVDS_DIG 0x0
|
|
GRB_TRG_0_AC1_LVDS_DIG 0x0
|
|
GRB_TRG_0_AC2_LVDS_DIG 0x0
|
|
GRB_TRG_0_AC3_LVDS_DIG 0x0
|
|
GRB_TRG_2_AC0_AUX1_TTL_DIG 0x0
|
|
GRB_TRG_3_AC0_AUX2_TTL_DIG 0x0
|
|
GRB_TRG_2_AC1_AUX1_TTL_DIG 0x0
|
|
GRB_TRG_3_AC1_AUX2_TTL_DIG 0x0
|
|
GRB_TRG_2_AC2_AUX1_TTL_DIG 0x0
|
|
GRB_TRG_3_AC2_AUX2_TTL_DIG 0x0
|
|
GRB_TRG_2_AC3_AUX1_TTL_DIG 0x0
|
|
GRB_TRG_3_AC3_AUX2_TTL_DIG 0x0
|
|
GRB_TRG_2_AC0_AUX1_LVDS_DIG 0x0
|
|
GRB_TRG_3_AC0_AUX2_LVDS_DIG 0x0
|
|
GRB_TRG_2_AC1_AUX1_LVDS_DIG 0x0
|
|
GRB_TRG_3_AC1_AUX2_LVDS_DIG 0x0
|
|
GRB_TRG_2_AC2_AUX1_LVDS_DIG 0x0
|
|
GRB_TRG_3_AC2_AUX2_LVDS_DIG 0x0
|
|
GRB_TRG_2_AC3_AUX1_LVDS_DIG 0x0
|
|
GRB_TRG_3_AC3_AUX2_LVDS_DIG 0x0
|
|
GRB_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
GRB_TRG_LVDS_ROTARY_ENCODER 0x0
|
|
GRB_DISABLED_ARM 0x0
|
|
GRB_HARDWARE_ARM 0x0
|
|
GRB_SOFTWARE_ARM 0x0
|
|
GRB_HARDWARE_LATCH_ARM 0x0
|
|
EXP_TRG_TTL_TIMER0 0x0
|
|
EXP_TRG_CNTEQ0_TIMER0 0x0
|
|
EXP_TRG_TIMER1 0x0
|
|
EXP_TRG_TIMER2 0x0
|
|
EXP_TRG_TIMER3 0x0
|
|
EXP_0_TRG_TIMER0_AC0 0x0
|
|
EXP_0_TRG_TIMER0_AC1 0x0
|
|
EXP_0_TRG_TIMER0_AC2 0x0
|
|
EXP_0_TRG_TIMER0_AC3 0x0
|
|
EXP_0_TRG_2_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_3_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_2_AC01_OPTO_CL 0x0
|
|
EXP_0_TRG_3_AC01_OPTO_CL 0x0
|
|
EXP_0_TRG_0_AC0_OPTO_CL_SOL_BASE 0x0
|
|
EXP_0_TRG_1_AC0_OPTO_CL_SOL_BASE 0x0
|
|
EXP_0_TRG_0_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_1_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_0_AC0_OPTO_CL 0x0
|
|
EXP_0_TRG_1_AC0_OPTO_CL 0x0
|
|
EXP_0_TRG_0_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_1_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_0_AC1_OPTO_CL 0x0
|
|
EXP_0_TRG_1_AC1_OPTO_CL 0x0
|
|
EXP_0_TRG_0_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
EXP_0_TRG_1_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
EXP_0_TRG_0_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
EXP_0_TRG_1_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
EXP_0_TRG_2_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
EXP_0_TRG_3_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
EXP_0_TRG_2_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
EXP_0_TRG_3_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
EXP_0_TRG_0_AC0_TTL_CL_SOL_BASE 0x0
|
|
EXP_0_TRG_1_AC0_TTL_CL_SOL_BASE 0x0
|
|
EXP_0_TRG_0_AC0_TTL_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_1_AC0_TTL_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_0_AC0_TTL_CL 0x0
|
|
EXP_0_TRG_1_AC0_TTL_CL 0x0
|
|
EXP_0_TRG_0_AC1_TTL_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_1_AC1_TTL_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_0_AC1_TTL_CL 0x0
|
|
EXP_0_TRG_1_AC1_TTL_CL 0x0
|
|
EXP_0_TRG_2_AC01_TTL_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_3_AC01_TTL_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_2_AC01_TTL_CL 0x0
|
|
EXP_0_TRG_3_AC01_TTL_CL 0x0
|
|
EXP_0_TRG_0_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_1_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_0_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_1_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_0_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_1_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_0_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_1_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_2_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_3_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_2_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_3_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
EXP_0_TRG_0_AC0_LVDS_CL_SOL_BASE 0x0
|
|
EXP_0_TRG_1_AC0_LVDS_CL_SOL_BASE 0x0
|
|
EXP_0_TRG_0_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_1_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_0_AC0_LVDS_CL 0x0
|
|
EXP_0_TRG_1_AC0_LVDS_CL 0x0
|
|
EXP_0_TRG_0_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_1_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_0_AC1_LVDS_CL 0x0
|
|
EXP_0_TRG_1_AC1_LVDS_CL 0x0
|
|
EXP_0_TRG_2_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_3_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_0_TRG_2_AC01_LVDS_CL 0x0
|
|
EXP_0_TRG_3_AC01_LVDS_CL 0x0
|
|
EXP_0_TRG_0_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
EXP_0_TRG_1_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
EXP_0_TRG_0_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
EXP_0_TRG_1_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
EXP_0_TRG_2_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
EXP_0_TRG_3_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
EXP_0_TRG_2_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
EXP_0_TRG_3_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
EXP_0_TRG_1_AC0_OPTO_ANA 0x0
|
|
EXP_0_TRG_1_AC1_OPTO_ANA 0x0
|
|
EXP_0_TRG_1_AC2_OPTO_ANA 0x0
|
|
EXP_0_TRG_1_AC3_OPTO_ANA 0x0
|
|
EXP_0_TRG_0_AC0_TTL_ANA 0x0
|
|
EXP_0_TRG_0_AC1_TTL_ANA 0x0
|
|
EXP_0_TRG_0_AC2_TTL_ANA 0x0
|
|
EXP_0_TRG_0_AC3_TTL_ANA 0x0
|
|
EXP_0_TRG_2_4AC_AUX0_TTL_ANA 0x0
|
|
EXP_0_TRG_3_4AC_AUX1_TTL_ANA 0x0
|
|
EXP_0_TRG_2_4AC_AUX2_TTL_ANA 0x0
|
|
EXP_0_TRG_3_4AC_AUX3_TTL_ANA 0x0
|
|
EXP_0_TRG_2_4AC_AUX4_TTL_ANA 0x0
|
|
EXP_0_TRG_3_4AC_AUX5_TTL_ANA 0x0
|
|
EXP_0_TRG_2_4AC_AUX6_TTL_ANA 0x0
|
|
EXP_0_TRG_3_4AC_AUX7_TTL_ANA 0x0
|
|
EXP_0_TRG_2_4AC_AUX0_LVDS_ANA 0x0
|
|
EXP_0_TRG_3_4AC_AUX1_LVDS_ANA 0x0
|
|
EXP_0_TRG_2_4AC_AUX2_LVDS_ANA 0x0
|
|
EXP_0_TRG_3_4AC_AUX3_LVDS_ANA 0x0
|
|
EXP_0_TRG_2_4AC_AUX4_LVDS_ANA 0x0
|
|
EXP_0_TRG_3_4AC_AUX5_LVDS_ANA 0x0
|
|
EXP_0_TRG_2_4AC_AUX6_LVDS_ANA 0x0
|
|
EXP_0_TRG_3_4AC_AUX7_LVDS_ANA 0x0
|
|
EXP_0_TRG_0_AC0_OPTO_DIG 0x0
|
|
EXP_0_TRG_1_AC0_OPTO_DIG 0x0
|
|
EXP_0_TRG_0_AC1_OPTO_DIG 0x0
|
|
EXP_0_TRG_1_AC1_OPTO_DIG 0x0
|
|
EXP_0_TRG_0_AC2_OPTO_DIG 0x0
|
|
EXP_0_TRG_1_AC2_OPTO_DIG 0x0
|
|
EXP_0_TRG_0_AC3_OPTO_DIG 0x0
|
|
EXP_0_TRG_1_AC3_OPTO_DIG 0x0
|
|
EXP_0_TRG_1_AC0_TTL_DIG 0x0
|
|
EXP_0_TRG_1_AC1_TTL_DIG 0x0
|
|
EXP_0_TRG_1_AC2_TTL_DIG 0x0
|
|
EXP_0_TRG_1_AC3_TTL_DIG 0x0
|
|
EXP_0_TRG_0_AC0_LVDS_DIG 0x0
|
|
EXP_0_TRG_0_AC1_LVDS_DIG 0x0
|
|
EXP_0_TRG_0_AC2_LVDS_DIG 0x0
|
|
EXP_0_TRG_0_AC3_LVDS_DIG 0x0
|
|
EXP_0_TRG_2_AC0_AUX1_TTL_DIG 0x0
|
|
EXP_0_TRG_3_AC0_AUX2_TTL_DIG 0x0
|
|
EXP_0_TRG_2_AC1_AUX1_TTL_DIG 0x0
|
|
EXP_0_TRG_3_AC1_AUX2_TTL_DIG 0x0
|
|
EXP_0_TRG_2_AC2_AUX1_TTL_DIG 0x0
|
|
EXP_0_TRG_3_AC2_AUX2_TTL_DIG 0x0
|
|
EXP_0_TRG_2_AC3_AUX1_TTL_DIG 0x0
|
|
EXP_0_TRG_3_AC3_AUX2_TTL_DIG 0x0
|
|
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG 0x0
|
|
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG 0x0
|
|
EXP_0_TRG_2_AC1_AUX1_LVDS_DIG 0x0
|
|
EXP_0_TRG_3_AC1_AUX2_LVDS_DIG 0x0
|
|
EXP_0_TRG_2_AC2_AUX1_LVDS_DIG 0x0
|
|
EXP_0_TRG_3_AC2_AUX2_LVDS_DIG 0x0
|
|
EXP_0_TRG_2_AC3_AUX1_LVDS_DIG 0x0
|
|
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG 0x0
|
|
EXP_0_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
EXP_0_TRG_LVDS_ROTARY_ENCODER 0x0
|
|
EXP_CLK_CLKGEN 0x0
|
|
EXP_CLK_HS 0x0
|
|
EXP_CLK_VS 0x0
|
|
EXP_CLK_TIMER1 0x0
|
|
EXP_CLK_TIMER2 0x0
|
|
EXP_CLK_TIMER3 0x0
|
|
EXP_CLK_AUXIN1_LVDS 0x0
|
|
EXP_CLK_AUXIN3_LVDS 0x0
|
|
EXP_CLK_AUXIN1_AC0_CL 0x0
|
|
EXP_CLK_AUXIN3_AC1_CL 0x0
|
|
EXP_CLK_AUXIN1_AC0_CL_SOL_BASE_EVCL_RADIENT 0x1
|
|
EXP_CLK_AUXIN3_AC1_CL_SOL_BASE_EVCL_RADIENT 0x0
|
|
EXP_CLK_AUXIN1_AC2_CL_RADIENT 0x0
|
|
EXP_CLK_AUXIN3_AC3_CL_RADIENT 0x0
|
|
EXP_CLK_AUXIN1_AC0_ANA 0x0
|
|
EXP_CLK_AUXIN3_AC1_ANA 0x0
|
|
EXP_CLK_AUXIN5_AC2_ANA 0x0
|
|
EXP_CLK_AUXIN7_AC3_ANA 0x0
|
|
EXP_CLK_AUXIN2_AC0_DIG 0x0
|
|
EXP_CLK_AUXIN2_AC1_DIG 0x0
|
|
EXP_CLK_AUXIN2_AC2_DIG 0x0
|
|
EXP_CLK_AUXIN2_AC3_DIG 0x0
|
|
EXP_CLK_AUXIN1_AC0_CL_SOL_EVCL 0x0
|
|
EXP_CLK_AUXIN3_AC1_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_CNTEQ0 0x1
|
|
ARM_EXP_0_SOFTWARE 0x0
|
|
ARM_EXP_0_TIMER1 0x0
|
|
ARM_EXP_0_TIMER2 0x0
|
|
ARM_EXP_0_TIMER3 0x0
|
|
ARM_EXP_0_TRG_TIMER0_AC0 0x0
|
|
ARM_EXP_0_TRG_TIMER0_AC1 0x0
|
|
ARM_EXP_0_TRG_TIMER0_AC2 0x0
|
|
ARM_EXP_0_TRG_TIMER0_AC3 0x0
|
|
ARM_EXP_0_HS_PSG 0x0
|
|
ARM_EXP_0_VS_PSG 0x0
|
|
ARM_EXP_0_TRG_2_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_3_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_2_AC01_OPTO_CL 0x0
|
|
ARM_EXP_0_TRG_3_AC01_OPTO_CL 0x0
|
|
ARM_EXP_0_TRG_0_AC0_OPTO_CL_SOL_BASE 0x0
|
|
ARM_EXP_0_TRG_1_AC0_OPTO_CL_SOL_BASE 0x0
|
|
ARM_EXP_0_TRG_0_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_1_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_0_AC0_OPTO_CL 0x0
|
|
ARM_EXP_0_TRG_1_AC0_OPTO_CL 0x0
|
|
ARM_EXP_0_TRG_0_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_1_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_0_AC1_OPTO_CL 0x0
|
|
ARM_EXP_0_TRG_1_AC1_OPTO_CL 0x0
|
|
ARM_EXP_0_TRG_0_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_1_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_0_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_1_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_2_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_3_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_2_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_3_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_0_AC0_TTL_CL_SOL_BASE 0x0
|
|
ARM_EXP_0_TRG_1_AC0_TTL_CL_SOL_BASE 0x0
|
|
ARM_EXP_0_TRG_0_AC0_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_1_AC0_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_0_AC0_TTL_CL 0x0
|
|
ARM_EXP_0_TRG_1_AC0_TTL_CL 0x0
|
|
ARM_EXP_0_TRG_0_AC1_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_1_AC1_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_0_AC1_TTL_CL 0x0
|
|
ARM_EXP_0_TRG_1_AC1_TTL_CL 0x0
|
|
ARM_EXP_0_TRG_2_AC01_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_3_AC01_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_2_AC01_TTL_CL 0x0
|
|
ARM_EXP_0_TRG_3_AC01_TTL_CL 0x0
|
|
ARM_EXP_0_TRG_0_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_1_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_0_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_1_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_0_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_1_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_0_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_1_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_2_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_3_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_2_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_3_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_0_AC0_LVDS_CL_SOL_BASE 0x0
|
|
ARM_EXP_0_TRG_1_AC0_LVDS_CL_SOL_BASE 0x0
|
|
ARM_EXP_0_TRG_0_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_1_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_0_AC0_LVDS_CL 0x0
|
|
ARM_EXP_0_TRG_1_AC0_LVDS_CL 0x0
|
|
ARM_EXP_0_TRG_0_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_1_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_0_AC1_LVDS_CL 0x0
|
|
ARM_EXP_0_TRG_1_AC1_LVDS_CL 0x0
|
|
ARM_EXP_0_TRG_2_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_3_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_0_TRG_2_AC01_LVDS_CL 0x0
|
|
ARM_EXP_0_TRG_3_AC01_LVDS_CL 0x0
|
|
ARM_EXP_0_TRG_0_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_1_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_0_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_1_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_2_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_3_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_2_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_3_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_0_TRG_1_AC0_OPTO_ANA 0x0
|
|
ARM_EXP_0_TRG_1_AC1_OPTO_ANA 0x0
|
|
ARM_EXP_0_TRG_1_AC2_OPTO_ANA 0x0
|
|
ARM_EXP_0_TRG_1_AC3_OPTO_ANA 0x0
|
|
ARM_EXP_0_TRG_0_AC0_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_0_AC1_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_0_AC2_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_0_AC3_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA 0x0
|
|
ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA 0x0
|
|
ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA 0x0
|
|
ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA 0x0
|
|
ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA 0x0
|
|
ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA 0x0
|
|
ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA 0x0
|
|
ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA 0x0
|
|
ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA 0x0
|
|
ARM_EXP_0_TRG_0_AC0_OPTO_DIG 0x0
|
|
ARM_EXP_0_TRG_1_AC0_OPTO_DIG 0x0
|
|
ARM_EXP_0_TRG_0_AC1_OPTO_DIG 0x0
|
|
ARM_EXP_0_TRG_1_AC1_OPTO_DIG 0x0
|
|
ARM_EXP_0_TRG_0_AC2_OPTO_DIG 0x0
|
|
ARM_EXP_0_TRG_1_AC2_OPTO_DIG 0x0
|
|
ARM_EXP_0_TRG_0_AC3_OPTO_DIG 0x0
|
|
ARM_EXP_0_TRG_1_AC3_OPTO_DIG 0x0
|
|
ARM_EXP_0_TRG_1_AC0_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_1_AC1_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_1_AC2_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_1_AC3_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_0_AC0_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_0_AC1_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_0_AC2_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_0_AC3_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG 0x0
|
|
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER 0x0
|
|
EXP_NOCOMBINE 0x0
|
|
EXP_COMBINE_XOR_T1 0x0
|
|
EXP_COMBINE_XOR_T0AC1 0x0
|
|
EXP_COMBINE_T1 0x0
|
|
EXP_0_NOCOMBINE_AC0_CL_SOL_BASE_HD_CC 0x1
|
|
EXP_0_COMBINE_XOR_T1_AC0_CL_SOL_BASE_HD_CC 0x0
|
|
EXP_0_COMBINE_T1_AC0_CL_SOL_BASE_HD_CC 0x0
|
|
EXP_0_NOCOMBINE_AC0_CL_HD_CC 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC0_CL_HD_CC 0x0
|
|
EXP_0_COMBINE_T1_AC0_CL_HD_CC 0x0
|
|
EXP_0_NOCOMBINE_AC1_CL_HD_CC 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC1_CL_HD_CC 0x0
|
|
EXP_0_COMBINE_T1_AC1_CL_HD_CC 0x0
|
|
EXP_0_NOCOMBINE_CL_CC 0x0
|
|
EXP_0_COMBINE_XOR_T1_CL_CC 0x0
|
|
EXP_0_COMBINE_T1_CL_CC 0x0
|
|
EXP_0_NOCOMBINE_AC0_ANA_HD_DVI 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC0_ANA_HD_DVI 0x0
|
|
EXP_0_COMBINE_T1_AC0_ANA_HD_DVI 0x0
|
|
EXP_0_NOCOMBINE_AC1_ANA_HD_DVI 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC1_ANA_HD_DVI 0x0
|
|
EXP_0_COMBINE_T1_AC1_ANA_HD_DVI 0x0
|
|
EXP_0_NOCOMBINE_AC2_ANA_HD_DVI 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC2_ANA_HD_DVI 0x0
|
|
EXP_0_COMBINE_T1_AC2_ANA_HD_DVI 0x0
|
|
EXP_0_NOCOMBINE_AC3_ANA_HD_DVI 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC3_ANA_HD_DVI 0x0
|
|
EXP_0_COMBINE_T1_AC3_ANA_HD_DVI 0x0
|
|
EXP_0_NOCOMBINE_AC0_ANA_DVI 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC0_ANA_DVI 0x0
|
|
EXP_0_COMBINE_T1_AC0_ANA_DVI 0x0
|
|
EXP_0_NOCOMBINE_AC1_ANA_DVI 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC1_ANA_DVI 0x0
|
|
EXP_0_COMBINE_T1_AC1_ANA_DVI 0x0
|
|
EXP_0_NOCOMBINE_AC2_ANA_DVI 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC2_ANA_DVI 0x0
|
|
EXP_0_COMBINE_T1_AC2_ANA_DVI 0x0
|
|
EXP_0_NOCOMBINE_AC3_ANA_DVI 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC3_ANA_DVI 0x0
|
|
EXP_0_COMBINE_T1_AC3_ANA_DVI 0x0
|
|
EXP_0_NOCOMBINE_AC0_DIG_HD_DCON 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC0_DIG_HD_DCON 0x0
|
|
EXP_0_COMBINE_T1_AC0_DIG_HD_DCON 0x0
|
|
EXP_0_NOCOMBINE_AC1_DIG_HD_DCON 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC1_DIG_HD_DCON 0x0
|
|
EXP_0_COMBINE_T1_AC1_DIG_HD_DCON 0x0
|
|
EXP_0_NOCOMBINE_AC2_DIG_HD_DCON 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC2_DIG_HD_DCON 0x0
|
|
EXP_0_COMBINE_T1_AC2_DIG_HD_DCON 0x0
|
|
EXP_0_NOCOMBINE_AC3_DIG_HD_DCON 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC3_DIG_HD_DCON 0x0
|
|
EXP_0_COMBINE_T1_AC3_DIG_HD_DCON 0x0
|
|
EXP_0_NOCOMBINE_AC0_DIG_DCON 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC0_DIG_DCON 0x0
|
|
EXP_0_COMBINE_T1_AC0_DIG_DCON 0x0
|
|
EXP_0_NOCOMBINE_AC1_DIG_DCON 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC1_DIG_DCON 0x0
|
|
EXP_0_COMBINE_T1_AC1_DIG_DCON 0x0
|
|
EXP_0_NOCOMBINE_AC2_DIG_DCON 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC2_DIG_DCON 0x0
|
|
EXP_0_COMBINE_T1_AC2_DIG_DCON 0x0
|
|
EXP_0_NOCOMBINE_AC3_DIG_DCON 0x0
|
|
EXP_0_COMBINE_XOR_T1_AC3_DIG_DCON 0x0
|
|
EXP_0_COMBINE_T1_AC3_DIG_DCON 0x0
|
|
EXP_PRESCALE1_1 0x0
|
|
EXP_PRESCALE1_2 0x0
|
|
EXP_PRESCALE1_4 0x0
|
|
EXP_PRESCALE1_8 0x0
|
|
EXP_PRESCALE1_16 0x0
|
|
EXP_TRG_TTL_TIMER1 0x0
|
|
EXP_TRG_TTL_TIMER2 0x0
|
|
EXP_TRG_CNTEQ0_TIMER1 0x0
|
|
EXP_TRG_TIMER0_2 0x0
|
|
EXP_TRG_TIMER2_2 0x0
|
|
EXP_TRG_TIMER3_2 0x0
|
|
EXP_1_TRG_TIMER1_AC0 0x0
|
|
EXP_1_TRG_TIMER1_AC1 0x0
|
|
EXP_1_TRG_TIMER1_AC2 0x0
|
|
EXP_1_TRG_TIMER1_AC3 0x0
|
|
EXP_1_TRG_2_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_3_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_2_AC01_OPTO_CL 0x0
|
|
EXP_1_TRG_3_AC01_OPTO_CL 0x0
|
|
EXP_1_TRG_0_AC0_OPTO_CL_SOL_BASE 0x0
|
|
EXP_1_TRG_1_AC0_OPTO_CL_SOL_BASE 0x0
|
|
EXP_1_TRG_0_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_1_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_0_AC0_OPTO_CL 0x0
|
|
EXP_1_TRG_1_AC0_OPTO_CL 0x0
|
|
EXP_1_TRG_0_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_1_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_0_AC1_OPTO_CL 0x0
|
|
EXP_1_TRG_1_AC1_OPTO_CL 0x0
|
|
EXP_1_TRG_0_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
EXP_1_TRG_1_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
EXP_1_TRG_0_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
EXP_1_TRG_1_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
EXP_1_TRG_2_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
EXP_1_TRG_3_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
EXP_1_TRG_2_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
EXP_1_TRG_3_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
EXP_1_TRG_0_AC0_TTL_CL_SOL_BASE 0x0
|
|
EXP_1_TRG_1_AC0_TTL_CL_SOL_BASE 0x0
|
|
EXP_1_TRG_0_AC0_TTL_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_1_AC0_TTL_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_0_AC0_TTL_CL 0x0
|
|
EXP_1_TRG_1_AC0_TTL_CL 0x0
|
|
EXP_1_TRG_0_AC1_TTL_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_1_AC1_TTL_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_0_AC1_TTL_CL 0x0
|
|
EXP_1_TRG_1_AC1_TTL_CL 0x0
|
|
EXP_1_TRG_2_AC01_TTL_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_3_AC01_TTL_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_2_AC01_TTL_CL 0x0
|
|
EXP_1_TRG_3_AC01_TTL_CL 0x0
|
|
EXP_1_TRG_0_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_1_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_0_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_1_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_0_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_1_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_0_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_1_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_2_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_3_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_2_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_3_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
EXP_1_TRG_0_AC0_LVDS_CL_SOL_BASE 0x0
|
|
EXP_1_TRG_1_AC0_LVDS_CL_SOL_BASE 0x0
|
|
EXP_1_TRG_0_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_1_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_0_AC0_LVDS_CL 0x0
|
|
EXP_1_TRG_1_AC0_LVDS_CL 0x0
|
|
EXP_1_TRG_0_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_1_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_0_AC1_LVDS_CL 0x0
|
|
EXP_1_TRG_1_AC1_LVDS_CL 0x0
|
|
EXP_1_TRG_2_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_3_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
EXP_1_TRG_2_AC01_LVDS_CL 0x0
|
|
EXP_1_TRG_3_AC01_LVDS_CL 0x0
|
|
EXP_1_TRG_0_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
EXP_1_TRG_1_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
EXP_1_TRG_0_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
EXP_1_TRG_1_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
EXP_1_TRG_2_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
EXP_1_TRG_3_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
EXP_1_TRG_2_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
EXP_1_TRG_3_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
EXP_1_TRG_1_AC0_OPTO_ANA 0x0
|
|
EXP_1_TRG_1_AC1_OPTO_ANA 0x0
|
|
EXP_1_TRG_1_AC2_OPTO_ANA 0x0
|
|
EXP_1_TRG_1_AC3_OPTO_ANA 0x0
|
|
EXP_1_TRG_0_AC0_TTL_ANA 0x0
|
|
EXP_1_TRG_0_AC1_TTL_ANA 0x0
|
|
EXP_1_TRG_0_AC2_TTL_ANA 0x0
|
|
EXP_1_TRG_0_AC3_TTL_ANA 0x0
|
|
EXP_1_TRG_2_4AC_AUX0_TTL_ANA 0x0
|
|
EXP_1_TRG_3_4AC_AUX1_TTL_ANA 0x0
|
|
EXP_1_TRG_2_4AC_AUX2_TTL_ANA 0x0
|
|
EXP_1_TRG_3_4AC_AUX3_TTL_ANA 0x0
|
|
EXP_1_TRG_2_4AC_AUX4_TTL_ANA 0x0
|
|
EXP_1_TRG_3_4AC_AUX5_TTL_ANA 0x0
|
|
EXP_1_TRG_2_4AC_AUX6_TTL_ANA 0x0
|
|
EXP_1_TRG_3_4AC_AUX7_TTL_ANA 0x0
|
|
EXP_1_TRG_2_4AC_AUX0_LVDS_ANA 0x0
|
|
EXP_1_TRG_3_4AC_AUX1_LVDS_ANA 0x0
|
|
EXP_1_TRG_2_4AC_AUX2_LVDS_ANA 0x0
|
|
EXP_1_TRG_3_4AC_AUX3_LVDS_ANA 0x0
|
|
EXP_1_TRG_2_4AC_AUX4_LVDS_ANA 0x0
|
|
EXP_1_TRG_3_4AC_AUX5_LVDS_ANA 0x0
|
|
EXP_1_TRG_2_4AC_AUX6_LVDS_ANA 0x0
|
|
EXP_1_TRG_3_4AC_AUX7_LVDS_ANA 0x0
|
|
EXP_1_TRG_0_AC0_OPTO_DIG 0x0
|
|
EXP_1_TRG_1_AC0_OPTO_DIG 0x0
|
|
EXP_1_TRG_0_AC1_OPTO_DIG 0x0
|
|
EXP_1_TRG_1_AC1_OPTO_DIG 0x0
|
|
EXP_1_TRG_0_AC2_OPTO_DIG 0x0
|
|
EXP_1_TRG_1_AC2_OPTO_DIG 0x0
|
|
EXP_1_TRG_0_AC3_OPTO_DIG 0x0
|
|
EXP_1_TRG_1_AC3_OPTO_DIG 0x0
|
|
EXP_1_TRG_1_AC0_TTL_DIG 0x0
|
|
EXP_1_TRG_1_AC1_TTL_DIG 0x0
|
|
EXP_1_TRG_1_AC2_TTL_DIG 0x0
|
|
EXP_1_TRG_1_AC3_TTL_DIG 0x0
|
|
EXP_1_TRG_0_AC0_LVDS_DIG 0x0
|
|
EXP_1_TRG_0_AC1_LVDS_DIG 0x0
|
|
EXP_1_TRG_0_AC2_LVDS_DIG 0x0
|
|
EXP_1_TRG_0_AC3_LVDS_DIG 0x0
|
|
EXP_1_TRG_2_AC0_AUX1_TTL_DIG 0x0
|
|
EXP_1_TRG_3_AC0_AUX2_TTL_DIG 0x0
|
|
EXP_1_TRG_2_AC1_AUX1_TTL_DIG 0x0
|
|
EXP_1_TRG_3_AC1_AUX2_TTL_DIG 0x0
|
|
EXP_1_TRG_2_AC2_AUX1_TTL_DIG 0x0
|
|
EXP_1_TRG_3_AC2_AUX2_TTL_DIG 0x0
|
|
EXP_1_TRG_2_AC3_AUX1_TTL_DIG 0x0
|
|
EXP_1_TRG_3_AC3_AUX2_TTL_DIG 0x0
|
|
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG 0x0
|
|
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG 0x0
|
|
EXP_1_TRG_2_AC1_AUX1_LVDS_DIG 0x0
|
|
EXP_1_TRG_3_AC1_AUX2_LVDS_DIG 0x0
|
|
EXP_1_TRG_2_AC2_AUX1_LVDS_DIG 0x0
|
|
EXP_1_TRG_3_AC2_AUX2_LVDS_DIG 0x0
|
|
EXP_1_TRG_2_AC3_AUX1_LVDS_DIG 0x0
|
|
EXP_1_TRG_3_AC3_AUX2_LVDS_DIG 0x0
|
|
EXP_1_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
EXP_1_TRG_LVDS_ROTARY_ENCODER 0x0
|
|
EXP_CLK_2_CLKGEN 0x0
|
|
EXP_CLK_2_HS 0x0
|
|
EXP_CLK_2_VS 0x0
|
|
EXP_CLK_2_TIMER0 0x0
|
|
EXP_CLK_2_TIMER2 0x0
|
|
EXP_CLK_2_TIMER3 0x0
|
|
EXP_CLK_2_AUXIN1_LVDS 0x0
|
|
EXP_CLK_2_AUXIN3_LVDS 0x0
|
|
EXP_CLK_2_AUXIN1_AC0_CL 0x0
|
|
EXP_CLK_2_AUXIN3_AC1_CL 0x0
|
|
EXP_CLK_2_AUXIN1_AC0_CL_SOL_BASE_EVCL_RADIENT 0x0
|
|
EXP_CLK_2_AUXIN3_AC1_CL_SOL_BASE_EVCL_RADIENT 0x0
|
|
EXP_CLK_2_AUXIN1_AC2_CL_RADIENT 0x0
|
|
EXP_CLK_2_AUXIN3_AC3_CL_RADIENT 0x0
|
|
EXP_CLK_2_AUXIN1_AC0_ANA 0x0
|
|
EXP_CLK_2_AUXIN3_AC1_ANA 0x0
|
|
EXP_CLK_2_AUXIN5_AC2_ANA 0x0
|
|
EXP_CLK_2_AUXIN7_AC3_ANA 0x0
|
|
EXP_CLK_2_AUXIN2_AC0_DIG 0x0
|
|
EXP_CLK_2_AUXIN2_AC1_DIG 0x0
|
|
EXP_CLK_2_AUXIN2_AC2_DIG 0x0
|
|
EXP_CLK_2_AUXIN2_AC3_DIG 0x0
|
|
EXP_CLK_2_AUXIN1_AC0_CL_SOL_EVCL 0x0
|
|
EXP_CLK_2_AUXIN3_AC1_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_CNTEQ0 0x1
|
|
ARM_EXP_1_SOFTWARE 0x0
|
|
ARM_EXP_1_TIMER0 0x0
|
|
ARM_EXP_1_TIMER2 0x0
|
|
ARM_EXP_1_TIMER3 0x0
|
|
ARM_EXP_1_TRG_TIMER1_AC0 0x0
|
|
ARM_EXP_1_TRG_TIMER1_AC1 0x0
|
|
ARM_EXP_1_TRG_TIMER1_AC2 0x0
|
|
ARM_EXP_1_TRG_TIMER1_AC3 0x0
|
|
ARM_EXP_1_HS_PSG 0x0
|
|
ARM_EXP_1_VS_PSG 0x0
|
|
ARM_EXP_1_TRG_2_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_3_AC01_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_2_AC01_OPTO_CL 0x0
|
|
ARM_EXP_1_TRG_3_AC01_OPTO_CL 0x0
|
|
ARM_EXP_1_TRG_0_AC0_OPTO_CL_SOL_BASE 0x0
|
|
ARM_EXP_1_TRG_1_AC0_OPTO_CL_SOL_BASE 0x0
|
|
ARM_EXP_1_TRG_0_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_1_AC0_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_0_AC0_OPTO_CL 0x0
|
|
ARM_EXP_1_TRG_1_AC0_OPTO_CL 0x0
|
|
ARM_EXP_1_TRG_0_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_1_AC1_OPTO_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_0_AC1_OPTO_CL 0x0
|
|
ARM_EXP_1_TRG_1_AC1_OPTO_CL 0x0
|
|
ARM_EXP_1_TRG_0_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_1_4AC_CON0_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_0_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_1_4AC_CON2_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_2_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_3_4AC_CON1_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_2_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_3_4AC_CON3_OPTO_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_0_AC0_TTL_CL_SOL_BASE 0x0
|
|
ARM_EXP_1_TRG_1_AC0_TTL_CL_SOL_BASE 0x0
|
|
ARM_EXP_1_TRG_0_AC0_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_1_AC0_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_0_AC0_TTL_CL 0x0
|
|
ARM_EXP_1_TRG_1_AC0_TTL_CL 0x0
|
|
ARM_EXP_1_TRG_0_AC1_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_1_AC1_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_0_AC1_TTL_CL 0x0
|
|
ARM_EXP_1_TRG_1_AC1_TTL_CL 0x0
|
|
ARM_EXP_1_TRG_2_AC01_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_3_AC01_TTL_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_2_AC01_TTL_CL 0x0
|
|
ARM_EXP_1_TRG_3_AC01_TTL_CL 0x0
|
|
ARM_EXP_1_TRG_0_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_1_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_0_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_1_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_0_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_1_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_0_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_1_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_2_4AC_CON0_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_3_4AC_CON1_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_2_4AC_CON2_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_3_4AC_CON3_TTL_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_0_AC0_LVDS_CL_SOL_BASE 0x0
|
|
ARM_EXP_1_TRG_1_AC0_LVDS_CL_SOL_BASE 0x0
|
|
ARM_EXP_1_TRG_0_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_1_AC0_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_0_AC0_LVDS_CL 0x0
|
|
ARM_EXP_1_TRG_1_AC0_LVDS_CL 0x0
|
|
ARM_EXP_1_TRG_0_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_1_AC1_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_0_AC1_LVDS_CL 0x0
|
|
ARM_EXP_1_TRG_1_AC1_LVDS_CL 0x0
|
|
ARM_EXP_1_TRG_2_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_3_AC01_LVDS_CL_SOL_EVCL 0x0
|
|
ARM_EXP_1_TRG_2_AC01_LVDS_CL 0x0
|
|
ARM_EXP_1_TRG_3_AC01_LVDS_CL 0x0
|
|
ARM_EXP_1_TRG_0_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_1_4AC_CON0_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_0_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_1_4AC_CON2_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_2_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_3_4AC_CON1_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_2_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_3_4AC_CON3_LVDS_CL_RADIENT 0x0
|
|
ARM_EXP_1_TRG_1_AC0_OPTO_ANA 0x0
|
|
ARM_EXP_1_TRG_1_AC1_OPTO_ANA 0x0
|
|
ARM_EXP_1_TRG_1_AC2_OPTO_ANA 0x0
|
|
ARM_EXP_1_TRG_1_AC3_OPTO_ANA 0x0
|
|
ARM_EXP_1_TRG_0_AC0_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_0_AC1_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_0_AC2_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_0_AC3_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA 0x0
|
|
ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA 0x0
|
|
ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA 0x0
|
|
ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA 0x0
|
|
ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA 0x0
|
|
ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA 0x0
|
|
ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA 0x0
|
|
ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA 0x0
|
|
ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA 0x0
|
|
ARM_EXP_1_TRG_0_AC0_OPTO_DIG 0x0
|
|
ARM_EXP_1_TRG_1_AC0_OPTO_DIG 0x0
|
|
ARM_EXP_1_TRG_0_AC1_OPTO_DIG 0x0
|
|
ARM_EXP_1_TRG_1_AC1_OPTO_DIG 0x0
|
|
ARM_EXP_1_TRG_0_AC2_OPTO_DIG 0x0
|
|
ARM_EXP_1_TRG_1_AC2_OPTO_DIG 0x0
|
|
ARM_EXP_1_TRG_0_AC3_OPTO_DIG 0x0
|
|
ARM_EXP_1_TRG_1_AC3_OPTO_DIG 0x0
|
|
ARM_EXP_1_TRG_1_AC0_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_1_AC1_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_1_AC2_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_1_AC3_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_0_AC0_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_0_AC1_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_0_AC2_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_0_AC3_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG 0x0
|
|
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_CL_SOL_BASE_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_CL_SOL_EVCL_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC2_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC3_LVDS_CL_RADIENT_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_FOW 0x0
|
|
ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_REV 0x0
|
|
ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER 0x0
|
|
EXP_NOCOMBINE_2 0x0
|
|
EXP_COMBINE_2_XOR_T0 0x0
|
|
EXP_COMBINE_2_XOR_T1AC1 0x0
|
|
EXP_COMBINE_2_T0 0x0
|
|
EXP_1_NOCOMBINE_AC0_CL_SOL_BASE_HD_CC 0x1
|
|
EXP_1_COMBINE_XOR_T0_AC0_CL_SOL_BASE_HD_CC 0x0
|
|
EXP_1_COMBINE_T0_AC0_CL_SOL_BASE_HD_CC 0x0
|
|
EXP_1_NOCOMBINE_AC0_CL_HD_CC 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC0_CL_HD_CC 0x0
|
|
EXP_1_COMBINE_T0_AC0_CL_HD_CC 0x0
|
|
EXP_1_NOCOMBINE_AC1_CL_HD_CC 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC1_CL_HD_CC 0x0
|
|
EXP_1_COMBINE_T0_AC1_CL_HD_CC 0x0
|
|
EXP_1_NOCOMBINE_CL_CC 0x0
|
|
EXP_1_COMBINE_XOR_T0_CL_CC 0x0
|
|
EXP_1_COMBINE_T0_CL_CC 0x0
|
|
EXP_1_NOCOMBINE_AC0_ANA_HD 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC0_ANA_HD 0x0
|
|
EXP_1_COMBINE_T0_AC0_ANA_HD 0x0
|
|
EXP_1_NOCOMBINE_AC1_ANA_HD 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC1_ANA_HD 0x0
|
|
EXP_1_COMBINE_T0_AC1_ANA_HD 0x0
|
|
EXP_1_NOCOMBINE_AC2_ANA_HD 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC2_ANA_HD 0x0
|
|
EXP_1_COMBINE_T0_AC2_ANA_HD 0x0
|
|
EXP_1_NOCOMBINE_AC3_ANA_HD 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC3_ANA_HD 0x0
|
|
EXP_1_COMBINE_T0_AC3_ANA_HD 0x0
|
|
EXP_1_NOCOMBINE_AC0_DIG_DCON 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC0_DIG_DCON 0x0
|
|
EXP_1_COMBINE_T0_AC0_DIG_DCON 0x0
|
|
EXP_1_NOCOMBINE_AC1_DIG_DCON 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC1_DIG_DCON 0x0
|
|
EXP_1_COMBINE_T0_AC1_DIG_DCON 0x0
|
|
EXP_1_NOCOMBINE_AC2_DIG_DCON 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC2_DIG_DCON 0x0
|
|
EXP_1_COMBINE_T0_AC2_DIG_DCON 0x0
|
|
EXP_1_NOCOMBINE_AC3_DIG_DCON 0x0
|
|
EXP_1_COMBINE_XOR_T0_AC3_DIG_DCON 0x0
|
|
EXP_1_COMBINE_T0_AC3_DIG_DCON 0x0
|
|
EXP_PRESCALE2_1 0x0
|
|
EXP_PRESCALE2_2 0x0
|
|
EXP_PRESCALE2_4 0x0
|
|
EXP_PRESCALE2_8 0x0
|
|
EXP_PRESCALE2_16 0x0
|
|
DEF_CAMERA_LINK_TIME_MULTIPLEX_MODES 0x0
|
|
DEF_RADIENT_CL_DUAL 0x1
|
|
DEF_RADIENT_CL_QUAD 0x0
|
|
DEF_RADIENT_CL_DUAL_FULL 0x0
|
|
DEF_RADIENT_ALL_CL 0x1
|
|
DEF_AC0_PROGRAMMED 0x1
|
|
DEF_AC1_PROGRAMMED 0x0
|
|
DEF_AC2_PROGRAMMED 0x0
|
|
DEF_AC3_PROGRAMMED 0x0
|
|
DEF_ABSOLUTE_TRIGGERS 0x0
|
|
DEF_ABSOLUTE_TRIGGER_OPTO 0x0
|
|
DEF_ABSOLUTE_TRIGGER_TTL 0x0
|
|
DEF_ABSOLUTE_TRIGGER_LVDS 0x0
|
|
DEF_AC0_CL_TRG2_TTL_ACTIF 0x0
|
|
DEF_AC1_CL_TRG3_TTL_ACTIF 0x0
|
|
DEF_TAPS_MULTIPLEX_X 0x1
|
|
DEF_TAPS_MULTIPLEX_Y 0x1
|
|
DEF_INFO_XSIZE_DIVISOR 0x1
|
|
DEF_INFO_YSIZE_DIVISOR 0x1
|
|
DEF_ADD_HACTIVE_MULTIPLEX 0x0
|
|
DEF_ADD_VACTIVE_MULTIPLEX 0x0
|
|
DEF_HTOTAL_ENTRY 0x1010
|
|
DEF_HACTIVE_ENTRY 0x1000
|
|
DEF_VTOTAL_ENTRY 0x200
|
|
DEF_VACTIVE_ENTRY 0x200
|
|
DEF_CL_NEW_HCROPPING 0x10
|
|
DEF_CL_NEW_VCROPPING 0x0
|
|
DEF_NTSC 0x0
|
|
DEF_PAL 0x0
|
|
DEF_CCIR601 0x0
|
|
DEF_MONO_CAM 0x0
|
|
DEF_COLOR_CAM 0x1
|
|
DEF_VACTIVE_ODD 0x0
|
|
DEF_VSTART_ODD 0x0
|
|
DEF_VTOTAL_ENTRY_NOTSTD 0x1
|
|
DEF_VINTRL_ODD_EVEN 0x0
|
|
DEF_VSVAL_EQUA_ZERO 0x1
|
|
DEF_VEVAL_EQUA_VTOTAL 0x1
|
|
DEF_DIGITIZER_MASTER 0x0
|
|
DEF_CASE_HVBLANK_ZERO 0x0
|
|
DEF_ADD_3MAX_TOTAL_HVBLANK_ZERO 0x0
|
|
DEF_ADD_HTOTAL_EQUA_HEVAL 0x0
|
|
DEF_HOR_COUNT_MAX_BITWISE 0xffff
|
|
DEF_VERT_COUNT_MAX_BITWISE 0xffff
|
|
DEF_DIG_HTOTAL 0x100f
|
|
DEF_DIG_VTOTAL 0x1ff
|
|
DEF_TEST_MODE_HFP_MIN 0x0
|
|
DEF_TEST_MODE_HSY_HBP_MIN_CL 0x0
|
|
DEF_TEST_MODE_VFP_MIN 0x0
|
|
DEF_TEST_MODE_VBP_MIN 0x0
|
|
DEF_TEST_MODE_VS_VBP_MIN_ANA_DIG_CL 0x0
|
|
DEF_HSVAL_EQUA_ZERO 0x0
|
|
DEF_HEVAL_EQUA_HTOTAL 0x1
|
|
DEF_HTOTAL_OVERFLOW 0x0
|
|
DEF_HACTIVE_OVERFLOW 0x0
|
|
DEF_VTOTAL_OVERFLOW 0x0
|
|
DEF_VACTIVE_OVERFLOW 0x0
|
|
DEF_VAL_SOFSEL 0x1
|
|
DEF_ANA_TANDEM_MODE 0x0
|
|
DEF_TIMER0_ENABLED 0x0
|
|
DEF_TIMER1_ENABLED 0x0
|
|
DEF_TIMER0_TRIGGERS_PIPE_DELAY 0x0
|
|
DEF_TIMER1_TRIGGERS_PIPE_DELAY 0x0
|
|
DEF_TIMER0_CLK_NOTAV 0x0
|
|
DEF_TIMER1_CLK_NOTAV 0x0
|
|
DEF_TIMER0_FREQ_NO_T1CLK 0x4c4b400
|
|
DEF_TIMER1_FREQ_NO_T0CLK 0x0
|
|
DEF_TIMER0_FREQ 0x4c4b400
|
|
DEF_TIMER1_FREQ 0x0
|
|
DEF_TIMER0_AUX_CLK_IN 0x1
|
|
DEF_TIMER1_AUX_CLK_2_IN 0x0
|
|
DEF_TIMER0_PIPE_DELAY1 0x0
|
|
DEF_TIMER1_PIPE_DELAY1 0x0
|
|
DEF_TMR0_CLKTMR1_CNT 0x0
|
|
DEF_TMR1_CLKTMR0_CNT 0x0
|
|
DEF_TIMER01_CLK_HS_FREQ 0x4c03
|
|
DEF_TIMER01_CLK_HS_PERIOD 0xc8be
|
|
DEF_TIMER0_CLK_HS_PERIOD_DLY1_CNT 0x0
|
|
DEF_TIMER0_CLK_HS_PERIOD_DLY2_CNT 0x0
|
|
DEF_TIMER0_CLK_HS_PERIOD_T1_CNT 0x0
|
|
DEF_TIMER0_CLK_HS_PERIOD_T2_CNT 0x0
|
|
DEF_VALUE_EXP_0_DELAY1 0x0
|
|
DEF_VALUE_EXP_0_DELAY2 0x0
|
|
DEF_VALUE_EXP_0_TIME1 0x0
|
|
DEF_VALUE_EXP_0_TIME2 0x0
|
|
DEF_TIMER1_CLK_HS_PERIOD_DLY1_CNT 0x0
|
|
DEF_TIMER1_CLK_HS_PERIOD_DLY2_CNT 0x0
|
|
DEF_TIMER1_CLK_HS_PERIOD_T1_CNT 0x0
|
|
DEF_TIMER1_CLK_HS_PERIOD_T2_CNT 0x0
|
|
DEF_VALUE_EXP_1_DELAY1 0x0
|
|
DEF_VALUE_EXP_1_DELAY2 0x0
|
|
DEF_VALUE_EXP_1_TIME1 0x0
|
|
DEF_VALUE_EXP_1_TIME2 0x0
|
|
DEF_PCLK_PERIOD_NS_NO_ROUND 0xc
|
|
DEF_PCLK_PERIOD_NS_ROUND 0xd
|
|
DEF_TOTAL_TIME_VALUE_EXP_0_NO_CLK_TMR1 0x0
|
|
DEF_TOTAL_TIME_VALUE_EXP_1_NO_CLK_TMR0 0x0
|
|
DEF_VALUE_EXP_0_CLK_TMR1_DELAY1 0x0
|
|
DEF_VALUE_EXP_0_CLK_TMR1_DELAY2 0x0
|
|
DEF_VALUE_EXP_0_CLK_TMR1_TIME1 0x0
|
|
DEF_VALUE_EXP_0_CLK_TMR1_TIME2 0x0
|
|
DEF_VALUE_EXP_1_CLK_TMR0_DELAY1 0x0
|
|
DEF_VALUE_EXP_1_CLK_TMR0_DELAY2 0x0
|
|
DEF_VALUE_EXP_1_CLK_TMR0_TIME1 0x0
|
|
DEF_VALUE_EXP_1_CLK_TMR0_TIME2 0x0
|
|
DEF_VALUE_EXP_0_CLK_TMR1_DELAY1_ADJUST 0x0
|
|
DEF_VALUE_EXP_0_CLK_TMR1_TIME1_ADJUST 0x0
|
|
DEF_VALUE_EXP_1_CLK_TMR0_DELAY1_ADJUST 0x0
|
|
DEF_VALUE_EXP_1_CLK_TMR0_TIME1_ADJUST 0x0
|
|
DEF_EXP_0_TIME1_VALUE_LESS_HW 0x0
|
|
DEF_TIMER0_MAX_CNT_TIM_DLY 0x147ae148
|
|
DEF_TIMER1_MAX_CNT_TIM_DLY 0x0
|
|
DEF_INFO_TIME_OVRF_EXP0 0x0
|
|
DEF_INFO_TIME_OVRF_EXP1 0x0
|
|
DEF_TIMER0_CNT_OVERFLOW 0x0
|
|
DEF_TIMER1_CNT_OVERFLOW 0x0
|
|
DEF_TIMER0_T1CLK_PERD_FREQ 0x1
|
|
DEF_TIMER1_T0CLK_PERD_FREQ 0x1
|
|
DEF_TMR0_CLKFREQ_LESS_EQU_TRGFREQ 0x0
|
|
DEF_TMR1_CLKFREQ_LESS_EQU_TRGFREQ 0x0
|
|
DEF_RADIENT_TIMER0_OUT_AV 0x1
|
|
DEF_RADIENT_TIMER1_OUT_AV 0x1
|
|
DEF_HW_CHANNEL_USED 0x1
|
|
DEF_ATTENUATOR 0x1
|
|
DEF_CODE_GAIN 0x5b7
|
|
DEF_CODE_OFFSET 0x800
|
|
DEF_CL_BUS_WIDTH 0x8
|
|
DEF_CL_NUM_TAPS 0x1
|
|
DEF_ERR_BUS_WIDTH 0x0
|
|
DEF_GRAB_PSG_CHANGE_ERROR 0x0
|
|
DEF_EXP0_PSG_CHANGE_ERROR 0x0
|
|
DEF_ARM_EXP0_PSG_CHANGE_ERROR 0x0
|
|
DEF_EXP1_PSG_CHANGE_ERROR 0x0
|
|
DEF_ARM_EXP1_PSG_CHANGE_ERROR 0x0
|
|
DEF_ERR_TIMER0_OUT_TRG1_CONFLICT 0x0
|
|
DEF_ERR_TIMER1_OUT_TRG2_CONFLICT 0x0
|
|
DEF_ERR_TIMER1_OUT_TRG3_CONFLICT 0x0
|
|
DEF_ERR_INTERNAL_TRG0_2_FORMATS_SEL 0x0
|
|
DEF_ERR_INTERNAL_TRG1_2_FORMATS_SEL 0x0
|
|
DEF_ERR_INTERNAL_TRG2_2_FORMATS_SEL 0x0
|
|
DEF_ERR_INTERNAL_TRG3_2_FORMATS_SEL 0x0
|
|
DEF_ROTARY_CL_GRB_AC01_NOT_REV 0x1
|
|
DEF_ROTARY_CL_EXP0_AC01_NOT_REV 0x1
|
|
DEF_ROTARY_CL_EXP1_AC01_NOT_REV 0x1
|
|
DEF_ROTARY_CL_AEXP0_AC01_NOT_REV 0x1
|
|
DEF_ROTARY_CL_AEXP1_AC01_NOT_REV 0x1
|
|
DEF_ROTARY_CL_GRB_AC01_NOT_FOW 0x1
|
|
DEF_ROTARY_CL_EXP0_AC01_NOT_FOW 0x1
|
|
DEF_ROTARY_CL_EXP1_AC01_NOT_FOW 0x1
|
|
DEF_ROTARY_CL_AEXP0_AC01_NOT_FOW 0x1
|
|
DEF_ROTARY_CL_AEXP1_AC01_NOT_FOW 0x1
|
|
DEF_USE_ROTARY_ALL_BOARDS_GRB 0x0
|
|
DEF_USE_ROTARY_ALL_BOARDS_EXP0 0x0
|
|
DEF_USE_ROTARY_ALL_BOARDS_EXP1 0x0
|
|
DEF_USE_ROTARY_ALL_BOARDS_AEXP0 0x0
|
|
DEF_USE_ROTARY_ALL_BOARDS_AEXP1 0x0
|
|
DEF_USE_ROTARY_CL_BOARD 0x0
|
|
DEF_DIG1_TAPDIR 0x0
|
|
DEF_DIG2_TAPDIR 0x0
|
|
DEF_DIG3_TAPDIR 0x0
|
|
DEF_DIG4_TAPDIR 0x0
|
|
DEF_DIG5_TAPDIR 0x0
|
|
DEF_DIG6_TAPDIR 0x0
|
|
DEF_DIG7_TAPDIR 0x0
|
|
DEF_DIG8_TAPDIR 0x0
|
|
DEF_DIG9_TAPDIR 0x0
|
|
DEF_DIG10_TAPDIR 0x0
|
|
DEF_DIG10_TAPORDER 0x0
|
|
DEF_DIG9_TAPORDER 0x8
|
|
DEF_DIG8_TAPORDER 0x7
|
|
DEF_DIG7_TAPORDER 0x6
|
|
DEF_DIG6_TAPORDER 0x5
|
|
DEF_DIG5_TAPORDER 0x4
|
|
DEF_DIG4_TAPORDER 0x3
|
|
DEF_DIG3_TAPORDER 0x2
|
|
DEF_DIG2_TAPORDER 0x1
|
|
DEF_DIG1_TAPORDER 0x0
|
|
DEF_TAPS_ORDER 0x76543210
|
|
DEF_TAPS_ORDER_HIGH 0x0
|
|
DEF_BYTESORDER 0x73625140
|
|
DEF_DIG8_BYTESORDER 0x3
|
|
DEF_DIG7_BYTESORDER 0x5
|
|
DEF_DIG6_BYTESORDER 0x8
|
|
DEF_DIG5_BYTESORDER 0x2
|
|
DEF_DIG4_BYTESORDER 0x3
|
|
DEF_DIG3_BYTESORDER 0x1
|
|
DEF_DIG2_BYTESORDER 0x6
|
|
DEF_DIG1_BYTESORDER 0x8
|
|
[REG_DIGIT]
|
|
INFO_CUSTOM 0x0
|
|
INFO_REGISTER_REV 0x1
|
|
INFO_XSIZE 0x1000
|
|
INFO_YSIZE 0x200
|
|
INFO_TYPE 0x1
|
|
INFO_BAYER 0x0
|
|
INFO_BURSTSIZE 0x0
|
|
INFO_CAM 0x2
|
|
INFO_GRABPATH 0x1
|
|
INFO_SSPCLKSEL 0x0
|
|
INFO_SSHREFSEL 0x0
|
|
INFO_PIXCLK 0x4c4b400
|
|
INFO_CLOCKDELAY 0x0
|
|
INFO_USRCLK 0x4c4b400
|
|
INFO_SAMPLEMODE 0x0
|
|
INFO_SIGNALTYPE 0x2
|
|
INFO_INPUTSOURCE 0x0
|
|
INFO_CHANNEL 0x1
|
|
INFO_SYNCGRABCHAN 0x1
|
|
INFO_SYNCCHANNEL 0x0
|
|
INFO_ATTENUATION 0x0
|
|
INFO_GAIN0 0x0
|
|
INFO_GAIN1 0x0
|
|
INFO_GAIN2 0x0
|
|
INFO_GAIN3 0x0
|
|
INFO_OFFSET0 0x0
|
|
INFO_OFFSET1 0x0
|
|
INFO_OFFSET2 0x0
|
|
INFO_OFFSET3 0x0
|
|
INFO_CLAMP 0x1
|
|
INFO_LUTBUFID 0x0
|
|
INFO_LUTPROG 0x0
|
|
INFO_LUTMODE 0x1
|
|
INFO_LUTPALETTE 0x0
|
|
INFO_CLMODE 0x0
|
|
INFO_TESTMODE 0x0
|
|
INFO_BITSPERCOMPONENT 0x8
|
|
INFO_NUMCOMPONENTS 0x3
|
|
INFO_COMPONENTSPERPIXEL 0x3
|
|
INFO_PACKEDCOMPONENTS 0x0
|
|
INFO_HDELAY 0x0
|
|
INFO_LINEDELAY 0x0
|
|
INFO_TIMEMULTICH 0x1
|
|
INFO_TIMEMULTIPIX 0x1
|
|
INFO_XTAPSPERCH 0x1
|
|
INFO_YTAPSPERCH 0x1
|
|
INFO_XTAPSPERCHADJ 0x1
|
|
INFO_YTAPSPERCHADJ 0x1
|
|
INFO_TAPSDIR 0x0
|
|
INFO_TAPSDIRH 0x0
|
|
INFO_TAPSORDER 0x76543210
|
|
INFO_TAPSORDERH 0x0
|
|
INFO_BYTESORDER 0x76543210
|
|
INFO_BYTESORDERH 0x0
|
|
INFO_HARDGRABTRIG 0x0
|
|
INFO_TRIGSRC 0x1
|
|
INFO_T0DELAY 0x0
|
|
INFO_T0DELAY1 0x0
|
|
INFO_T0TRIGSRC 0x0
|
|
INFO_T0CLKSRC 0x0
|
|
INFO_T0USRCLK 0x0
|
|
INFO_T0OTHERUSRCLK 0x0
|
|
INFO_T1DELAY 0x0
|
|
INFO_T1DELAY1 0x0
|
|
INFO_T1TRIGSRC 0x0
|
|
INFO_T1CLKSRC 0x0
|
|
INFO_T1USRCLK 0x0
|
|
INFO_T1OTHERUSRCLK 0x0
|
|
INFO_T2DELAY 0x0
|
|
INFO_T2DELAY1 0x0
|
|
INFO_T2TRIGSRC 0x0
|
|
INFO_T2CLKSRC 0x0
|
|
INFO_T2USRCLK 0x0
|
|
INFO_T2OTHERUSRCLK 0x0
|
|
INFO_T3DELAY 0x0
|
|
INFO_T3DELAY1 0x0
|
|
INFO_T3TRIGSRC 0x0
|
|
INFO_T3CLKSRC 0x0
|
|
INFO_T3USRCLK 0x0
|
|
INFO_T3OTHERUSRCLK 0x0
|
|
INFO_MISC 0x0
|
|
INFO_DEPTH 0x8
|
|
INFO_BAND 0x3
|
|
INFO_INPUT 0x0
|
|
INFO_MODULE_422 0x0
|
|
INFO_FORMAT 0x0
|
|
INFO_INPUT_MUX_SEL 0x0
|
|
INFO_M_CHANNEL 0x1
|
|
INFO_M_CHANNEL_SYNC 0x0
|
|
INFO_M_GRAB_INPUT_GAIN 0x1
|
|
INFO_M_INPUT_FILTER 0x0
|
|
INFO_M_GRAB_TRIGGER_ENABLE 0x0
|
|
INFO_M_GRAB_TRIGGER_MODE 0x1
|
|
INFO_M_GRAB_TRIGGER_FORMAT 0x0
|
|
INFO_M_GRAB_TRIGGER_SOURCE 0x0
|
|
INFO_M_GRAB_EXPOSURE_0_MODE 0x0
|
|
INFO_M_GRAB_EXPOSURE_0_TRIGGER_MODE 0x1
|
|
INFO_M_GRAB_EXPOSURE_0_TRIGGER_FORMAT 0x1
|
|
INFO_M_GRAB_EXPOSURE_0_TRIGGER_SOURCE 0x0
|
|
INFO_M_GRAB_EXPOSURE_0_TIME_DELAY1 0x0
|
|
INFO_M_GRAB_EXPOSURE_0_TIME_DELAY2 0x0
|
|
INFO_M_GRAB_EXPOSURE_0_TIME1 0x0
|
|
INFO_M_GRAB_EXPOSURE_0_TIME2 0x0
|
|
INFO_M_GRAB_EXPOSURE_1_MODE 0x0
|
|
INFO_M_GRAB_EXPOSURE_1_TRIGGER_MODE 0x1
|
|
INFO_M_GRAB_EXPOSURE_1_TRIGGER_FORMAT 0x1
|
|
INFO_M_GRAB_EXPOSURE_1_TRIGGER_SOURCE 0x0
|
|
INFO_M_GRAB_EXPOSURE_1_TIME_DELAY1 0x0
|
|
INFO_M_GRAB_EXPOSURE_1_TIME_DELAY2 0x0
|
|
INFO_M_GRAB_EXPOSURE_1_TIME1 0x0
|
|
INFO_M_GRAB_EXPOSURE_1_TIME2 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_MODE 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_MODE 0x1
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_FORMAT 0x1
|
|
INFO_M_GRAB_EXPOSURE_2_TIME_DELAY1 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_TIME_DELAY2 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_TIME1 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_TIME2 0x0
|
|
INFO_M_GRAB_EXPOSURE_3_MODE 0x0
|
|
INFO_M_GRAB_EXPOSURE_3_TRIGGER_MODE 0x1
|
|
INFO_M_GRAB_EXPOSURE_3_TRIGGER_FORMAT 0x1
|
|
INFO_M_GRAB_EXPOSURE_3_TIME_DELAY1 0x0
|
|
INFO_M_GRAB_EXPOSURE_3_TIME_DELAY2 0x0
|
|
INFO_M_GRAB_EXPOSURE_3_TIME1 0x0
|
|
INFO_M_GRAB_EXPOSURE_3_TIME2 0x0
|
|
INFO_MODE 0x0
|
|
INFO_SIGNALBLACKLVL 0x0
|
|
INFO_SIGNALWHITELVL 0x0
|
|
INFO_LUTINSIZE 0x0
|
|
INFO_LUTOUTSIZE 0x0
|
|
INFO_CLCONFIGMODE 0x0
|
|
INFO_PACKEDPIXELS 0x0
|
|
INFO_T0TRGSRC 0x0
|
|
INFO_T1TRGSRC 0x0
|
|
INFO_T2TRGSRC 0x0
|
|
INFO_T3TRGSRC 0x0
|
|
INFO_T1EXPMOD 0x0
|
|
INFO_T1DELAY2 0x0
|
|
INFO_T2EXPMOD 0x0
|
|
INFO_T2DELAY2 0x0
|
|
INFO_M_GRAB_EXPOSURE_0_CLOCK_SOURCE 0x0
|
|
INFO_M_GRAB_EXPOSURE_1_CLOCK_SOURCE 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_CLOCK_SOURCE 0x0
|
|
INFO_M_GRAB_EXPOSURE_3_CLOCK_SOURCE 0x0
|
|
INFO_M_GRAB_EXPOSURE_1_TIME 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_TIME 0x0
|
|
INFO_M_GRAB_EXPOSURE_1_TIME_DELAY 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_TIME_DELAY 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_SOURCE 0x0
|
|
INFO_M_GRAB_EXPOSURE_3_TRIGGER_SOURCE 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_MODE 0x0
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_FORMAT 0x0
|
|
INFO_MASK_TRGIN 0xf
|
|
INFO_MASK_USROUTDYN 0x0
|
|
INFO_MASK_USROUT0 0x0
|
|
INFO_MASK_USROUT1 0x0
|
|
INFO_MASK_USROUT2 0x0
|
|
INFO_MASK_USROUT3 0x0
|
|
INFO_MASK_IOCTLCLDYNL 0x0
|
|
INFO_MASK_IOCTLCLDYNH 0x0
|
|
INFO_MASK_IOCTLCL0L 0x0
|
|
INFO_MASK_IOCTLCL0H 0x0
|
|
INFO_MASK_IOCTLCL1L 0x0
|
|
INFO_MASK_IOCTLCL1H 0x0
|
|
INFO_MASK_IOCTLANDYN 0x0
|
|
INFO_MASK_IOCTLAN0 0x0
|
|
INFO_MASK_IOCTLAN1 0x0
|
|
INFO_MASK_IOCTLAN2 0x0
|
|
INFO_MASK_IOCTLAN3 0x0
|
|
INFO_MASK_IOCTLDIDYN 0x0
|
|
INFO_MASK_IOCTLDI0 0x0
|
|
INFO_MASK_IOCTLDI1 0x0
|
|
INFO_MASK_IOCTLDI2 0x0
|
|
INFO_MASK_IOCTLDI3 0x0
|
|
INFO_MASK_ENCTLCLDYN 0x0
|
|
INFO_MASK_ENCTLCL0 0x0
|
|
INFO_MASK_ENCTLCL1 0x0
|
|
INFO_MASK_ENCTLANDYN 0x0
|
|
INFO_MASK_ENCTLAN0 0x0
|
|
INFO_MASK_ENCTLAN1 0x0
|
|
INFO_MASK_ENCTLAN2 0x0
|
|
INFO_MASK_ENCTLAN3 0x0
|
|
INFO_MASK_ENCTLDIDYN 0x0
|
|
INFO_MASK_ENCTLDI0 0x0
|
|
INFO_MASK_ENCTLDI1 0x0
|
|
INFO_MASK_ENCTLDI2 0x0
|
|
INFO_MASK_ENCTLDI3 0x0
|
|
INFO_MASK_T0CTLL 0x0
|
|
INFO_MASK_T0CTLH 0x0
|
|
INFO_MASK_T1CTLL 0x0
|
|
INFO_MASK_T1CTLH 0x0
|
|
INFO_MASK_T2CTLL 0x0
|
|
INFO_MASK_T2CTLH 0x0
|
|
INFO_MASK_T3CTLL 0x0
|
|
INFO_MASK_T3CTLH 0x0
|
|
DIG_HCNT 0x1
|
|
DIG_HTOTAL 0x100f
|
|
DIG_HSCNT 0x0
|
|
DIG_HECNT 0x1
|
|
DIG_HSSYNC 0x0
|
|
DIG_HESYNC 0x0
|
|
DIG_HSVAL 0x10
|
|
DIG_HEVAL 0x100f
|
|
DIG_HSCLM 0x0
|
|
DIG_HECLM 0x0
|
|
DIG_HCTL 0x1e0
|
|
DIG_VCNT 0x1
|
|
DIG_VTOTAL 0x1ff
|
|
DIG_VSCNT 0x0
|
|
DIG_VECNT 0x0
|
|
DIG_VSSYNC 0x0
|
|
DIG_VESYNC 0x1
|
|
DIG_VSVAL 0x0
|
|
DIG_VEVAL 0xfffff
|
|
DIG_VSCLM 0x0
|
|
DIG_VECLM 0x0
|
|
DIG_VCTL 0x2100
|
|
DIG_T0CNT 0x0
|
|
DIG_T0SCNT 0x0
|
|
DIG_T0S0PUL 0x0
|
|
DIG_T0E0PUL 0x0
|
|
DIG_T0S1PUL 0x0
|
|
DIG_T0CTLL 0x0
|
|
DIG_T0CTLH 0x1
|
|
DIG_T1CNT 0x0
|
|
DIG_T1SCNT 0x0
|
|
DIG_T1S0PUL 0x0
|
|
DIG_T1E0PUL 0x0
|
|
DIG_T1S1PUL 0x0
|
|
DIG_T1CTLL 0x0
|
|
DIG_T1CTLH 0x1
|
|
DIG_BAYERCTL 0x0
|
|
DIG_QUADCTL 0x90001
|
|
DIG_QUADCTL_HIGH 0x0
|
|
DIG_QUADCNT 0x0
|
|
DIG_PULMCTL 0x0
|
|
DIG_PULMCTL_HIGH 0x0
|
|
DIG_CLKCTL 0x0
|
|
DIG_GRBCTL 0x5
|
|
DIG_VALCTL 0x23138950
|
|
DIG_FLDCTL 0x2
|
|
DIG_SYNCOUT 0x88
|
|
DIG_TRGIN 0x0
|
|
DIG_EXPOUT 0x0
|
|
DIG_USROUT 0x0
|
|
DIG_USROUT0 0x0
|
|
DIG_USROUT1 0x0
|
|
DIG_USROUT2 0x0
|
|
DIG_USROUT3 0x0
|
|
DIG_CLCTL 0x1c
|
|
DIG_IOCTL0L 0x0
|
|
DIG_IOCTL0H 0x0
|
|
DIG_IOCTLCL0L 0x0
|
|
DIG_IOCTLCL0H 0x0
|
|
DIG_IOCTLCL1L 0x0
|
|
DIG_IOCTLCL1H 0x0
|
|
DIG_IOCTL1 0x0
|
|
DIG_IOCTLAN0 0x0
|
|
DIG_IOCTLAN1 0x0
|
|
DIG_IOCTLAN2 0x0
|
|
DIG_IOCTLAN3 0x0
|
|
DIG_IOCTL2 0x0
|
|
DIG_IOCTLDI0 0x0
|
|
DIG_IOCTLDI1 0x0
|
|
DIG_IOCTLDI2 0x0
|
|
DIG_IOCTLDI3 0x0
|
|
DIG_ENCTL0 0x0
|
|
DIG_ENCTLCL0 0x0
|
|
DIG_ENCTLCL1 0x0
|
|
DIG_ENCTL1 0x0
|
|
DIG_ENCTLAN0 0x0
|
|
DIG_ENCTLAN1 0x0
|
|
DIG_ENCTLAN2 0x0
|
|
DIG_ENCTLAN3 0x0
|
|
DIG_ENCTL2 0x0
|
|
DIG_ENCTLDI0 0x0
|
|
DIG_ENCTLDI1 0x0
|
|
DIG_ENCTLDI2 0x0
|
|
DIG_ENCTLDI3 0x0
|
|
DIG_ANACTL 0x0
|
|
DIG_ANCTL 0x0
|
|
DIG_ANCTL0 0x0
|
|
DIG_ANCTL1 0x0
|
|
DIG_ANCTL2 0x0
|
|
DIG_ANCTL3 0x0
|
|
DIG_PLLCTL 0x0
|
|
DIG_NGHECNT 0x0
|
|
DIG_NGVECNT 0x0
|
|
DIG_NGFECNT 0x0
|
|
DIG_GRABCTRL 0x4540
|
|
DIG_GTM 0x1c002
|
|
DIG_GCTRLCHNL 0x40
|
|
DIG_DESCTL0L 0xc0c0001
|
|
DIG_DESCTL0H 0xc0c
|
|
DIG_DESCTL1L 0xc0c0001
|
|
DIG_DESCTL1H 0xc0c
|
|
DIG_DESCTL2L 0xc0c0001
|
|
DIG_DESCTL2H 0xc0c
|
|
DIG_T0CTL_L 0x0
|
|
DIG_T0CTL_H 0x0
|
|
DIG_T1CTL_L 0x0
|
|
DIG_T1CTL_H 0x0
|
|
DIG_IOCTL0_L 0x0
|
|
DIG_IOCTL0_H 0x0
|
|
DIG_IOCTL1_L 0x0
|
|
DIG_IOCTL1_H 0x0
|
|
DIG_IOCTL1L 0x0
|
|
DIG_IOCTL1H 0x0
|
|
DIG_IOCTL0_L 0x0
|
|
DIG_ENCTL 0x0
|
|
[REG_MODIF_STATE]
|
|
INFO_CUSTOM not_modified
|
|
INFO_REGISTER_REV not_modified
|
|
INFO_XSIZE not_modified
|
|
INFO_YSIZE not_modified
|
|
INFO_TYPE not_modified
|
|
INFO_BAYER not_modified
|
|
INFO_BURSTSIZE not_modified
|
|
INFO_CAM not_modified
|
|
INFO_GRABPATH not_modified
|
|
INFO_SSPCLKSEL not_modified
|
|
INFO_SSHREFSEL not_modified
|
|
INFO_PIXCLK not_modified
|
|
INFO_CLOCKDELAY not_modified
|
|
INFO_USRCLK not_modified
|
|
INFO_SAMPLEMODE not_modified
|
|
INFO_SIGNALTYPE not_modified
|
|
INFO_INPUTSOURCE not_modified
|
|
INFO_CHANNEL not_modified
|
|
INFO_SYNCGRABCHAN not_modified
|
|
INFO_SYNCCHANNEL not_modified
|
|
INFO_ATTENUATION not_modified
|
|
INFO_GAIN0 not_modified
|
|
INFO_GAIN1 not_modified
|
|
INFO_GAIN2 not_modified
|
|
INFO_GAIN3 not_modified
|
|
INFO_OFFSET0 not_modified
|
|
INFO_OFFSET1 not_modified
|
|
INFO_OFFSET2 not_modified
|
|
INFO_OFFSET3 not_modified
|
|
INFO_CLAMP not_modified
|
|
INFO_LUTBUFID not_modified
|
|
INFO_LUTPROG not_modified
|
|
INFO_LUTMODE not_modified
|
|
INFO_LUTPALETTE not_modified
|
|
INFO_CLMODE not_modified
|
|
INFO_TESTMODE not_modified
|
|
INFO_BITSPERCOMPONENT not_modified
|
|
INFO_NUMCOMPONENTS not_modified
|
|
INFO_COMPONENTSPERPIXEL not_modified
|
|
INFO_PACKEDCOMPONENTS not_modified
|
|
INFO_HDELAY not_modified
|
|
INFO_LINEDELAY not_modified
|
|
INFO_TIMEMULTICH not_modified
|
|
INFO_TIMEMULTIPIX not_modified
|
|
INFO_XTAPSPERCH not_modified
|
|
INFO_YTAPSPERCH not_modified
|
|
INFO_XTAPSPERCHADJ not_modified
|
|
INFO_YTAPSPERCHADJ not_modified
|
|
INFO_TAPSDIR not_modified
|
|
INFO_TAPSDIRH not_modified
|
|
INFO_TAPSORDER not_modified
|
|
INFO_TAPSORDERH not_modified
|
|
INFO_BYTESORDER not_modified
|
|
INFO_BYTESORDERH not_modified
|
|
INFO_HARDGRABTRIG not_modified
|
|
INFO_TRIGSRC not_modified
|
|
INFO_T0DELAY not_modified
|
|
INFO_T0DELAY1 not_modified
|
|
INFO_T0TRIGSRC not_modified
|
|
INFO_T0CLKSRC not_modified
|
|
INFO_T0USRCLK not_modified
|
|
INFO_T0OTHERUSRCLK not_modified
|
|
INFO_T1DELAY not_modified
|
|
INFO_T1DELAY1 not_modified
|
|
INFO_T1TRIGSRC not_modified
|
|
INFO_T1CLKSRC not_modified
|
|
INFO_T1USRCLK not_modified
|
|
INFO_T1OTHERUSRCLK not_modified
|
|
INFO_T2DELAY not_modified
|
|
INFO_T2DELAY1 not_modified
|
|
INFO_T2TRIGSRC not_modified
|
|
INFO_T2CLKSRC not_modified
|
|
INFO_T2USRCLK not_modified
|
|
INFO_T2OTHERUSRCLK not_modified
|
|
INFO_T3DELAY not_modified
|
|
INFO_T3DELAY1 not_modified
|
|
INFO_T3TRIGSRC not_modified
|
|
INFO_T3CLKSRC not_modified
|
|
INFO_T3USRCLK not_modified
|
|
INFO_T3OTHERUSRCLK not_modified
|
|
INFO_MISC not_modified
|
|
INFO_DEPTH not_modified
|
|
INFO_BAND not_modified
|
|
INFO_INPUT not_modified
|
|
INFO_MODULE_422 not_modified
|
|
INFO_FORMAT not_modified
|
|
INFO_INPUT_MUX_SEL not_modified
|
|
INFO_M_CHANNEL not_modified
|
|
INFO_M_CHANNEL_SYNC not_modified
|
|
INFO_M_GRAB_INPUT_GAIN not_modified
|
|
INFO_M_INPUT_FILTER not_modified
|
|
INFO_M_GRAB_TRIGGER_ENABLE not_modified
|
|
INFO_M_GRAB_TRIGGER_MODE not_modified
|
|
INFO_M_GRAB_TRIGGER_FORMAT not_modified
|
|
INFO_M_GRAB_TRIGGER_SOURCE not_modified
|
|
INFO_M_GRAB_EXPOSURE_0_MODE not_modified
|
|
INFO_M_GRAB_EXPOSURE_0_TRIGGER_MODE not_modified
|
|
INFO_M_GRAB_EXPOSURE_0_TRIGGER_FORMAT not_modified
|
|
INFO_M_GRAB_EXPOSURE_0_TRIGGER_SOURCE not_modified
|
|
INFO_M_GRAB_EXPOSURE_0_TIME_DELAY1 not_modified
|
|
INFO_M_GRAB_EXPOSURE_0_TIME_DELAY2 not_modified
|
|
INFO_M_GRAB_EXPOSURE_0_TIME1 not_modified
|
|
INFO_M_GRAB_EXPOSURE_0_TIME2 not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_MODE not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_TRIGGER_MODE not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_TRIGGER_FORMAT not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_TRIGGER_SOURCE not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_TIME_DELAY1 not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_TIME_DELAY2 not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_TIME1 not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_TIME2 not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_MODE not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_MODE not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_FORMAT not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TIME_DELAY1 not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TIME_DELAY2 not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TIME1 not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TIME2 not_modified
|
|
INFO_M_GRAB_EXPOSURE_3_MODE not_modified
|
|
INFO_M_GRAB_EXPOSURE_3_TRIGGER_MODE not_modified
|
|
INFO_M_GRAB_EXPOSURE_3_TRIGGER_FORMAT not_modified
|
|
INFO_M_GRAB_EXPOSURE_3_TIME_DELAY1 not_modified
|
|
INFO_M_GRAB_EXPOSURE_3_TIME_DELAY2 not_modified
|
|
INFO_M_GRAB_EXPOSURE_3_TIME1 not_modified
|
|
INFO_M_GRAB_EXPOSURE_3_TIME2 not_modified
|
|
INFO_MODE not_modified
|
|
INFO_SIGNALBLACKLVL not_modified
|
|
INFO_SIGNALWHITELVL not_modified
|
|
INFO_LUTINSIZE not_modified
|
|
INFO_LUTOUTSIZE not_modified
|
|
INFO_CLCONFIGMODE not_modified
|
|
INFO_PACKEDPIXELS not_modified
|
|
INFO_T0TRGSRC not_modified
|
|
INFO_T1TRGSRC not_modified
|
|
INFO_T2TRGSRC not_modified
|
|
INFO_T3TRGSRC not_modified
|
|
INFO_T1EXPMOD not_modified
|
|
INFO_T1DELAY2 not_modified
|
|
INFO_T2EXPMOD not_modified
|
|
INFO_T2DELAY2 not_modified
|
|
INFO_M_GRAB_EXPOSURE_0_CLOCK_SOURCE not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_CLOCK_SOURCE not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_CLOCK_SOURCE not_modified
|
|
INFO_M_GRAB_EXPOSURE_3_CLOCK_SOURCE not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_TIME not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TIME not_modified
|
|
INFO_M_GRAB_EXPOSURE_1_TIME_DELAY not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TIME_DELAY not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_SOURCE not_modified
|
|
INFO_M_GRAB_EXPOSURE_3_TRIGGER_SOURCE not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_MODE not_modified
|
|
INFO_M_GRAB_EXPOSURE_2_TRIGGER_FORMAT not_modified
|
|
INFO_MASK_TRGIN not_modified
|
|
INFO_MASK_USROUTDYN not_modified
|
|
INFO_MASK_USROUT0 not_modified
|
|
INFO_MASK_USROUT1 not_modified
|
|
INFO_MASK_USROUT2 not_modified
|
|
INFO_MASK_USROUT3 not_modified
|
|
INFO_MASK_IOCTLCLDYNL not_modified
|
|
INFO_MASK_IOCTLCLDYNH not_modified
|
|
INFO_MASK_IOCTLCL0L not_modified
|
|
INFO_MASK_IOCTLCL0H not_modified
|
|
INFO_MASK_IOCTLCL1L not_modified
|
|
INFO_MASK_IOCTLCL1H not_modified
|
|
INFO_MASK_IOCTLANDYN not_modified
|
|
INFO_MASK_IOCTLAN0 not_modified
|
|
INFO_MASK_IOCTLAN1 not_modified
|
|
INFO_MASK_IOCTLAN2 not_modified
|
|
INFO_MASK_IOCTLAN3 not_modified
|
|
INFO_MASK_IOCTLDIDYN not_modified
|
|
INFO_MASK_IOCTLDI0 not_modified
|
|
INFO_MASK_IOCTLDI1 not_modified
|
|
INFO_MASK_IOCTLDI2 not_modified
|
|
INFO_MASK_IOCTLDI3 not_modified
|
|
INFO_MASK_ENCTLCLDYN not_modified
|
|
INFO_MASK_ENCTLCL0 not_modified
|
|
INFO_MASK_ENCTLCL1 not_modified
|
|
INFO_MASK_ENCTLANDYN not_modified
|
|
INFO_MASK_ENCTLAN0 not_modified
|
|
INFO_MASK_ENCTLAN1 not_modified
|
|
INFO_MASK_ENCTLAN2 not_modified
|
|
INFO_MASK_ENCTLAN3 not_modified
|
|
INFO_MASK_ENCTLDIDYN not_modified
|
|
INFO_MASK_ENCTLDI0 not_modified
|
|
INFO_MASK_ENCTLDI1 not_modified
|
|
INFO_MASK_ENCTLDI2 not_modified
|
|
INFO_MASK_ENCTLDI3 not_modified
|
|
INFO_MASK_T0CTLL not_modified
|
|
INFO_MASK_T0CTLH not_modified
|
|
INFO_MASK_T1CTLL not_modified
|
|
INFO_MASK_T1CTLH not_modified
|
|
INFO_MASK_T2CTLL not_modified
|
|
INFO_MASK_T2CTLH not_modified
|
|
INFO_MASK_T3CTLL not_modified
|
|
INFO_MASK_T3CTLH not_modified
|
|
DIG_HCNT not_modified
|
|
DIG_HTOTAL not_modified
|
|
DIG_HSCNT not_modified
|
|
DIG_HECNT not_modified
|
|
DIG_HSSYNC not_modified
|
|
DIG_HESYNC not_modified
|
|
DIG_HSVAL not_modified
|
|
DIG_HEVAL not_modified
|
|
DIG_HSCLM not_modified
|
|
DIG_HECLM not_modified
|
|
DIG_HCTL not_modified
|
|
DIG_VCNT not_modified
|
|
DIG_VTOTAL not_modified
|
|
DIG_VSCNT not_modified
|
|
DIG_VECNT not_modified
|
|
DIG_VSSYNC not_modified
|
|
DIG_VESYNC not_modified
|
|
DIG_VSVAL not_modified
|
|
DIG_VEVAL not_modified
|
|
DIG_VSCLM not_modified
|
|
DIG_VECLM not_modified
|
|
DIG_VCTL not_modified
|
|
DIG_T0CNT not_modified
|
|
DIG_T0SCNT not_modified
|
|
DIG_T0S0PUL not_modified
|
|
DIG_T0E0PUL not_modified
|
|
DIG_T0S1PUL not_modified
|
|
DIG_T0CTLL not_modified
|
|
DIG_T0CTLH not_modified
|
|
DIG_T1CNT not_modified
|
|
DIG_T1SCNT not_modified
|
|
DIG_T1S0PUL not_modified
|
|
DIG_T1E0PUL not_modified
|
|
DIG_T1S1PUL not_modified
|
|
DIG_T1CTLL not_modified
|
|
DIG_T1CTLH not_modified
|
|
DIG_BAYERCTL not_modified
|
|
DIG_QUADCTL not_modified
|
|
DIG_QUADCTL_HIGH not_modified
|
|
DIG_QUADCNT not_modified
|
|
DIG_PULMCTL not_modified
|
|
DIG_PULMCTL_HIGH not_modified
|
|
DIG_CLKCTL not_modified
|
|
DIG_GRBCTL not_modified
|
|
DIG_VALCTL not_modified
|
|
DIG_FLDCTL not_modified
|
|
DIG_SYNCOUT not_modified
|
|
DIG_TRGIN not_modified
|
|
DIG_EXPOUT not_modified
|
|
DIG_USROUT not_modified
|
|
DIG_USROUT0 not_modified
|
|
DIG_USROUT1 not_modified
|
|
DIG_USROUT2 not_modified
|
|
DIG_USROUT3 not_modified
|
|
DIG_CLCTL not_modified
|
|
DIG_IOCTL0L not_modified
|
|
DIG_IOCTL0H not_modified
|
|
DIG_IOCTLCL0L not_modified
|
|
DIG_IOCTLCL0H not_modified
|
|
DIG_IOCTLCL1L not_modified
|
|
DIG_IOCTLCL1H not_modified
|
|
DIG_IOCTL1 not_modified
|
|
DIG_IOCTLAN0 not_modified
|
|
DIG_IOCTLAN1 not_modified
|
|
DIG_IOCTLAN2 not_modified
|
|
DIG_IOCTLAN3 not_modified
|
|
DIG_IOCTL2 not_modified
|
|
DIG_IOCTLDI0 not_modified
|
|
DIG_IOCTLDI1 not_modified
|
|
DIG_IOCTLDI2 not_modified
|
|
DIG_IOCTLDI3 not_modified
|
|
DIG_ENCTL0 not_modified
|
|
DIG_ENCTLCL0 not_modified
|
|
DIG_ENCTLCL1 not_modified
|
|
DIG_ENCTL1 not_modified
|
|
DIG_ENCTLAN0 not_modified
|
|
DIG_ENCTLAN1 not_modified
|
|
DIG_ENCTLAN2 not_modified
|
|
DIG_ENCTLAN3 not_modified
|
|
DIG_ENCTL2 not_modified
|
|
DIG_ENCTLDI0 not_modified
|
|
DIG_ENCTLDI1 not_modified
|
|
DIG_ENCTLDI2 not_modified
|
|
DIG_ENCTLDI3 not_modified
|
|
DIG_ANACTL not_modified
|
|
DIG_ANCTL not_modified
|
|
DIG_ANCTL0 not_modified
|
|
DIG_ANCTL1 not_modified
|
|
DIG_ANCTL2 not_modified
|
|
DIG_ANCTL3 not_modified
|
|
DIG_PLLCTL not_modified
|
|
DIG_NGHECNT not_modified
|
|
DIG_NGVECNT not_modified
|
|
DIG_NGFECNT not_modified
|
|
DIG_GRABCTRL not_modified
|
|
DIG_GTM not_modified
|
|
DIG_GCTRLCHNL not_modified
|
|
DIG_DESCTL0L not_modified
|
|
DIG_DESCTL0H not_modified
|
|
DIG_DESCTL1L not_modified
|
|
DIG_DESCTL1H not_modified
|
|
DIG_DESCTL2L not_modified
|
|
DIG_DESCTL2H not_modified
|
|
DIG_T0CTL_L not_modified
|
|
DIG_T0CTL_H not_modified
|
|
DIG_T1CTL_L not_modified
|
|
DIG_T1CTL_H not_modified
|
|
DIG_IOCTL0_L not_modified
|
|
DIG_IOCTL0_H not_modified
|
|
DIG_IOCTL1_L not_modified
|
|
DIG_IOCTL1_H not_modified
|
|
DIG_IOCTL1L not_modified
|
|
DIG_IOCTL1H not_modified
|
|
DIG_IOCTL0_L not_modified
|
|
DIG_ENCTL not_modified
|
|
[EOF]
|
|
00007FF7D438AAA8 0x400c8
|
|
00007FF7D438AA90 0x3942cb8e |