mirror of
https://github.com/NanjingForestryUniversity/valveboard.git
synced 2025-11-09 06:44:07 +00:00
58 lines
3.0 KiB
Plaintext
58 lines
3.0 KiB
Plaintext
# Reading pref.tcl
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# do PF1_run_msim_rtl_verilog.do
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# if {[file exists rtl_work]} {
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# vdel -lib rtl_work -all
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# }
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# vlib rtl_work
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# vmap work rtl_work
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# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
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# vmap work rtl_work
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# Copying C:/ProgramData/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
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# Modifying modelsim.ini
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#
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# vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/PF1.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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# Start time: 12:49:27 on Nov 09,2021
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/miaow/Desktop/valve_board_kun" C:/Users/miaow/Desktop/valve_board_kun/PF1.v
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# -- Compiling module PF1
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#
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# Top level modules:
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# PF1
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# End time: 12:49:28 on Nov 09,2021, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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#
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# vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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# Start time: 12:49:28 on Nov 09,2021
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/miaow/Desktop/valve_board_kun" C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v
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# -- Compiling module tb_PF1
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#
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# Top level modules:
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# tb_PF1
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# End time: 12:49:28 on Nov 09,2021, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc" tb_PF1
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# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs=""+acc"" tb_PF1
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# Start time: 12:49:28 on Nov 09,2021
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# Loading work.tb_PF1
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# Loading work.PF1
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# ** Warning: (vsim-3015) [PCDPC] - Port size (48) does not match connection size (49) for port 'signal_high_voltage'. The port definition is at: C:/Users/miaow/Desktop/valve_board_kun/PF1.v(13).
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# Time: 0 ps Iteration: 0 Instance: /tb_PF1/inst_PF1 File: C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v Line: 12
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# ** Warning: (vsim-3015) [PCDPC] - Port size (48) does not match connection size (49) for port 'signal_low_voltage'. The port definition is at: C:/Users/miaow/Desktop/valve_board_kun/PF1.v(14).
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# Time: 0 ps Iteration: 0 Instance: /tb_PF1/inst_PF1 File: C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v Line: 12
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#
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# add wave *
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# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
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# File in use by: miaow Hostname: DESKTOP-RVHBS6P ProcessID: 1008
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# Attempting to use alternate WLF file "./wlftyh13a8".
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# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
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# Using alternate file: ./wlftyh13a8
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# view structure
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# .main_pane.structure.interior.cs.body.struct
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# view signals
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# .main_pane.objects.interior.cs.body.tree
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# run 5 ms
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# End time: 12:49:48 on Nov 09,2021, Elapsed time: 0:00:20
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# Errors: 0, Warnings: 4
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