valveboard/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak4
2021-11-22 00:34:34 +08:00

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if ![file isdirectory verilog_libs] {
file mkdir verilog_libs
}
vlib verilog_libs/altera_ver
vmap altera_ver ./verilog_libs/altera_ver
vlog -vlog01compat -work altera_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_primitives.v}
vlib verilog_libs/lpm_ver
vmap lpm_ver ./verilog_libs/lpm_ver
vlog -vlog01compat -work lpm_ver {d:/altera/11.0/quartus/eda/sim_lib/220model.v}
vlib verilog_libs/sgate_ver
vmap sgate_ver ./verilog_libs/sgate_ver
vlog -vlog01compat -work sgate_ver {d:/altera/11.0/quartus/eda/sim_lib/sgate.v}
vlib verilog_libs/altera_mf_ver
vmap altera_mf_ver ./verilog_libs/altera_mf_ver
vlog -vlog01compat -work altera_mf_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_mf.v}
vlib verilog_libs/altera_lnsim_ver
vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver
vlog -sv -work altera_lnsim_ver {d:/altera/11.0/quartus/eda/sim_lib/altera_lnsim.sv}
vlib verilog_libs/maxii_ver
vmap maxii_ver ./verilog_libs/maxii_ver
vlog -vlog01compat -work maxii_ver {d:/altera/11.0/quartus/eda/sim_lib/maxii_atoms.v}
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vlog -vlog01compat -work work +incdir+C:/Users/3304/Desktop/codes/codes\ from\ HY/PF_old\ bottom/PF_DS0401/PF_DS {C:/Users/3304/Desktop/codes/codes from HY/PF_old bottom/PF_DS0401/PF_DS/PF1.v}