mirror of
https://github.com/NanjingForestryUniversity/valveboard.git
synced 2025-11-09 06:44:07 +00:00
71 lines
2.9 KiB
Plaintext
71 lines
2.9 KiB
Plaintext
// Copyright (C) 1991-2011 Altera Corporation
|
|
// Your use of Altera Corporation's design tools, logic functions
|
|
// and other software and tools, and its AMPP partner logic
|
|
// functions, and any output files from any of the foregoing
|
|
// (including device programming or simulation files), and any
|
|
// associated documentation or information are expressly subject
|
|
// to the terms and conditions of the Altera Program License
|
|
// Subscription Agreement, Altera MegaCore Function License
|
|
// Agreement, or other applicable license agreement, including,
|
|
// without limitation, that your use is for the sole purpose of
|
|
// programming logic devices manufactured by Altera and sold by
|
|
// Altera or its authorized distributors. Please refer to the
|
|
// applicable agreement for further details.
|
|
|
|
// *****************************************************************************
|
|
// This file contains a Verilog test bench template that is freely editable to
|
|
// suit user's needs .Comments are provided in each section to help the user
|
|
// fill out necessary details.
|
|
// *****************************************************************************
|
|
// Generated on "12/11/2013 17:08:40"
|
|
|
|
// Verilog Test Bench template for design : PF1
|
|
//
|
|
// Simulation tool : ModelSim-Altera (Verilog)
|
|
//
|
|
|
|
`timescale 1 ns/ 1 ps
|
|
module PF1_vlg_tst();
|
|
// constants
|
|
// general purpose registers
|
|
reg eachvec;
|
|
// test vector input registers
|
|
reg SCLK;
|
|
reg SDATA;
|
|
reg SEN;
|
|
reg clk;
|
|
reg rst_n;
|
|
// wires
|
|
wire [47:0] S_PF;
|
|
|
|
// assign statements (if any)
|
|
PF1 i1 (
|
|
// port map - connection between master ports and signals/registers
|
|
.SCLK(SCLK),
|
|
.SDATA(SDATA),
|
|
.SEN(SEN),
|
|
.S_PF(S_PF),
|
|
.clk(clk),
|
|
.rst_n(rst_n)
|
|
);
|
|
initial
|
|
begin
|
|
// code that executes only once
|
|
// insert code here --> begin
|
|
|
|
// --> end
|
|
$display("Running testbench");
|
|
end
|
|
always
|
|
// optional sensitivity list
|
|
// @(event1 or event2 or .... eventn)
|
|
begin
|
|
// code executes for every event on sensitivity list
|
|
// insert code here --> begin
|
|
|
|
@eachvec;
|
|
// --> end
|
|
end
|
|
endmodule
|
|
|