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113 lines
2.4 KiB
Plaintext
113 lines
2.4 KiB
Plaintext
// Copyright (C) 1991-2011 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// *****************************************************************************
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// This file contains a Verilog test bench template that is freely editable to
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// suit user's needs .Comments are provided in each section to help the user
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// fill out necessary details.
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// *****************************************************************************
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// Generated on "12/11/2013 17:08:40"
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// Verilog Test Bench template for design : PF1
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//
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// Simulation tool : ModelSim-Altera (Verilog)
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//
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`timescale 1 ns/ 1 ns
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module PF1_vlg_tst();
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// constants
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// general purpose registers
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reg eachvec;
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// test vector input registers
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reg SCLK;
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reg SDATA;
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reg SEN;
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reg clk;
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reg rst_n;
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// wires
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wire [47:0] S_PF;
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parameter PERIOD=20;//ʱÖÓÖÜÆÚ£¬µ¥Î»NS
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// assign statements (if any)
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PF1 i1 (
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// port map - connection between master ports and signals/registers
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.SCLK(SCLK),
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.SDATA(SDATA),
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.SEN(SEN),
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.S_PF(S_PF),
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.clk(clk),
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.rst_n(rst_n)
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);
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initial begin
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clk=0;
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forever
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#(PERIOD/2)clk = ~clk;
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end
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initial begin
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SCLK=1;
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end
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initial begin
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rst_n=1;
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end
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initial begin
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SEN=1;
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end
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initial begin
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SDATA=0;
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#20
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SDATA=0;
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#20
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SDATA=0;
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#20
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SDATA=0;
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#20
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SDATA=0;
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#20
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SDATA=0;
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#20
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SDATA=0;
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#20
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SDATA=0;
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#20
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SDATA=0;
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#1000 $stop;
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end
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endmodule
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