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12 lines
4.8 KiB
Plaintext
12 lines
4.8 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:50:47 2011 " "Info: Processing started: Mon Dec 26 14:50:47 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
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{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "PF1 PF1.v(7) " "Warning (10238): Verilog Module Declaration warning at PF1.v(7): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"PF1\"" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 7 0 0 } } } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0 "" 0 -1}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PF1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file PF1.v" { { "Info" "ISGN_ENTITY_NAME" "1 PF1 " "Info: Found entity 1: PF1" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
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{ "Info" "ISGN_START_ELABORATION_TOP" "PF1 " "Info: Elaborating entity \"PF1\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "o_rising_edge PF1.v(32) " "Warning (10036): Verilog HDL or VHDL warning at PF1.v(32): object \"o_rising_edge\" assigned a value but never read" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 32 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
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{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "i\[6\] " "Info: Register \"i\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
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{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_n " "Warning (15610): No output dependent on input pin \"rst_n\"" { } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 10 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Info: Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "48 " "Info: Implemented 48 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "188 " "Info: Implemented 188 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Peak virtual memory: 171 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:50:50 2011 " "Info: Processing ended: Mon Dec 26 14:50:50 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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