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112 lines
11 KiB
Plaintext
112 lines
11 KiB
Plaintext
Design Assistant report for PF1
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Thu Nov 04 10:40:09 2021
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Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Design Assistant Summary
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3. Design Assistant Settings
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4. Design Assistant Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+-------------------------------------------------------------------------+
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; Design Assistant Summary ;
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+-----------------------------------+-------------------------------------+
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; Design Assistant Status ; Analyzed - Thu Nov 04 10:40:09 2021 ;
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; Revision Name ; PF1 ;
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; Top-level Entity Name ; PF1 ;
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; Family ; MAX II ;
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; Total Critical Violations ; 0 ;
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; Total High Violations ; 0 ;
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; Total Medium Violations ; 0 ;
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; Total Information only Violations ; 0 ;
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+-----------------------------------+-------------------------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Design Assistant Settings ;
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
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; Option ; Setting ; To ;
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
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; Design Assistant mode ; Post-Fitting ; ;
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; Threshold value for clock net not mapped to clock spines rule ; 25 ; ;
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; Minimum number of clock port feed by gated clocks ; 30 ; ;
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; Minimum number of node fan-out ; 30 ; ;
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; Maximum number of nodes to report ; 50 ; ;
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; Rule C101: Gated clock should be implemented according to the Intel FPGA standard scheme ; On ; ;
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; Rule C102: Logic cell should not be used to generate an inverted clock signal ; On ; ;
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; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power ; On ; ;
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; Rule C104: Clock signal source should drive only clock input ports ; On ; ;
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; Rule C105: Clock signal should be a global signal ; On ; ;
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; Rule C106: Clock signal source should not drive registers triggered by different clock edges ; On ; ;
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; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ;
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; Rule R102: External reset signals should be synchronized using two cascaded registers ; On ; ;
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; Rule R103: External reset signal should be correctly synchronized ; On ; ;
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; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized ; On ; ;
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; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized ; On ; ;
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; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ;
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; Rule T102: Top nodes with the highest number of fan-outs ; On ; ;
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; Rule A101: Design should not contain combinational loops ; On ; ;
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; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ;
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; Rule A103: Design should not contain delay chains ; On ; ;
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; Rule A104: Design should not contain ripple clock structures ; On ; ;
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; Rule A105: Pulses should not be implemented asynchronously ; On ; ;
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; Rule A106: Multiple pulses should not be generated in design ; On ; ;
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; Rule A107: Design should not contain SR latches ; On ; ;
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; Rule A108: Design should not contain latches ; On ; ;
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; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ;
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; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ;
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; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source ; On ; ;
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; Rule S104: Clock port and any other port of a register should not be driven by the same signal source ; On ; ;
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; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ;
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; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ;
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; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ;
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
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+---------------------------+
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; Design Assistant Messages ;
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+---------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Design Assistant
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Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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Info: Processing started: Thu Nov 04 10:40:08 2021
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Info: Command: quartus_drc PF1 -c PF1
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Critical Warning (332012): Synopsys Design Constraints File file not found: 'PF1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Info (332144): No user constrained base clocks found in the design
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Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
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Warning (332068): No clocks defined in design.
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Info (308007): Design Assistant information: finished post-fitting analysis of current design -- generated 0 information messages and 0 warning messages
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Info: Quartus Prime Design Assistant was successful. 0 errors, 3 warnings
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Info: Peak virtual memory: 4625 megabytes
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Info: Processing ended: Thu Nov 04 10:40:09 2021
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:00
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