mirror of
https://github.com/NanjingForestryUniversity/valveboard.git
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58 lines
1.0 KiB
Verilog
58 lines
1.0 KiB
Verilog
`timescale 1ns / 100ps
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module tb_PF1();
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reg sys_clk;
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reg rst_n;
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reg line_sclk;
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reg line_sen;
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reg line_sdata;
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wire [48:0] signal_high_voltage;
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wire [48:0] signal_low_voltage;
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PF1 inst_PF1(
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.sys_clk (sys_clk),
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.rst_n (rst_n),
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.line_sclk (line_sclk),
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.line_sen (line_sen),
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.line_sdata (line_sdata),
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.signal_high_voltage (signal_high_voltage),
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.signal_low_voltage (signal_low_voltage)
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);
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initial begin
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sys_clk = 0;
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rst_n = 0;
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line_sclk = 0;
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line_sen = 0;
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line_sdata = 1;
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#500;
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rst_n = 1;
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#500;
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end
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integer idx;
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reg [47:0] valve_data;
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always #1000000 begin
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valve_data <= ~48'b1000_0000_0000_0000_0000_0000_0000_0001_0000_0000_0000_1001;
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line_sen = 1;#100;
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for (idx = 0; idx < 48; idx = idx + 1) begin
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if (valve_data[idx] == 0) begin
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line_sdata = 0;#250;
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line_sclk = 1;#250;
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line_sdata = 1;#250;
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line_sclk = 0;#500;
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end
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else begin
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line_sclk = 1;#500;
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line_sclk = 0;#500;
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end
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end
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#100;
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line_sen = 0;
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end
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always #25 sys_clk = ~sys_clk;
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endmodule |