valveboard/firmware/simulation/modelsim/PF1_run_msim_rtl_verilog.do.bak3
2021-11-22 00:34:34 +08:00

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if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vlog -vlog01compat -work work +incdir+D:/quartusworkplace/PF_DS0401/PF_DS {D:/quartusworkplace/PF_DS0401/PF_DS/PF1.v}