Flow report for PF1 Thu Nov 11 17:04:11 2021 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Flow Summary 3. Flow Settings 4. Flow Non-Default Global Settings 5. Flow Elapsed Time 6. Flow OS Summary 7. Flow Log 8. Flow Messages 9. Flow Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2020 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details, at https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ ; Flow Status ; Successful - Thu Nov 11 17:04:11 2021 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; PF1 ; ; Top-level Entity Name ; PF1 ; ; Family ; MAX II ; ; Device ; EPM1270T144C5 ; ; Timing Models ; Final ; ; Total logic elements ; 460 / 1,270 ( 36 % ) ; ; Total pins ; 101 / 116 ( 87 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; +-----------------------+---------------------------------------------+ +-----------------------------------------+ ; Flow Settings ; +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ ; Start date & time ; 11/11/2021 17:03:53 ; ; Main task ; Compilation ; ; Revision Name ; PF1 ; +-------------------+---------------------+ +--------------------------------------------------------------------------------------------------------------------+ ; Flow Non-Default Global Settings ; +---------------------------------------+-----------------------------+---------------+-------------+----------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+-----------------------------+---------------+-------------+----------------+ ; COMPILER_SIGNATURE_ID ; 52234233346.163662143303348 ; -- ; -- ; -- ; ; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; tb_PF1 ; ; EDA_DESIGN_INSTANCE_NAME ; i1 ; -- ; -- ; -- ; ; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; tb_PF1 ; -- ; -- ; eda_simulation ; ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; ; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; ; EDA_TEST_BENCH_FILE ; tb_PF1.v ; -- ; -- ; tb_PF1 ; ; EDA_TEST_BENCH_FILE ; simulation/modelsim/PF1.vt ; -- ; -- ; -- ; ; EDA_TEST_BENCH_MODULE_NAME ; tb_PF1 ; -- ; -- ; tb_PF1 ; ; EDA_TEST_BENCH_MODULE_NAME ; PF1_vlg_tst ; -- ; -- ; -- ; ; EDA_TEST_BENCH_NAME ; PF1 ; -- ; -- ; eda_simulation ; ; EDA_TEST_BENCH_NAME ; tb_PF1 ; -- ; -- ; eda_simulation ; ; EDA_TEST_BENCH_RUN_SIM_FOR ; 5 ms ; -- ; -- ; tb_PF1 ; ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; ; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; ; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; +---------------------------------------+-----------------------------+---------------+-------------+----------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Flow Elapsed Time ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 4712 MB ; 00:00:17 ; ; Fitter ; 00:00:04 ; 1.1 ; 5906 MB ; 00:00:06 ; ; Assembler ; 00:00:01 ; 1.0 ; 4667 MB ; 00:00:00 ; ; Timing Analyzer ; 00:00:01 ; 1.0 ; 4687 MB ; 00:00:01 ; ; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4628 MB ; 00:00:01 ; ; Total ; 00:00:14 ; -- ; -- ; 00:00:25 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ +------------------------------------------------------------------------------------+ ; Flow OS Summary ; +----------------------+------------------+------------+------------+----------------+ ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +----------------------+------------------+------------+------------+----------------+ ; Analysis & Synthesis ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; ; Fitter ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; ; Assembler ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; ; Timing Analyzer ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; ; EDA Netlist Writer ; DESKTOP-RVHBS6P ; Windows 10 ; 10.0 ; x86_64 ; +----------------------+------------------+------------+------------+----------------+ ------------ ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off PF1 -c PF1 quartus_fit --read_settings_files=off --write_settings_files=off PF1 -c PF1 quartus_asm --read_settings_files=off --write_settings_files=off PF1 -c PF1 quartus_sta PF1 -c PF1 quartus_eda --read_settings_files=off --write_settings_files=off PF1 -c PF1