{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 26 14:51:01 2011 " "Info: Processing started: Mon Dec 26 14:51:01 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off PF1 -c PF1 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PF1 -c PF1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} { "Info" "ITAN_NODE_MAP_TO_CLK" "SCLK " "Info: Assuming node \"SCLK\" is an undefined clock" {  } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "SCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[17\] register S_PFr2\[41\] 95.93 MHz 10.424 ns Internal " "Info: Clock \"clk\" has Internal fmax of 95.93 MHz between source register \"cnt\[17\]\" and destination register \"S_PFr2\[41\]\" (period= 10.424 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.715 ns + Longest register register " "Info: + Longest register to register delay is 9.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[17\] 1 REG LC_X5_Y3_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N9; Fanout = 5; REG Node = 'cnt\[17\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[17] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.167 ns) + CELL(0.200 ns) 3.367 ns LessThan0~0 2 COMB LC_X5_Y4_N2 1 " "Info: 2: + IC(3.167 ns) + CELL(0.200 ns) = 3.367 ns; Loc. = LC_X5_Y4_N2; Fanout = 1; COMB Node = 'LessThan0~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.367 ns" { cnt[17] LessThan0~0 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.741 ns) + CELL(0.740 ns) 4.848 ns LessThan0~4 3 COMB LC_X5_Y4_N6 1 " "Info: 3: + IC(0.741 ns) + CELL(0.740 ns) = 4.848 ns; Loc. = LC_X5_Y4_N6; Fanout = 1; COMB Node = 'LessThan0~4'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.481 ns" { LessThan0~0 LessThan0~4 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.353 ns cnt\[20\]~44 4 COMB LC_X5_Y4_N7 72 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.353 ns; Loc. = LC_X5_Y4_N7; Fanout = 72; COMB Node = 'cnt\[20\]~44'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan0~4 cnt[20]~44 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.771 ns) + CELL(0.591 ns) 9.715 ns S_PFr2\[41\] 5 REG LC_X3_Y1_N5 2 " "Info: 5: + IC(3.771 ns) + CELL(0.591 ns) = 9.715 ns; Loc. = LC_X3_Y1_N5; Fanout = 2; REG Node = 'S_PFr2\[41\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.362 ns" { cnt[20]~44 S_PFr2[41] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.731 ns ( 17.82 % ) " "Info: Total cell delay = 1.731 ns ( 17.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.984 ns ( 82.18 % ) " "Info: Total interconnect delay = 7.984 ns ( 82.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.715 ns" { cnt[17] LessThan0~0 LessThan0~4 cnt[20]~44 S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.715 ns" { cnt[17] {} LessThan0~0 {} LessThan0~4 {} cnt[20]~44 {} S_PFr2[41] {} } { 0.000ns 3.167ns 0.741ns 0.305ns 3.771ns } { 0.000ns 0.200ns 0.740ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns S_PFr2\[41\] 2 REG LC_X3_Y1_N5 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y1_N5; Fanout = 2; REG Node = 'S_PFr2\[41\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk S_PFr2[41] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[41] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt\[17\] 2 REG LC_X5_Y3_N9 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N9; Fanout = 5; REG Node = 'cnt\[17\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt[17] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[17] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} cnt[17] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[41] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[17] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} cnt[17] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.715 ns" { cnt[17] LessThan0~0 LessThan0~4 cnt[20]~44 S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.715 ns" { cnt[17] {} LessThan0~0 {} LessThan0~4 {} cnt[20]~44 {} S_PFr2[41] {} } { 0.000ns 3.167ns 0.741ns 0.305ns 3.771ns } { 0.000ns 0.200ns 0.740ns 0.200ns 0.591ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[41] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[41] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[17] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} cnt[17] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SCLK register i\[4\] register S_PFr\[44\] 126.07 MHz 7.932 ns Internal " "Info: Clock \"SCLK\" has Internal fmax of 126.07 MHz between source register \"i\[4\]\" and destination register \"S_PFr\[44\]\" (period= 7.932 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.223 ns + Longest register register " "Info: + Longest register to register delay is 7.223 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i\[4\] 1 REG LC_X3_Y2_N5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'i\[4\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { i[4] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.511 ns) 1.529 ns Decoder0~1 2 COMB LC_X3_Y2_N9 7 " "Info: 2: + IC(1.018 ns) + CELL(0.511 ns) = 1.529 ns; Loc. = LC_X3_Y2_N9; Fanout = 7; COMB Node = 'Decoder0~1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.529 ns" { i[4] Decoder0~1 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.334 ns) + CELL(0.200 ns) 4.063 ns Decoder0~23 3 COMB LC_X6_Y1_N2 4 " "Info: 3: + IC(2.334 ns) + CELL(0.200 ns) = 4.063 ns; Loc. = LC_X6_Y1_N2; Fanout = 4; COMB Node = 'Decoder0~23'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.534 ns" { Decoder0~1 Decoder0~23 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.569 ns) + CELL(0.591 ns) 7.223 ns S_PFr\[44\] 4 REG LC_X4_Y2_N7 2 " "Info: 4: + IC(2.569 ns) + CELL(0.591 ns) = 7.223 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr\[44\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.160 ns" { Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.302 ns ( 18.03 % ) " "Info: Total cell delay = 1.302 ns ( 18.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.921 ns ( 81.97 % ) " "Info: Total interconnect delay = 5.921 ns ( 81.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.223 ns" { i[4] Decoder0~1 Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.223 ns" { i[4] {} Decoder0~1 {} Decoder0~23 {} S_PFr[44] {} } { 0.000ns 1.018ns 2.334ns 2.569ns } { 0.000ns 0.511ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SCLK destination 6.206 ns + Shortest register " "Info: + Shortest clock path from clock \"SCLK\" to destination register is 6.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SCLK 1 CLK PIN_41 54 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.156 ns) + CELL(0.918 ns) 6.206 ns S_PFr\[44\] 2 REG LC_X4_Y2_N7 2 " "Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr\[44\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.074 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 33.03 % ) " "Info: Total cell delay = 2.050 ns ( 33.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.156 ns ( 66.97 % ) " "Info: Total interconnect delay = 4.156 ns ( 66.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SCLK source 6.206 ns - Longest register " "Info: - Longest clock path from clock \"SCLK\" to source register is 6.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SCLK 1 CLK PIN_41 54 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.156 ns) + CELL(0.918 ns) 6.206 ns i\[4\] 2 REG LC_X3_Y2_N5 8 " "Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'i\[4\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.074 ns" { SCLK i[4] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 33.03 % ) " "Info: Total cell delay = 2.050 ns ( 33.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.156 ns ( 66.97 % ) " "Info: Total interconnect delay = 4.156 ns ( 66.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[4] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[4] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.223 ns" { i[4] Decoder0~1 Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.223 ns" { i[4] {} Decoder0~1 {} Decoder0~23 {} S_PFr[44] {} } { 0.000ns 1.018ns 2.334ns 2.569ns } { 0.000ns 0.511ns 0.200ns 0.591ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[4] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[4] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "S_PFr\[44\] SEN SCLK 3.893 ns register " "Info: tsu for register \"S_PFr\[44\]\" (data pin = \"SEN\", clock pin = \"SCLK\") is 3.893 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.766 ns + Longest pin register " "Info: + Longest pin to register delay is 9.766 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SEN 1 PIN PIN_40 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 8; PIN Node = 'SEN'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEN } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.740 ns) + CELL(0.200 ns) 4.072 ns Decoder0~1 2 COMB LC_X3_Y2_N9 7 " "Info: 2: + IC(2.740 ns) + CELL(0.200 ns) = 4.072 ns; Loc. = LC_X3_Y2_N9; Fanout = 7; COMB Node = 'Decoder0~1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.940 ns" { SEN Decoder0~1 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.334 ns) + CELL(0.200 ns) 6.606 ns Decoder0~23 3 COMB LC_X6_Y1_N2 4 " "Info: 3: + IC(2.334 ns) + CELL(0.200 ns) = 6.606 ns; Loc. = LC_X6_Y1_N2; Fanout = 4; COMB Node = 'Decoder0~23'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.534 ns" { Decoder0~1 Decoder0~23 } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.569 ns) + CELL(0.591 ns) 9.766 ns S_PFr\[44\] 4 REG LC_X4_Y2_N7 2 " "Info: 4: + IC(2.569 ns) + CELL(0.591 ns) = 9.766 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr\[44\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.160 ns" { Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.123 ns ( 21.74 % ) " "Info: Total cell delay = 2.123 ns ( 21.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.643 ns ( 78.26 % ) " "Info: Total interconnect delay = 7.643 ns ( 78.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.766 ns" { SEN Decoder0~1 Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.766 ns" { SEN {} SEN~combout {} Decoder0~1 {} Decoder0~23 {} S_PFr[44] {} } { 0.000ns 0.000ns 2.740ns 2.334ns 2.569ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SCLK destination 6.206 ns - Shortest register " "Info: - Shortest clock path from clock \"SCLK\" to destination register is 6.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SCLK 1 CLK PIN_41 54 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.156 ns) + CELL(0.918 ns) 6.206 ns S_PFr\[44\] 2 REG LC_X4_Y2_N7 2 " "Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X4_Y2_N7; Fanout = 2; REG Node = 'S_PFr\[44\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.074 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 33.03 % ) " "Info: Total cell delay = 2.050 ns ( 33.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.156 ns ( 66.97 % ) " "Info: Total interconnect delay = 4.156 ns ( 66.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "9.766 ns" { SEN Decoder0~1 Decoder0~23 S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "9.766 ns" { SEN {} SEN~combout {} Decoder0~1 {} Decoder0~23 {} S_PFr[44] {} } { 0.000ns 0.000ns 2.740ns 2.334ns 2.569ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.591ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK S_PFr[44] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} S_PFr[44] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk S_PF\[5\] S_PFr2\[5\] 8.833 ns register " "Info: tco from clock \"clk\" to destination pin \"S_PF\[5\]\" through register \"S_PFr2\[5\]\" is 8.833 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 76; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns S_PFr2\[5\] 2 REG LC_X6_Y2_N1 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; REG Node = 'S_PFr2\[5\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk S_PFr2[5] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[5] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.109 ns + Longest register pin " "Info: + Longest register to pin delay is 5.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns S_PFr2\[5\] 1 REG LC_X6_Y2_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; REG Node = 'S_PFr2\[5\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { S_PFr2[5] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.787 ns) + CELL(2.322 ns) 5.109 ns S_PF\[5\] 2 PIN PIN_5 0 " "Info: 2: + IC(2.787 ns) + CELL(2.322 ns) = 5.109 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'S_PF\[5\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.109 ns" { S_PFr2[5] S_PF[5] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 45.45 % ) " "Info: Total cell delay = 2.322 ns ( 45.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.787 ns ( 54.55 % ) " "Info: Total interconnect delay = 2.787 ns ( 54.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.109 ns" { S_PFr2[5] S_PF[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.109 ns" { S_PFr2[5] {} S_PF[5] {} } { 0.000ns 2.787ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk S_PFr2[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} S_PFr2[5] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.109 ns" { S_PFr2[5] S_PF[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.109 ns" { S_PFr2[5] {} S_PF[5] {} } { 0.000ns 2.787ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "i\[2\] SEN SCLK 0.072 ns register " "Info: th for register \"i\[2\]\" (data pin = \"SEN\", clock pin = \"SCLK\") is 0.072 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SCLK destination 6.206 ns + Longest register " "Info: + Longest clock path from clock \"SCLK\" to destination register is 6.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SCLK 1 CLK PIN_41 54 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 54; CLK Node = 'SCLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SCLK } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.156 ns) + CELL(0.918 ns) 6.206 ns i\[2\] 2 REG LC_X3_Y2_N3 13 " "Info: 2: + IC(4.156 ns) + CELL(0.918 ns) = 6.206 ns; Loc. = LC_X3_Y2_N3; Fanout = 13; REG Node = 'i\[2\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.074 ns" { SCLK i[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 33.03 % ) " "Info: Total cell delay = 2.050 ns ( 33.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.156 ns ( 66.97 % ) " "Info: Total interconnect delay = 4.156 ns ( 66.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[2] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[2] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.355 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SEN 1 PIN PIN_40 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 8; PIN Node = 'SEN'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEN } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.463 ns) + CELL(1.760 ns) 6.355 ns i\[2\] 2 REG LC_X3_Y2_N3 13 " "Info: 2: + IC(3.463 ns) + CELL(1.760 ns) = 6.355 ns; Loc. = LC_X3_Y2_N3; Fanout = 13; REG Node = 'i\[2\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.223 ns" { SEN i[2] } "NODE_NAME" } } { "PF1.v" "" { Text "D:/proj/quartus/TEA/PF_DS/PF1.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.892 ns ( 45.51 % ) " "Info: Total cell delay = 2.892 ns ( 45.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.463 ns ( 54.49 % ) " "Info: Total interconnect delay = 3.463 ns ( 54.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.355 ns" { SEN i[2] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.355 ns" { SEN {} SEN~combout {} i[2] {} } { 0.000ns 0.000ns 3.463ns } { 0.000ns 1.132ns 1.760ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.206 ns" { SCLK i[2] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.206 ns" { SCLK {} SCLK~combout {} i[2] {} } { 0.000ns 0.000ns 4.156ns } { 0.000ns 1.132ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "6.355 ns" { SEN i[2] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "6.355 ns" { SEN {} SEN~combout {} i[2] {} } { 0.000ns 0.000ns 3.463ns } { 0.000ns 1.132ns 1.760ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "130 " "Info: Peak virtual memory: 130 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 26 14:51:02 2011 " "Info: Processing ended: Mon Dec 26 14:51:02 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}