{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1653573984153 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1653573984153 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 26 22:06:24 2022 " "Processing started: Thu May 26 22:06:24 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1653573984153 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1653573984153 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1653573984153 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1653573984403 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1653573984403 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 valveboard_firmware " "Found entity 1: valveboard_firmware" {  } { { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 8 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1653573990653 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1653573990653 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_valveboard_firmware " "Found entity 1: tb_valveboard_firmware" {  } { { "tb_valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/tb_valveboard_firmware.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1653573990653 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1653573990653 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "valveboard_firmware " "Elaborating entity \"valveboard_firmware\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1653573990669 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 valveboard_firmware.v(90) " "Verilog HDL assignment warning at valveboard_firmware.v(90): truncated value with size 32 to match size of target (5)" {  } { { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1653573990684 "|valveboard_firmware"}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 290 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 266 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 145 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 93 -1 0 } }  } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1653573991184 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1653573991278 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1653573991278 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1653573991278 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1653573991278 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4709 " "Peak virtual memory: 4709 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1653573991325 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 26 22:06:31 2022 " "Processing ended: Thu May 26 22:06:31 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1653573991325 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1653573991325 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1653573991325 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1653573991325 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1653573992481 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1653573992481 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 26 22:06:32 2022 " "Processing started: Thu May 26 22:06:32 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1653573992481 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1653573992481 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1653573992481 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1653573992559 ""}
{ "Info" "0" "" "Project  = valveboard_firmware" {  } {  } 0 0 "Project  = valveboard_firmware" 0 0 "Fitter" 0 0 1653573992559 ""}
{ "Info" "0" "" "Revision = valveboard_firmware" {  } {  } 0 0 "Revision = valveboard_firmware" 0 0 "Fitter" 0 0 1653573992559 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1653573992591 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1653573992591 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "valveboard_firmware EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"valveboard_firmware\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1653573992591 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1653573992622 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1653573992622 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1653573992653 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1653573992653 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1653573992731 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1653573992731 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1653573992731 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1653573992731 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1653573992731 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1653573992731 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1653573992809 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1653573992809 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1653573992809 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1653573992809 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1653573992809 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1653573992809 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000      sys_clk " "   1.000      sys_clk" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1653573992809 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1653573992809 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1653573992825 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1653573992825 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1653573992825 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" {  } { { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 9 -1 0 } }  } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1653573992841 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" {  } { { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 106 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1653573992841 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" {  } { { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 87 -1 0 } }  } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1653573992841 ""}  } { { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 10 -1 0 } }  } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1653573992841 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst_n " "Pin \"rst_n\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "valveboard_firmware.v" "" { Text "C:/Users/miaow/Desktop/firmware/valveboard_firmware.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/miaow/Desktop/firmware/" { { 0 { 0 ""} 0 655 14177 15141 0 0 "" 0 "" "" }  }  } }  } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1653573992841 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" {  } {  } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1653573992841 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1653573992841 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" {  } {  } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1653573992872 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" {  } {  } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1653573992919 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" {  } {  } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1653573992919 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1653573992919 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" {  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1653573992919 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653573992966 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1653573992966 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1653573993059 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653573993294 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1653573993294 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1653573994653 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653573994653 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1653573994700 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "11 " "Router estimated average interconnect usage is 11% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "13 X0_Y0 X8_Y11 " "Router estimated peak interconnect usage is 13% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" {  } { { "loc" "" { Generic "C:/Users/miaow/Desktop/firmware/" { { 1 { 0 "Router estimated peak interconnect usage is 13% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11"} { { 12 { 0 ""} 0 0 9 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1653573994919 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1653573994919 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1653573995200 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1653573995200 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653573995200 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.47 " "Total time spent on timing analysis during the Fitter is 0.47 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1653573995216 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1653573995216 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1653573995263 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/miaow/Desktop/firmware/output_files/valveboard_firmware.fit.smsg " "Generated suppressed messages file C:/Users/miaow/Desktop/firmware/output_files/valveboard_firmware.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1653573995309 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5910 " "Peak virtual memory: 5910 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1653573995325 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 26 22:06:35 2022 " "Processing ended: Thu May 26 22:06:35 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1653573995325 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1653573995325 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1653573995325 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1653573995325 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1653573996325 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1653573996325 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 26 22:06:36 2022 " "Processing started: Thu May 26 22:06:36 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1653573996325 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1653573996325 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1653573996325 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1653573996513 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1653573996544 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1653573996544 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4671 " "Peak virtual memory: 4671 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1653573996653 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 26 22:06:36 2022 " "Processing ended: Thu May 26 22:06:36 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1653573996653 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1653573996653 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1653573996653 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1653573996653 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1653573997231 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1653573997747 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1653573997747 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 26 22:06:37 2022 " "Processing started: Thu May 26 22:06:37 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1653573997747 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1653573997747 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta valveboard_firmware -c valveboard_firmware " "Command: quartus_sta valveboard_firmware -c valveboard_firmware" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1653573997747 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1653573997826 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1653573997919 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1653573997919 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1653573997951 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1653573997951 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1653573997997 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1653573998310 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1653573998357 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1653573998357 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1653573998357 ""}  } {  } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1653573998357 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1653573998357 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1653573998372 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1653573998372 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.920 " "Worst-case setup slack is -10.920" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1653573998372 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1653573998372 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -10.920           -2224.374 sys_clk  " "  -10.920           -2224.374 sys_clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1653573998372 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1653573998372 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.397 " "Worst-case hold slack is 1.397" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1653573998388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1653573998388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.397               0.000 sys_clk  " "    1.397               0.000 sys_clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1653573998388 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1653573998388 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1653573998388 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1653573998388 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1653573998388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1653573998388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.289              -2.289 sys_clk  " "   -2.289              -2.289 sys_clk " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1653573998388 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1653573998388 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1653573998403 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1653573998419 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1653573998419 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4687 " "Peak virtual memory: 4687 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1653573998451 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 26 22:06:38 2022 " "Processing ended: Thu May 26 22:06:38 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1653573998451 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1653573998451 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1653573998451 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1653573998451 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 10 s " "Quartus Prime Full Compilation was successful. 0 errors, 10 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1653573999091 ""}