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// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "12/11/2013 17:08:40"
                                                                                
// Verilog Test Bench template for design : PF1
// 
// Simulation tool : ModelSim-Altera (Verilog)
// 

`timescale 1 ns/ 1 ps
module PF1_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg SCLK;
reg SDATA;
reg SEN;
reg clk;
reg rst_n;
// wires                                               
wire [47:0]  S_PF;

// assign statements (if any)                          
PF1 i1 (
// port map - connection between master ports and signals/registers   
	.SCLK(SCLK),
	.SDATA(SDATA),
	.SEN(SEN),
	.S_PF(S_PF),
	.clk(clk),
	.rst_n(rst_n)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
                                                       
// --> end                                             
$display("Running testbench");                       
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                                       
@eachvec;                                              
// --> end                                             
end                                                    
endmodule