# Reading pref.tcl
# do PF1_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
# vmap work rtl_work 
# Copying C:/ProgramData/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/PF1.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:49:27 on Nov 09,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/miaow/Desktop/valve_board_kun" C:/Users/miaow/Desktop/valve_board_kun/PF1.v 
# -- Compiling module PF1
# 
# Top level modules:
# 	PF1
# End time: 12:49:28 on Nov 09,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+C:/Users/miaow/Desktop/valve_board_kun {C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 12:49:28 on Nov 09,2021
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+C:/Users/miaow/Desktop/valve_board_kun" C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v 
# -- Compiling module tb_PF1
# 
# Top level modules:
# 	tb_PF1
# End time: 12:49:28 on Nov 09,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs="+acc"  tb_PF1
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L maxii_ver -L rtl_work -L work -voptargs=""+acc"" tb_PF1 
# Start time: 12:49:28 on Nov 09,2021
# Loading work.tb_PF1
# Loading work.PF1
# ** Warning: (vsim-3015) [PCDPC] - Port size (48) does not match connection size (49) for port 'signal_high_voltage'. The port definition is at: C:/Users/miaow/Desktop/valve_board_kun/PF1.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /tb_PF1/inst_PF1 File: C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v Line: 12
# ** Warning: (vsim-3015) [PCDPC] - Port size (48) does not match connection size (49) for port 'signal_low_voltage'. The port definition is at: C:/Users/miaow/Desktop/valve_board_kun/PF1.v(14).
#    Time: 0 ps  Iteration: 0  Instance: /tb_PF1/inst_PF1 File: C:/Users/miaow/Desktop/valve_board_kun/tb_PF1.v Line: 12
# 
# add wave *
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
#           File in use by: miaow  Hostname: DESKTOP-RVHBS6P  ProcessID: 1008
#           Attempting to use alternate WLF file "./wlftyh13a8".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
#           Using alternate file: ./wlftyh13a8
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run 5 ms
# End time: 12:49:48 on Nov 09,2021, Elapsed time: 0:00:20
# Errors: 0, Warnings: 4