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6 Commits
b02-h1.2-p ... b02-c48-pt

Author SHA1 Message Date
MIAOW
39bb13a2ff
更新了版本说明 2022-08-31 14:53:55 +08:00
Miaow
6201402bb4 确认了不需要长时间开启保护 issue#6 2022-08-31 14:46:32 +08:00
Miaow
6af8dfd09c 每路阀添加单独的开启超时机制 
改动了固件
 2022-08-24 22:10:11 +08:00
Miaow
054f1e9495 固件中添加了高电压抑制 
如果阀已经是开的，就不再施加加速开启的高电压
 2022-08-24 13:27:43 +08:00
Miaow
89bf50ea46 整理了原理图 修改了PCB 
1. 添加了防反接电路
2. 删除了保险丝
3. 增大了喷阀走线载流能力
 2022-07-26 20:47:43 +08:00
Miaow
528e8f10bf fix pin assignment 
pin 39, 40, 41 order was wrong, which makes it failed to communicate with lower machine
 2022-05-26 22:16:55 +08:00
111 changed files with 1359 additions and 5101 deletions
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8
README.md
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@ -13,7 +13,7 @@
## 版本 ## 版本
由于阀板经常有不同类型的新要求出现，比如24路阀板、32路阀板、控制不同参数的新阀，因此不同的阀板型号（注意不是更新，比如阀板上添加级联接口属于更新）应建立不同的分支，**主分支无实际意义** 由于阀板经常有不同类型的新要求出现，比如24路阀板、32路阀板、控制不同参数的新阀，因此不同的阀板型号（注意不是更新，比如阀板上添加级联接口属于更新）应建立不同的分支，**[b01-c48-ponlytest-vgeneral](https://github.com/NanjingForestryUniversity/valveboard/tree/b01-c48-ponlytest-vgeneral)分支无实际意义**
分支命名规则（不使用中文，小写无空格） 分支命名规则（不使用中文，小写无空格）
@ -35,5 +35,9 @@ b分支编号-h硬件版本-p协议版本-f固件版本
## 作者 ## 作者
**丁坤，2019年9月入学、丁坤QQ1091546069、丁坤电话17761700156**，他觉得老阀板工程很乱，重新开发了关于阀板的一切，并放到这个仓库里，计划以后就在这个仓库里迭代更新，无论有没有毕业，都很乐意解答关于阀板的所有问题 [过奕任](https://github.com/3703781)、丁坤。老阀板工程很乱，重新开发了关于阀板的一切，并放到这个仓库里，以后就在这个仓库里迭代更新。欢迎提[issue](https://github.com/NanjingForestryUniversity/valveboard/issues)，bug随缘解决。
丁坤2019年入学虽然已经毕业，但也很乐意解答关于阀板的所有问题。丁坤QQ1091546069、丁坤电话17761700156。
过奕任2020年入学，目前正打算找其他人接管这个库，毕业了就不要找他，但永远可以找丁坤。

5
examples/README.md
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@ -17,6 +17,9 @@
基于嵌入式linux的程序，线程安全，具体板子为EPC-9600I-L，是广州致远电子有限公司开发的基于AM335x系列处理器的工控主板，处理器内核为800MHz的Arm Cortex-A8。 基于嵌入式linux的程序，线程安全，具体板子为EPC-9600I-L，是广州致远电子有限公司开发的基于AM335x系列处理器的工控主板，处理器内核为800MHz的Arm Cortex-A8。
## 作者 ## 作者
[过奕任](https://github.com/3703781)、丁坤。欢迎提[issue](https://github.com/NanjingForestryUniversity/valveboard/issues)，bug随缘解决。
**丁坤，2019年9月入学、丁坤QQ1091546069、丁坤电话17761700156**，无论有没有毕业，都很乐意解答关于这份协议的所有问题
过奕任2020年入学，目前正打算找其他人接管这个库，毕业了就不要找他，但永远可以找丁坤。
丁坤2019年入学、丁坤QQ1091546069、丁坤电话17761700156，已经毕业，但很乐意解答所有问题。

36
firmware/README.md
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@ -1,16 +1,44 @@
# 阀板固件 # 阀板固件
这是阀板上CPLD的固件，严格意义上也属于硬件，因为是描述的硬件结构。这个固件是按照通信协议写的，但比通信协议能适应更广的传输速度，**烟梗分选机上`SCLK`为1MHz，高电平时间为0.37ms** 这是阀板上CPLD的固件，严格意义上也属于硬件，因为是描述的硬件结构。这个固件是按照通信协议写的，但比通信协议能适应更广的传输速度，**烟梗分选机上`SCLK`为2MHz，高电平时间为0.2ms**
## 如何烧录 ## 如何烧录
去学习下intel系列的FPGA，用的是Quartus软件，自然就会了 Quartus软件
## 程序说明 ## 程序说明
都在注释里，清清楚楚 看程序注释
## Changelog
### v1.0
继承自老程序
### v1.1
丁坤重写了
### v1.2
修正了引脚分配
### v1.3
- 添加了高电压抑制，见[issue#4](https://github.com/NanjingForestryUniversity/valveboard/issues/4)
- 修正了高电压时间为0.2ms
### v1.4
确认了阀不需要长时间开启保护，删除了阀板固件v1.4-beta1([commit 6af8df](https://github.com/NanjingForestryUniversity/valveboard/commit/6af8dfd09c268d677a46063cc9637f573e69919e))中的长时间开启保护，见[issue#6](https://github.com/NanjingForestryUniversity/valveboard/issues/6)
## 作者 ## 作者
[过奕任](https://github.com/3703781)、丁坤
**作者是丁坤，2019年9月入学、丁坤QQ1091546069、丁坤电话17761700156**，他是搞嵌入式的，自师兄王聪（2018年9月入学）毕业后硬件领域师门出现空档期，被老倪催的没办法了，就学了硬件并顺手写了这份FPGA代码，无论有没有毕业，作者都很乐意解答关于固件的所有问题 过奕任自师兄王聪（2018年入学）毕业后硬件方面师门出现空档期，被老倪催的没办法了，就学了硬件并顺手写了这份FPGA代码。丁坤是专门搞嵌入式的，但也看过这份代码。欢迎提[issue](https://github.com/NanjingForestryUniversity/valveboard/issues)，bug随缘解决。
过奕任2020年入学，目前正打算找其他人接管这个库，毕业了就不要找他，但永远可以找丁坤。
丁坤2019年入学、丁坤QQ1091546069、丁坤电话17761700156，已经毕业，但很乐意解答所有问题。

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firmware/db/prev_cmp_valveboard_firmware.qmsg
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@ -1,95 +0,0 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640336877070 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336877070 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:07:56 2021 " "Processing started: Fri Dec 24 17:07:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336877070 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336877070 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336877070 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1640336877625 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1640336877625 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 valveboard_firmware " "Found entity 1: valveboard_firmware" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640336891329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336891329 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_valveboard_firmware " "Found entity 1: tb_valveboard_firmware" { } { { "tb_valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/tb_valveboard_firmware.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640336891329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336891329 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "valveboard_firmware " "Elaborating entity \"valveboard_firmware\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1640336891389 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 valveboard_firmware.v(88) " "Verilog HDL assignment warning at valveboard_firmware.v(88): truncated value with size 32 to match size of target (5)" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1640336891406 "|valveboard_firmware"}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 288 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 264 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 143 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 91 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1640336892331 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1640336892525 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1640336892525 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1640336892525 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1640336892525 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4707 " "Peak virtual memory: 4707 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336892797 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:12 2021 " "Processing ended: Fri Dec 24 17:08:12 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336892797 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336892797 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336892797 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1640336892797 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1640336894843 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336894845 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:08:13 2021 " "Processing started: Fri Dec 24 17:08:13 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336894845 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1640336894845 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1640336894845 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1640336895074 ""}
{ "Info" "0" "" "Project = valveboard_firmware" { } { } 0 0 "Project = valveboard_firmware" 0 0 "Fitter" 0 0 1640336895074 ""}
{ "Info" "0" "" "Revision = valveboard_firmware" { } { } 0 0 "Revision = valveboard_firmware" 0 0 "Fitter" 0 0 1640336895074 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1640336895171 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1640336895174 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "valveboard_firmware EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"valveboard_firmware\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1640336895182 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640336895234 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640336895234 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1640336895393 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1640336895416 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640336895800 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1640336895800 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "101 101 " "No exact pin location assignment(s) for 101 pins of 101 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1640336895878 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1640336895979 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1640336895979 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1640336895995 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1640336895995 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640336895995 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640336895995 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640336895995 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1640336895995 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640336896027 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640336896027 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640336896043 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640336896074 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock in PIN 20 " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock in PIN 20" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640336896074 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640336896074 ""} } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640336896074 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640336896074 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1640336896090 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1640336896121 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1640336896182 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1640336896182 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1640336896182 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1640336896198 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "99 unused 3.3V 3 96 0 " "Number of I/O pins in group: 99 (unused VREF, 3.3V VCCIO, 3 input, 96 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1640336896198 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 24 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 24 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 30 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 30 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 30 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 30 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1640336896198 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1640336896198 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336896267 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1640336896272 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1640336896477 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336896817 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1640336896817 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1640336899127 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336899127 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1640336899172 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "10 " "Router estimated average interconnect usage is 10% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "14 X0_Y0 X8_Y11 " "Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11" { } { { "loc" "" { Generic "C:/Users/guoyr/Desktop/qwert/" { { 1 { 0 "Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11"} { { 12 { 0 ""} 0 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1640336899476 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1640336899476 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1640336899890 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1640336899890 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336899890 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.47 " "Total time spent on timing analysis during the Fitter is 0.47 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1640336899915 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640336899931 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1640336899978 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg " "Generated suppressed messages file C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1640336900065 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5080 " "Peak virtual memory: 5080 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336900127 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:20 2021 " "Processing ended: Fri Dec 24 17:08:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336900127 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336900127 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336900127 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1640336900127 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1640336901822 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336901822 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:08:21 2021 " "Processing started: Fri Dec 24 17:08:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336901822 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1640336901822 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1640336901822 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1640336902150 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1640336902281 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1640336902300 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336902543 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:22 2021 " "Processing ended: Fri Dec 24 17:08:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336902543 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336902543 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336902543 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1640336902543 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1640336903270 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1640336904213 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640336904213 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 24 17:08:23 2021 " "Processing started: Fri Dec 24 17:08:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640336904213 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1640336904213 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta valveboard_firmware -c valveboard_firmware " "Command: quartus_sta valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1640336904213 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1640336904372 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1640336904551 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1640336904551 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336904598 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336904598 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1640336904666 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1640336905141 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1640336905260 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905260 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1640336905261 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1640336905261 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1640336905265 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1640336905290 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1640336905292 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.630 " "Worst-case setup slack is -10.630" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.630 -2257.699 sys_clk " " -10.630 -2257.699 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905298 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905298 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.389 " "Worst-case hold slack is 1.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.389 0.000 sys_clk " " 1.389 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905307 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905307 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640336905320 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640336905323 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 sys_clk " " -2.289 -2.289 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640336905350 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640336905350 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1640336905378 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640336905400 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640336905403 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640336905474 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 24 17:08:25 2021 " "Processing ended: Fri Dec 24 17:08:25 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640336905474 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640336905474 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640336905474 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1640336905474 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Quartus Prime Full Compilation was successful. 0 errors, 11 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1640336906173 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640495500861 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640495500861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 26 13:11:40 2021 " "Processing started: Sun Dec 26 13:11:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640495500861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1640495500861 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1640495500861 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1640495501233 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1640495501358 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1640495501358 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495501576 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:41 2021 " "Processing ended: Sun Dec 26 13:11:41 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495501576 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495501576 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495501576 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1640495501576 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="valveboard_firmware">
</PROJECT>
</LOG_ROOT>

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v1

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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016 Version_Index = 520278016
Creation_Time = Sun Dec 26 13:10:10 2021 Creation_Time = Wed Aug 31 14:18:53 2022

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firmware/db/valveboard_firmware.fit.qmsg
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1640495495527 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1640495495527 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "valveboard_firmware EPM1270T144C5 " "Selected device EPM1270T144C5 for design \"valveboard_firmware\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1640495495527 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640495495605 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1640495495605 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1640495495699 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1640495495714 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Device EPM570T144C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Device EPM570T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144A5 " "Device EPM570T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Device EPM1270T144I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144A5 " "Device EPM1270T144A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1640495495917 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1640495495917 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1640495496089 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1640495496089 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1640495496105 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1640495496105 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640495496105 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640495496105 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 sys_clk " " 1.000 sys_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1640495496105 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1640495496105 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640495496120 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1640495496136 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640495496152 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sys_clk Global clock in PIN 18 " "Automatically promoted signal \"sys_clk\" to use Global clock in PIN 18" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 7 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640495496167 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst_n Global clock " "Automatically promoted some destinations of signal \"rst_n\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "negedge_line_sen " "Destination \"negedge_line_sen\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 104 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640495496167 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fiter_line_sdata " "Destination \"fiter_line_sdata\" may be non-global or may not use global clock" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 85 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1640495496167 ""} } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 8 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1640495496167 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst_n " "Pin \"rst_n\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/programdata/intelfpga_lite/20.1/quartus/bin64/pin_planner.ppl" { rst_n } } } { "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/programdata/intelfpga_lite/20.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 8 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/guoyr/Desktop/qwert/" { { 0 { 0 ""} 0 551 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1640495496167 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1640495496167 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1640495496183 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1640495496230 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1640495496292 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1640495496292 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1640495496292 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1640495496292 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495496402 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1640495496433 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1640495496636 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495496998 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1640495497013 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1640495498476 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495498476 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1640495498539 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "11 " "Router estimated average interconnect usage is 11% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "12 X9_Y0 X17_Y11 " "Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11" { } { { "loc" "" { Generic "C:/Users/guoyr/Desktop/qwert/" { { 1 { 0 "Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11"} { { 12 { 0 ""} 9 0 9 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1640495498835 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1640495498835 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1640495499160 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1640495499160 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495499160 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.46 " "Total time spent on timing analysis during the Fitter is 0.46 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1640495499206 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1640495499222 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1640495499285 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg " "Generated suppressed messages file C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1640495499363 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5080 " "Peak virtual memory: 5080 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495499425 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:39 2021 " "Processing ended: Sun Dec 26 13:11:39 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495499425 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495499425 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495499425 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1640495499425 ""}

731
firmware/db/valveboard_firmware.hier_info
View File

@ -1,731 +0,0 @@
|valveboard_firmware
sys_clk => signal_high_voltage[0]~reg0.CLK
sys_clk => signal_high_voltage[1]~reg0.CLK
sys_clk => signal_high_voltage[2]~reg0.CLK
sys_clk => signal_high_voltage[3]~reg0.CLK
sys_clk => signal_high_voltage[4]~reg0.CLK
sys_clk => signal_high_voltage[5]~reg0.CLK
sys_clk => signal_high_voltage[6]~reg0.CLK
sys_clk => signal_high_voltage[7]~reg0.CLK
sys_clk => signal_high_voltage[8]~reg0.CLK
sys_clk => signal_high_voltage[9]~reg0.CLK
sys_clk => signal_high_voltage[10]~reg0.CLK
sys_clk => signal_high_voltage[11]~reg0.CLK
sys_clk => signal_high_voltage[12]~reg0.CLK
sys_clk => signal_high_voltage[13]~reg0.CLK
sys_clk => signal_high_voltage[14]~reg0.CLK
sys_clk => signal_high_voltage[15]~reg0.CLK
sys_clk => signal_high_voltage[16]~reg0.CLK
sys_clk => signal_high_voltage[17]~reg0.CLK
sys_clk => signal_high_voltage[18]~reg0.CLK
sys_clk => signal_high_voltage[19]~reg0.CLK
sys_clk => signal_high_voltage[20]~reg0.CLK
sys_clk => signal_high_voltage[21]~reg0.CLK
sys_clk => signal_high_voltage[22]~reg0.CLK
sys_clk => signal_high_voltage[23]~reg0.CLK
sys_clk => signal_high_voltage[24]~reg0.CLK
sys_clk => signal_high_voltage[25]~reg0.CLK
sys_clk => signal_high_voltage[26]~reg0.CLK
sys_clk => signal_high_voltage[27]~reg0.CLK
sys_clk => signal_high_voltage[28]~reg0.CLK
sys_clk => signal_high_voltage[29]~reg0.CLK
sys_clk => signal_high_voltage[30]~reg0.CLK
sys_clk => signal_high_voltage[31]~reg0.CLK
sys_clk => signal_high_voltage[32]~reg0.CLK
sys_clk => signal_high_voltage[33]~reg0.CLK
sys_clk => signal_high_voltage[34]~reg0.CLK
sys_clk => signal_high_voltage[35]~reg0.CLK
sys_clk => signal_high_voltage[36]~reg0.CLK
sys_clk => signal_high_voltage[37]~reg0.CLK
sys_clk => signal_high_voltage[38]~reg0.CLK
sys_clk => signal_high_voltage[39]~reg0.CLK
sys_clk => signal_high_voltage[40]~reg0.CLK
sys_clk => signal_high_voltage[41]~reg0.CLK
sys_clk => signal_high_voltage[42]~reg0.CLK
sys_clk => signal_high_voltage[43]~reg0.CLK
sys_clk => signal_high_voltage[44]~reg0.CLK
sys_clk => signal_high_voltage[45]~reg0.CLK
sys_clk => signal_high_voltage[46]~reg0.CLK
sys_clk => signal_high_voltage[47]~reg0.CLK
sys_clk => signal_low_voltage[0]~reg0.CLK
sys_clk => signal_low_voltage[1]~reg0.CLK
sys_clk => signal_low_voltage[2]~reg0.CLK
sys_clk => signal_low_voltage[3]~reg0.CLK
sys_clk => signal_low_voltage[4]~reg0.CLK
sys_clk => signal_low_voltage[5]~reg0.CLK
sys_clk => signal_low_voltage[6]~reg0.CLK
sys_clk => signal_low_voltage[7]~reg0.CLK
sys_clk => signal_low_voltage[8]~reg0.CLK
sys_clk => signal_low_voltage[9]~reg0.CLK
sys_clk => signal_low_voltage[10]~reg0.CLK
sys_clk => signal_low_voltage[11]~reg0.CLK
sys_clk => signal_low_voltage[12]~reg0.CLK
sys_clk => signal_low_voltage[13]~reg0.CLK
sys_clk => signal_low_voltage[14]~reg0.CLK
sys_clk => signal_low_voltage[15]~reg0.CLK
sys_clk => signal_low_voltage[16]~reg0.CLK
sys_clk => signal_low_voltage[17]~reg0.CLK
sys_clk => signal_low_voltage[18]~reg0.CLK
sys_clk => signal_low_voltage[19]~reg0.CLK
sys_clk => signal_low_voltage[20]~reg0.CLK
sys_clk => signal_low_voltage[21]~reg0.CLK
sys_clk => signal_low_voltage[22]~reg0.CLK
sys_clk => signal_low_voltage[23]~reg0.CLK
sys_clk => signal_low_voltage[24]~reg0.CLK
sys_clk => signal_low_voltage[25]~reg0.CLK
sys_clk => signal_low_voltage[26]~reg0.CLK
sys_clk => signal_low_voltage[27]~reg0.CLK
sys_clk => signal_low_voltage[28]~reg0.CLK
sys_clk => signal_low_voltage[29]~reg0.CLK
sys_clk => signal_low_voltage[30]~reg0.CLK
sys_clk => signal_low_voltage[31]~reg0.CLK
sys_clk => signal_low_voltage[32]~reg0.CLK
sys_clk => signal_low_voltage[33]~reg0.CLK
sys_clk => signal_low_voltage[34]~reg0.CLK
sys_clk => signal_low_voltage[35]~reg0.CLK
sys_clk => signal_low_voltage[36]~reg0.CLK
sys_clk => signal_low_voltage[37]~reg0.CLK
sys_clk => signal_low_voltage[38]~reg0.CLK
sys_clk => signal_low_voltage[39]~reg0.CLK
sys_clk => signal_low_voltage[40]~reg0.CLK
sys_clk => signal_low_voltage[41]~reg0.CLK
sys_clk => signal_low_voltage[42]~reg0.CLK
sys_clk => signal_low_voltage[43]~reg0.CLK
sys_clk => signal_low_voltage[44]~reg0.CLK
sys_clk => signal_low_voltage[45]~reg0.CLK
sys_clk => signal_low_voltage[46]~reg0.CLK
sys_clk => signal_low_voltage[47]~reg0.CLK
sys_clk => cache2_line_sdata[0].CLK
sys_clk => cache2_line_sdata[1].CLK
sys_clk => cache2_line_sdata[2].CLK
sys_clk => cache2_line_sdata[3].CLK
sys_clk => cache2_line_sdata[4].CLK
sys_clk => cache2_line_sdata[5].CLK
sys_clk => cache2_line_sdata[6].CLK
sys_clk => cache2_line_sdata[7].CLK
sys_clk => cache2_line_sdata[8].CLK
sys_clk => cache2_line_sdata[9].CLK
sys_clk => cache2_line_sdata[10].CLK
sys_clk => cache2_line_sdata[11].CLK
sys_clk => cache2_line_sdata[12].CLK
sys_clk => cache2_line_sdata[13].CLK
sys_clk => cache2_line_sdata[14].CLK
sys_clk => cache2_line_sdata[15].CLK
sys_clk => cache2_line_sdata[16].CLK
sys_clk => cache2_line_sdata[17].CLK
sys_clk => cache2_line_sdata[18].CLK
sys_clk => cache2_line_sdata[19].CLK
sys_clk => cache2_line_sdata[20].CLK
sys_clk => cache2_line_sdata[21].CLK
sys_clk => cache2_line_sdata[22].CLK
sys_clk => cache2_line_sdata[23].CLK
sys_clk => cache2_line_sdata[24].CLK
sys_clk => cache2_line_sdata[25].CLK
sys_clk => cache2_line_sdata[26].CLK
sys_clk => cache2_line_sdata[27].CLK
sys_clk => cache2_line_sdata[28].CLK
sys_clk => cache2_line_sdata[29].CLK
sys_clk => cache2_line_sdata[30].CLK
sys_clk => cache2_line_sdata[31].CLK
sys_clk => cache2_line_sdata[32].CLK
sys_clk => cache2_line_sdata[33].CLK
sys_clk => cache2_line_sdata[34].CLK
sys_clk => cache2_line_sdata[35].CLK
sys_clk => cache2_line_sdata[36].CLK
sys_clk => cache2_line_sdata[37].CLK
sys_clk => cache2_line_sdata[38].CLK
sys_clk => cache2_line_sdata[39].CLK
sys_clk => cache2_line_sdata[40].CLK
sys_clk => cache2_line_sdata[41].CLK
sys_clk => cache2_line_sdata[42].CLK
sys_clk => cache2_line_sdata[43].CLK
sys_clk => cache2_line_sdata[44].CLK
sys_clk => cache2_line_sdata[45].CLK
sys_clk => cache2_line_sdata[46].CLK
sys_clk => cache2_line_sdata[47].CLK
sys_clk => enable_count_high_voltage_time.CLK
sys_clk => is_high_voltage_time.CLK
sys_clk => cnt_for_high_voltage_time[0].CLK
sys_clk => cnt_for_high_voltage_time[1].CLK
sys_clk => cnt_for_high_voltage_time[2].CLK
sys_clk => cnt_for_high_voltage_time[3].CLK
sys_clk => cnt_for_high_voltage_time[4].CLK
sys_clk => cnt_for_high_voltage_time[5].CLK
sys_clk => cnt_for_high_voltage_time[6].CLK
sys_clk => cnt_for_high_voltage_time[7].CLK
sys_clk => cnt_for_high_voltage_time[8].CLK
sys_clk => cnt_for_high_voltage_time[9].CLK
sys_clk => cnt_for_high_voltage_time[10].CLK
sys_clk => cnt_for_high_voltage_time[11].CLK
sys_clk => cnt_for_high_voltage_time[12].CLK
sys_clk => cnt_for_high_voltage_time[13].CLK
sys_clk => cnt_for_high_voltage_time[14].CLK
sys_clk => cnt_for_high_voltage_time[15].CLK
sys_clk => cnt_for_high_voltage_time[16].CLK
sys_clk => cnt_for_high_voltage_time[17].CLK
sys_clk => cnt_for_high_voltage_time[18].CLK
sys_clk => cnt_for_high_voltage_time[19].CLK
sys_clk => cnt_for_high_voltage_time[20].CLK
sys_clk => cnt_for_high_voltage_time[21].CLK
sys_clk => cnt_for_high_voltage_time[22].CLK
sys_clk => cnt_for_high_voltage_time[23].CLK
sys_clk => cnt_for_high_voltage_time[24].CLK
sys_clk => cnt_for_high_voltage_time[25].CLK
sys_clk => cnt_for_high_voltage_time[26].CLK
sys_clk => cnt_for_high_voltage_time[27].CLK
sys_clk => cnt_for_high_voltage_time[28].CLK
sys_clk => cnt_for_high_voltage_time[29].CLK
sys_clk => cnt_for_high_voltage_time[30].CLK
sys_clk => cnt_for_high_voltage_time[31].CLK
sys_clk => cache_enable_count_high_voltage_time[0].CLK
sys_clk => cache_enable_count_high_voltage_time[1].CLK
sys_clk => fault_flag[1][0].CLK
sys_clk => fault_counter[0].CLK
sys_clk => fault_counter[1].CLK
sys_clk => fault_counter[2].CLK
sys_clk => fault_counter[3].CLK
sys_clk => fault_counter[4].CLK
sys_clk => fault_counter[5].CLK
sys_clk => fault_counter[6].CLK
sys_clk => fault_counter[7].CLK
sys_clk => fault_counter[8].CLK
sys_clk => fault_counter[9].CLK
sys_clk => fault_counter[10].CLK
sys_clk => fault_counter[11].CLK
sys_clk => fault_counter[12].CLK
sys_clk => fault_counter[13].CLK
sys_clk => fault_counter[14].CLK
sys_clk => fault_counter[15].CLK
sys_clk => fault_counter[16].CLK
sys_clk => fault_counter[17].CLK
sys_clk => fault_counter[18].CLK
sys_clk => fault_counter[19].CLK
sys_clk => fault_counter[20].CLK
sys_clk => fault_counter[21].CLK
sys_clk => fault_counter[22].CLK
sys_clk => fault_counter[23].CLK
sys_clk => fault_counter[24].CLK
sys_clk => fault_counter[25].CLK
sys_clk => fault_counter[26].CLK
sys_clk => fault_counter[27].CLK
sys_clk => fault_counter[28].CLK
sys_clk => fault_counter[29].CLK
sys_clk => fault_counter[30].CLK
sys_clk => fault_counter[31].CLK
sys_clk => fault_flag[0][0].CLK
sys_clk => cache_line_sdata[0].CLK
sys_clk => cache_line_sdata[1].CLK
sys_clk => cache_line_sdata[2].CLK
sys_clk => cache_line_sdata[3].CLK
sys_clk => cache_line_sdata[4].CLK
sys_clk => cache_line_sdata[5].CLK
sys_clk => cache_line_sdata[6].CLK
sys_clk => cache_line_sdata[7].CLK
sys_clk => cache_line_sdata[8].CLK
sys_clk => cache_line_sdata[9].CLK
sys_clk => cache_line_sdata[10].CLK
sys_clk => cache_line_sdata[11].CLK
sys_clk => cache_line_sdata[12].CLK
sys_clk => cache_line_sdata[13].CLK
sys_clk => cache_line_sdata[14].CLK
sys_clk => cache_line_sdata[15].CLK
sys_clk => cache_line_sdata[16].CLK
sys_clk => cache_line_sdata[17].CLK
sys_clk => cache_line_sdata[18].CLK
sys_clk => cache_line_sdata[19].CLK
sys_clk => cache_line_sdata[20].CLK
sys_clk => cache_line_sdata[21].CLK
sys_clk => cache_line_sdata[22].CLK
sys_clk => cache_line_sdata[23].CLK
sys_clk => cache_line_sdata[24].CLK
sys_clk => cache_line_sdata[25].CLK
sys_clk => cache_line_sdata[26].CLK
sys_clk => cache_line_sdata[27].CLK
sys_clk => cache_line_sdata[28].CLK
sys_clk => cache_line_sdata[29].CLK
sys_clk => cache_line_sdata[30].CLK
sys_clk => cache_line_sdata[31].CLK
sys_clk => cache_line_sdata[32].CLK
sys_clk => cache_line_sdata[33].CLK
sys_clk => cache_line_sdata[34].CLK
sys_clk => cache_line_sdata[35].CLK
sys_clk => cache_line_sdata[36].CLK
sys_clk => cache_line_sdata[37].CLK
sys_clk => cache_line_sdata[38].CLK
sys_clk => cache_line_sdata[39].CLK
sys_clk => cache_line_sdata[40].CLK
sys_clk => cache_line_sdata[41].CLK
sys_clk => cache_line_sdata[42].CLK
sys_clk => cache_line_sdata[43].CLK
sys_clk => cache_line_sdata[44].CLK
sys_clk => cache_line_sdata[45].CLK
sys_clk => cache_line_sdata[46].CLK
sys_clk => cache_line_sdata[47].CLK
sys_clk => i[0].CLK
sys_clk => i[1].CLK
sys_clk => i[2].CLK
sys_clk => i[3].CLK
sys_clk => i[4].CLK
sys_clk => i[5].CLK
sys_clk => i[6].CLK
sys_clk => i[7].CLK
sys_clk => i[8].CLK
sys_clk => i[9].CLK
sys_clk => i[10].CLK
sys_clk => i[11].CLK
sys_clk => i[12].CLK
sys_clk => i[13].CLK
sys_clk => i[14].CLK
sys_clk => i[15].CLK
sys_clk => i[16].CLK
sys_clk => i[17].CLK
sys_clk => i[18].CLK
sys_clk => i[19].CLK
sys_clk => i[20].CLK
sys_clk => i[21].CLK
sys_clk => i[22].CLK
sys_clk => i[23].CLK
sys_clk => i[24].CLK
sys_clk => i[25].CLK
sys_clk => i[26].CLK
sys_clk => i[27].CLK
sys_clk => i[28].CLK
sys_clk => i[29].CLK
sys_clk => i[30].CLK
sys_clk => i[31].CLK
sys_clk => negedge_line_sen.CLK
sys_clk => filter_line_sen.CLK
sys_clk => cache_line_sen[0].CLK
sys_clk => cache_line_sen[1].CLK
sys_clk => cache_line_sen[2].CLK
sys_clk => cache_line_sen[3].CLK
sys_clk => cache_line_sen[4].CLK
sys_clk => fiter_line_sdata.CLK
sys_clk => tmp_cache_line_sdata[0].CLK
sys_clk => tmp_cache_line_sdata[1].CLK
sys_clk => tmp_cache_line_sdata[2].CLK
sys_clk => tmp_cache_line_sdata[3].CLK
sys_clk => tmp_cache_line_sdata[4].CLK
sys_clk => posedge_line_sclk.CLK
sys_clk => cache_line_sclk[0].CLK
sys_clk => cache_line_sclk[1].CLK
sys_clk => cache_line_sclk[2].CLK
sys_clk => cache_line_sclk[3].CLK
sys_clk => cache_line_sclk[4].CLK
rst_n => signal_high_voltage[0]~reg0.PRESET
rst_n => signal_high_voltage[1]~reg0.PRESET
rst_n => signal_high_voltage[2]~reg0.PRESET
rst_n => signal_high_voltage[3]~reg0.PRESET
rst_n => signal_high_voltage[4]~reg0.PRESET
rst_n => signal_high_voltage[5]~reg0.PRESET
rst_n => signal_high_voltage[6]~reg0.PRESET
rst_n => signal_high_voltage[7]~reg0.PRESET
rst_n => signal_high_voltage[8]~reg0.PRESET
rst_n => signal_high_voltage[9]~reg0.PRESET
rst_n => signal_high_voltage[10]~reg0.PRESET
rst_n => signal_high_voltage[11]~reg0.PRESET
rst_n => signal_high_voltage[12]~reg0.PRESET
rst_n => signal_high_voltage[13]~reg0.PRESET
rst_n => signal_high_voltage[14]~reg0.PRESET
rst_n => signal_high_voltage[15]~reg0.PRESET
rst_n => signal_high_voltage[16]~reg0.PRESET
rst_n => signal_high_voltage[17]~reg0.PRESET
rst_n => signal_high_voltage[18]~reg0.PRESET
rst_n => signal_high_voltage[19]~reg0.PRESET
rst_n => signal_high_voltage[20]~reg0.PRESET
rst_n => signal_high_voltage[21]~reg0.PRESET
rst_n => signal_high_voltage[22]~reg0.PRESET
rst_n => signal_high_voltage[23]~reg0.PRESET
rst_n => signal_high_voltage[24]~reg0.PRESET
rst_n => signal_high_voltage[25]~reg0.PRESET
rst_n => signal_high_voltage[26]~reg0.PRESET
rst_n => signal_high_voltage[27]~reg0.PRESET
rst_n => signal_high_voltage[28]~reg0.PRESET
rst_n => signal_high_voltage[29]~reg0.PRESET
rst_n => signal_high_voltage[30]~reg0.PRESET
rst_n => signal_high_voltage[31]~reg0.PRESET
rst_n => signal_high_voltage[32]~reg0.PRESET
rst_n => signal_high_voltage[33]~reg0.PRESET
rst_n => signal_high_voltage[34]~reg0.PRESET
rst_n => signal_high_voltage[35]~reg0.PRESET
rst_n => signal_high_voltage[36]~reg0.PRESET
rst_n => signal_high_voltage[37]~reg0.PRESET
rst_n => signal_high_voltage[38]~reg0.PRESET
rst_n => signal_high_voltage[39]~reg0.PRESET
rst_n => signal_high_voltage[40]~reg0.PRESET
rst_n => signal_high_voltage[41]~reg0.PRESET
rst_n => signal_high_voltage[42]~reg0.PRESET
rst_n => signal_high_voltage[43]~reg0.PRESET
rst_n => signal_high_voltage[44]~reg0.PRESET
rst_n => signal_high_voltage[45]~reg0.PRESET
rst_n => signal_high_voltage[46]~reg0.PRESET
rst_n => signal_high_voltage[47]~reg0.PRESET
rst_n => signal_low_voltage[0]~reg0.PRESET
rst_n => signal_low_voltage[1]~reg0.PRESET
rst_n => signal_low_voltage[2]~reg0.PRESET
rst_n => signal_low_voltage[3]~reg0.PRESET
rst_n => signal_low_voltage[4]~reg0.PRESET
rst_n => signal_low_voltage[5]~reg0.PRESET
rst_n => signal_low_voltage[6]~reg0.PRESET
rst_n => signal_low_voltage[7]~reg0.PRESET
rst_n => signal_low_voltage[8]~reg0.PRESET
rst_n => signal_low_voltage[9]~reg0.PRESET
rst_n => signal_low_voltage[10]~reg0.PRESET
rst_n => signal_low_voltage[11]~reg0.PRESET
rst_n => signal_low_voltage[12]~reg0.PRESET
rst_n => signal_low_voltage[13]~reg0.PRESET
rst_n => signal_low_voltage[14]~reg0.PRESET
rst_n => signal_low_voltage[15]~reg0.PRESET
rst_n => signal_low_voltage[16]~reg0.PRESET
rst_n => signal_low_voltage[17]~reg0.PRESET
rst_n => signal_low_voltage[18]~reg0.PRESET
rst_n => signal_low_voltage[19]~reg0.PRESET
rst_n => signal_low_voltage[20]~reg0.PRESET
rst_n => signal_low_voltage[21]~reg0.PRESET
rst_n => signal_low_voltage[22]~reg0.PRESET
rst_n => signal_low_voltage[23]~reg0.PRESET
rst_n => signal_low_voltage[24]~reg0.PRESET
rst_n => signal_low_voltage[25]~reg0.PRESET
rst_n => signal_low_voltage[26]~reg0.PRESET
rst_n => signal_low_voltage[27]~reg0.PRESET
rst_n => signal_low_voltage[28]~reg0.PRESET
rst_n => signal_low_voltage[29]~reg0.PRESET
rst_n => signal_low_voltage[30]~reg0.PRESET
rst_n => signal_low_voltage[31]~reg0.PRESET
rst_n => signal_low_voltage[32]~reg0.PRESET
rst_n => signal_low_voltage[33]~reg0.PRESET
rst_n => signal_low_voltage[34]~reg0.PRESET
rst_n => signal_low_voltage[35]~reg0.PRESET
rst_n => signal_low_voltage[36]~reg0.PRESET
rst_n => signal_low_voltage[37]~reg0.PRESET
rst_n => signal_low_voltage[38]~reg0.PRESET
rst_n => signal_low_voltage[39]~reg0.PRESET
rst_n => signal_low_voltage[40]~reg0.PRESET
rst_n => signal_low_voltage[41]~reg0.PRESET
rst_n => signal_low_voltage[42]~reg0.PRESET
rst_n => signal_low_voltage[43]~reg0.PRESET
rst_n => signal_low_voltage[44]~reg0.PRESET
rst_n => signal_low_voltage[45]~reg0.PRESET
rst_n => signal_low_voltage[46]~reg0.PRESET
rst_n => signal_low_voltage[47]~reg0.PRESET
rst_n => posedge_line_sclk.ACLR
rst_n => cache_line_sclk[0].ACLR
rst_n => cache_line_sclk[1].ACLR
rst_n => cache_line_sclk[2].ACLR
rst_n => cache_line_sclk[3].ACLR
rst_n => cache_line_sclk[4].ACLR
rst_n => tmp_cache_line_sdata[0].PRESET
rst_n => tmp_cache_line_sdata[1].PRESET
rst_n => tmp_cache_line_sdata[2].PRESET
rst_n => tmp_cache_line_sdata[3].PRESET
rst_n => tmp_cache_line_sdata[4].PRESET
rst_n => filter_line_sen.ACLR
rst_n => cache_line_sen[0].ACLR
rst_n => cache_line_sen[1].ACLR
rst_n => cache_line_sen[2].ACLR
rst_n => cache_line_sen[3].ACLR
rst_n => cache_line_sen[4].ACLR
rst_n => cache_line_sdata[0].PRESET
rst_n => cache_line_sdata[1].PRESET
rst_n => cache_line_sdata[2].PRESET
rst_n => cache_line_sdata[3].PRESET
rst_n => cache_line_sdata[4].PRESET
rst_n => cache_line_sdata[5].PRESET
rst_n => cache_line_sdata[6].PRESET
rst_n => cache_line_sdata[7].PRESET
rst_n => cache_line_sdata[8].PRESET
rst_n => cache_line_sdata[9].PRESET
rst_n => cache_line_sdata[10].PRESET
rst_n => cache_line_sdata[11].PRESET
rst_n => cache_line_sdata[12].PRESET
rst_n => cache_line_sdata[13].PRESET
rst_n => cache_line_sdata[14].PRESET
rst_n => cache_line_sdata[15].PRESET
rst_n => cache_line_sdata[16].PRESET
rst_n => cache_line_sdata[17].PRESET
rst_n => cache_line_sdata[18].PRESET
rst_n => cache_line_sdata[19].PRESET
rst_n => cache_line_sdata[20].PRESET
rst_n => cache_line_sdata[21].PRESET
rst_n => cache_line_sdata[22].PRESET
rst_n => cache_line_sdata[23].PRESET
rst_n => cache_line_sdata[24].PRESET
rst_n => cache_line_sdata[25].PRESET
rst_n => cache_line_sdata[26].PRESET
rst_n => cache_line_sdata[27].PRESET
rst_n => cache_line_sdata[28].PRESET
rst_n => cache_line_sdata[29].PRESET
rst_n => cache_line_sdata[30].PRESET
rst_n => cache_line_sdata[31].PRESET
rst_n => cache_line_sdata[32].PRESET
rst_n => cache_line_sdata[33].PRESET
rst_n => cache_line_sdata[34].PRESET
rst_n => cache_line_sdata[35].PRESET
rst_n => cache_line_sdata[36].PRESET
rst_n => cache_line_sdata[37].PRESET
rst_n => cache_line_sdata[38].PRESET
rst_n => cache_line_sdata[39].PRESET
rst_n => cache_line_sdata[40].PRESET
rst_n => cache_line_sdata[41].PRESET
rst_n => cache_line_sdata[42].PRESET
rst_n => cache_line_sdata[43].PRESET
rst_n => cache_line_sdata[44].PRESET
rst_n => cache_line_sdata[45].PRESET
rst_n => cache_line_sdata[46].PRESET
rst_n => cache_line_sdata[47].PRESET
rst_n => i[0].ACLR
rst_n => i[1].ACLR
rst_n => i[2].ACLR
rst_n => i[3].ACLR
rst_n => i[4].ACLR
rst_n => i[5].ACLR
rst_n => i[6].ACLR
rst_n => i[7].ACLR
rst_n => i[8].ACLR
rst_n => i[9].ACLR
rst_n => i[10].ACLR
rst_n => i[11].ACLR
rst_n => i[12].ACLR
rst_n => i[13].ACLR
rst_n => i[14].ACLR
rst_n => i[15].ACLR
rst_n => i[16].ACLR
rst_n => i[17].ACLR
rst_n => i[18].ACLR
rst_n => i[19].ACLR
rst_n => i[20].ACLR
rst_n => i[21].ACLR
rst_n => i[22].ACLR
rst_n => i[23].ACLR
rst_n => i[24].ACLR
rst_n => i[25].ACLR
rst_n => i[26].ACLR
rst_n => i[27].ACLR
rst_n => i[28].ACLR
rst_n => i[29].ACLR
rst_n => i[30].ACLR
rst_n => i[31].ACLR
rst_n => fault_flag[0][0].ACLR
rst_n => fault_flag[1][0].ACLR
rst_n => fault_counter[0].ACLR
rst_n => fault_counter[1].ACLR
rst_n => fault_counter[2].ACLR
rst_n => fault_counter[3].ACLR
rst_n => fault_counter[4].ACLR
rst_n => fault_counter[5].ACLR
rst_n => fault_counter[6].ACLR
rst_n => fault_counter[7].ACLR
rst_n => fault_counter[8].ACLR
rst_n => fault_counter[9].ACLR
rst_n => fault_counter[10].ACLR
rst_n => fault_counter[11].ACLR
rst_n => fault_counter[12].ACLR
rst_n => fault_counter[13].ACLR
rst_n => fault_counter[14].ACLR
rst_n => fault_counter[15].ACLR
rst_n => fault_counter[16].ACLR
rst_n => fault_counter[17].ACLR
rst_n => fault_counter[18].ACLR
rst_n => fault_counter[19].ACLR
rst_n => fault_counter[20].ACLR
rst_n => fault_counter[21].ACLR
rst_n => fault_counter[22].ACLR
rst_n => fault_counter[23].ACLR
rst_n => fault_counter[24].ACLR
rst_n => fault_counter[25].ACLR
rst_n => fault_counter[26].ACLR
rst_n => fault_counter[27].ACLR
rst_n => fault_counter[28].ACLR
rst_n => fault_counter[29].ACLR
rst_n => fault_counter[30].ACLR
rst_n => fault_counter[31].ACLR
rst_n => cache_enable_count_high_voltage_time[0].ACLR
rst_n => cache_enable_count_high_voltage_time[1].ACLR
rst_n => is_high_voltage_time.ACLR
rst_n => cnt_for_high_voltage_time[0].ACLR
rst_n => cnt_for_high_voltage_time[1].ACLR
rst_n => cnt_for_high_voltage_time[2].ACLR
rst_n => cnt_for_high_voltage_time[3].ACLR
rst_n => cnt_for_high_voltage_time[4].ACLR
rst_n => cnt_for_high_voltage_time[5].ACLR
rst_n => cnt_for_high_voltage_time[6].ACLR
rst_n => cnt_for_high_voltage_time[7].ACLR
rst_n => cnt_for_high_voltage_time[8].ACLR
rst_n => cnt_for_high_voltage_time[9].ACLR
rst_n => cnt_for_high_voltage_time[10].ACLR
rst_n => cnt_for_high_voltage_time[11].ACLR
rst_n => cnt_for_high_voltage_time[12].ACLR
rst_n => cnt_for_high_voltage_time[13].ACLR
rst_n => cnt_for_high_voltage_time[14].ACLR
rst_n => cnt_for_high_voltage_time[15].ACLR
rst_n => cnt_for_high_voltage_time[16].ACLR
rst_n => cnt_for_high_voltage_time[17].ACLR
rst_n => cnt_for_high_voltage_time[18].ACLR
rst_n => cnt_for_high_voltage_time[19].ACLR
rst_n => cnt_for_high_voltage_time[20].ACLR
rst_n => cnt_for_high_voltage_time[21].ACLR
rst_n => cnt_for_high_voltage_time[22].ACLR
rst_n => cnt_for_high_voltage_time[23].ACLR
rst_n => cnt_for_high_voltage_time[24].ACLR
rst_n => cnt_for_high_voltage_time[25].ACLR
rst_n => cnt_for_high_voltage_time[26].ACLR
rst_n => cnt_for_high_voltage_time[27].ACLR
rst_n => cnt_for_high_voltage_time[28].ACLR
rst_n => cnt_for_high_voltage_time[29].ACLR
rst_n => cnt_for_high_voltage_time[30].ACLR
rst_n => cnt_for_high_voltage_time[31].ACLR
rst_n => cache2_line_sdata[0].PRESET
rst_n => cache2_line_sdata[1].PRESET
rst_n => cache2_line_sdata[2].PRESET
rst_n => cache2_line_sdata[3].PRESET
rst_n => cache2_line_sdata[4].PRESET
rst_n => cache2_line_sdata[5].PRESET
rst_n => cache2_line_sdata[6].PRESET
rst_n => cache2_line_sdata[7].PRESET
rst_n => cache2_line_sdata[8].PRESET
rst_n => cache2_line_sdata[9].PRESET
rst_n => cache2_line_sdata[10].PRESET
rst_n => cache2_line_sdata[11].PRESET
rst_n => cache2_line_sdata[12].PRESET
rst_n => cache2_line_sdata[13].PRESET
rst_n => cache2_line_sdata[14].PRESET
rst_n => cache2_line_sdata[15].PRESET
rst_n => cache2_line_sdata[16].PRESET
rst_n => cache2_line_sdata[17].PRESET
rst_n => cache2_line_sdata[18].PRESET
rst_n => cache2_line_sdata[19].PRESET
rst_n => cache2_line_sdata[20].PRESET
rst_n => cache2_line_sdata[21].PRESET
rst_n => cache2_line_sdata[22].PRESET
rst_n => cache2_line_sdata[23].PRESET
rst_n => cache2_line_sdata[24].PRESET
rst_n => cache2_line_sdata[25].PRESET
rst_n => cache2_line_sdata[26].PRESET
rst_n => cache2_line_sdata[27].PRESET
rst_n => cache2_line_sdata[28].PRESET
rst_n => cache2_line_sdata[29].PRESET
rst_n => cache2_line_sdata[30].PRESET
rst_n => cache2_line_sdata[31].PRESET
rst_n => cache2_line_sdata[32].PRESET
rst_n => cache2_line_sdata[33].PRESET
rst_n => cache2_line_sdata[34].PRESET
rst_n => cache2_line_sdata[35].PRESET
rst_n => cache2_line_sdata[36].PRESET
rst_n => cache2_line_sdata[37].PRESET
rst_n => cache2_line_sdata[38].PRESET
rst_n => cache2_line_sdata[39].PRESET
rst_n => cache2_line_sdata[40].PRESET
rst_n => cache2_line_sdata[41].PRESET
rst_n => cache2_line_sdata[42].PRESET
rst_n => cache2_line_sdata[43].PRESET
rst_n => cache2_line_sdata[44].PRESET
rst_n => cache2_line_sdata[45].PRESET
rst_n => cache2_line_sdata[46].PRESET
rst_n => cache2_line_sdata[47].PRESET
rst_n => enable_count_high_voltage_time.ACLR
rst_n => fiter_line_sdata.ENA
rst_n => negedge_line_sen.ENA
line_sclk => cache_line_sclk[0].DATAIN
line_sclk => Equal0.IN4
line_sen => cache_line_sen[0].DATAIN
line_sen => Equal1.IN4
line_sen => Equal2.IN5
line_sdata => tmp_cache_line_sdata[0].DATAIN
signal_high_voltage[0] << signal_high_voltage[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[1] << signal_high_voltage[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[2] << signal_high_voltage[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[3] << signal_high_voltage[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[4] << signal_high_voltage[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[5] << signal_high_voltage[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[6] << signal_high_voltage[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[7] << signal_high_voltage[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[8] << signal_high_voltage[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[9] << signal_high_voltage[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[10] << signal_high_voltage[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[11] << signal_high_voltage[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[12] << signal_high_voltage[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[13] << signal_high_voltage[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[14] << signal_high_voltage[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[15] << signal_high_voltage[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[16] << signal_high_voltage[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[17] << signal_high_voltage[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[18] << signal_high_voltage[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[19] << signal_high_voltage[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[20] << signal_high_voltage[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[21] << signal_high_voltage[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[22] << signal_high_voltage[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[23] << signal_high_voltage[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[24] << signal_high_voltage[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[25] << signal_high_voltage[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[26] << signal_high_voltage[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[27] << signal_high_voltage[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[28] << signal_high_voltage[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[29] << signal_high_voltage[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[30] << signal_high_voltage[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[31] << signal_high_voltage[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[32] << signal_high_voltage[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[33] << signal_high_voltage[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[34] << signal_high_voltage[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[35] << signal_high_voltage[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[36] << signal_high_voltage[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[37] << signal_high_voltage[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[38] << signal_high_voltage[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[39] << signal_high_voltage[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[40] << signal_high_voltage[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[41] << signal_high_voltage[41]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[42] << signal_high_voltage[42]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[43] << signal_high_voltage[43]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[44] << signal_high_voltage[44]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[45] << signal_high_voltage[45]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[46] << signal_high_voltage[46]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_high_voltage[47] << signal_high_voltage[47]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[0] << signal_low_voltage[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[1] << signal_low_voltage[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[2] << signal_low_voltage[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[3] << signal_low_voltage[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[4] << signal_low_voltage[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[5] << signal_low_voltage[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[6] << signal_low_voltage[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[7] << signal_low_voltage[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[8] << signal_low_voltage[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[9] << signal_low_voltage[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[10] << signal_low_voltage[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[11] << signal_low_voltage[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[12] << signal_low_voltage[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[13] << signal_low_voltage[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[14] << signal_low_voltage[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[15] << signal_low_voltage[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[16] << signal_low_voltage[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[17] << signal_low_voltage[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[18] << signal_low_voltage[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[19] << signal_low_voltage[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[20] << signal_low_voltage[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[21] << signal_low_voltage[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[22] << signal_low_voltage[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[23] << signal_low_voltage[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[24] << signal_low_voltage[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[25] << signal_low_voltage[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[26] << signal_low_voltage[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[27] << signal_low_voltage[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[28] << signal_low_voltage[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[29] << signal_low_voltage[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[30] << signal_low_voltage[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[31] << signal_low_voltage[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[32] << signal_low_voltage[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[33] << signal_low_voltage[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[34] << signal_low_voltage[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[35] << signal_low_voltage[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[36] << signal_low_voltage[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[37] << signal_low_voltage[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[38] << signal_low_voltage[38]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[39] << signal_low_voltage[39]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[40] << signal_low_voltage[40]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[41] << signal_low_voltage[41]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[42] << signal_low_voltage[42]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[43] << signal_low_voltage[43]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[44] << signal_low_voltage[44]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[45] << signal_low_voltage[45]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[46] << signal_low_voltage[46]~reg0.DB_MAX_OUTPUT_PORT_TYPE
signal_low_voltage[47] << signal_low_voltage[47]~reg0.DB_MAX_OUTPUT_PORT_TYPE

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firmware/db/valveboard_firmware.lpc.html
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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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firmware/db/valveboard_firmware.lpc.txt
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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v1

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640495479244 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640495479244 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 26 13:11:19 2021 " "Processing started: Sun Dec 26 13:11:19 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640495479244 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495479244 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware " "Command: quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495479244 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1640495479775 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1640495479775 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 valveboard_firmware " "Found entity 1: valveboard_firmware" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640495492300 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495492300 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tb_valveboard_firmware.v 1 1 " "Found 1 design units, including 1 entities, in source file tb_valveboard_firmware.v" { { "Info" "ISGN_ENTITY_NAME" "1 tb_valveboard_firmware " "Found entity 1: tb_valveboard_firmware" { } { { "tb_valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/tb_valveboard_firmware.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1640495492300 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495492300 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "valveboard_firmware " "Elaborating entity \"valveboard_firmware\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1640495492362 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 valveboard_firmware.v(88) " "Verilog HDL assignment warning at valveboard_firmware.v(88): truncated value with size 32 to match size of target (5)" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1640495492362 "|valveboard_firmware"}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 288 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 264 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 143 -1 0 } } { "valveboard_firmware.v" "" { Text "C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v" 91 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1640495493222 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "569 " "Implemented 569 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1640495493456 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1640495493456 ""} { "Info" "ICUT_CUT_TM_LCELLS" "468 " "Implemented 468 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1640495493456 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1640495493456 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4700 " "Peak virtual memory: 4700 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495493628 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:33 2021 " "Processing ended: Sun Dec 26 13:11:33 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495493628 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495493628 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495493628 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1640495493628 ""}

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firmware/db/valveboard_firmware.map.rdb
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firmware/db/valveboard_firmware.pplq.rdb
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firmware/db/valveboard_firmware.pre_map.hdb
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firmware/db/valveboard_firmware.root_partition.map.reg_db.cdb
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firmware/db/valveboard_firmware.routing.rdb
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firmware/db/valveboard_firmware.rtlv.hdb
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firmware/db/valveboard_firmware.rtlv_sg.cdb
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firmware/db/valveboard_firmware.rtlv_sg_swap.cdb
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firmware/db/valveboard_firmware.sld_design_entry_dsc.sci
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1
firmware/db/valveboard_firmware.smart_action.txt
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DONE

25
firmware/db/valveboard_firmware.sta.qmsg
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@ -1,25 +0,0 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1640495503198 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1640495503214 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 26 13:11:42 2021 " "Processing started: Sun Dec 26 13:11:42 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1640495503214 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1640495503214 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta valveboard_firmware -c valveboard_firmware " "Command: quartus_sta valveboard_firmware -c valveboard_firmware" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1640495503214 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1640495503432 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1640495503716 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1640495503716 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495503841 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495503841 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1640495503962 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1640495504494 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "valveboard_firmware.sdc " "Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1640495504592 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495504592 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1640495504592 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1640495504592 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1640495504607 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1640495504623 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1640495504639 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -11.085 " "Worst-case setup slack is -11.085" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.085 -2239.564 sys_clk " " -11.085 -2239.564 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495504639 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.386 " "Worst-case hold slack is 1.386" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.386 0.000 sys_clk " " 1.386 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504639 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495504639 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640495504639 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1640495504654 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 sys_clk " " -2.289 -2.289 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1640495504670 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1640495504670 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1640495504701 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640495504748 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1640495504748 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1640495504811 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 26 13:11:44 2021 " "Processing ended: Sun Dec 26 13:11:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1640495504811 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1640495504811 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1640495504811 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1640495504811 ""}

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firmware/db/valveboard_firmware.sta.rdb
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firmware/db/valveboard_firmware.sta_cmp.5_slow.tdb
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firmware/db/valveboard_firmware.tis_db_list.ddb
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6
firmware/db/valveboard_firmware.tmw_info
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@ -1,6 +0,0 @@
start_full_compilation:s:00:00:27
start_analysis_synthesis:s:00:00:16-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:06-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:03-start_full_compilation

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firmware/db/valveboard_firmware.vpr.ammdb
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11
firmware/incremental_db/README
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@ -1,11 +0,0 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
firmware/incremental_db/compiled_partitions/valveboard_firmware.db_info
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@ -1,3 +0,0 @@
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Fri Dec 24 17:19:42 2021

BIN
firmware/incremental_db/compiled_partitions/valveboard_firmware.root_partition.map.kpt
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92
firmware/output_files/valveboard_firmware.asm.rpt
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@ -1,92 +0,0 @@
Assembler report for valveboard_firmware
Sun Dec 26 13:11:41 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.pof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Dec 26 13:11:41 2021 ;
; Revision Name ; valveboard_firmware ;
; Top-level Entity Name ; valveboard_firmware ;
; Family ; MAX II ;
; Device ; EPM1270T144C5 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+-------------------------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------------------------+
; File Name ;
+-------------------------------------------------------------------+
; C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.pof ;
+-------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.pof ;
+----------------+----------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------------------------+
; JTAG usercode ; 0x005D43EC ;
; Checksum ; 0x005D4406 ;
+----------------+----------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sun Dec 26 13:11:40 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4662 megabytes
Info: Processing ended: Sun Dec 26 13:11:41 2021
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

13
firmware/output_files/valveboard_firmware.cdf
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@ -1,13 +0,0 @@
/* Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM1270T144) Path("C:/Users/guoyr/Desktop/qwert/output_files/") File("valveboard_firmware.pof") MfrSpec(OpMask(23) SEC_Device(EPM1270T144) Child_OpMask(2 7 7));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

1
firmware/output_files/valveboard_firmware.done
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@ -1 +0,0 @@
Sun Dec 26 13:11:45 2021

835
firmware/output_files/valveboard_firmware.fit.rpt
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@ -1,835 +0,0 @@
Fitter report for valveboard_firmware
Sun Dec 26 13:11:39 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. I/O Bank Usage
10. All Package Pins
11. Output Pin Default Load For Reported TCO
12. Fitter Resource Utilization by Entity
13. Delay Chain Summary
14. Control Signals
15. Global & Other Fast Signals
16. Routing Usage Summary
17. LAB Logic Elements
18. LAB-wide Signals
19. LAB Signals Sourced
20. LAB Signals Sourced Out
21. LAB Distinct Inputs
22. Fitter Device Options
23. Fitter Messages
24. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Sun Dec 26 13:11:39 2021 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; valveboard_firmware ;
; Top-level Entity Name ; valveboard_firmware ;
; Family ; MAX II ;
; Device ; EPM1270T144C5 ;
; Timing Models ; Final ;
; Total logic elements ; 460 / 1,270 ( 36 % ) ;
; Total pins ; 101 / 116 ( 87 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+---------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EPM1270T144C5 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing ; Off ; Off ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;
; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Delay Chains ; On ; On ;
; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.01 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 1.0% ;
+----------------------------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.pin.
+---------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-----------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Total logic elements ; 460 / 1,270 ( 36 % ) ;
; -- Combinational with no register ; 147 ;
; -- Register only ; 10 ;
; -- Combinational with a register ; 303 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 229 ;
; -- 3 input functions ; 111 ;
; -- 2 input functions ; 105 ;
; -- 1 input functions ; 5 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 367 ;
; -- arithmetic mode ; 93 ;
; -- qfbk mode ; 7 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 77 ;
; -- asynchronous clear/load mode ; 311 ;
; ; ;
; Total registers ; 313 / 1,270 ( 25 % ) ;
; Total LABs ; 51 / 127 ( 40 % ) ;
; Logic elements in carry chains ; 96 ;
; Virtual pins ; 0 ;
; I/O pins ; 101 / 116 ( 87 % ) ;
; -- Clock pins ; 3 / 4 ( 75 % ) ;
; ; ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ; ;
; -- Total Fixed Point DSP Blocks ; 0 ;
; -- Total Floating Point DSP Blocks ; 0 ;
; ; ;
; Global signals ; 2 ;
; -- Global clocks ; 2 / 4 ( 50 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 14.5% / 16.0% / 12.9% ;
; Peak interconnect usage (total/H/V) ; 16.1% / 16.7% / 15.4% ;
; Maximum fan-out ; 313 ;
; Highest non-global fan-out ; 181 ;
; Total fan-out ; 2471 ;
; Average fan-out ; 4.40 ;
+---------------------------------------------+-----------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
+------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
; line_sclk ; 41 ; 4 ; 3 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; line_sdata ; 39 ; 4 ; 2 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; line_sen ; 40 ; 4 ; 3 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; rst_n ; 37 ; 4 ; 1 ; 3 ; 0 ; 313 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; sys_clk ; 18 ; 1 ; 0 ; 7 ; 5 ; 313 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
+------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+-------------------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------------------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; signal_high_voltage[0] ; 43 ; 4 ; 5 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[10] ; 67 ; 4 ; 12 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[11] ; 68 ; 4 ; 13 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[12] ; 73 ; 3 ; 17 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[13] ; 74 ; 3 ; 17 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[14] ; 75 ; 3 ; 17 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[15] ; 76 ; 3 ; 17 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[16] ; 81 ; 3 ; 17 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[17] ; 84 ; 3 ; 17 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[18] ; 85 ; 3 ; 17 ; 5 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[19] ; 86 ; 3 ; 17 ; 5 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[1] ; 44 ; 4 ; 5 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[20] ; 93 ; 3 ; 17 ; 6 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[21] ; 94 ; 3 ; 17 ; 6 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[22] ; 95 ; 3 ; 17 ; 6 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[23] ; 96 ; 3 ; 17 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[24] ; 103 ; 3 ; 17 ; 8 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[25] ; 104 ; 3 ; 17 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[26] ; 105 ; 3 ; 17 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[27] ; 106 ; 3 ; 17 ; 9 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[28] ; 113 ; 2 ; 13 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[29] ; 114 ; 2 ; 12 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[2] ; 45 ; 4 ; 6 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[30] ; 117 ; 2 ; 11 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[31] ; 118 ; 2 ; 11 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[32] ; 123 ; 2 ; 9 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[33] ; 124 ; 2 ; 9 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[34] ; 125 ; 2 ; 9 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[35] ; 127 ; 2 ; 9 ; 11 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[36] ; 133 ; 2 ; 7 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[37] ; 134 ; 2 ; 7 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[38] ; 137 ; 2 ; 6 ; 11 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[39] ; 138 ; 2 ; 5 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[3] ; 48 ; 4 ; 7 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[40] ; 1 ; 1 ; 0 ; 10 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[41] ; 2 ; 1 ; 0 ; 10 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[42] ; 3 ; 1 ; 0 ; 10 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[43] ; 4 ; 1 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[44] ; 12 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[45] ; 13 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[46] ; 14 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[47] ; 15 ; 1 ; 0 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[4] ; 53 ; 4 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[5] ; 55 ; 4 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[6] ; 57 ; 4 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[7] ; 58 ; 4 ; 9 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_high_voltage[8] ; 63 ; 4 ; 10 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; signal_high_voltage[9] ; 66 ; 4 ; 12 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[0] ; 49 ; 4 ; 7 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[10] ; 71 ; 4 ; 16 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[11] ; 72 ; 4 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[12] ; 77 ; 3 ; 17 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[13] ; 78 ; 3 ; 17 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[14] ; 79 ; 3 ; 17 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[15] ; 80 ; 3 ; 17 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[16] ; 87 ; 3 ; 17 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[17] ; 88 ; 3 ; 17 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[18] ; 89 ; 3 ; 17 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[19] ; 91 ; 3 ; 17 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[1] ; 50 ; 4 ; 7 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[20] ; 97 ; 3 ; 17 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[21] ; 98 ; 3 ; 17 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[22] ; 101 ; 3 ; 17 ; 7 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[23] ; 102 ; 3 ; 17 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[24] ; 109 ; 2 ; 16 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[25] ; 110 ; 2 ; 16 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[26] ; 111 ; 2 ; 15 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[27] ; 112 ; 2 ; 14 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[28] ; 119 ; 2 ; 11 ; 11 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[29] ; 120 ; 2 ; 10 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[2] ; 51 ; 4 ; 7 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[30] ; 121 ; 2 ; 10 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[31] ; 122 ; 2 ; 10 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[32] ; 129 ; 2 ; 8 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[33] ; 130 ; 2 ; 8 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[34] ; 131 ; 2 ; 8 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[35] ; 132 ; 2 ; 7 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[36] ; 139 ; 2 ; 5 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[37] ; 140 ; 2 ; 4 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[38] ; 141 ; 2 ; 4 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[39] ; 142 ; 2 ; 3 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[3] ; 52 ; 4 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[40] ; 5 ; 1 ; 0 ; 9 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[41] ; 6 ; 1 ; 0 ; 9 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[42] ; 7 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[43] ; 8 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[44] ; 21 ; 1 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[45] ; 22 ; 1 ; 0 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[46] ; 23 ; 1 ; 0 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[47] ; 24 ; 1 ; 0 ; 6 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[4] ; 59 ; 4 ; 9 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; signal_low_voltage[5] ; 60 ; 4 ; 9 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; signal_low_voltage[6] ; 61 ; 4 ; 10 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[7] ; 62 ; 4 ; 10 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; signal_low_voltage[8] ; 69 ; 4 ; 14 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; signal_low_voltage[9] ; 70 ; 4 ; 15 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+-------------------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
+------------------------------------------------------------+
; I/O Bank Usage ;
+----------+------------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+------------------+---------------+--------------+
; 1 ; 17 / 26 ( 65 % ) ; 3.3V ; -- ;
; 2 ; 28 / 30 ( 93 % ) ; 3.3V ; -- ;
; 3 ; 28 / 30 ( 93 % ) ; 3.3V ; -- ;
; 4 ; 28 / 30 ( 93 % ) ; 3.3V ; -- ;
+----------+------------------+---------------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+-------------------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+-------------------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
; 1 ; 2 ; 1 ; signal_high_voltage[40] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 2 ; 3 ; 1 ; signal_high_voltage[41] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 3 ; 5 ; 1 ; signal_high_voltage[42] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 4 ; 7 ; 1 ; signal_high_voltage[43] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 5 ; 9 ; 1 ; signal_low_voltage[40] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 6 ; 10 ; 1 ; signal_low_voltage[41] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 7 ; 14 ; 1 ; signal_low_voltage[42] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 8 ; 15 ; 1 ; signal_low_voltage[43] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 11 ; 20 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 12 ; 21 ; 1 ; signal_high_voltage[44] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 13 ; 22 ; 1 ; signal_high_voltage[45] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 14 ; 23 ; 1 ; signal_high_voltage[46] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 15 ; 24 ; 1 ; signal_high_voltage[47] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 16 ; 25 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 17 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 18 ; 26 ; 1 ; sys_clk ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 19 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 20 ; 27 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 21 ; 28 ; 1 ; signal_low_voltage[44] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 22 ; 29 ; 1 ; signal_low_voltage[45] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 23 ; 30 ; 1 ; signal_low_voltage[46] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 24 ; 31 ; 1 ; signal_low_voltage[47] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 25 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 26 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 27 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 28 ; 36 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 29 ; 37 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 30 ; 41 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 31 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 32 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 33 ; 50 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 34 ; 51 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 35 ; 52 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 36 ; 53 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 37 ; 56 ; 4 ; rst_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 38 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 39 ; 60 ; 4 ; line_sdata ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 40 ; 62 ; 4 ; line_sen ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 41 ; 63 ; 4 ; line_sclk ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 42 ; 67 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 43 ; 68 ; 4 ; signal_high_voltage[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 44 ; 69 ; 4 ; signal_high_voltage[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 45 ; 74 ; 4 ; signal_high_voltage[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 46 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 47 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 48 ; 75 ; 4 ; signal_high_voltage[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 76 ; 4 ; signal_low_voltage[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 77 ; 4 ; signal_low_voltage[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 78 ; 4 ; signal_low_voltage[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 79 ; 4 ; signal_low_voltage[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 53 ; 80 ; 4 ; signal_high_voltage[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 54 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 55 ; 81 ; 4 ; signal_high_voltage[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 56 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 57 ; 82 ; 4 ; signal_high_voltage[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 58 ; 83 ; 4 ; signal_high_voltage[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 59 ; 84 ; 4 ; signal_low_voltage[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 60 ; 85 ; 4 ; signal_low_voltage[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 61 ; 86 ; 4 ; signal_low_voltage[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 62 ; 87 ; 4 ; signal_low_voltage[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 63 ; 88 ; 4 ; signal_high_voltage[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 64 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 65 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; 91 ; 4 ; signal_high_voltage[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 67 ; 92 ; 4 ; signal_high_voltage[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 68 ; 95 ; 4 ; signal_high_voltage[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 69 ; 98 ; 4 ; signal_low_voltage[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 70 ; 101 ; 4 ; signal_low_voltage[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 71 ; 104 ; 4 ; signal_low_voltage[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 72 ; 107 ; 4 ; signal_low_voltage[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 73 ; 111 ; 3 ; signal_high_voltage[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 74 ; 112 ; 3 ; signal_high_voltage[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 75 ; 113 ; 3 ; signal_high_voltage[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 76 ; 115 ; 3 ; signal_high_voltage[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 77 ; 118 ; 3 ; signal_low_voltage[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 78 ; 122 ; 3 ; signal_low_voltage[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 79 ; 123 ; 3 ; signal_low_voltage[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 80 ; 124 ; 3 ; signal_low_voltage[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 81 ; 127 ; 3 ; signal_high_voltage[16] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 82 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 83 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 84 ; 129 ; 3 ; signal_high_voltage[17] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 85 ; 130 ; 3 ; signal_high_voltage[18] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 86 ; 131 ; 3 ; signal_high_voltage[19] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 87 ; 132 ; 3 ; signal_low_voltage[16] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 88 ; 133 ; 3 ; signal_low_voltage[17] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 89 ; 134 ; 3 ; signal_low_voltage[18] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 90 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 91 ; 135 ; 3 ; signal_low_voltage[19] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 92 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 93 ; 136 ; 3 ; signal_high_voltage[20] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 94 ; 137 ; 3 ; signal_high_voltage[21] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 95 ; 138 ; 3 ; signal_high_voltage[22] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 96 ; 139 ; 3 ; signal_high_voltage[23] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 97 ; 140 ; 3 ; signal_low_voltage[20] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 98 ; 141 ; 3 ; signal_low_voltage[21] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 99 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 100 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 101 ; 142 ; 3 ; signal_low_voltage[22] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 102 ; 146 ; 3 ; signal_low_voltage[23] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 103 ; 147 ; 3 ; signal_high_voltage[24] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 104 ; 151 ; 3 ; signal_high_voltage[25] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 105 ; 152 ; 3 ; signal_high_voltage[26] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 106 ; 154 ; 3 ; signal_high_voltage[27] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 107 ; 156 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 108 ; 158 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
; 109 ; 164 ; 2 ; signal_low_voltage[24] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 110 ; 165 ; 2 ; signal_low_voltage[25] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 111 ; 166 ; 2 ; signal_low_voltage[26] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 112 ; 171 ; 2 ; signal_low_voltage[27] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 113 ; 174 ; 2 ; signal_high_voltage[28] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 114 ; 177 ; 2 ; signal_high_voltage[29] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 115 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 116 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 117 ; 180 ; 2 ; signal_high_voltage[30] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 118 ; 181 ; 2 ; signal_high_voltage[31] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 119 ; 182 ; 2 ; signal_low_voltage[28] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 120 ; 183 ; 2 ; signal_low_voltage[29] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 121 ; 184 ; 2 ; signal_low_voltage[30] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 122 ; 185 ; 2 ; signal_low_voltage[31] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 123 ; 186 ; 2 ; signal_high_voltage[32] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 124 ; 187 ; 2 ; signal_high_voltage[33] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 125 ; 188 ; 2 ; signal_high_voltage[34] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 126 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 127 ; 189 ; 2 ; signal_high_voltage[35] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 128 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 129 ; 190 ; 2 ; signal_low_voltage[32] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 130 ; 191 ; 2 ; signal_low_voltage[33] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 131 ; 192 ; 2 ; signal_low_voltage[34] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 132 ; 193 ; 2 ; signal_low_voltage[35] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 133 ; 194 ; 2 ; signal_high_voltage[36] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 134 ; 195 ; 2 ; signal_high_voltage[37] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 135 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 136 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 137 ; 199 ; 2 ; signal_high_voltage[38] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 138 ; 200 ; 2 ; signal_high_voltage[39] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 139 ; 201 ; 2 ; signal_low_voltage[36] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 140 ; 204 ; 2 ; signal_low_voltage[37] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 141 ; 205 ; 2 ; signal_low_voltage[38] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 142 ; 208 ; 2 ; signal_low_voltage[39] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 143 ; 212 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 144 ; 215 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+----------+------------+----------+-------------------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+-------------------------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+----------------------------+-------+------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+----------------------------+-------+------------------------+
; 3.3-V LVTTL ; 10 pF ; Not Available ;
; 3.3-V LVCMOS ; 10 pF ; Not Available ;
; 2.5 V ; 10 pF ; Not Available ;
; 1.8 V ; 10 pF ; Not Available ;
; 1.5 V ; 10 pF ; Not Available ;
; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ;
; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ;
; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+----------------------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+
; |valveboard_firmware ; 460 (460) ; 313 ; 0 ; 101 ; 0 ; 147 (147) ; 10 (10) ; 303 (303) ; 96 (96) ; 7 (7) ; |valveboard_firmware ; valveboard_firmware ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------+
; Delay Chain Summary ;
+-------------------------+----------+---------------+
; Name ; Pin Type ; Pad to Core 0 ;
+-------------------------+----------+---------------+
; signal_high_voltage[0] ; Output ; -- ;
; signal_high_voltage[1] ; Output ; -- ;
; signal_high_voltage[2] ; Output ; -- ;
; signal_high_voltage[3] ; Output ; -- ;
; signal_high_voltage[4] ; Output ; -- ;
; signal_high_voltage[5] ; Output ; -- ;
; signal_high_voltage[6] ; Output ; -- ;
; signal_high_voltage[7] ; Output ; -- ;
; signal_high_voltage[8] ; Output ; -- ;
; signal_high_voltage[9] ; Output ; -- ;
; signal_high_voltage[10] ; Output ; -- ;
; signal_high_voltage[11] ; Output ; -- ;
; signal_high_voltage[12] ; Output ; -- ;
; signal_high_voltage[13] ; Output ; -- ;
; signal_high_voltage[14] ; Output ; -- ;
; signal_high_voltage[15] ; Output ; -- ;
; signal_high_voltage[16] ; Output ; -- ;
; signal_high_voltage[17] ; Output ; -- ;
; signal_high_voltage[18] ; Output ; -- ;
; signal_high_voltage[19] ; Output ; -- ;
; signal_high_voltage[20] ; Output ; -- ;
; signal_high_voltage[21] ; Output ; -- ;
; signal_high_voltage[22] ; Output ; -- ;
; signal_high_voltage[23] ; Output ; -- ;
; signal_high_voltage[24] ; Output ; -- ;
; signal_high_voltage[25] ; Output ; -- ;
; signal_high_voltage[26] ; Output ; -- ;
; signal_high_voltage[27] ; Output ; -- ;
; signal_high_voltage[28] ; Output ; -- ;
; signal_high_voltage[29] ; Output ; -- ;
; signal_high_voltage[30] ; Output ; -- ;
; signal_high_voltage[31] ; Output ; -- ;
; signal_high_voltage[32] ; Output ; -- ;
; signal_high_voltage[33] ; Output ; -- ;
; signal_high_voltage[34] ; Output ; -- ;
; signal_high_voltage[35] ; Output ; -- ;
; signal_high_voltage[36] ; Output ; -- ;
; signal_high_voltage[37] ; Output ; -- ;
; signal_high_voltage[38] ; Output ; -- ;
; signal_high_voltage[39] ; Output ; -- ;
; signal_high_voltage[40] ; Output ; -- ;
; signal_high_voltage[41] ; Output ; -- ;
; signal_high_voltage[42] ; Output ; -- ;
; signal_high_voltage[43] ; Output ; -- ;
; signal_high_voltage[44] ; Output ; -- ;
; signal_high_voltage[45] ; Output ; -- ;
; signal_high_voltage[46] ; Output ; -- ;
; signal_high_voltage[47] ; Output ; -- ;
; signal_low_voltage[0] ; Output ; -- ;
; signal_low_voltage[1] ; Output ; -- ;
; signal_low_voltage[2] ; Output ; -- ;
; signal_low_voltage[3] ; Output ; -- ;
; signal_low_voltage[4] ; Output ; -- ;
; signal_low_voltage[5] ; Output ; -- ;
; signal_low_voltage[6] ; Output ; -- ;
; signal_low_voltage[7] ; Output ; -- ;
; signal_low_voltage[8] ; Output ; -- ;
; signal_low_voltage[9] ; Output ; -- ;
; signal_low_voltage[10] ; Output ; -- ;
; signal_low_voltage[11] ; Output ; -- ;
; signal_low_voltage[12] ; Output ; -- ;
; signal_low_voltage[13] ; Output ; -- ;
; signal_low_voltage[14] ; Output ; -- ;
; signal_low_voltage[15] ; Output ; -- ;
; signal_low_voltage[16] ; Output ; -- ;
; signal_low_voltage[17] ; Output ; -- ;
; signal_low_voltage[18] ; Output ; -- ;
; signal_low_voltage[19] ; Output ; -- ;
; signal_low_voltage[20] ; Output ; -- ;
; signal_low_voltage[21] ; Output ; -- ;
; signal_low_voltage[22] ; Output ; -- ;
; signal_low_voltage[23] ; Output ; -- ;
; signal_low_voltage[24] ; Output ; -- ;
; signal_low_voltage[25] ; Output ; -- ;
; signal_low_voltage[26] ; Output ; -- ;
; signal_low_voltage[27] ; Output ; -- ;
; signal_low_voltage[28] ; Output ; -- ;
; signal_low_voltage[29] ; Output ; -- ;
; signal_low_voltage[30] ; Output ; -- ;
; signal_low_voltage[31] ; Output ; -- ;
; signal_low_voltage[32] ; Output ; -- ;
; signal_low_voltage[33] ; Output ; -- ;
; signal_low_voltage[34] ; Output ; -- ;
; signal_low_voltage[35] ; Output ; -- ;
; signal_low_voltage[36] ; Output ; -- ;
; signal_low_voltage[37] ; Output ; -- ;
; signal_low_voltage[38] ; Output ; -- ;
; signal_low_voltage[39] ; Output ; -- ;
; signal_low_voltage[40] ; Output ; -- ;
; signal_low_voltage[41] ; Output ; -- ;
; signal_low_voltage[42] ; Output ; -- ;
; signal_low_voltage[43] ; Output ; -- ;
; signal_low_voltage[44] ; Output ; -- ;
; signal_low_voltage[45] ; Output ; -- ;
; signal_low_voltage[46] ; Output ; -- ;
; signal_low_voltage[47] ; Output ; -- ;
; sys_clk ; Input ; (0) ;
; rst_n ; Input ; (1) ;
; line_sen ; Input ; (1) ;
; line_sclk ; Input ; (1) ;
; line_sdata ; Input ; (1) ;
+-------------------------+----------+---------------+
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+-----------------------------------+--------------+---------+----------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-----------------------------------+--------------+---------+----------------------------+--------+----------------------+------------------+
; Equal0~1 ; LC_X8_Y9_N2 ; 34 ; Sync. clear ; no ; -- ; -- ;
; cache2_line_sdata[45]~50 ; LC_X11_Y5_N8 ; 48 ; Clock enable ; no ; -- ; -- ;
; cnt_for_high_voltage_time[18]~129 ; LC_X14_Y5_N5 ; 32 ; Clock enable ; no ; -- ; -- ;
; cnt_for_high_voltage_time~128 ; LC_X10_Y6_N8 ; 51 ; Sync. clear ; no ; -- ; -- ;
; fault_counter[26]~69 ; LC_X9_Y10_N7 ; 32 ; Clock enable ; no ; -- ; -- ;
; i[26]~68 ; LC_X9_Y6_N8 ; 32 ; Sync. clear ; no ; -- ; -- ;
; i[26]~69 ; LC_X9_Y6_N9 ; 32 ; Clock enable ; no ; -- ; -- ;
; rst_n ; PIN_37 ; 313 ; Async. clear, Clock enable ; yes ; Global Clock ; GCLK3 ;
; sys_clk ; PIN_18 ; 313 ; Clock ; yes ; Global Clock ; GCLK0 ;
+-----------------------------------+--------------+---------+----------------------------+--------+----------------------+------------------+
+------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+---------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+---------+----------+---------+----------------------+------------------+
; rst_n ; PIN_37 ; 313 ; Global Clock ; GCLK3 ;
; sys_clk ; PIN_18 ; 313 ; Global Clock ; GCLK0 ;
+---------+----------+---------+----------------------+------------------+
+----------------------------------------------+
; Routing Usage Summary ;
+-----------------------+----------------------+
; Routing Resource Type ; Usage ;
+-----------------------+----------------------+
; C4s ; 301 / 2,870 ( 10 % ) ;
; Direct links ; 80 / 3,938 ( 2 % ) ;
; Global clocks ; 2 / 4 ( 50 % ) ;
; LAB clocks ; 24 / 72 ( 33 % ) ;
; LUT chains ; 57 / 1,143 ( 5 % ) ;
; Local interconnects ; 638 / 3,938 ( 16 % ) ;
; R4s ; 382 / 2,832 ( 13 % ) ;
+-----------------------+----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 9.02) ; Number of LABs (Total = 51) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 3 ;
; 7 ; 3 ;
; 8 ; 4 ;
; 9 ; 8 ;
; 10 ; 31 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 2.63) ; Number of LABs (Total = 51) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 47 ;
; 1 Clock ; 48 ;
; 1 Clock enable ; 30 ;
; 1 Sync. clear ; 9 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 9.16) ; Number of LABs (Total = 51) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 4 ;
; 7 ; 2 ;
; 8 ; 3 ;
; 9 ; 9 ;
; 10 ; 30 ;
; 11 ; 2 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.35) ; Number of LABs (Total = 51) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 1 ;
; 3 ; 3 ;
; 4 ; 6 ;
; 5 ; 3 ;
; 6 ; 10 ;
; 7 ; 8 ;
; 8 ; 5 ;
; 9 ; 5 ;
; 10 ; 7 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 11.43) ; Number of LABs (Total = 51) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 5 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 8 ;
; 10 ; 6 ;
; 11 ; 5 ;
; 12 ; 3 ;
; 13 ; 4 ;
; 14 ; 2 ;
; 15 ; 1 ;
; 16 ; 4 ;
; 17 ; 3 ;
; 18 ; 1 ;
; 19 ; 0 ;
; 20 ; 0 ;
; 21 ; 0 ;
; 22 ; 0 ;
; 23 ; 1 ;
; 24 ; 0 ;
; 25 ; 2 ;
+----------------------------------------------+------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
+----------------------------------------------+--------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (119006): Selected device EPM1270T144C5 for design "valveboard_firmware"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EPM570T144C5 is compatible
Info (176445): Device EPM570T144I5 is compatible
Info (176445): Device EPM570T144A5 is compatible
Info (176445): Device EPM1270T144I5 is compatible
Info (176445): Device EPM1270T144A5 is compatible
Critical Warning (332012): Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info (332127): Assuming a default timing requirement
Info (332111): Found 1 clocks
Info (332111): Period Clock Name
Info (332111): ======== ============
Info (332111): 1.000 sys_clk
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "sys_clk" to use Global clock in PIN 18 File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 7
Info (186216): Automatically promoted some destinations of signal "rst_n" to use Global clock File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 8
Info (186217): Destination "negedge_line_sen" may be non-global or may not use global clock File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 104
Info (186217): Destination "fiter_line_sdata" may be non-global or may not use global clock File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 85
Info (186228): Pin "rst_n" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 8
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 11% of the available device resources
Info (170196): Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.46 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 5080 megabytes
Info: Processing ended: Sun Dec 26 13:11:39 2021
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Users/guoyr/Desktop/qwert/output_files/valveboard_firmware.fit.smsg.

4
firmware/output_files/valveboard_firmware.fit.smsg
View File

@ -1,4 +0,0 @@
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176244): Moving registers into LUTs to improve timing and density
Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00

11
firmware/output_files/valveboard_firmware.fit.summary
View File

@ -1,11 +0,0 @@
Fitter Status : Successful - Sun Dec 26 13:11:39 2021
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : valveboard_firmware
Top-level Entity Name : valveboard_firmware
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Total logic elements : 460 / 1,270 ( 36 % )
Total pins : 101 / 116 ( 87 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )

116
firmware/output_files/valveboard_firmware.flow.rpt
View File

@ -1,116 +0,0 @@
Flow report for valveboard_firmware
Sun Dec 26 13:11:44 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Sun Dec 26 13:11:41 2021 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; valveboard_firmware ;
; Top-level Entity Name ; valveboard_firmware ;
; Family ; MAX II ;
; Device ; EPM1270T144C5 ;
; Timing Models ; Final ;
; Total logic elements ; 460 / 1,270 ( 36 % ) ;
; Total pins ; 101 / 116 ( 87 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/26/2021 13:11:19 ;
; Main task ; Compilation ;
; Revision Name ; valveboard_firmware ;
+-------------------+---------------------+
+----------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+-----------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+-----------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 91767680144.164049547909464 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+---------------------------------------+-----------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:14 ; 1.0 ; 4700 MB ; 00:00:32 ;
; Fitter ; 00:00:05 ; 1.0 ; 5080 MB ; 00:00:05 ;
; Assembler ; 00:00:01 ; 1.0 ; 4658 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 4662 MB ; 00:00:02 ;
; Total ; 00:00:22 ; -- ; -- ; 00:00:40 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-2056RVF ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; DESKTOP-2056RVF ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; DESKTOP-2056RVF ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; DESKTOP-2056RVF ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware
quartus_fit --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware
quartus_asm --read_settings_files=off --write_settings_files=off valveboard_firmware -c valveboard_firmware
quartus_sta valveboard_firmware -c valveboard_firmware

8
firmware/output_files/valveboard_firmware.jdi
View File

@ -1,8 +0,0 @@
<sld_project_info>
<project>
<hash md5_digest_80b="21af8f9bb8b71ac0420a"/>
</project>
<file_info>
<file device="EPM1270T144C5" path="valveboard_firmware.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

381
firmware/output_files/valveboard_firmware.map.rpt
View File

@ -1,381 +0,0 @@
Analysis & Synthesis report for valveboard_firmware
Sun Dec 26 13:11:33 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Inverted Register Statistics
10. Multiplexer Restructuring Statistics (Restructuring Performed)
11. Parameter Settings for User Entity Instance: Top-level Entity: |valveboard_firmware
12. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Dec 26 13:11:33 2021 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; valveboard_firmware ;
; Top-level Entity Name ; valveboard_firmware ;
; Family ; MAX II ;
; Total logic elements ; 468 ;
; Total pins ; 101 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------------+---------------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------+---------------------+---------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+---------------------+---------------------+
; Device ; EPM1270T144C5 ; ;
; Top-level entity name ; valveboard_firmware ; valveboard_firmware ;
; Family name ; MAX II ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+------------------------------------------------------------------+---------------------+---------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
; valveboard_firmware.v ; yes ; User Verilog HDL File ; C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v ; ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------+---------+
+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
; Total logic elements ; 468 ;
; -- Combinational with no register ; 155 ;
; -- Register only ; 18 ;
; -- Combinational with a register ; 295 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 229 ;
; -- 3 input functions ; 111 ;
; -- 2 input functions ; 105 ;
; -- 1 input functions ; 5 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 375 ;
; -- arithmetic mode ; 93 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 65 ;
; -- asynchronous clear/load mode ; 311 ;
; ; ;
; Total registers ; 313 ;
; Total logic cells in carry chains ; 96 ;
; I/O pins ; 101 ;
; Maximum fan-out node ; sys_clk ;
; Maximum fan-out ; 313 ;
; Total fan-out ; 2413 ;
; Average fan-out ; 4.24 ;
+---------------------------------------------+---------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+
; |valveboard_firmware ; 468 (468) ; 313 ; 0 ; 101 ; 0 ; 155 (155) ; 18 (18) ; 295 (295) ; 96 (96) ; 0 (0) ; |valveboard_firmware ; valveboard_firmware ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 313 ;
; Number of registers using Synchronous Clear ; 65 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 311 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 146 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------+
; Inverted Register Statistics ;
+-------------------------------------------+---------+
; Inverted Register ; Fan out ;
+-------------------------------------------+---------+
; signal_high_voltage[0]~reg0 ; 1 ;
; signal_high_voltage[1]~reg0 ; 1 ;
; signal_high_voltage[2]~reg0 ; 1 ;
; signal_high_voltage[3]~reg0 ; 1 ;
; signal_high_voltage[4]~reg0 ; 1 ;
; signal_high_voltage[5]~reg0 ; 1 ;
; signal_high_voltage[6]~reg0 ; 1 ;
; signal_high_voltage[7]~reg0 ; 1 ;
; signal_high_voltage[8]~reg0 ; 1 ;
; signal_high_voltage[9]~reg0 ; 1 ;
; signal_high_voltage[10]~reg0 ; 1 ;
; signal_high_voltage[11]~reg0 ; 1 ;
; signal_high_voltage[12]~reg0 ; 1 ;
; signal_high_voltage[13]~reg0 ; 1 ;
; signal_high_voltage[14]~reg0 ; 1 ;
; signal_high_voltage[15]~reg0 ; 1 ;
; signal_high_voltage[16]~reg0 ; 1 ;
; signal_high_voltage[17]~reg0 ; 1 ;
; signal_high_voltage[18]~reg0 ; 1 ;
; signal_high_voltage[19]~reg0 ; 1 ;
; signal_high_voltage[20]~reg0 ; 1 ;
; signal_high_voltage[21]~reg0 ; 1 ;
; signal_high_voltage[22]~reg0 ; 1 ;
; signal_high_voltage[23]~reg0 ; 1 ;
; signal_high_voltage[24]~reg0 ; 1 ;
; signal_high_voltage[25]~reg0 ; 1 ;
; signal_high_voltage[26]~reg0 ; 1 ;
; signal_high_voltage[27]~reg0 ; 1 ;
; signal_high_voltage[28]~reg0 ; 1 ;
; signal_high_voltage[29]~reg0 ; 1 ;
; signal_high_voltage[30]~reg0 ; 1 ;
; signal_high_voltage[31]~reg0 ; 1 ;
; signal_high_voltage[32]~reg0 ; 1 ;
; signal_high_voltage[33]~reg0 ; 1 ;
; signal_high_voltage[34]~reg0 ; 1 ;
; signal_high_voltage[35]~reg0 ; 1 ;
; signal_high_voltage[36]~reg0 ; 1 ;
; signal_high_voltage[37]~reg0 ; 1 ;
; signal_high_voltage[38]~reg0 ; 1 ;
; signal_high_voltage[39]~reg0 ; 1 ;
; signal_high_voltage[40]~reg0 ; 1 ;
; signal_high_voltage[41]~reg0 ; 1 ;
; signal_high_voltage[42]~reg0 ; 1 ;
; signal_high_voltage[43]~reg0 ; 1 ;
; signal_high_voltage[44]~reg0 ; 1 ;
; signal_high_voltage[45]~reg0 ; 1 ;
; signal_high_voltage[46]~reg0 ; 1 ;
; signal_high_voltage[47]~reg0 ; 1 ;
; signal_low_voltage[0]~reg0 ; 1 ;
; signal_low_voltage[1]~reg0 ; 1 ;
; signal_low_voltage[2]~reg0 ; 1 ;
; signal_low_voltage[3]~reg0 ; 1 ;
; signal_low_voltage[4]~reg0 ; 1 ;
; signal_low_voltage[5]~reg0 ; 1 ;
; signal_low_voltage[6]~reg0 ; 1 ;
; signal_low_voltage[7]~reg0 ; 1 ;
; signal_low_voltage[8]~reg0 ; 1 ;
; signal_low_voltage[9]~reg0 ; 1 ;
; signal_low_voltage[10]~reg0 ; 1 ;
; signal_low_voltage[11]~reg0 ; 1 ;
; signal_low_voltage[12]~reg0 ; 1 ;
; signal_low_voltage[13]~reg0 ; 1 ;
; signal_low_voltage[14]~reg0 ; 1 ;
; signal_low_voltage[15]~reg0 ; 1 ;
; signal_low_voltage[16]~reg0 ; 1 ;
; signal_low_voltage[17]~reg0 ; 1 ;
; signal_low_voltage[18]~reg0 ; 1 ;
; signal_low_voltage[19]~reg0 ; 1 ;
; signal_low_voltage[20]~reg0 ; 1 ;
; signal_low_voltage[21]~reg0 ; 1 ;
; signal_low_voltage[22]~reg0 ; 1 ;
; signal_low_voltage[23]~reg0 ; 1 ;
; signal_low_voltage[24]~reg0 ; 1 ;
; signal_low_voltage[25]~reg0 ; 1 ;
; signal_low_voltage[26]~reg0 ; 1 ;
; signal_low_voltage[27]~reg0 ; 1 ;
; signal_low_voltage[28]~reg0 ; 1 ;
; signal_low_voltage[29]~reg0 ; 1 ;
; signal_low_voltage[30]~reg0 ; 1 ;
; signal_low_voltage[31]~reg0 ; 1 ;
; signal_low_voltage[32]~reg0 ; 1 ;
; signal_low_voltage[33]~reg0 ; 1 ;
; signal_low_voltage[34]~reg0 ; 1 ;
; signal_low_voltage[35]~reg0 ; 1 ;
; signal_low_voltage[36]~reg0 ; 1 ;
; signal_low_voltage[37]~reg0 ; 1 ;
; signal_low_voltage[38]~reg0 ; 1 ;
; signal_low_voltage[39]~reg0 ; 1 ;
; signal_low_voltage[40]~reg0 ; 1 ;
; signal_low_voltage[41]~reg0 ; 1 ;
; signal_low_voltage[42]~reg0 ; 1 ;
; signal_low_voltage[43]~reg0 ; 1 ;
; signal_low_voltage[44]~reg0 ; 1 ;
; signal_low_voltage[45]~reg0 ; 1 ;
; signal_low_voltage[46]~reg0 ; 1 ;
; signal_low_voltage[47]~reg0 ; 1 ;
; cache2_line_sdata[0] ; 2 ;
; cache2_line_sdata[1] ; 2 ;
; cache2_line_sdata[2] ; 2 ;
; cache2_line_sdata[3] ; 2 ;
; Total number of inverted registers = 197* ; ;
+-------------------------------------------+---------+
* Table truncated at 100 items. To change the number of inverted registers reported, set the "Number of Inverted Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------+
; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |valveboard_firmware|fault_counter[26] ;
; 4:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |valveboard_firmware|i[26] ;
; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |valveboard_firmware|cnt_for_high_voltage_time[18] ;
; 3:1 ; 48 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |valveboard_firmware|signal_high_voltage[3]~reg0 ;
; 3:1 ; 48 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |valveboard_firmware|cache2_line_sdata[45] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------+
+--------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |valveboard_firmware ;
+---------------------------------+----------------------------------+-----------------+
; Parameter Name ; Value ; Type ;
+---------------------------------+----------------------------------+-----------------+
; CHANNEL_NUM ; 48 ; Signed Integer ;
; CHANNEL_NUM_MINUS_1 ; 47 ; Signed Integer ;
; HIGH_VOLTAGE_TIME ; 00000000000000000001110011101000 ; Unsigned Binary ;
; HIGH_VOLTAGE_TIME_MINUS_1 ; 00000000000000000001110011100111 ; Unsigned Binary ;
; FAULT_COUNTER_THRESHOLD ; 00000001001100010010110100000000 ; Unsigned Binary ;
; FAULT_COUNTER_THRESHOLD_MINUS_1 ; 00000001001100010010110011111111 ; Unsigned Binary ;
; FAULT_COUNTER_THRESHOLD_PLUS_1 ; 00000001001100010010110100000001 ; Unsigned Binary ;
+---------------------------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sun Dec 26 13:11:19 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off valveboard_firmware -c valveboard_firmware
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file valveboard_firmware.v
Info (12023): Found entity 1: valveboard_firmware File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 6
Info (12021): Found 1 design units, including 1 entities, in source file tb_valveboard_firmware.v
Info (12023): Found entity 1: tb_valveboard_firmware File: C:/Users/guoyr/Desktop/qwert/tb_valveboard_firmware.v Line: 2
Info (12127): Elaborating entity "valveboard_firmware" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at valveboard_firmware.v(88): truncated value with size 32 to match size of target (5) File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 88
Info (18000): Registers with preset signals will power-up high File: C:/Users/guoyr/Desktop/qwert/valveboard_firmware.v Line: 288
Info (21057): Implemented 569 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 5 input pins
Info (21059): Implemented 96 output pins
Info (21061): Implemented 468 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 4700 megabytes
Info: Processing ended: Sun Dec 26 13:11:33 2021
Info: Elapsed time: 00:00:14
Info: Total CPU time (on all processors): 00:00:32

9
firmware/output_files/valveboard_firmware.map.summary
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@ -1,9 +0,0 @@
Analysis & Synthesis Status : Successful - Sun Dec 26 13:11:33 2021
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : valveboard_firmware
Top-level Entity Name : valveboard_firmware
Family : MAX II
Total logic elements : 468
Total pins : 101
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )

211
firmware/output_files/valveboard_firmware.pin
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@ -1,211 +0,0 @@
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
CHIP "valveboard_firmware" ASSIGNED TO AN: EPM1270T144C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
signal_high_voltage[40] : 1 : output : 3.3-V LVTTL : : 1 : Y
signal_high_voltage[41] : 2 : output : 3.3-V LVTTL : : 1 : Y
signal_high_voltage[42] : 3 : output : 3.3-V LVTTL : : 1 : Y
signal_high_voltage[43] : 4 : output : 3.3-V LVTTL : : 1 : Y
signal_low_voltage[40] : 5 : output : 3.3-V LVTTL : : 1 : Y
signal_low_voltage[41] : 6 : output : 3.3-V LVTTL : : 1 : Y
signal_low_voltage[42] : 7 : output : 3.3-V LVTTL : : 1 : Y
signal_low_voltage[43] : 8 : output : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 9 : power : : 3.3V : 1 :
GNDIO : 10 : gnd : : : :
GND* : 11 : : : : 1 :
signal_high_voltage[44] : 12 : output : 3.3-V LVTTL : : 1 : Y
signal_high_voltage[45] : 13 : output : 3.3-V LVTTL : : 1 : Y
signal_high_voltage[46] : 14 : output : 3.3-V LVTTL : : 1 : Y
signal_high_voltage[47] : 15 : output : 3.3-V LVTTL : : 1 : Y
GND* : 16 : : : : 1 :
GNDINT : 17 : gnd : : : :
sys_clk : 18 : input : 3.3-V LVTTL : : 1 : Y
VCCINT : 19 : power : : 2.5V/3.3V : :
GND* : 20 : : : : 1 :
signal_low_voltage[44] : 21 : output : 3.3-V LVTTL : : 1 : Y
signal_low_voltage[45] : 22 : output : 3.3-V LVTTL : : 1 : Y
signal_low_voltage[46] : 23 : output : 3.3-V LVTTL : : 1 : Y
signal_low_voltage[47] : 24 : output : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 25 : power : : 3.3V : 1 :
GNDIO : 26 : gnd : : : :
GND* : 27 : : : : 1 :
GND* : 28 : : : : 1 :
GND* : 29 : : : : 1 :
GND* : 30 : : : : 1 :
GND* : 31 : : : : 1 :
GND* : 32 : : : : 1 :
TMS : 33 : input : : : 1 :
TDI : 34 : input : : : 1 :
TCK : 35 : input : : : 1 :
TDO : 36 : output : : : 1 :
rst_n : 37 : input : 3.3-V LVTTL : : 4 : Y
GND* : 38 : : : : 4 :
line_sdata : 39 : input : 3.3-V LVTTL : : 4 : Y
line_sen : 40 : input : 3.3-V LVTTL : : 4 : Y
line_sclk : 41 : input : 3.3-V LVTTL : : 4 : Y
GND* : 42 : : : : 4 :
signal_high_voltage[0] : 43 : output : 3.3-V LVTTL : : 4 : Y
signal_high_voltage[1] : 44 : output : 3.3-V LVTTL : : 4 : Y
signal_high_voltage[2] : 45 : output : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 46 : power : : 3.3V : 4 :
GNDIO : 47 : gnd : : : :
signal_high_voltage[3] : 48 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[0] : 49 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[1] : 50 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[2] : 51 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[3] : 52 : output : 3.3-V LVTTL : : 4 : Y
signal_high_voltage[4] : 53 : output : 3.3-V LVTTL : : 4 : Y
GNDINT : 54 : gnd : : : :
signal_high_voltage[5] : 55 : output : 3.3-V LVTTL : : 4 : Y
VCCINT : 56 : power : : 2.5V/3.3V : :
signal_high_voltage[6] : 57 : output : 3.3-V LVTTL : : 4 : Y
signal_high_voltage[7] : 58 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[4] : 59 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[5] : 60 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[6] : 61 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[7] : 62 : output : 3.3-V LVTTL : : 4 : Y
signal_high_voltage[8] : 63 : output : 3.3-V LVTTL : : 4 : Y
VCCIO4 : 64 : power : : 3.3V : 4 :
GNDIO : 65 : gnd : : : :
signal_high_voltage[9] : 66 : output : 3.3-V LVTTL : : 4 : Y
signal_high_voltage[10] : 67 : output : 3.3-V LVTTL : : 4 : Y
signal_high_voltage[11] : 68 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[8] : 69 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[9] : 70 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[10] : 71 : output : 3.3-V LVTTL : : 4 : Y
signal_low_voltage[11] : 72 : output : 3.3-V LVTTL : : 4 : Y
signal_high_voltage[12] : 73 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[13] : 74 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[14] : 75 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[15] : 76 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[12] : 77 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[13] : 78 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[14] : 79 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[15] : 80 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[16] : 81 : output : 3.3-V LVTTL : : 3 : Y
VCCIO3 : 82 : power : : 3.3V : 3 :
GNDIO : 83 : gnd : : : :
signal_high_voltage[17] : 84 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[18] : 85 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[19] : 86 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[16] : 87 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[17] : 88 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[18] : 89 : output : 3.3-V LVTTL : : 3 : Y
VCCINT : 90 : power : : 2.5V/3.3V : :
signal_low_voltage[19] : 91 : output : 3.3-V LVTTL : : 3 : Y
GNDINT : 92 : gnd : : : :
signal_high_voltage[20] : 93 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[21] : 94 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[22] : 95 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[23] : 96 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[20] : 97 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[21] : 98 : output : 3.3-V LVTTL : : 3 : Y
GNDIO : 99 : gnd : : : :
VCCIO3 : 100 : power : : 3.3V : 3 :
signal_low_voltage[22] : 101 : output : 3.3-V LVTTL : : 3 : Y
signal_low_voltage[23] : 102 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[24] : 103 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[25] : 104 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[26] : 105 : output : 3.3-V LVTTL : : 3 : Y
signal_high_voltage[27] : 106 : output : 3.3-V LVTTL : : 3 : Y
GND* : 107 : : : : 3 :
GND* : 108 : : : : 3 :
signal_low_voltage[24] : 109 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[25] : 110 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[26] : 111 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[27] : 112 : output : 3.3-V LVTTL : : 2 : Y
signal_high_voltage[28] : 113 : output : 3.3-V LVTTL : : 2 : Y
signal_high_voltage[29] : 114 : output : 3.3-V LVTTL : : 2 : Y
GNDIO : 115 : gnd : : : :
VCCIO2 : 116 : power : : 3.3V : 2 :
signal_high_voltage[30] : 117 : output : 3.3-V LVTTL : : 2 : Y
signal_high_voltage[31] : 118 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[28] : 119 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[29] : 120 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[30] : 121 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[31] : 122 : output : 3.3-V LVTTL : : 2 : Y
signal_high_voltage[32] : 123 : output : 3.3-V LVTTL : : 2 : Y
signal_high_voltage[33] : 124 : output : 3.3-V LVTTL : : 2 : Y
signal_high_voltage[34] : 125 : output : 3.3-V LVTTL : : 2 : Y
VCCINT : 126 : power : : 2.5V/3.3V : :
signal_high_voltage[35] : 127 : output : 3.3-V LVTTL : : 2 : Y
GNDINT : 128 : gnd : : : :
signal_low_voltage[32] : 129 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[33] : 130 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[34] : 131 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[35] : 132 : output : 3.3-V LVTTL : : 2 : Y
signal_high_voltage[36] : 133 : output : 3.3-V LVTTL : : 2 : Y
signal_high_voltage[37] : 134 : output : 3.3-V LVTTL : : 2 : Y
GNDIO : 135 : gnd : : : :
VCCIO2 : 136 : power : : 3.3V : 2 :
signal_high_voltage[38] : 137 : output : 3.3-V LVTTL : : 2 : Y
signal_high_voltage[39] : 138 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[36] : 139 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[37] : 140 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[38] : 141 : output : 3.3-V LVTTL : : 2 : Y
signal_low_voltage[39] : 142 : output : 3.3-V LVTTL : : 2 : Y
GND* : 143 : : : : 2 :
GND* : 144 : : : : 2 :

BIN
firmware/output_files/valveboard_firmware.pof
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firmware/output_files/valveboard_firmware.sld
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<sld_project_info/>

691
firmware/output_files/valveboard_firmware.sta.rpt
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Timing Analyzer report for valveboard_firmware
Sun Dec 26 13:11:44 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Fmax Summary
6. Setup Summary
7. Hold Summary
8. Recovery Summary
9. Removal Summary
10. Minimum Pulse Width Summary
11. Setup: 'sys_clk'
12. Hold: 'sys_clk'
13. Setup Transfers
14. Hold Transfers
15. Report TCCS
16. Report RSKM
17. Unconstrained Paths Summary
18. Clock Status Summary
19. Unconstrained Input Ports
20. Unconstrained Output Ports
21. Unconstrained Input Ports
22. Unconstrained Output Ports
23. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; valveboard_firmware ;
; Device Family ; MAX II ;
; Device Name ; EPM1270T144C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
; sys_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { sys_clk } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
+-------------------------------------------------+
; Fmax Summary ;
+-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 82.75 MHz ; 82.75 MHz ; sys_clk ; ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+-----------------------------------+
; Setup Summary ;
+---------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+---------+---------+---------------+
; sys_clk ; -11.085 ; -2239.564 ;
+---------+---------+---------------+
+---------------------------------+
; Hold Summary ;
+---------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+---------+-------+---------------+
; sys_clk ; 1.386 ; 0.000 ;
+---------+-------+---------------+
--------------------
; Recovery Summary ;
--------------------
No paths to report.
-------------------
; Removal Summary ;
-------------------
No paths to report.
+----------------------------------+
; Minimum Pulse Width Summary ;
+---------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+---------+--------+---------------+
; sys_clk ; -2.289 ; -2.289 ;
+---------+--------+---------------+
+-------------------------------------------------------------------------------------------------------------------+
; Setup: 'sys_clk' ;
+---------+-----------+-----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------+-----------------------+--------------+-------------+--------------+------------+------------+
; -11.085 ; i[29] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.752 ;
; -11.085 ; i[29] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.752 ;
; -11.085 ; i[29] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.752 ;
; -11.040 ; i[29] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.707 ;
; -11.040 ; i[29] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.707 ;
; -10.937 ; i[28] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.604 ;
; -10.937 ; i[28] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.604 ;
; -10.937 ; i[28] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.604 ;
; -10.902 ; i[29] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.569 ;
; -10.902 ; i[29] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.569 ;
; -10.902 ; i[29] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.569 ;
; -10.895 ; i[11] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.562 ;
; -10.895 ; i[11] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.562 ;
; -10.895 ; i[11] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.562 ;
; -10.892 ; i[28] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.559 ;
; -10.892 ; i[28] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.559 ;
; -10.862 ; i[25] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.529 ;
; -10.862 ; i[25] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.529 ;
; -10.862 ; i[25] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.529 ;
; -10.850 ; i[11] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.517 ;
; -10.850 ; i[11] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.517 ;
; -10.817 ; i[25] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.484 ;
; -10.817 ; i[25] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.484 ;
; -10.754 ; i[28] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.421 ;
; -10.754 ; i[28] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.421 ;
; -10.754 ; i[28] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.421 ;
; -10.753 ; i[3] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.420 ;
; -10.753 ; i[3] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.420 ;
; -10.753 ; i[3] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.420 ;
; -10.750 ; i[26] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.417 ;
; -10.750 ; i[26] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.417 ;
; -10.750 ; i[26] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.417 ;
; -10.712 ; i[11] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.379 ;
; -10.712 ; i[11] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.379 ;
; -10.712 ; i[11] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.379 ;
; -10.708 ; i[3] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.375 ;
; -10.708 ; i[3] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.375 ;
; -10.705 ; i[26] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.372 ;
; -10.705 ; i[26] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.372 ;
; -10.679 ; i[25] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.346 ;
; -10.679 ; i[25] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.346 ;
; -10.679 ; i[25] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.346 ;
; -10.670 ; i[15] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.337 ;
; -10.670 ; i[15] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.337 ;
; -10.670 ; i[15] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.337 ;
; -10.663 ; i[29] ; cache_line_sdata[11] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.330 ;
; -10.662 ; i[12] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.329 ;
; -10.662 ; i[12] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.329 ;
; -10.662 ; i[12] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.329 ;
; -10.634 ; i[24] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.301 ;
; -10.634 ; i[24] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.301 ;
; -10.634 ; i[24] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.301 ;
; -10.625 ; i[15] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.292 ;
; -10.625 ; i[15] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.292 ;
; -10.617 ; i[12] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.284 ;
; -10.617 ; i[12] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.284 ;
; -10.609 ; i[2] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.276 ;
; -10.609 ; i[2] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.276 ;
; -10.609 ; i[2] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.276 ;
; -10.604 ; i[1] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.271 ;
; -10.604 ; i[1] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.271 ;
; -10.604 ; i[1] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.271 ;
; -10.599 ; i[13] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.266 ;
; -10.599 ; i[13] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.266 ;
; -10.599 ; i[13] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.266 ;
; -10.589 ; i[24] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.256 ;
; -10.589 ; i[24] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.256 ;
; -10.580 ; i[20] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.247 ;
; -10.580 ; i[20] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.247 ;
; -10.580 ; i[20] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.247 ;
; -10.570 ; i[3] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.237 ;
; -10.570 ; i[3] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.237 ;
; -10.570 ; i[3] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.237 ;
; -10.567 ; i[26] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.234 ;
; -10.567 ; i[26] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.234 ;
; -10.567 ; i[26] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.234 ;
; -10.564 ; i[2] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.231 ;
; -10.564 ; i[2] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.231 ;
; -10.559 ; i[1] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.226 ;
; -10.559 ; i[1] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.226 ;
; -10.554 ; i[13] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ;
; -10.554 ; i[13] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ;
; -10.554 ; i[14] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ;
; -10.554 ; i[14] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ;
; -10.554 ; i[14] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.221 ;
; -10.535 ; i[20] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.202 ;
; -10.535 ; i[20] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.202 ;
; -10.516 ; i[22] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.183 ;
; -10.516 ; i[22] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.183 ;
; -10.516 ; i[22] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.183 ;
; -10.515 ; i[28] ; cache_line_sdata[11] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.182 ;
; -10.509 ; i[14] ; cache2_line_sdata[19] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.176 ;
; -10.509 ; i[14] ; cache2_line_sdata[25] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.176 ;
; -10.504 ; i[17] ; cache2_line_sdata[17] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.171 ;
; -10.504 ; i[17] ; cache2_line_sdata[20] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.171 ;
; -10.504 ; i[17] ; cache2_line_sdata[21] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.171 ;
; -10.487 ; i[15] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.154 ;
; -10.487 ; i[15] ; cache2_line_sdata[14] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.154 ;
; -10.487 ; i[15] ; cache2_line_sdata[15] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.154 ;
; -10.479 ; i[12] ; cache2_line_sdata[13] ; sys_clk ; sys_clk ; 1.000 ; 0.000 ; 11.146 ;
+---------+-----------+-----------------------+--------------+-------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'sys_clk' ;
+-------+-----------------------------------------+-----------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------+-----------------------------------------+--------------+-------------+--------------+------------+------------+
; 1.386 ; tmp_cache_line_sdata[1] ; tmp_cache_line_sdata[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.607 ;
; 1.387 ; tmp_cache_line_sdata[3] ; tmp_cache_line_sdata[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.608 ;
; 1.396 ; cache_line_sclk[1] ; cache_line_sclk[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.617 ;
; 1.412 ; cache_line_sen[3] ; cache_line_sen[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.633 ;
; 1.424 ; cache_line_sen[1] ; cache_line_sen[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.645 ;
; 1.642 ; tmp_cache_line_sdata[2] ; tmp_cache_line_sdata[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.863 ;
; 1.653 ; tmp_cache_line_sdata[4] ; fiter_line_sdata ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.874 ;
; 1.655 ; cache_line_sclk[0] ; cache_line_sclk[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.876 ;
; 1.656 ; tmp_cache_line_sdata[0] ; tmp_cache_line_sdata[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.877 ;
; 1.659 ; cache2_line_sdata[21] ; signal_low_voltage[21]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.880 ;
; 1.662 ; cache2_line_sdata[13] ; signal_high_voltage[13]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.883 ;
; 1.662 ; cache2_line_sdata[14] ; signal_low_voltage[14]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.883 ;
; 1.662 ; cache_line_sen[0] ; cache_line_sen[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.883 ;
; 1.662 ; cache_line_sclk[2] ; cache_line_sclk[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.883 ;
; 1.664 ; cache_line_sdata[35] ; cache2_line_sdata[35] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.885 ;
; 1.666 ; cache2_line_sdata[7] ; signal_high_voltage[7]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.887 ;
; 1.667 ; cache2_line_sdata[14] ; signal_high_voltage[14]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.888 ;
; 1.671 ; cache2_line_sdata[17] ; signal_low_voltage[17]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.892 ;
; 1.678 ; cache2_line_sdata[16] ; signal_low_voltage[16]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.899 ;
; 1.679 ; cache2_line_sdata[27] ; signal_high_voltage[27]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.900 ;
; 1.679 ; cache2_line_sdata[19] ; signal_low_voltage[19]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.900 ;
; 1.681 ; cache2_line_sdata[22] ; signal_low_voltage[22]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.902 ;
; 1.682 ; cache2_line_sdata[27] ; signal_low_voltage[27]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.903 ;
; 1.685 ; cache2_line_sdata[22] ; signal_high_voltage[22]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.906 ;
; 1.685 ; cache2_line_sdata[25] ; signal_low_voltage[25]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.906 ;
; 1.686 ; cache2_line_sdata[16] ; signal_high_voltage[16]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.907 ;
; 1.686 ; cache2_line_sdata[38] ; signal_low_voltage[38]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.907 ;
; 1.687 ; cache2_line_sdata[38] ; signal_high_voltage[38]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.908 ;
; 1.748 ; cache_line_sclk[3] ; cache_line_sclk[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.969 ;
; 1.867 ; cache_enable_count_high_voltage_time[0] ; cache_enable_count_high_voltage_time[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.088 ;
; 1.875 ; cache_line_sen[4] ; negedge_line_sen ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.096 ;
; 1.898 ; cache_line_sdata[14] ; cache_line_sdata[14] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ;
; 1.898 ; cache_line_sdata[26] ; cache_line_sdata[26] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ;
; 1.898 ; cache_line_sdata[42] ; cache_line_sdata[42] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.119 ;
; 1.899 ; cache_line_sdata[9] ; cache_line_sdata[9] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.120 ;
; 1.907 ; cache_line_sdata[20] ; cache_line_sdata[20] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.128 ;
; 1.907 ; cache_line_sdata[21] ; cache_line_sdata[21] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.128 ;
; 1.908 ; cache_line_sdata[4] ; cache_line_sdata[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.129 ;
; 1.908 ; cache_line_sdata[12] ; cache_line_sdata[12] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.129 ;
; 1.908 ; cache_line_sdata[19] ; cache_line_sdata[19] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.129 ;
; 1.908 ; cache_line_sdata[28] ; cache_line_sdata[28] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.129 ;
; 1.909 ; cache_line_sdata[22] ; cache_line_sdata[22] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.130 ;
; 1.916 ; cache_line_sdata[45] ; cache_line_sdata[45] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.137 ;
; 1.918 ; cache_line_sdata[1] ; cache_line_sdata[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.139 ;
; 1.918 ; cache_line_sdata[17] ; cache_line_sdata[17] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.139 ;
; 1.919 ; cache_line_sdata[0] ; cache_line_sdata[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.140 ;
; 1.920 ; cache2_line_sdata[31] ; signal_high_voltage[31]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.141 ;
; 1.922 ; cache_line_sdata[0] ; cache2_line_sdata[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.143 ;
; 1.923 ; cache2_line_sdata[20] ; signal_high_voltage[20]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.144 ;
; 1.924 ; cache_line_sdata[1] ; cache2_line_sdata[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.145 ;
; 1.925 ; cache2_line_sdata[20] ; signal_low_voltage[20]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.146 ;
; 1.925 ; cache2_line_sdata[31] ; signal_low_voltage[31]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.146 ;
; 1.929 ; cache_line_sdata[32] ; cache_line_sdata[32] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.150 ;
; 1.930 ; cache_line_sdata[32] ; cache2_line_sdata[32] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.151 ;
; 1.934 ; cache_line_sdata[31] ; cache_line_sdata[31] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.155 ;
; 1.935 ; cache2_line_sdata[26] ; signal_high_voltage[26]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.156 ;
; 1.939 ; cache2_line_sdata[29] ; signal_high_voltage[29]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.160 ;
; 1.940 ; cache2_line_sdata[26] ; signal_low_voltage[26]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.161 ;
; 1.940 ; cache2_line_sdata[29] ; signal_low_voltage[29]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.161 ;
; 1.941 ; cache2_line_sdata[28] ; signal_low_voltage[28]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.162 ;
; 1.947 ; cache2_line_sdata[30] ; signal_low_voltage[30]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.168 ;
; 1.955 ; cache2_line_sdata[46] ; signal_high_voltage[46]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.176 ;
; 1.958 ; cache2_line_sdata[42] ; signal_high_voltage[42]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.179 ;
; 2.013 ; cache2_line_sdata[8] ; signal_low_voltage[8]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.234 ;
; 2.017 ; cache2_line_sdata[8] ; signal_high_voltage[8]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.238 ;
; 2.107 ; cache_line_sdata[8] ; cache_line_sdata[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ;
; 2.107 ; cache_line_sdata[25] ; cache_line_sdata[25] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ;
; 2.107 ; cache_line_sdata[30] ; cache_line_sdata[30] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.328 ;
; 2.111 ; filter_line_sen ; filter_line_sen ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.332 ;
; 2.116 ; i[6] ; i[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ;
; 2.116 ; i[16] ; i[16] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ;
; 2.116 ; fault_counter[16] ; fault_counter[16] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ;
; 2.116 ; fault_counter[6] ; fault_counter[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.337 ;
; 2.117 ; i[13] ; i[13] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; i[23] ; i[23] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; fault_counter[13] ; fault_counter[13] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; fault_counter[23] ; fault_counter[23] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; cache_line_sdata[2] ; cache_line_sdata[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; cache_line_sdata[23] ; cache_line_sdata[23] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; cache_line_sdata[34] ; cache_line_sdata[34] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; cache_line_sdata[36] ; cache_line_sdata[36] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; cache_line_sdata[44] ; cache_line_sdata[44] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.338 ;
; 2.123 ; cache2_line_sdata[6] ; signal_low_voltage[6]~reg0 ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.344 ;
; 2.126 ; i[5] ; i[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; i[7] ; i[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; i[8] ; i[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; i[15] ; i[15] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; i[17] ; i[17] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; i[18] ; i[18] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; i[25] ; i[25] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; fault_counter[15] ; fault_counter[15] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; fault_counter[8] ; fault_counter[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; fault_counter[7] ; fault_counter[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; fault_counter[17] ; fault_counter[17] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; fault_counter[18] ; fault_counter[18] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; fault_counter[25] ; fault_counter[25] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; fault_counter[26] ; fault_counter[26] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.347 ;
; 2.127 ; cache_line_sdata[7] ; cache_line_sdata[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ;
; 2.127 ; cache_line_sdata[24] ; cache_line_sdata[24] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ;
; 2.127 ; cache_line_sdata[33] ; cache_line_sdata[33] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 2.348 ;
+-------+-----------------------------------------+-----------------------------------------+--------------+-------------+--------------+------------+------------+
+-------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; sys_clk ; sys_clk ; 10137 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; sys_clk ; sys_clk ; 10137 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 4 ; 4 ;
; Unconstrained Input Port Paths ; 353 ; 353 ;
; Unconstrained Output Ports ; 96 ; 96 ;
; Unconstrained Output Port Paths ; 96 ; 96 ;
+---------------------------------+-------+------+
+----------------------------------------+
; Clock Status Summary ;
+---------+---------+------+-------------+
; Target ; Clock ; Type ; Status ;
+---------+---------+------+-------------+
; sys_clk ; sys_clk ; Base ; Constrained ;
+---------+---------+------+-------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; line_sclk ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; line_sdata ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; line_sen ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------------------+---------------------------------------------------------------------------------------+
; signal_high_voltage[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[14] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[15] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[16] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[17] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[18] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[19] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[20] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[21] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[22] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[23] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[24] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[25] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[26] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[27] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[28] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[29] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[30] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[31] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[32] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[33] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[34] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[35] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[36] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[37] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[38] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[39] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[40] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[41] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[42] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[43] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[44] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[45] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[46] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[47] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[14] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[15] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[16] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[17] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[18] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[19] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[20] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[21] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[22] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[23] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[24] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[25] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[26] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[27] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[28] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[29] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[30] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[31] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[32] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[33] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[34] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[35] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[36] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[37] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[38] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[39] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[40] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[41] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[42] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[43] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[44] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[45] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[46] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[47] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; line_sclk ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; line_sdata ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; line_sen ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------------------+---------------------------------------------------------------------------------------+
; signal_high_voltage[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[14] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[15] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[16] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[17] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[18] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[19] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[20] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[21] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[22] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[23] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[24] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[25] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[26] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[27] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[28] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[29] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[30] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[31] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[32] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[33] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[34] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[35] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[36] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[37] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[38] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[39] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[40] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[41] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[42] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[43] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[44] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[45] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[46] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_high_voltage[47] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[14] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[15] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[16] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[17] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[18] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[19] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[20] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[21] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[22] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[23] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[24] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[25] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[26] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[27] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[28] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[29] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[30] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[31] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[32] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[33] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[34] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[35] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[36] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[37] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[38] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[39] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[40] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[41] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[42] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[43] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[44] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[45] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[46] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; signal_low_voltage[47] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sun Dec 26 13:11:42 2021
Info: Command: quartus_sta valveboard_firmware -c valveboard_firmware
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Critical Warning (332012): Synopsys Design Constraints File file not found: 'valveboard_firmware.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name sys_clk sys_clk
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -11.085
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -11.085 -2239.564 sys_clk
Info (332146): Worst-case hold slack is 1.386
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 1.386 0.000 sys_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.289
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.289 -2.289 sys_clk
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 4662 megabytes
Info: Processing ended: Sun Dec 26 13:11:44 2021
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02

17
firmware/output_files/valveboard_firmware.sta.summary
View File

@ -1,17 +0,0 @@
------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'sys_clk'
Slack : -11.085
TNS : -2239.564
Type : Hold 'sys_clk'
Slack : 1.386
TNS : 0.000
Type : Minimum Pulse Width 'sys_clk'
Slack : -2.289
TNS : -2.289
------------------------------------------------------------

31
firmware/tb_valveboard_firmware.v
View File

@ -6,8 +6,8 @@ module tb_valveboard_firmware();
reg line_sen; reg line_sen;
reg line_sdata; reg line_sdata;
wire [48:0] signal_high_voltage; wire [47:0] signal_high_voltage;
wire [48:0] signal_low_voltage; wire [47:0] signal_low_voltage;
valveboard_firmware inst_valveboard_firmware( valveboard_firmware inst_valveboard_firmware(
.sys_clk (sys_clk), .sys_clk (sys_clk),
@ -18,7 +18,7 @@ module tb_valveboard_firmware();
.signal_high_voltage (signal_high_voltage), .signal_high_voltage (signal_high_voltage),
.signal_low_voltage (signal_low_voltage) .signal_low_voltage (signal_low_voltage)
); );
reg [47:0] valve_data;
initial begin initial begin
sys_clk = 0; sys_clk = 0;
rst_n = 0; rst_n = 0;
@ -28,27 +28,28 @@ module tb_valveboard_firmware();
#500; #500;
rst_n = 1; rst_n = 1;
#500; #500;
valve_data = 0;
end end
integer idx; integer idx;
reg [47:0] valve_data;
always #1000000 begin always #500000 begin
valve_data <= ~48'b1000_0000_0000_0000_0000_0000_0000_0001_0000_0000_0000_1001; valve_data = valve_data + 1;
line_sen = 1;#100; line_sen = 1;#50;
for (idx = 0; idx < 48; idx = idx + 1) begin for (idx = 0; idx < 48; idx = idx + 1) begin
if (valve_data[idx] == 0) begin if (valve_data[idx] == 1) begin
line_sdata = 0;#250; line_sdata = 0;#125;
line_sclk = 1;#250; line_sclk = 1;#125;
line_sdata = 1;#250; line_sdata = 1;#125;
line_sclk = 0;#500; line_sclk = 0;#250;
end end
else begin else begin
line_sclk = 1;#500; line_sclk = 1;#250;
line_sclk = 0;#500; line_sclk = 0;#250;
end end
end end
#100; #50;
line_sen = 0; line_sen = 0;
end end

121
firmware/valveboard_firmware.qsf
View File

@ -149,6 +149,121 @@ set_location_assignment PIN_51 -to signal_low_voltage[2]
set_location_assignment PIN_50 -to signal_low_voltage[1] set_location_assignment PIN_50 -to signal_low_voltage[1]
set_location_assignment PIN_49 -to signal_low_voltage[0] set_location_assignment PIN_49 -to signal_low_voltage[0]
set_location_assignment PIN_18 -to sys_clk set_location_assignment PIN_18 -to sys_clk
set_location_assignment PIN_41 -to line_sclk set_location_assignment PIN_40 -to line_sclk
set_location_assignment PIN_39 -to line_sdata set_location_assignment PIN_41 -to line_sdata
set_location_assignment PIN_40 -to line_sen set_location_assignment PIN_39 -to line_sen
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to line_sclk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to line_sdata
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to line_sen
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[47]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[46]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[45]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[44]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[43]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[42]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[41]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[40]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[39]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[38]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[37]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[36]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[35]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[34]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[33]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[32]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[31]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_high_voltage[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[47]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[46]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[45]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[44]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[43]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[42]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[41]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[40]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[39]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[38]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[37]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[36]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[35]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[34]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[33]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[32]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[31]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[30]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[29]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[28]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[27]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[26]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[25]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[24]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to signal_low_voltage[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH nnormal_test -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME nnormal_test -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id nnormal_test
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME nnormal_test -section_id nnormal_test
set_global_assignment -name EDA_TEST_BENCH_FILE tb_valveboard_firmware.v -section_id nnormal_test

53
firmware/valveboard_firmware.qsf.bak
View File

@ -1,53 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
# Date created = 16:15:48 December 24, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# valveboard_firmware_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM1270T144C5
set_global_assignment -name TOP_LEVEL_ENTITY valveboard_firmware
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:15:48 DECEMBER 24, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name VERILOG_FILE valveboard_firmware.v
set_global_assignment -name VERILOG_FILE tb_valveboard_firmware.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V

BIN
firmware/valveboard_firmware.qws
View File

Binary file not shown.

25
firmware/valveboard_firmware.v
View File

@ -1,8 +1,7 @@
/* /*
丁坤的阀板程序 2021/12/26 阀板程序v1.4 2022/8/31
对应原理图ValveBoard Kun v1.1.pdf 经测试，高压时间改为0.2ms
将b01-h1.1-p1.1-f1.1中的高压时间改为0.37ms 使用的是合肥的阀，1.5A电流需0.2ms的100V(阀标称100V，现场供电为96V)高电压
使用的是合肥的阀，1A电流需0.37ms的100V(阀标称100V，现场供电为96V)高电压
*/ */
module valveboard_firmware( module valveboard_firmware(
@ -19,9 +18,9 @@ module valveboard_firmware(
parameter CHANNEL_NUM = 48; parameter CHANNEL_NUM = 48;
parameter CHANNEL_NUM_MINUS_1 = CHANNEL_NUM - 1; parameter CHANNEL_NUM_MINUS_1 = CHANNEL_NUM - 1;
parameter HIGH_VOLTAGE_TIME = 32'd7400; // 高压时间HIGH_VOLTAGE_TIME / 20MHz = 0.37ms parameter HIGH_VOLTAGE_TIME = 32'd4000; // 高压时间HIGH_VOLTAGE_TIME / 20MHz = 0.2ms
parameter HIGH_VOLTAGE_TIME_MINUS_1 = HIGH_VOLTAGE_TIME - 1; // 高压时间HIGH_VOLTAGE_TIME / 20MHz = 2ms parameter HIGH_VOLTAGE_TIME_MINUS_1 = HIGH_VOLTAGE_TIME - 1;
parameter FAULT_COUNTER_THRESHOLD = 32'd20_000_000; // 通讯中断超过FAULT_COUNTER_THRESHOLD / 20MHz = 1s，就关所有阀 parameter FAULT_COUNTER_THRESHOLD = 32'd20_000_000; // 通讯中断超过FAULT_COUNTER_THRESHOLD / 20MHz = 200ms，就关所有阀
parameter FAULT_COUNTER_THRESHOLD_MINUS_1 = FAULT_COUNTER_THRESHOLD - 1; parameter FAULT_COUNTER_THRESHOLD_MINUS_1 = FAULT_COUNTER_THRESHOLD - 1;
parameter FAULT_COUNTER_THRESHOLD_PLUS_1 = FAULT_COUNTER_THRESHOLD + 1; parameter FAULT_COUNTER_THRESHOLD_PLUS_1 = FAULT_COUNTER_THRESHOLD + 1;
@ -32,6 +31,7 @@ module valveboard_firmware(
reg [31:0] fault_counter; reg [31:0] fault_counter;
reg [0:0] fault_flag [0:7]; // fault_flag支持8类错误信号 reg [0:0] fault_flag [0:7]; // fault_flag支持8类错误信号
/** /**
* 维护错误信号 * 维护错误信号
*/ */
@ -256,19 +256,24 @@ module valveboard_firmware(
/** /**
* recv_complete下降沿缓存cache_line_sdata数据到cache2_line_sdata并开始高电压时间计时 * recv_complete下降沿缓存cache_line_sdata数据到cache2_line_sdata并开始高电压时间计时
* last_line_data则保存上一次的输出数据
*/ */
reg [CHANNEL_NUM_MINUS_1:0] cache2_line_sdata; reg [CHANNEL_NUM_MINUS_1:0] cache2_line_sdata;
reg [CHANNEL_NUM_MINUS_1:0] last_line_sdata;
always @(posedge sys_clk or negedge rst_n) begin always @(posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
enable_count_high_voltage_time <= 0; enable_count_high_voltage_time <= 0;
cache2_line_sdata <= ~0; cache2_line_sdata <= ~0;
last_line_sdata <= ~0;
end end
else if (total_fault_flag) begin else if (total_fault_flag) begin
enable_count_high_voltage_time <= 0; enable_count_high_voltage_time <= 0;
cache2_line_sdata <= ~0; cache2_line_sdata <= ~0;
last_line_sdata <= ~0;
end end
else if (recv_complete) begin else if (recv_complete) begin
enable_count_high_voltage_time <= 1; enable_count_high_voltage_time <= 1;
last_line_sdata <= cache2_line_sdata;
cache2_line_sdata <= cache_line_sdata; cache2_line_sdata <= cache_line_sdata;
end end
else begin else begin
@ -276,9 +281,10 @@ module valveboard_firmware(
end end
end end
/** /**
* 高电压时间内(is_high_voltage_time高电平时)，按cache2_line_sdata打开所需高电压；高电压时间后关闭 * 高电压时间内(is_high_voltage_time高电平时)，按cache2_line_sdata打开所需高电压；高电压时间后关闭
* 需要注意的是，已经开着的喷阀， 在高压时间内，不会再次使用高电压，只是保持低电压
* 按cache2_line_sdata打开低电压 * 按cache2_line_sdata打开低电压
* total_fault_flag会关闭所有喷阀 * total_fault_flag会关闭所有喷阀
*/ */
@ -292,7 +298,8 @@ module valveboard_firmware(
signal_high_voltage <= ~0; signal_high_voltage <= ~0;
end end
else if (is_high_voltage_time) begin else if (is_high_voltage_time) begin
signal_high_voltage <= cache2_line_sdata; // 已经开着的喷阀，在高压时间内，不会再次使用高电压，只是保持低电压
signal_high_voltage <= ~last_line_sdata | cache2_line_sdata;
signal_low_voltage <= cache2_line_sdata; signal_low_voltage <= cache2_line_sdata;
end end
else begin else begin

303
firmware/valveboard_firmware.v.bak
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@ -1,303 +0,0 @@
/*
丁坤的阀板程序 2021/11/02
对应原理图ValveBoard Kun v1.1.pdf
*/
module PF1(
input sys_clk, // 20MHz
input rst_n,
input line_sclk,
input line_sen,
input line_sdata,
output reg [47:0] signal_high_voltage,
output reg [47:0] signal_low_voltage
);
parameter CHANNEL_NUM = 48;
parameter CHANNEL_NUM_MINUS_1 = CHANNEL_NUM - 1;
parameter HIGH_VOLTAGE_TIME = 32'd40_000; // 高压时间HIGH_VOLTAGE_TIME / 20MHz = 2ms
parameter HIGH_VOLTAGE_TIME_MINUS_1 = HIGH_VOLTAGE_TIME - 1; // 高压时间HIGH_VOLTAGE_TIME / 20MHz = 2ms
parameter FAULT_COUNTER_THRESHOLD = 32'd20_000_000; // 通讯中断超过FAULT_COUNTER_THRESHOLD / 20MHz = 1s，就关所有阀
parameter FAULT_COUNTER_THRESHOLD_MINUS_1 = FAULT_COUNTER_THRESHOLD - 1;
parameter FAULT_COUNTER_THRESHOLD_PLUS_1 = FAULT_COUNTER_THRESHOLD + 1;
reg [CHANNEL_NUM_MINUS_1:0] cache_signal_high_voltage;
reg [31:0] i;
reg [31:0] fault_counter;
reg [0:0] fault_flag [0:7]; // fault_flag支持8类错误信号
/**
* 维护错误信号
*/
wire total_fault_flag = fault_flag[7] | fault_flag[6] | fault_flag[5] | fault_flag[4] | fault_flag[3] | fault_flag[2] | fault_flag[1] | fault_flag[0];
integer j;
initial begin
for (j = 0; j < 8; j = j + 1) begin
fault_flag[j] = 1'b0;
end
end
// /**
// * 产生周期为100kHz的posedge_100khz信号，信号高电平持续1个sys_clk
// */
// reg[7:0] cnt_for_posedge_100khz;
// reg posedge_100khz;
// always @(posedge sys_clk or negedge rst_n) begin
// if(!rst_n) begin
// cnt_for_posedge_100khz <= 0;
// end
// else if(cnt_for_posedge_100khz == 199) begin
// posedge_100khz <= 1;
// cnt_for_posedge_100khz <= 0;
// end
// else begin
// cnt_for_posedge_100khz <= cnt_for_posedge_100khz + 1;
// posedge_100khz <= 0;
// end
// end
/**
* 在输入的line_sclk信号上升沿产生1个sys_clk时长高电平的脉冲信号posedge_line_sclk，比原信号延迟(4,5]个sys_clk
*/
reg [4:0] cache_line_sclk;
reg posedge_line_sclk;
always@(posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
cache_line_sclk <= 0;
posedge_line_sclk <= 0;
end
else begin
cache_line_sclk <= {cache_line_sclk[3:0], line_sclk};
if ({cache_line_sclk, line_sclk} == 6'b011111)
posedge_line_sclk <= 1;
else
posedge_line_sclk <= 0;
end
end
/**
* filter_line_sdata比原信号延迟(4,5]个sys_clk
*/
reg [4:0] tmp_cache_line_sdata;
reg fiter_line_sdata;
always@(posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
tmp_cache_line_sdata <= ~0;
end
else begin
tmp_cache_line_sdata <= {tmp_cache_line_sdata[3:0], line_sdata};
fiter_line_sdata <= tmp_cache_line_sdata[4];
end
end
/**
* 在输入的line_sen信号上升沿产生1个sys_clk时长高电平的脉冲信号posedge_line_sen，比原信号延迟(4,5]个sys_clk
* 在输入的line_sen信号下降沿产生1个sys_clk时长高电平的脉冲信号negedge_line_sen，比原信号延迟(4,5]个sys_clk
* 缓存和整理line_sen信号得filter_line_sen，比原信号延迟(4,5]个sys_clk
*/
reg [4:0] cache_line_sen;
// reg posedge_line_sen;
reg filter_line_sen;
reg negedge_line_sen;
always@(posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
cache_line_sen <= 0;
filter_line_sen <= 0;
// posedge_line_sen <= 0;
end
else begin
cache_line_sen <= {cache_line_sen[3:0], line_sen};
if ({cache_line_sen, line_sen} == 6'b011111) begin
// posedge_line_sen <= 1;
filter_line_sen <= 1;
negedge_line_sen <= 0;
end
else if ({cache_line_sen, line_sen} == 6'b100000) begin
// posedge_line_sen <= 0;
filter_line_sen <= 0;
negedge_line_sen <= 1;
end
else begin
// posedge_line_sen <= 0;
filter_line_sen <= filter_line_sen;
negedge_line_sen <= 0;
end
end
end
/**
* line_clk上升沿采样line_sdata，采样时刻与posedge_line_sclk下降沿对齐
* total_fault_flag会相对line_clk异步结束本次通信
* recv_complete指示是否接收完成，单sys_clk周期宽度，与negedge_line_sen信号对齐
*/
reg [CHANNEL_NUM_MINUS_1:0] cache_line_sdata;
wire recv_complete = negedge_line_sen && (i == CHANNEL_NUM);
always @ (posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
i <= 0;
cache_line_sdata <= ~0;
end
else if (total_fault_flag) begin
i <= 0;
cache_line_sdata <= ~0;
end
else if (filter_line_sen && posedge_line_sclk) begin
cache_line_sdata[i] <= fiter_line_sdata;
i <= i + 1;
end
else if (negedge_line_sen) begin
i <= 0;
end
end
/**
* 若接收超过CHANNEL_NUM个数据，产生错误信号fault_flag[0]；fault_flag[0]将在posedge_line_sen上升沿时刻清楚
*/
always @ (posedge sys_clk or negedge rst_n) begin
if (!rst_n)
fault_flag[0] <= 0;
else if (i > CHANNEL_NUM)
fault_flag[0] <= 1;
else if ({cache_line_sen, line_sen} == 6'b011111)
fault_flag[0] <= 0;
else
fault_flag[0] <= fault_flag[0];
end
/**
* 若通讯中断，超过FAULT_COUNTER_THRESHOLD个csys_clk就置位fault_flag[1]
* fault_flag[1]在posedge_line_sclk上升沿时刻清楚
*/
always @(posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
fault_counter <= 0;
fault_flag[1] <= 0;
end
else if ({cache_line_sclk, line_sclk} == 6'b011111) begin
fault_counter <= 0;
fault_flag[1] <= 0;
end
else begin
if (fault_counter >= FAULT_COUNTER_THRESHOLD_PLUS_1)
fault_flag[1] <= 1;
else if (fault_counter >= FAULT_COUNTER_THRESHOLD_MINUS_1) begin
fault_counter <= fault_counter + 1;
fault_flag[1] <= 1;
end
else begin
fault_counter <= fault_counter + 1;
fault_flag[1] <= 0;
end
end
end
/**
* 得到enable_count_high_voltage_time的上升沿脉冲posedge_enable_count_high_voltage_time
* enable_count_high_voltage_time是用于开启高电压计时的信号，在其上升沿开启计时
*/
reg [1:0] cache_enable_count_high_voltage_time;
reg enable_count_high_voltage_time;
wire posedge_enable_count_high_voltage_time = cache_enable_count_high_voltage_time[0] & ~cache_enable_count_high_voltage_time[1];
always @(posedge sys_clk or negedge rst_n) begin
if (!rst_n)
cache_enable_count_high_voltage_time <= 0;
else begin
cache_enable_count_high_voltage_time[0] <= enable_count_high_voltage_time;
cache_enable_count_high_voltage_time[1] <= cache_enable_count_high_voltage_time[0];
end
end
/**
* posedge_enable_count_high_voltage_time下降沿开始从HIGH_VOLTAGE_TIME-1向下计数，count_high_voltage_time_end上升沿与到0瞬间对齐
* is_high_voltage_time表示当前是否需要输出高电平，其宽度为HIGH_VOLTAGE_TIME
* posedge_count_high_voltage_time_complete脉冲时长为一个sys_clk
*/
reg [31:0] cnt_for_high_voltage_time;
// reg high_voltage_time_end;
reg is_high_voltage_time;
always @(posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
cnt_for_high_voltage_time <= 0;
// high_voltage_time_end <= 0;
is_high_voltage_time <= 0;
end
else if (total_fault_flag) begin
cnt_for_high_voltage_time <= 0;
// high_voltage_time_end <= 0;
is_high_voltage_time <= 0;
end
else if (posedge_enable_count_high_voltage_time) begin
cnt_for_high_voltage_time <= HIGH_VOLTAGE_TIME_MINUS_1;
// high_voltage_time_end <= 0;
is_high_voltage_time <= 1;
end
else if (cnt_for_high_voltage_time > 1) begin
cnt_for_high_voltage_time <= cnt_for_high_voltage_time - 1;
// high_voltage_time_end <= 0;
is_high_voltage_time <= 1;
end
else if (cnt_for_high_voltage_time == 1) begin
cnt_for_high_voltage_time <= cnt_for_high_voltage_time - 1;
// high_voltage_time_end <= 1;
is_high_voltage_time <= 1;
end
else begin
// high_voltage_time_end <= 0;
is_high_voltage_time <= 0;
end
end
/**
* recv_complete下降沿缓存cache_line_sdata数据到cache2_line_sdata并开始高电压时间计时
*/
reg [CHANNEL_NUM_MINUS_1:0] cache2_line_sdata;
always @(posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
enable_count_high_voltage_time <= 0;
cache2_line_sdata <= ~0;
end
else if (total_fault_flag) begin
enable_count_high_voltage_time <= 0;
cache2_line_sdata <= ~0;
end
else if (recv_complete) begin
enable_count_high_voltage_time <= 1;
cache2_line_sdata <= cache_line_sdata;
end
else begin
enable_count_high_voltage_time <= 0;
end
end
/**
* 高电压时间内(is_high_voltage_time高电平时)，按cache2_line_sdata打开所需高电压；高电压时间后关闭
* 按cache2_line_sdata打开低电压
* total_fault_flag会关闭所有喷阀
*/
always @ (posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
signal_low_voltage <= ~0;
signal_high_voltage <= ~0;
end
else if (total_fault_flag) begin
signal_low_voltage <= ~0;
signal_high_voltage <= ~0;
end
else if (is_high_voltage_time) begin
signal_high_voltage <= cache2_line_sdata;
signal_low_voltage <= cache2_line_sdata;
end
else begin
signal_high_voltage <= ~0;
signal_low_voltage <= cache2_line_sdata;
end
end
endmodule

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hardware/README.md
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@ -1,17 +1,11 @@
# 阀板硬件 # 阀板硬件
相对于以前v1.1版本，终于，**改成超六类屏蔽网线通信了**，这是为了改善通信质量，并没有用网络相关的协议 这个文件夹下是48路阀板的原理图和PCB，用于烟梗分选机。整个机器用了六块48路阀板，驱动256路喷嘴，阀的型号是合肥旭伟电子气动有限公司的XW-F16，这个阀一个可以连接并控制16个喷嘴。每个阀的电阻是14欧姆，高压启动时峰值电流约1.5A，低压保持电流约0.8A。
这个文件夹下是丁坤画的48路阀板的原理图和PCB，用于烟梗分选机。整个机器用了六块48路阀板，驱动200路喷嘴，阀的型号是合肥旭伟电子气动有限公司的XW-F16，这个阀一个可以连接并控制16个喷嘴。
![image-20211226143651047](README.assets/image-20211226143651047.png) ![image-20211226143651047](README.assets/image-20211226143651047.png)
**下面的说明仅针对丁坤画的阀板v1.2，丁坤的阀板简化了供电，添加了不同的接口，但总体思路是一样的**，此外丁坤和汪学良的阀板引脚分配并不相同，具体见阀板程序`../firmware`。
## 概述 ## 概述
**汪学良的板子供电数量和标号与下面所述的丁坤阀板v1.2稍有不同，非粗体字体是对丁坤板子的说明，请留意。**
48个电磁阀连接在顶部的12个接口上，当接口上有电压时电流流过电磁阀，电磁阀打开。由于电磁阀工作需要大电流大电压且为感性器件，容易影响发出控制信号的CPLD芯片，因此需要独立且隔离的电源，这个电源标为`LOW`，参考为`PGND`。为加快电磁阀开启，在开启瞬间会输出一个高电压，这是另一个独立的电源，标为`HIGH`，参考也为`PGND`。这个高电压会在电磁阀开启后被断开，随后施加标号为`LOW`的保持电压，用来保持电磁阀的打开状态。需要电磁阀关闭则切断保持电压。 48个电磁阀连接在顶部的12个接口上，当接口上有电压时电流流过电磁阀，电磁阀打开。由于电磁阀工作需要大电流大电压且为感性器件，容易影响发出控制信号的CPLD芯片，因此需要独立且隔离的电源，这个电源标为`LOW`，参考为`PGND`。为加快电磁阀开启，在开启瞬间会输出一个高电压，这是另一个独立的电源，标为`HIGH`，参考也为`PGND`。这个高电压会在电磁阀开启后被断开，随后施加标号为`LOW`的保持电压，用来保持电磁阀的打开状态。需要电磁阀关闭则切断保持电压。
上面的过程由光耦隔离驱动端MOS和控制芯片CPLD，提供给光耦输出端的电压标号为`+12V`，参考为`PGND`。 上面的过程由光耦隔离驱动端MOS和控制芯片CPLD，提供给光耦输出端的电压标号为`+12V`，参考为`PGND`。
@ -31,31 +25,13 @@ CPLD为控制芯片，接收外部信号并将控制信号输出到板上的光
| DGND | 0V | | DGND | 0V |
| +12V | 12V | | +12V | 12V |
**本次所用的阀板加速开启用的高电压为直流100V、保持用的低电压为直流12V，另有光耦、CPLD等的弱电供电。** 本次所用的阀板加速开启用的高电压为直流100V、保持用的低电压为直流12V
下面是阀板正面视图。
![image-20220519222236422](./README.assets/image-20220519222236422.png)
## 通信接口
**下面非粗体字体是丁坤的阀板v1.2说明，请注意**
![image-20211121225906720](README.assets/image-20211121225906720.png)
`LVDS`的接口的信号是遵循通信协议的LVDS信号，注意虽然看起来像网口，实则为LVDS信号，具体引脚定义自行看原理图。
## 版号
**下面非粗体字体是丁坤的阀板v1.2说明，需要注意的是，版号没有意义，CPLD中程序目前不识别**
## 调试 ## 调试
**版号** **版号**
在`MB VER.`丝印标志的区域有`S1`、`S2`、`S3`、`S4`标注的0欧电阻焊接位，按`0`、`1`标注焊接即可，注意0和1不能都焊。这个设置是为阀板级联做的冗余。 在`INFO`丝印标志的区域有`S1`、`S2`、`S3`、`S4`标注的0欧电阻焊接位，按`0`、`1`标注焊接即可，注意0和1不能都焊。这个设置是为阀板级联做的冗余。
**烧录** **烧录**
@ -63,22 +39,56 @@ CPLD烧录口为简牛口，用USB Blaster烧录的，开发软件为Quartus。
**观察开关量** **观察开关量**
在正面那排光耦前有LED焊接位可以焊接上LED，打开的阀门那一路对应的LED亮，当然注意重新计算和焊接所需的串联限流电阻 在正面那排光耦前有LED，打开的阀门那一路对应的LED亮。选用LED和串联限流电阻时，查看[issue#2](https://github.com/NanjingForestryUniversity/valveboard/issues/2)
**电源** **电源**
数字电源输入为12V，在板子上转换为3.3V，网络标号+3.3V，为防止电磁阀上电瞬间直接误动作，因此给光耦电源加入RC延时电路，输出标号为+3.3VGG，按设计延时约500ms，这个时间远大于CPLD初始化开始工作的时间，因此电磁阀上电瞬间不会误动作。 数字电源输入为12V，在板子上转换为3.3V，网络标号+3.3V，为防止电磁阀上电瞬间直接误动作，因此给光耦电源加入RC延时电路，输出标号为+3.3VGG，按设计延时约500ms，这个时间远大于CPLD初始化开始工作的时间，因此电磁阀上电瞬间不会误动作。此外还添加了防反接保护，查看[issue#3](https://github.com/NanjingForestryUniversity/valveboard/issues/3)
数字电源输入附近`3.3V`的LED亮不代表真的就是3.3V，也许是12V直接短路到了网络上。右上角电源接口附近的灯指示输入的电压。另外板子上有大量保险丝，包括右上角附近的两个黑色壳子，里面打开也是保险丝。
## 生产制造 ## 生产制造
所需器件BOM里都有，板子开窗部分要加锡，钢网上已经体现了 所需器件BOM里都有，板子开窗部分要加锡，钢网上已经体现了。测试板子是嘉立创做的，SMT也是嘉立创，直插元件和芯片需手焊
测试板子是嘉立创做的，SMT也是嘉立创，直插元件和芯片需手焊 ## Changelog
### v1.0
## 其他信息 绿色的阀板，测试版本，继承于远古的原理图和布局
板子上标有CE、FC、WEEE等认证，这些都是随手放上去的，完全没有进行过这些认证。如果要了解板子工作原理，自行看原理图，原理图内的标号命名来自于老阀板，很让人不知所措，要有耐心才能看下去 ### v1.1
蓝色的阀板，过奕任选型和画原理图，丁坤layout，具有ISO、LVDS、TTL接口，见[b01-h1.1-p1.1-f1.1](https://github.com/NanjingForestryUniversity/valveboard/releases/tag/b01-h1.1-p1.1-f1.1)
### v1.2
黄色的阀板，过奕任画原理图和layout，见 [b02-h1.2-p1.1-f1.2](https://github.com/NanjingForestryUniversity/valveboard/releases/tag/b02-h1.2-p1.1-f1.2)
- 采用带屏蔽的超六类RJ45端口代替原来的牛角座，增强了通信的稳定性
- 删除了ISO（隔离）端口
- 删除了LVDS的BYPASS端口
- 删除了TTL端口
- 修改电磁喷阀的接口为更容易买到的器件，[器件详情](https://detail.tmall.com/item.htm?spm=a230r.1.14.52.2b5b4e50D2a4NS&id=633917290163&ns=1&abbucket=5&skuId=4696862330457)
- 增加了光隔数字部分电源的延迟上电电路，避免启动瞬间喷阀动作
- 修改了1N4148的封装为SOD-123，方便SMT
- 略微优化了板子尺寸，调整了安装孔位置和个数
### v1.3
绿色的阀板，过奕任画原理图和layout，见[b02-h1.3-p1.1-f1.3](https://github.com/NanjingForestryUniversity/valveboard/releases/tag/b02-h1.3-p1.1-f1.3)
- 重画了原理图和PCB，PCB尺寸减小
- 增大阻容器件封装，解决100V耐压风险，[issue#1](https://github.com/NanjingForestryUniversity/valveboard/issues/1)
- LED改为黄绿色，[issue#2](https://github.com/NanjingForestryUniversity/valveboard/issues/2)
- 添加了数字电源防反接，[issue#3](https://github.com/NanjingForestryUniversity/valveboard/issues/3)
- 取消了所有保险丝
- 增加了每一路的标识丝印，南林的徽标
- 重新排列了阀的连接器，方便插拔
- 有需要的线路上增加了开窗，提高载流能力
## 作者
[过奕任](https://github.com/3703781)和丁坤一起设计了电路，画了板子。欢迎提[issue](https://github.com/NanjingForestryUniversity/valveboard/issues)，bug随缘解决。
丁坤2019年入学时就被师兄叫去焊接汪学良的阀板，后来和过奕任接替师兄做了这个仓库里的阀板。丁坤已经毕业，但也很乐意解答关于板子的所有问题。丁坤QQ1091546069、丁坤电话17761700156。
过奕任2020年入学，目前正打算找其他人接管这个库，毕业了就不要找他，但永远可以找丁坤。
丁坤2019年9月入学、丁坤QQ1091546069、丁坤电话17761700156，他刚入学时就被师兄叫去焊接汪学良的阀板，后来接替师兄做了这个仓库里的阀板，无论有没有毕业，都很乐意解答关于板子的所有问题

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DocumentUniqueId=
[Document22]
DocumentPath=Job.OutJob
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document23]
DocumentPath=pcb\VALVEBOARD_Kun.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=XRFYHIXV
[Configuration1] [Configuration1]
Name=Sources Name=Sources
ParameterCount=0 ParameterCount=0
@ -353,18 +470,18 @@ SCH_ShowBlankets=-1
SCH_NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle SCH_NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle
SCH_ShowNote=-1 SCH_ShowNote=-1
SCH_ShowNoteCollapsed=-1 SCH_ShowNoteCollapsed=-1
SCH_ExpandLogicalToPhysical=0 SCH_ExpandLogicalToPhysical=-1
SCH_VariantName=[No Variations] SCH_VariantName=[No Variations]
SCH_ExpandComponentDesignators=-1 SCH_ExpandComponentDesignators=-1
SCH_ExpandNetlabels=0 SCH_ExpandNetlabels=-1
SCH_ExpandPorts=0 SCH_ExpandPorts=-1
SCH_ExpandSheetNumber=0 SCH_ExpandSheetNumber=-1
SCH_ExpandDocumentNumber=0 SCH_ExpandDocumentNumber=-1
SCH_HasExpandLogicalToPhysicalSheets=-1 SCH_HasExpandLogicalToPhysicalSheets=-1
SaveSettingsToOutJob=0 SaveSettingsToOutJob=0
[Generic_EDE] [Generic_EDE]
OutputDir= OutputDir=Project Outputs for ValveBoard - Copy
[OutputGroup1] [OutputGroup1]
Name=Netlist Outputs Name=Netlist Outputs
@ -381,11 +498,101 @@ OutputName2=PADS ASCII Netlist
OutputDocumentPath2= OutputDocumentPath2=
OutputVariantName2= OutputVariantName2=
OutputDefault2=0 OutputDefault2=0
OutputType3=CadnetixNetlist
OutputName3=Cadnetix Netlist
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
OutputType4=CalayNetlist
OutputName4=Calay Netlist
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
OutputType5=EDIF
OutputName5=EDIF for PCB
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
OutputType6=EESofNetlist
OutputName6=EESof Netlist
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
OutputType7=IntergraphNetlist
OutputName7=Intergraph Netlist
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
OutputType8=MentorBoardStationNetlist
OutputName8=Mentor BoardStation Netlist
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
OutputType9=MultiWire
OutputName9=MultiWire
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=OrCadPCB2Netlist
OutputName10=Orcad/PCB2 Netlist
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=Pcad
OutputName11=Pcad for PCB
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=PCADnltNetlist
OutputName12=PCADnlt Netlist
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=Protel2Netlist
OutputName13=Protel2 Netlist
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=ProtelNetlist
OutputName14=Protel
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=RacalNetlist
OutputName15=Racal Netlist
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=RINFNetlist
OutputName16=RINF Netlist
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=SciCardsNetlist
OutputName17=SciCards Netlist
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=TangoNetlist
OutputName18=Tango Netlist
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
OutputType19=TelesisNetlist
OutputName19=Telesis Netlist
OutputDocumentPath19=
OutputVariantName19=
OutputDefault19=0
OutputType20=WireListNetlist
OutputName20=WireList Netlist
OutputDocumentPath20=
OutputVariantName20=
OutputDefault20=0
[OutputGroup2] [OutputGroup2]
Name=Simulator Outputs Name=Simulator Outputs
Description= Description=
TargetPrinter=Microsoft XPS Document Writer TargetPrinter=\\Desktop-k75ippc\HP LaserJet Professional M1136 MFP
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
[OutputGroup3] [OutputGroup3]
@ -399,6 +606,30 @@ OutputDocumentPath1=
OutputVariantName1= OutputVariantName1=
OutputDefault1=0 OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
Configuration1_Name1=OutputConfigurationParameter1
Configuration1_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name2=OutputConfigurationParameter2
Configuration1_Item2=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name3=OutputConfigurationParameter3
Configuration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name4=OutputConfigurationParameter4
Configuration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name5=OutputConfigurationParameter5
Configuration1_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name6=OutputConfigurationParameter6
Configuration1_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name7=OutputConfigurationParameter7
Configuration1_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name8=OutputConfigurationParameter8
Configuration1_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name9=OutputConfigurationParameter9
Configuration1_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name10=OutputConfigurationParameter10
Configuration1_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical2|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name11=OutputConfigurationParameter11
Configuration1_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
Configuration1_Name12=OutputConfigurationParameter12
Configuration1_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\guoyr\Desktop\valveboard\hardware\sch\VALVEBOARD_Kun.PcbDoc
OutputType2=PCB 3D Print OutputType2=PCB 3D Print
OutputName2=PCB 3D Print OutputName2=PCB 3D Print
OutputDocumentPath2= OutputDocumentPath2=
@ -449,11 +680,23 @@ OutputDocumentPath9=
OutputVariantName9= OutputVariantName9=
OutputDefault9=0 OutputDefault9=0
PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType10=PDF3D
OutputName10=PDF3D
OutputDocumentPath10=
OutputVariantName10=[No Variations]
OutputDefault10=0
PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType11=PDF3D MBA
OutputName11=PDF3D MBA
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
[OutputGroup4] [OutputGroup4]
Name=Assembly Outputs Name=Assembly Outputs
Description= Description=
TargetPrinter=HP LaserJet Professional M1136 MFP TargetPrinter=\\Desktop-k75ippc\HP LaserJet Professional M1136 MFP
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
OutputType1=Assembly OutputType1=Assembly
OutputName1=Assembly Drawings OutputName1=Assembly Drawings
@ -511,7 +754,7 @@ OutputDefault3=0
[OutputGroup5] [OutputGroup5]
Name=Fabrication Outputs Name=Fabrication Outputs
Description= Description=
TargetPrinter=HP LaserJet Professional M1136 MFP TargetPrinter=\\Desktop-k75ippc\HP LaserJet Professional M1136 MFP
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
OutputType1=NC Drill OutputType1=NC Drill
OutputName1=NC Drill Files OutputName1=NC Drill Files
@ -848,6 +1091,21 @@ OutputName8=Specctra Design PCB
OutputDocumentPath8= OutputDocumentPath8=
OutputVariantName8= OutputVariantName8=
OutputDefault8=0 OutputDefault8=0
OutputType9=ExportIDF
OutputName9=Export IDF
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=MBAExportPARASOLID
OutputName10=Export PARASOLID
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=MBAExportSTEP
OutputName11=Export STEP
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
[OutputGroup10] [OutputGroup10]
Name=PostProcess Outputs Name=PostProcess Outputs
@ -1177,7 +1435,6 @@ Type122=2
Type123=1 Type123=1
Type124=1 Type124=1
Type125=1 Type125=1
Type126=1
[ERC Connection Matrix] [ERC Connection Matrix]
L1=NNNNNNNNNNNWNNNWW L1=NNNNNNNNNNNWNNNWW
@ -1215,7 +1472,7 @@ CompClassManualEnabled=0
CompClassManualRoomEnabled=0 CompClassManualRoomEnabled=0
NetClassAutoBusEnabled=1 NetClassAutoBusEnabled=1
NetClassAutoCompEnabled=0 NetClassAutoCompEnabled=0
NetClassAutoNamedHarnessEnabled=0 NetClassAutoNamedHarnessEnabled=1
NetClassManualEnabled=1 NetClassManualEnabled=1
NetClassSeparateForBusSections=0 NetClassSeparateForBusSections=0

30
hardware/ValveBoard - Copy.PrjPcbStructure
View File

@ -1,7 +1,23 @@
Record=TopLevelDocument|FileName=VALVEBOARD_DigitalPower_DigitalInterface_Controller.SchDoc|SheetNumber=1 Record=TopLevelDocument|FileName=VALVEBOARD_Top.SchDoc|SheetNumber=1
Record=NoMainPathDocument|SourceDocument=VALVEBOARD_DigitalPower_DigitalInterface_Controller.SchDoc|FileName=VALVEBOARD_Isolation.SchDoc|SheetNumber=2 Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=Controller|SchDesignator=Controller|FileName=VALVEBOARD_Controller.SchDoc|SheetNumber=2|SymbolType=Normal|RawFileName=VALVEBOARD_Controller.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=NoMainPathDocument|SourceDocument=VALVEBOARD_DigitalPower_DigitalInterface_Controller.SchDoc|FileName=VALVEBOARD_ValveDrive1.SchDoc|SheetNumber=4 Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=DigitalInterface|SchDesignator=DigitalInterface|FileName=VALVEBOARD_DigitalInterface.SchDoc|SheetNumber=9|SymbolType=Normal|RawFileName=VALVEBOARD_DigitalInterface.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=NoMainPathDocument|SourceDocument=VALVEBOARD_DigitalPower_DigitalInterface_Controller.SchDoc|FileName=VALVEBOARD_ValveDrive2.SchDoc|SheetNumber=5 Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=DigitalPower|SchDesignator=DigitalPower|FileName=VALVEBOARD_DigitalPower.SchDoc|SheetNumber=3|SymbolType=Normal|RawFileName=VALVEBOARD_DigitalPower.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=NoMainPathDocument|SourceDocument=VALVEBOARD_DigitalPower_DigitalInterface_Controller.SchDoc|FileName=VALVEBOARD_ValveDrive3.SchDoc|SheetNumber=6 Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation1|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=NoMainPathDocument|SourceDocument=VALVEBOARD_DigitalPower_DigitalInterface_Controller.SchDoc|FileName=VALVEBOARD_ValveDrive4.SchDoc|SheetNumber=7 Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation2|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=NoMainPathDocument|SourceDocument=VALVEBOARD_DigitalPower_DigitalInterface_Controller.SchDoc|FileName=VALVEBOARD_ValvePower_ValveInterface.SchDoc|SheetNumber=3 Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation3|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation4|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation5|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation6|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation7|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation8|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation9|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation10|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation11|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=PostIsolation12|SchDesignator=Repeat(PostIsolation,1,12)|FileName=VALVEBOARD_PostIsolation.SchDoc|SheetNumber=5|SymbolType=Normal|RawFileName=VALVEBOARD_PostIsolation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_Top.SchDoc|Designator=ValvePower|SchDesignator=ValvePower|FileName=VALVEBOARD_ValvePower.SchDoc|SheetNumber=4|SymbolType=Normal|RawFileName=VALVEBOARD_ValvePower.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_PostIsolation.SchDoc|Designator=Drive1|SchDesignator=Repeat(Drive,1,4)|FileName=VALVEBOARD_ValveDrive.SchDoc|SheetNumber=8|SymbolType=Normal|RawFileName=VALVEBOARD_ValveDrive.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_PostIsolation.SchDoc|Designator=Drive2|SchDesignator=Repeat(Drive,1,4)|FileName=VALVEBOARD_ValveDrive.SchDoc|SheetNumber=8|SymbolType=Normal|RawFileName=VALVEBOARD_ValveDrive.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=VALVEBOARD_PostIsolation.SchDoc|Designator=Drive3|SchDesignator=Repeat(Drive,1,4)|FileName=VALVEBOARD_ValveDrive.SchDoc|SheetNumber=8|SymbolType=Normal|RawFileName=VALVEBOARD_ValveDrive.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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