faae382955
1. 添加pl端vivado工程生成脚本和源码 2. pl端设计删除本项目无关的fifo和valve interfaces模块 3. 系统部署脚本中删除fifo相关内容 4. 删除linux下的fifo驱动 5. 修改与上述内容有关的文档 BREAKING CHANGE: fifo有关功能和寄存器不再有效 Co-authored-by: lyz <1942503466@qq.com>
649 lines
28 KiB
Tcl
649 lines
28 KiB
Tcl
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################################################################
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# This is a generated script based on design: system
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2022.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source system_script.tcl
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xc7z010clg400-1
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name system
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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user.org:user:ip_encoder:1.1\
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user.org:user:ip_fan:1.0\
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xilinx.com:ip:processing_system7:5.5\
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xilinx.com:ip:proc_sys_reset:5.0\
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"
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set list_ips_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
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set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
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# Create ports
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set encoder_signal [ create_bd_port -dir I encoder_signal ]
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set exrst_n [ create_bd_port -dir I exrst_n ]
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set fan [ create_bd_port -dir O fan ]
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set out_signal_camera_a [ create_bd_port -dir O out_signal_camera_a ]
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set out_signal_camera_b [ create_bd_port -dir O out_signal_camera_b ]
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set out_signal_camera_c [ create_bd_port -dir O out_signal_camera_c ]
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set out_signal_camera_d [ create_bd_port -dir O out_signal_camera_d ]
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# Create instance: ip_encoder_0, and set properties
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set ip_encoder_0 [ create_bd_cell -type ip -vlnv user.org:user:ip_encoder:1.1 ip_encoder_0 ]
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# Create instance: ip_fan_0, and set properties
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set ip_fan_0 [ create_bd_cell -type ip -vlnv user.org:user:ip_fan:1.0 ip_fan_0 ]
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# Create instance: processing_system7_0, and set properties
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set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
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set_property -dict [ list \
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CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
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CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
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CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
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CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
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CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_CLK0_FREQ {200000000} \
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CONFIG.PCW_CLK1_FREQ {10000000} \
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CONFIG.PCW_CLK2_FREQ {10000000} \
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CONFIG.PCW_CLK3_FREQ {10000000} \
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CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
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CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
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CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
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CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
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CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
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CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
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CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
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CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
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CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
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CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
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CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
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CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
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CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
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CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
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CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
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CONFIG.PCW_ENET0_RESET_ENABLE {1} \
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CONFIG.PCW_ENET0_RESET_IO {MIO 7} \
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CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_ENET1_RESET_ENABLE {0} \
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CONFIG.PCW_ENET_RESET_ENABLE {1} \
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CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
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CONFIG.PCW_EN_EMIO_ENET0 {0} \
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CONFIG.PCW_EN_EMIO_SDIO1 {0} \
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CONFIG.PCW_EN_EMIO_TTC0 {1} \
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CONFIG.PCW_EN_EMIO_UART0 {0} \
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CONFIG.PCW_EN_ENET0 {1} \
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CONFIG.PCW_EN_GPIO {1} \
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CONFIG.PCW_EN_QSPI {1} \
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CONFIG.PCW_EN_SDIO0 {1} \
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CONFIG.PCW_EN_SDIO1 {1} \
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CONFIG.PCW_EN_TTC0 {1} \
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CONFIG.PCW_EN_UART0 {1} \
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CONFIG.PCW_EN_USB0 {1} \
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CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
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CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {200} \
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CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
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CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
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CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
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CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
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CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
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CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
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CONFIG.PCW_I2C0_RESET_ENABLE {0} \
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CONFIG.PCW_I2C1_RESET_ENABLE {0} \
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CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
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CONFIG.PCW_I2C_RESET_ENABLE {1} \
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CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
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CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
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CONFIG.PCW_MIO_0_DIRECTION {inout} \
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CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_0_PULLUP {enabled} \
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CONFIG.PCW_MIO_0_SLEW {slow} \
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CONFIG.PCW_MIO_10_DIRECTION {inout} \
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CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_10_PULLUP {enabled} \
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CONFIG.PCW_MIO_10_SLEW {slow} \
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CONFIG.PCW_MIO_11_DIRECTION {inout} \
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CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_11_PULLUP {enabled} \
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CONFIG.PCW_MIO_11_SLEW {slow} \
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CONFIG.PCW_MIO_12_DIRECTION {inout} \
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CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_12_PULLUP {enabled} \
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CONFIG.PCW_MIO_12_SLEW {slow} \
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CONFIG.PCW_MIO_13_DIRECTION {inout} \
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CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_13_PULLUP {enabled} \
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CONFIG.PCW_MIO_13_SLEW {slow} \
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CONFIG.PCW_MIO_14_DIRECTION {in} \
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CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_14_PULLUP {enabled} \
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CONFIG.PCW_MIO_14_SLEW {slow} \
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CONFIG.PCW_MIO_15_DIRECTION {out} \
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CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_15_PULLUP {enabled} \
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CONFIG.PCW_MIO_15_SLEW {slow} \
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CONFIG.PCW_MIO_16_DIRECTION {out} \
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CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_16_PULLUP {enabled} \
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CONFIG.PCW_MIO_16_SLEW {fast} \
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CONFIG.PCW_MIO_17_DIRECTION {out} \
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CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_17_PULLUP {enabled} \
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CONFIG.PCW_MIO_17_SLEW {fast} \
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CONFIG.PCW_MIO_18_DIRECTION {out} \
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CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_18_PULLUP {enabled} \
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CONFIG.PCW_MIO_18_SLEW {fast} \
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CONFIG.PCW_MIO_19_DIRECTION {out} \
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CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_19_PULLUP {enabled} \
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CONFIG.PCW_MIO_19_SLEW {fast} \
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CONFIG.PCW_MIO_1_DIRECTION {out} \
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CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_1_PULLUP {enabled} \
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CONFIG.PCW_MIO_1_SLEW {fast} \
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CONFIG.PCW_MIO_20_DIRECTION {out} \
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CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_20_PULLUP {enabled} \
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CONFIG.PCW_MIO_20_SLEW {fast} \
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CONFIG.PCW_MIO_21_DIRECTION {out} \
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CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_21_PULLUP {enabled} \
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CONFIG.PCW_MIO_21_SLEW {fast} \
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CONFIG.PCW_MIO_22_DIRECTION {in} \
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CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_22_PULLUP {enabled} \
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CONFIG.PCW_MIO_22_SLEW {fast} \
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CONFIG.PCW_MIO_23_DIRECTION {in} \
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CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
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CONFIG.PCW_MIO_23_PULLUP {enabled} \
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CONFIG.PCW_MIO_23_SLEW {fast} \
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CONFIG.PCW_MIO_24_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_24_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_24_SLEW {fast} \
|
|
CONFIG.PCW_MIO_25_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_25_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_25_SLEW {fast} \
|
|
CONFIG.PCW_MIO_26_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_26_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_26_SLEW {fast} \
|
|
CONFIG.PCW_MIO_27_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_27_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_27_SLEW {fast} \
|
|
CONFIG.PCW_MIO_28_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_28_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_28_SLEW {slow} \
|
|
CONFIG.PCW_MIO_29_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_29_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_29_SLEW {slow} \
|
|
CONFIG.PCW_MIO_2_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_2_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_2_SLEW {fast} \
|
|
CONFIG.PCW_MIO_30_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_30_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_30_SLEW {slow} \
|
|
CONFIG.PCW_MIO_31_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_31_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_31_SLEW {slow} \
|
|
CONFIG.PCW_MIO_32_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_32_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_32_SLEW {slow} \
|
|
CONFIG.PCW_MIO_33_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_33_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_33_SLEW {slow} \
|
|
CONFIG.PCW_MIO_34_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_34_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_34_SLEW {slow} \
|
|
CONFIG.PCW_MIO_35_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_35_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_35_SLEW {slow} \
|
|
CONFIG.PCW_MIO_36_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_36_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_36_SLEW {slow} \
|
|
CONFIG.PCW_MIO_37_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_37_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_37_SLEW {slow} \
|
|
CONFIG.PCW_MIO_38_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_38_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_38_SLEW {slow} \
|
|
CONFIG.PCW_MIO_39_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_39_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_39_SLEW {slow} \
|
|
CONFIG.PCW_MIO_3_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_3_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_3_SLEW {fast} \
|
|
CONFIG.PCW_MIO_40_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_40_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_40_SLEW {slow} \
|
|
CONFIG.PCW_MIO_41_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_41_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_41_SLEW {slow} \
|
|
CONFIG.PCW_MIO_42_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_42_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_42_SLEW {slow} \
|
|
CONFIG.PCW_MIO_43_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_43_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_43_SLEW {slow} \
|
|
CONFIG.PCW_MIO_44_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_44_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_44_SLEW {slow} \
|
|
CONFIG.PCW_MIO_45_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_45_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_45_SLEW {slow} \
|
|
CONFIG.PCW_MIO_46_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_46_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_46_SLEW {slow} \
|
|
CONFIG.PCW_MIO_47_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_47_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_47_SLEW {slow} \
|
|
CONFIG.PCW_MIO_48_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_48_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_48_SLEW {slow} \
|
|
CONFIG.PCW_MIO_49_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_49_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_49_SLEW {slow} \
|
|
CONFIG.PCW_MIO_4_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_4_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_4_SLEW {fast} \
|
|
CONFIG.PCW_MIO_50_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_50_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_50_SLEW {slow} \
|
|
CONFIG.PCW_MIO_51_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_51_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_51_SLEW {slow} \
|
|
CONFIG.PCW_MIO_52_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_52_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_52_SLEW {slow} \
|
|
CONFIG.PCW_MIO_53_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_53_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_53_SLEW {slow} \
|
|
CONFIG.PCW_MIO_5_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_5_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_5_SLEW {fast} \
|
|
CONFIG.PCW_MIO_6_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_6_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_6_SLEW {fast} \
|
|
CONFIG.PCW_MIO_7_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_7_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_7_SLEW {slow} \
|
|
CONFIG.PCW_MIO_8_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_8_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_8_SLEW {slow} \
|
|
CONFIG.PCW_MIO_9_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_9_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_9_SLEW {slow} \
|
|
CONFIG.PCW_MIO_TREE_PERIPHERALS {\
|
|
GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI\
|
|
Flash#Quad SPI Flash#ENET Reset#USB Reset#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART\
|
|
0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet\
|
|
0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\
|
|
0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0} \
|
|
CONFIG.PCW_MIO_TREE_SIGNALS {\
|
|
gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#reset#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#data[0]#cmd#clk#data[1]#data[2]#data[3]#mdc#mdio} \
|
|
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
|
|
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
|
|
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
|
|
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
|
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
|
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
|
CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
|
|
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
|
|
CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
|
|
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
|
|
CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
|
|
CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
|
|
CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
|
|
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_SD1_SD1_IO {MIO 46 .. 51} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
|
|
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
|
|
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
|
|
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
|
|
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
|
|
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
|
|
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
|
|
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
|
|
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
|
|
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
|
|
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
|
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
|
|
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
|
|
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
|
|
CONFIG.PCW_UIPARAM_DDR_CL {7} \
|
|
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
|
|
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
|
|
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
|
|
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
|
|
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-125} \
|
|
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \
|
|
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
|
|
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
|
|
CONFIG.PCW_USB0_RESET_ENABLE {1} \
|
|
CONFIG.PCW_USB0_RESET_IO {MIO 8} \
|
|
CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
|
|
CONFIG.PCW_USB1_RESET_ENABLE {0} \
|
|
CONFIG.PCW_USB_RESET_ENABLE {1} \
|
|
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
|
|
] $processing_system7_0
|
|
|
|
# Create instance: ps7_0_axi_periph, and set properties
|
|
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
|
|
set_property -dict [ list \
|
|
CONFIG.NUM_MI {2} \
|
|
] $ps7_0_axi_periph
|
|
|
|
# Create instance: rst_ps7_0_200M, and set properties
|
|
set rst_ps7_0_200M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_200M ]
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
|
|
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
|
|
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
|
|
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ip_encoder_0/S00_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
|
|
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ip_fan_0/S00_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net exrst_n_0_1 [get_bd_ports exrst_n] [get_bd_pins ip_encoder_0/exrst_n]
|
|
connect_bd_net -net in_signal_0_1 [get_bd_ports encoder_signal] [get_bd_pins ip_encoder_0/in_signal]
|
|
connect_bd_net -net ip_encoder_0_out_signal_camera_a [get_bd_ports out_signal_camera_a] [get_bd_pins ip_encoder_0/out_signal_camera_a]
|
|
connect_bd_net -net ip_encoder_0_out_signal_camera_b [get_bd_ports out_signal_camera_b] [get_bd_pins ip_encoder_0/out_signal_camera_b]
|
|
connect_bd_net -net ip_encoder_0_out_signal_camera_c [get_bd_ports out_signal_camera_c] [get_bd_pins ip_encoder_0/out_signal_camera_c]
|
|
connect_bd_net -net ip_encoder_0_out_signal_camera_d [get_bd_ports out_signal_camera_d] [get_bd_pins ip_encoder_0/out_signal_camera_d]
|
|
connect_bd_net -net ip_fan_0_fan [get_bd_ports fan] [get_bd_pins ip_fan_0/fan]
|
|
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins ip_encoder_0/s00_axi_aclk] [get_bd_pins ip_fan_0/s00_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_200M/slowest_sync_clk]
|
|
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_200M/ext_reset_in]
|
|
connect_bd_net -net rst_ps7_0_200M_peripheral_aresetn [get_bd_pins ip_encoder_0/s00_axi_aresetn] [get_bd_pins ip_fan_0/s00_axi_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_200M/peripheral_aresetn]
|
|
|
|
# Create address segments
|
|
assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs ip_encoder_0/S00_AXI/S00_AXI_reg] -force
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assign_bd_address -offset 0x43C20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs ip_fan_0/S00_AXI/S00_AXI_reg] -force
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# Restore current instance
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current_bd_instance $oldCurInst
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validate_bd_design
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save_bd_design
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}
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# End of create_root_design()
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##################################################################
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# MAIN FLOW
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##################################################################
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create_root_design ""
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