寒假前烟梗分选机上已经开始用的
测试能否打中暂时没啥问题，但溜的急，没充分测试
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# 下位机
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# 下位机
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下位机根据传送带脉冲等触发相机，接收上位机给的数据，按其要求控制阀板，用在各种分选机上。
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下位机根据传送带脉冲等触发相机，接收上位机给的数据，按其要求控制阀板。本次下位机采用的硬件是[Microphase](https://www.microphase.cn/)的XME0724CB ZYNQ开发板，具体核心板型号为XME0724-10，到手后记得把各排插针焊一下，如左图：
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为了供电稳定，采用叠板给底板5V供电，由底板输出3.3V供回给叠板，叠板就是IO扩展板，将IO扩展板插在底板排针上，叠起来，因此称为叠板，如上图中和上图右。
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IO扩展版提供了
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- 1个12V电源输入
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- 3个相机触发，2个为冗余
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- 1个ZYNQ散热风扇接口
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- 6个编码器输入，5个为冗余
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- 8个阀板接口，2个为冗余
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接线时，12V电源连接到IO扩展板的电源接口，阀板从左到右应连接在阀板接口1~6上，相机线应连接相机触发接口`TRIG1`和对应的`GND`接口，编码器线应连接在编码器输入接口`E1`和对应的`GND`接口。注意底板不连接任何外部电源。
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开发和部署说明见[doc/develop_and_deploy.md](doc/develop_and_deploy.md)
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## 目录结构
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## 目录结构
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- binary为编译好的可执行文件
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- doc为说明文档，包括开发和部署细节、硬件设计的描述等
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- [develop_and_deploy.md](doc/develop_and_deploy.md)为开发和部署说明，首先看这个文档
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- [hardware_description.md](doc/hardware_description.md)为PL端逻辑设计说明，阐述了硬件工作的整体流程
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- [pl_reference_mannual.md](doc/pl_reference_mannual.md)为PL端逻辑在AXI总线上映射的寄存器参考手册
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- script为配置系统、安装环境、安装可执行文件、卸载可执行文件等的脚本
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- script为配置系统、安装环境、安装可执行文件、卸载可执行文件等的脚本
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关于脚本的使用，见[doc/develop_and_deploy.md](doc/develop_and_deploy.md)
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- target.sh为嵌入式linux中自动启动应用程序脚本
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- load\*.sh为嵌入式linux中加载驱动的脚本
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- .bashrc为嵌入式linux中配置环境变量的脚本
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- protocol为上位机和下位机通信的协议
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- protocol为上位机和下位机通信的协议
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- hardware下位机主板、接口板、底板等的硬件设计
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- hardware下位机主板、接口板、底板等的硬件设计
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- source为可执行文件的源程序
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- pl_platform为PL端硬件设计
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- xme0724ioextend为IO叠板的原理图和PCB
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- source为XME0724板子上运行的源程序
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- liunx_app为Linux上运行的应用程序，即业务逻辑
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- linux_driver为Linux上的驱动，用于控制自定义的PL端硬件
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- petalinux_config为petalinux工具在编译u-boot、kernel、rootfs前进行的配置
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- petalinux_devicetree为本次自定义的Linux设备树文件部分，其余设备树为自动生成的
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- petalinux_hwdescription为petalinux所使用的硬件描述文件，包含了vivado工程中的比特流等信息
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## 版本
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## 版本
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# 开发和部署
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## 开发
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本次开发基于zynq芯片，因此FPGA设计软件为Vitis中包含的[Vivado 2021.2](https://china.xilinx.com/support/download/index.html/content/xilinx/zh/downloadNav/vitis.html)，Linux编译工具为[petalinux 2022.1](https://china.xilinx.com/support/download/index.html/content/xilinx/zh/downloadNav/embedded-design-tools.html)，Linux应用程序编译工具为linaro的[arm-linux-gnueabihf-gcc 12.0.1](https://snapshots.linaro.org/gnu-toolchain/12.0-2022.02-1/arm-linux-gnueabihf/)。
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### 生成硬件描述文件
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见[doc/hardware_description.md](hardware_description.md)
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### 创建PETALINUX工程
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1. 创建名为`ps-linux`的工程，并创建两个模块
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```shell
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$ cd ~
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$ petalinux-create -t project --template zynq -n ps-linux
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$ petalinux-create -t modules --name fifo --enable
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$ petalinux-create -t modules --name encoder --enable
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```
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2. 上传驱动代码[source/linux_driver/fifo.c](../source/linux_driver/fifo.c)和[source/linux_driver/encoder.c](../source/linux_driver/encoder.c)
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```shell
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$ cd ~/ps-linux/project-spec/meta-user/recipes-modules/fifo
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$ rz # 上传source/linux_driver/fifo.c
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$ cd ~/ps-linux/project-spec/meta-user/recipes-modules/encoder
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$ rz # 上传source/linux_driver/encoder.c
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```
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3. 上传xsa文件并config
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```shell
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$ cd ~/ps-linux; rz # 上传source/petalinux_hwdescription/system_wrapper.xsa
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$ petalinux-config --get-hw-description system_wrapper.xsa
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```
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在`petalinux-config`时候，按下面提示配置
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```shell
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# Subsystem AUTO Hardware Settings
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# ├─Serial Settings
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# | ├─FSBL Serial stdin/stdout (设为ps7_uart_0)
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# | ├─DTG Serial stdin/stdout (设为ps7_uart_0)
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# | └─System stdin/stdout baudrate for ps7_uart_0 (设为115200)
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# ├─Ethernet Settings
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# | ├─Randomise MAC address (不选)
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# | ├─Primary Ethernet (设为ps7_ethernet_0)
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# | ├─Ethernet MAC address (设为00:0a:35:00:1e:53)
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# | ├─Obtain IP address automatically (不选)
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# | ├─Static IP address (设为192.168.10.10)
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# | ├─Static IP netmask (设为255.255.255.0)
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# | └─Static IP gateway (设为192.168.10.1)
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# ├─Flash Settings
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# | └─Primary Flash (设为ps7_qspi_0)
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# ├─Flash Settings
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# | └─Primary Flash (设为ps7_qspi_0)
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# ├─SD/SDIO Settings
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# | └─Primary SD/SDIO (设为ps7_sd_0)
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# Image Packaging Configuration
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# └─Image Packaging Configuration
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# ├─Root filesystem type (设为EXT4 (SD/eMMC/SATA/USB))
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# ├─name for bootable kernel image (设为image.ub)
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# ├─Root filesystem formats (设为ext4 tar.gz)
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# └─Copy final images to tftpboot (不选)
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```
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4. 修改设备树，需要修改的文件为`project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi`，先删除该文件，然后上传新的自定义设备树文件[source/petalinux_devicetree/system-user.dtsi](../source/petalinux_devicetree/system-user.dtsi)
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```shell
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$ cd ~/ps-linux/project-spec/meta-user/recipes-bsp/device-tree/files
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$ rm system-user.dtsi
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$ rz # 上传source/petalinux_devicetree/system-user.dtsi
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```
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5. 配置kernel，使用命令`petalinux-config -c kernel`，按下面提示或[source/petalinux_config/kernel.cfg](../source/petalinux_config/kernel.cfg)配置
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```shell
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# File systems
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# ├─FUSE (Filesystem in Userspace) support (勾选为星号)
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# └─DOS/FAT/EXFAT/NT Filesystems
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# ├─Enable FAT UTF-8 option by default (勾选为星号)
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# ├─exFAT filesystem support (勾选为星号)
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# ├─NTFS file system support (勾选为星号)
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# └─NTFS write support (勾选为星号)
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# Device Drivers
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# └─USB support
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# └─OTG support (勾选为星号)
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```
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6. 配置rootfs，使用命令`petalinux-config -c rootfs`，按下面提示或[source/petalinux_config/rootfs_config](../source/petalinux_config/rootfs_config)配置
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```shell
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# Filesystem Packages
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# ├─base
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# | ├─shell
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# | | └─bash
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# | | └─bash (勾选为星号)
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# | ├─tar
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# | | └─tar (勾选为星号)
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# | ├─util-linux
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# | | ├─util-linux-blkid (勾选为星号)
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# | | ├─util-linux-lscpu (勾选为星号)
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# | | ├─util-linux-umount (勾选为星号)
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# | | └─util-linux-mount (勾选为星号)
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# | └─xz
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# | ├─xz (勾选为星号)
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# | └─liblzma (勾选为星号)
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# ├─console
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# | ├─network
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# | | ├─curl
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# | | | ├─curl (勾选为星号)
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# | | | └─libcurl (勾选为星号)
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# | | ├─dropbear
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# | | | └─dropbear (不选)
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# | | ├─ethtool
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# | | | └─ethtool (勾选为星号)
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# | | ├─lrzsz
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# | | | └─lrzsz (勾选为星号)
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# | | ├─minicom
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# | | | └─minicom (勾选为星号)
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# | | ├─openssh
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# | | | ├─openssh (勾选为星号)
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# | | | ├─openssh-misc (勾选为星号)
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# | | | ├─openssh-sshd (勾选为星号)
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# | | | ├─openssh-keygen (勾选为星号)
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# | | | ├─openssh-ssh (勾选为星号)
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# | | | ├─openssh-sftp (勾选为星号)
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# | | | ├─openssh-sftp-server (勾选为星号)
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# | | | └─openssh-scp (勾选为星号)
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# | | └─wget
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# | | └─wget (勾选为星号)
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# | ├─utils
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# | | ├─bash-completion
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# | | | ├─bash-completion (勾选为星号)
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# | | | └─bash-completion-extra (勾选为星号)
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# | ├─bzip2
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# | | ├─bzip2 (勾选为星号)
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# | | └─libbz2 (勾选为星号)
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# | ├─file
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# | | └─file (勾选为星号)
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# | ├─findutils
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# | | └─findutils (勾选为星号)
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# | ├─gawk
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# | | └─gawk (勾选为星号)
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# | ├─grep
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# | | └─grep (勾选为星号)
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# | ├─gzip
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# | | └─gzip (勾选为星号)
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# | ├─less
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# | | └─less (勾选为星号)
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# | ├─man
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# | | └─man (勾选为星号)
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# | ├─man-pages
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# | | └─man-pages (勾选为星号)
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# | ├─screen
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# | | └─screen (勾选为星号)
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# | ├─sed
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# | | └─sed (勾选为星号)
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# | ├─unzip
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# | | └─unzip (勾选为星号)
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# | ├─vim
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# | | ├─vim (勾选为星号)
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# | | ├─vim-syntax (勾选为星号)
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# | | └─vim-common (勾选为星号)
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# | └─zip
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# | └─zip (勾选为星号)
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# ├─devel
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# | └─lsof
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# | └─lsof (勾选为星号)
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# ├─misc
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# | └─perf
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# | └─perf (勾选为星号)
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# Image Features
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# ├─imagefeature-ssh-server-dropbear (不选)
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# ├─imagefeature-ssh-server-openssh (勾选为星号)
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# ├─imagefeature-hwcodecs (勾选为星号)
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# └─imagefeature-package-management (勾选为星号)
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# modules
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# ├─encoder (勾选为星号)
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# └─fifo (勾选为星号)
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# PetaLinux RootFS Settings
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# ├─ADD_EXTRA_USERS (root:3703;petalinux:3703;)
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# ├─ADD_USERS_TO_GROUPS (petalinux:audio,video;)
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# └─ADD_USERS_TO_SUDOERS (petalinux)
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```
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### 编译PETALINUX工程
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1. 编译工程，使用命令`petalinux-build`。编译完成，在当前工程目录下生成images文件夹，该命令将生成设备树文件、FSBL文件、U-Boot文件，Linux Kernel文件和rootfs文件镜像
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2. 制作BOOT.BIN启动文件，具体命令如下：
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```shell
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$ cd ~/petalinux-projects/ps-linux/images/linux/ # 生成的BOOT.BIN也在该路径下
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$ petalinux-package --boot --fsbl ./zynq_fsbl.elf --fpga ./system.bit --u-boot ./u-boot.elf --force
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```
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## 部署
|
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|
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> 注意：这部分所需的文件按上一章节编译得到或者从github的release中下载
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### SSH连接
|
||||||
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||||||
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1. 电脑网卡设置到开发板同一网段
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||||||
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2. SSH连接信息如下
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||||||
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|
||||||
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```shell
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||||||
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$ sshpass -p "3703" ssh root@192.168.10.10 -p 22
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||||||
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```
|
||||||
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|
||||||
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|
||||||
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### 修改文件系统
|
||||||
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|
||||||
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> 注意：github的release中包含了修改完成的rootfs.tar.gz，因此无需重复本节的步骤，本节仅用作记录修改步骤
|
||||||
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||||||
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1. 给SD卡创建DOS分区表，然后分2个区并创建文件系统，细节如下表：
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||||||
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|
||||||
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| 扇区 | 大小 | 分区类型 | 文件系统 | 卷标 |
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||||||
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| -------------- | -------------- | ----------------- | -------- | ------ |
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||||||
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| 2048~x扇区 | 100M | C W95 FAT32 (LBA) | FAT32 | boot |
|
||||||
|
| x扇区~最后扇区 | ≈SD卡大小-100M | 83 Linux | ext4 | rootfs |
|
||||||
|
|
||||||
|
2. 将打包和编译得到的BOOT.BIN、boot.scr和image.ub复制到boot分区；将rootfs.tar.gz解压到rootfs分区。
|
||||||
|
|
||||||
|
3. 拨码开关拨到SD卡启动，插入SD卡到XME0724底板上，上电启动。
|
||||||
|
|
||||||
|
4. 终端软件连接底板上的串口，波特率115200，8位，1停止位，无校验
|
||||||
|
|
||||||
|
5. 修改/etc/shadow文件，将root用户的密码删除，切换到root用户并设定密码为3703，具体命令如下:
|
||||||
|
|
||||||
|
```shell
|
||||||
|
$ sudo sed "1c root::15069:0:99999:7:::" /etc/shadow
|
||||||
|
# 如果没有sed命令，用任何其他方式都可以，比如vim
|
||||||
|
$ su root
|
||||||
|
$ passwd
|
||||||
|
```
|
||||||
|
|
||||||
|
|
||||||
|
6. 配置网络和ssh服务，用root登录：
|
||||||
|
|
||||||
|
```shell
|
||||||
|
$ vi /etc/network/interfaces
|
||||||
|
添加或确认内容如下：
|
||||||
|
auto eth0
|
||||||
|
iface eth0 inet static
|
||||||
|
address 192.168.10.10
|
||||||
|
netmask 255.255.255.0
|
||||||
|
gateway 192.168.10.1
|
||||||
|
$ vi /etc/ssh/sshd_config
|
||||||
|
确认修改如下选项：
|
||||||
|
PermitRootLogin yes
|
||||||
|
PermitEmptyPasswords yes
|
||||||
|
PasswordAuthentication yes
|
||||||
|
$ reboot
|
||||||
|
```
|
||||||
|
|
||||||
|
7. 安装编译得到的驱动文件fifo.ko和encode.ko，并设置自动加载，对应脚本见[script/loadfifo.sh](../script/loadfifo.sh)和[script/loadencoder.sh](../script/loadencoder.sh)
|
||||||
|
|
||||||
|
ssh方式，root登录:
|
||||||
|
|
||||||
|
```shell
|
||||||
|
$ cd ~; rz #上传fifo.ko
|
||||||
|
$ rz # 上传encoder.ko
|
||||||
|
$ mv fifo.ko encoder.ko /lib/modules/[内核版本]/kernel/drivers/
|
||||||
|
$ cd /lib/modules/[内核版本]; depmod
|
||||||
|
$ echo "#!/bin/sh\nmodprobe fifo" > /etc/init.d/loadfifo.sh
|
||||||
|
$ echo "#!/bin/sh\nmodprobe encoder" > /etc/init.d/loadencoder.sh
|
||||||
|
$ chmod 755 /etc/init.d/loadfifo.sh
|
||||||
|
$ chmod 755 /etc/init.d/loadencoder.sh
|
||||||
|
$ cd /etc/rc5.d
|
||||||
|
$ ln -s ../init.d/loadfifo.sh S20loadfifo.sh
|
||||||
|
$ ln -s ../init.d/loadencoder.sh S20loadencoder.sh
|
||||||
|
```
|
||||||
|
|
||||||
|
8. 安装编译得到的应用程序target，并设置自启动，对应脚本见[script/target.sh](../script/target.sh)
|
||||||
|
|
||||||
|
ssh方式，root登录:
|
||||||
|
|
||||||
|
```shell
|
||||||
|
$ cd ~; rz # 上传target
|
||||||
|
$ chmod 755 target
|
||||||
|
$ echo "#!/bin/sh\nif [ -x /home/root/target ]; then\n /home/root/target\nfi" > /etc/init.d/target.sh
|
||||||
|
$ chmod 755 /etc/init.d/target.sh
|
||||||
|
$ cd /etc/rc5.d
|
||||||
|
$ ln -s ../init.d/target.sh S99target.sh
|
||||||
|
```
|
||||||
|
|
||||||
|
9. \[可选\] 设置.bashrc，美化PS1，对应脚本见[script/.profile](../script/.profile)和[script/.bashrc](../script/.bashrc)
|
||||||
|
|
||||||
|
```shell
|
||||||
|
$ cd ~; rz # 上传.bashrc
|
||||||
|
$ rz # 上传.profile
|
||||||
|
$ if [ ! -a /home/petalinux/.profile ]; then cp /home/root/.profile /home/petalinux/ fi
|
||||||
|
$ if [ ! -a /home/petalinux/.bashrc ]; then cp /home/root/.bashrc /home/petalinux/ & chown petalinux:petalinux -R /home/petalinux fi
|
||||||
|
$ source ~/.profile
|
||||||
|
```
|
||||||
|
|
||||||
|
10. \[可选\] 安装ncurses-6.3和htop.
|
||||||
|
|
||||||
|
```shell
|
||||||
|
$ cd ~; rz # 上传ncurses-6.3.tar.gz
|
||||||
|
$ tar xzf /home/root/ncurses-6.3.tar.gz -C /usr/
|
||||||
|
$ rz # 上传htop.tar.gz
|
||||||
|
$ tar xzf /home/root/htop.tar.gz -C /usr/
|
||||||
|
```
|
||||||
|
|
||||||
|
### SD卡启动
|
||||||
|
|
||||||
|
1. 给SD卡创建DOS分区表，然后分2个区并创建文件系统，细节如下表：
|
||||||
|
|
||||||
|
| 扇区 | 大小 | 分区类型 | 文件系统 | 卷标 |
|
||||||
|
| -------------- | -------------- | ----------------- | -------- | ------ |
|
||||||
|
| 2048~x扇区 | 100M | C W95 FAT32 (LBA) | FAT32 | boot |
|
||||||
|
| x扇区~最后扇区 | ≈SD卡大小-100M | 83 Linux | ext4 | rootfs |
|
||||||
|
|
||||||
|
2. 将Github Release中的BOOT.BIN、boot.scr和image.ub复制到boot分区；将rootfs.tar.gz解压到rootfs分区。
|
||||||
|
|
||||||
|
3. 拨码开关拨到SD卡启动，插入SD卡到XME0724底板上，上电启动。
|
||||||
BIN
doc/hardware_description.assets/2.png
Normal file
BIN
doc/hardware_description.assets/2.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 203 KiB |
54
doc/hardware_description.md
Normal file
54
doc/hardware_description.md
Normal file
@ -0,0 +1,54 @@
|
|||||||
|
# 硬件平台
|
||||||
|
|
||||||
|
PL端主要由4个外设组成，分别时**风扇控制器**(FAN)，**编码和分频控制器**(ENCODER)，**先入先出队列**(FIFO)和**阀板控制器**(VALVE)。其中阀板控制器没有提供AXI接口，因此并没有映射寄存器，软件也无法进行控制。各个控制器的连接关系如下图所示。
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
由于开发板的PL端没有自带晶振，所以4个外设由统一的同步时钟驱动，时钟源来自PS端，为200MHz，软件不可修改。外部编码器信号输入**编码和分频控制器**，控制器根据软件设置的阀触发分频值和相机触发分频值对编码器信号进行分频，分频后的信号用于驱动喷阀动作和触发相机拍照。为同步触发相机和移出队列以及保持队列中数据的动态平衡，**先入先出队列**在相机触发同时输出一个数据，即**先入先出队列**读信号和相机触发共用同一个信号。而由于电磁阀的物理特性导致电磁阀无法以触发相机的频率进行开关，因此**阀板控制器**对先入先出队列输出总线上的数据进行重采样，即按照**编码和分频控制器**输出的阀触发信号更新并转换为阀板协议，输出电磁阀的状态。设计的风扇控制器用于驱动风扇的启停，给ZYNQ芯片进行降温，防止芯片过热导致工作中出现问题。
|
||||||
|
|
||||||
|
## 生成硬件描述文件
|
||||||
|
|
||||||
|
1. 创建名为test_lower_machine的工程，打开**Block Design**，添加ZYNQ7 Processing System、ip_fifo、ip_encoder、ip_fan、valve_interfaces模块。
|
||||||
|
2. 在ZYNQ7 Processing System中勾选Quad SPI Flash [1-6]、Ethernet 0 [16-27]、USB 0 [28-39]、SD 0 [40-45]、SD 1 [46-51]、UART 0 [14-15]、TTC 0 [EMIO]、GPIO MIO {Ethernet PHY Reset [7]、USB PHY Reset[8]}
|
||||||
|
3. 按顺序点击**Generate Outputs Product** -> **Create HDL Wrapper** -> **Generate Bitstream**，**File** -> **Export Export Hardware** ，得到xsa文件。
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
## ENCODER模块
|
||||||
|
|
||||||
|
1. encoder模块自定义接口in_signal、out_signal_camera_posedge、out_signal_valve_posedge、out_signal_camera、out_signal_valve
|
||||||
|
|
||||||
|
2. in_signal接口与外部编码器相连，接收外部编码器信号
|
||||||
|
|
||||||
|
3. out_signal_camera为分频后的信号，用于驱动相机拍照
|
||||||
|
|
||||||
|
4. out_signal_camera_posedge为out_signal_camera的上升沿，该信号输出给fifo模块的rd_en接口，用来驱动fifo模块将数据加载到AXI总线上
|
||||||
|
|
||||||
|
5. out_signal_valve_posedge为out_signal_valve的上升沿，该信号输出给valve_interfaces模块的valve_en信号，用于输出AXI总线上的数据，驱动喷阀动作
|
||||||
|
|
||||||
|
6. ENCODER模块寄存器说明见[doc/pl_reference_mannual.md](pl_reference_mannual.md)中的ENCODER控制器部分
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
## FIFO模块
|
||||||
|
|
||||||
|
1. fifo模块自定义接口rd_en、dout[383:0]、empty、full、almost_full、almost_empty、data_count[11:0]、fifo_valid
|
||||||
|
2. rd_en接收out_signal_camera_posedge传来的信号，用来驱动fifo模块将数据加载到AXI总线上
|
||||||
|
3. dout[383:0]为驱动喷阀动作的总数据，数据位宽为384bit
|
||||||
|
4. 当empty信号拉高时，表示fifo中数据已经为空，无法输出有效数据
|
||||||
|
5. fifo模块寄存器说明见[doc/pl_reference_mannual.md](pl_reference_mannual.md)中的FIFO控制器部分
|
||||||
|
|
||||||
|
## FAN模块
|
||||||
|
|
||||||
|
1. fan模块自定义接口fan用于控制风扇的启停
|
||||||
|
2. fan模块寄存器说明见[doc/pl_reference_mannual.md](pl_reference_mannual.md)中的FAN控制器部分
|
||||||
|
|
||||||
|
> Note：fan模块代码中设计了PWM调速功能，但由于硬件兼容问题导致，无法观察到调速现象。但正常的启停可以做到
|
||||||
|
|
||||||
|
## VALVE_INTERFACES模块
|
||||||
|
|
||||||
|
1. valve_interfaces模块自定义接口total_valve_data[383:0]、empty、valve_en、sclk[7:0]、sen[7:0]、sdata[7:0]
|
||||||
|
2. total_valve_data[383:0]接收fifo模块dout接口传输的数据，对其重采样后由sdata接口输出给各个阀板
|
||||||
|
3. empty信号与fifo模块的empty信号相连。valve_interfaces模块检测到empty信号为高后，表示fifo中的数据被读空，此时将total_valve_data的384bit的数据全部置为0，然后输出给阀板
|
||||||
|
4. valve_en信号拉高后将384bit的数据输出给阀板，更新喷阀状态。该信号不拉高时则不更新喷阀状态
|
||||||
|
5. sclk[7:0]、sen[7:0]、sdata[7:0]为对应8块阀板的时钟信号线、使能信号线以及数据信号线
|
||||||
BIN
doc/pl_reference_mannual.assets/blocks.pptx
Normal file
BIN
doc/pl_reference_mannual.assets/blocks.pptx
Normal file
Binary file not shown.
1
doc/pl_reference_mannual.assets/encoder_block.svg
Normal file
1
doc/pl_reference_mannual.assets/encoder_block.svg
Normal file
@ -0,0 +1 @@
|
|||||||
|
<svg width="1384" height="987" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xml:space="preserve" overflow="hidden"><defs><clipPath id="clip0"><rect x="1288" y="870" width="1384" height="987"/></clipPath></defs><g clip-path="url(#clip0)" transform="translate(-1288 -870)"><path d="M1288 1378 1442.99 1378" stroke="#B4C7E7" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2479.5 1538.5 2656.49 1538.5" stroke="#2F5597" stroke-width="20.625" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2479.5 1427.5 2656.49 1427.5" stroke="#2F5597" stroke-width="20.625" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2479 1060 2655.99 1060" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2479 1180 2655.99 1180" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2479 1300 2655.99 1300" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1288 1138 1442.99 1138" stroke="#B4C7E7" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1288 1259 1464.99 1259" stroke="#B4C7E7" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1386.5 951.632C1386.5 908.481 1421.48 873.5 1464.63 873.5L2465.37 873.5C2508.52 873.5 2543.5 908.481 2543.5 951.632L2543.5 1664.37C2543.5 1707.52 2508.52 1742.5 2465.37 1742.5L1464.63 1742.5C1421.48 1742.5 1386.5 1707.52 1386.5 1664.37Z" stroke="#2F5597" stroke-width="6.875" stroke-miterlimit="8" fill="#DAE3F3" fill-rule="evenodd"/><text font-family="Arial,Arial_MSFontService,sans-serif" font-weight="700" font-size="73" transform="matrix(1 0 0 1 2121.52 1072)">Virtual Trig<tspan font-size="73" x="53.2813" y="124">Ex/In Trig</tspan><tspan font-size="73" x="237.76" y="247">CLR</tspan><tspan font-size="73" x="-101.406" y="370">Cam </tspan><tspan font-size="73" x="77.9165" y="370">Div</tspan><tspan font-size="73" x="191.927" y="370">[31:0]</tspan><tspan font-size="73" x="-134.063" y="493">Valve </tspan><tspan font-size="73" x="77.9165" y="493">Div</tspan><tspan font-size="73" x="191.927" y="493">[31:0]</tspan><tspan fill="#767171" font-size="73" x="-702.381" y="85">Cam </tspan><tspan fill="#767171" font-size="73" x="-523.058" y="85">Trig</tspan><tspan fill="#767171" font-size="73" x="-702.381" y="209">Valve Trig</tspan><tspan fill="#767171" font-size="73" x="-702.381" y="332">Encoder </tspan><tspan fill="#767171" font-size="73" x="-388.996" y="332">In</tspan></text></g></svg>
|
||||||
|
After Width: | Height: | Size: 2.7 KiB |
BIN
doc/pl_reference_mannual.assets/encoder_cdivr.png
Normal file
BIN
doc/pl_reference_mannual.assets/encoder_cdivr.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 6.2 KiB |
BIN
doc/pl_reference_mannual.assets/encoder_cr.png
Normal file
BIN
doc/pl_reference_mannual.assets/encoder_cr.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 5.7 KiB |
BIN
doc/pl_reference_mannual.assets/encoder_regs.png
Normal file
BIN
doc/pl_reference_mannual.assets/encoder_regs.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 25 KiB |
BIN
doc/pl_reference_mannual.assets/encoder_vdivr.png
Normal file
BIN
doc/pl_reference_mannual.assets/encoder_vdivr.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 6.1 KiB |
1
doc/pl_reference_mannual.assets/fan_block.svg
Normal file
1
doc/pl_reference_mannual.assets/fan_block.svg
Normal file
@ -0,0 +1 @@
|
|||||||
|
<svg width="1226" height="662" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xml:space="preserve" overflow="hidden"><defs><clipPath id="clip0"><rect x="1440" y="922" width="1226" height="662"/></clipPath></defs><g clip-path="url(#clip0)" transform="translate(-1440 -922)"><path d="M1440 1415 1594.99 1415" stroke="#B4C7E7" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1467 1140 1621.66 1140" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2504 1228 2658.66 1228" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1551.5 984.391C1551.5 951.866 1577.87 925.5 1610.39 925.5L2503.61 925.5C2536.13 925.5 2562.5 951.866 2562.5 984.391L2562.5 1521.61C2562.5 1554.13 2536.13 1580.5 2503.61 1580.5L1610.39 1580.5C1577.87 1580.5 1551.5 1554.13 1551.5 1521.61Z" stroke="#2F5597" stroke-width="6.875" stroke-miterlimit="8" fill="#DAE3F3" fill-rule="evenodd"/><text font-family="Arial,Arial_MSFontService,sans-serif" font-weight="700" font-size="73" transform="matrix(1 0 0 1 2378.67 1268)">SPD<tspan font-size="73" x="-800.976" y="-85">EN</tspan><tspan fill="#767171" font-size="73" x="-800.976" y="162">FAN</tspan></text></g></svg>
|
||||||
|
After Width: | Height: | Size: 1.3 KiB |
BIN
doc/pl_reference_mannual.assets/fan_cr.png
Normal file
BIN
doc/pl_reference_mannual.assets/fan_cr.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 4.9 KiB |
BIN
doc/pl_reference_mannual.assets/fan_regs.png
Normal file
BIN
doc/pl_reference_mannual.assets/fan_regs.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 19 KiB |
BIN
doc/pl_reference_mannual.assets/fan_spdr.png
Normal file
BIN
doc/pl_reference_mannual.assets/fan_spdr.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 6.1 KiB |
1
doc/pl_reference_mannual.assets/fifo_block.svg
Normal file
1
doc/pl_reference_mannual.assets/fifo_block.svg
Normal file
@ -0,0 +1 @@
|
|||||||
|
<svg width="1398" height="862" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xml:space="preserve" overflow="hidden"><defs><clipPath id="clip0"><rect x="1180" y="712" width="1398" height="862"/></clipPath></defs><g clip-path="url(#clip0)" transform="translate(-1180 -712)"><path d="M1180 1330 1356.99 1330" stroke="#2F5597" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1180 1214 1356.99 1214" stroke="#2F5597" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1180 1087 1356.99 1087" stroke="#2F5597" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385.5 855.5 2562.49 855.5" stroke="#B4C7E7" stroke-width="20.625" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385 973 2561.99 973.001" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385 1093 2561.99 1093" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385 1214 2561.99 1214" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385 1330 2561.99 1330" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385.5 1447.5 2562.49 1447.5" stroke="#2F5597" stroke-width="20.625" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1180 844 1334.99 844" stroke="#B4C7E7" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1180 962 1356.99 962.001" stroke="#B4C7E7" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1289.5 792.373C1289.5 749.917 1323.92 715.5 1366.37 715.5L2369.63 715.5C2412.08 715.5 2446.5 749.917 2446.5 792.373L2446.5 1493.63C2446.5 1536.08 2412.08 1570.5 2369.63 1570.5L1366.37 1570.5C1323.92 1570.5 1289.5 1536.08 1289.5 1493.63Z" stroke="#2F5597" stroke-width="6.875" stroke-miterlimit="8" fill="#DAE3F3" fill-rule="evenodd"/><text fill="#767171" font-family="Arial,Arial_MSFontService,sans-serif" font-weight="700" font-size="73" transform="matrix(1 0 0 1 1874.98 867)">DT_OUT<tspan font-size="73" x="292.76" y="0">[</tspan><tspan font-size="73" x="317.396" y="0">383:0</tspan><tspan font-size="73" x="504.74" y="0">]</tspan><tspan fill="#000000" font-size="73" x="236.615" y="124">xEMPTY</tspan><tspan fill="#000000" font-size="73" x="342.604" y="247">FULL</tspan><tspan fill="#000000" font-size="73" x="-72.7605" y="370">ALMOST_EMPTY</tspan><tspan fill="#000000" font-size="73" x="-7.448" y="493">ALMOST_FULL</tspan><tspan fill="#000000" font-size="73" x="73.3333" y="616">COUNT[11:0]</tspan><tspan font-size="73" x="-518.112" y="0">FIFO_VALID</tspan><tspan font-size="73" x="-518.112" y="124">RD_SYN</tspan><tspan fill="#000000" font-size="73" x="-518.112" y="247">WR_SYN</tspan><tspan fill="#000000" font-size="73" x="-518.112" y="370">CLEAR</tspan><tspan fill="#000000" font-size="73" x="-518.112" y="493">DT_IN</tspan><tspan fill="#000000" font-size="73" x="-306.705" y="493">[383:0]</tspan></text></g></svg>
|
||||||
|
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|
|||||||
|
# PL 端自定义外设参考手册
|
||||||
|
|
||||||
|
## 存储器和总线架构
|
||||||
|
|
||||||
|
### 系统架构
|
||||||
|
|
||||||
|
PL端主要由4个外设组成，分别时**风扇控制器**(FAN)，**编码和分频控制器**(ENCODER)，**先入先出队列**(FIFO)和**阀板控制器**(VALVE)。其中阀板控制器没有提供AXI接口，因此并没有映射寄存器，软件也无法进行控制。各个控制器的连接关系如下图所示。
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
4个外设由统一的同步时钟驱动，时钟源来自PS端，为200MHz，软件不可修改。外部编码器信号输入**编码和分频控制器**，控制器根据软件设置的阀触发分频值和相机触发分频值对编码器信号进行分频。为同步触发相机和移出队列，**先入先出队列**在相机触发同时输出一个数据，即**先入先出队列**读信号和相机触发共用同一个信号。而由于电磁阀的物理特性导致电磁阀无法以触发相机的频率进行开关，因此**阀板控制器**对先入先出队列输出总线上的数据进行重采样，即按照**编码和分频控制器**输出的阀触发信号更新并转换为阀板协议，输出电磁阀的状态。
|
||||||
|
|
||||||
|
具体的硬件设计和信号说明见[doc/hardware_description.md](hardware_description.md)
|
||||||
|
|
||||||
|
各控制器的边界地址和所属总线等信息如下表所示
|
||||||
|
|
||||||
|
| 边界地址 | 外设 | 总线 |
|
||||||
|
| ----------------------- | ---------------- | --------- |
|
||||||
|
| 0x43c00000 - 0x43c0ffff | 先入先出队列 | M_AXI_GP0 |
|
||||||
|
| 0x43c10000 - 0x43c1ffff | 编码和分频控制器 | M_AXI_GP0 |
|
||||||
|
| 0x43c20000 - 0x43c2ffff | 风扇控制器 | M_AXI_GP0 |
|
||||||
|
|
||||||
|
## 风扇控制器 (FAN)
|
||||||
|
|
||||||
|
### FAN简介
|
||||||
|
|
||||||
|
FAN模块用于控 制散热风扇的启停以及通过PWM调整风扇速度。通过对寄存器写入值，该模块能正常启停散热风扇，但由于代码与硬件兼容问题，导致无法观察到调速现象。
|
||||||
|
|
||||||
|
### FAN主要特性
|
||||||
|
|
||||||
|
- 能控制风扇的启停
|
||||||
|
- 自定义占空比，调整风扇转速
|
||||||
|
|
||||||
|
### FAN功能说明
|
||||||
|
|
||||||
|
<img src="pl_reference_mannual.assets/fan_block.svg" alt="fan_block" style="zoom:20%;" />
|
||||||
|
|
||||||
|
通过将开启使能拉高，开启风扇。通过向风速寄存器写入PWM占空值，控制风扇减少或提高风速。
|
||||||
|
|
||||||
|
### FAN寄存器说明
|
||||||
|
|
||||||
|
FAN模块寄存器主要包括控制寄存器 (FAN_CR)、风速寄存器 (FAN_SPDR)。控制寄存器 (FAN_CR)用于控制风扇开启或关闭的状态，风速寄存器 (FAN_SPDR)通过PWM技术设置风扇转动的速度。
|
||||||
|
|
||||||
|
**Base Address: 0x43c20000**
|
||||||
|
|
||||||
|
#### FAN控制寄存器 (FAN_CR)
|
||||||
|
|
||||||
|
偏移地址: 0x00<br/>复位值: 0x0000 0000
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
| **Field** | **Description** |
|
||||||
|
| :----------- | :----------------------------------------------------------- |
|
||||||
|
| 位31:16 保留 | 必须保持复位值 |
|
||||||
|
| 位0 **EN** | 内部触发信号 (Virtual Triggle Signal)<br /> 0: 停止风扇<br/> 1: 开启风扇 |
|
||||||
|
|
||||||
|
#### FAN风速寄存器 (FAN_SPDR)
|
||||||
|
|
||||||
|
偏移地址: 0x04<br/>复位值: 0x0000 0000
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
| **Field** | **Description** |
|
||||||
|
| :------------- | :----------------------------------------------------------- |
|
||||||
|
| 位31:0 **SPD** | 该寄存器值表示设置的风扇PWM占空值，占空比转换公式如下。<br />占空比% = SPD / (2 ^ 32 - 1) * 100% |
|
||||||
|
|
||||||
|
#### FAN寄存器映射
|
||||||
|
|
||||||
|
FAN寄存器可映射为32位可寻址寄存器，如下表所述：
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
## 编码和分频控制器 (ENCODER)
|
||||||
|
|
||||||
|
### ENCODER简介
|
||||||
|
|
||||||
|
ENCODER模块主要用于实现编码器计数以及对编码器脉冲进行分频，分频后的脉冲信号输出给相机和阀板，并且能控制FIFO模块的读操作，将数据加载到AXI数据总线上。该模块包括1个控制寄存器 (ENCODER_CR)、阀触发分频寄存器 (ENCODER_VDIVR)、相机触发分频寄存器 (ENCODER_CDIVR)。
|
||||||
|
|
||||||
|
### ENCODER主要特性
|
||||||
|
|
||||||
|
- 独立设置对相机和喷阀的分频系数
|
||||||
|
- 内外两种触发模式选择
|
||||||
|
- 清空功能
|
||||||
|
|
||||||
|
### ENCODER功能说明
|
||||||
|
|
||||||
|
下图给出了ENCODER的主要信号：
|
||||||
|
|
||||||
|
<img src="pl_reference_mannual.assets/encoder_block.svg" alt="图片1" style="zoom: 20%;" />
|
||||||
|
|
||||||
|
ENCODER模块接收编码器脉冲信号，通过设置的相机和喷阀分频系数，生成对应的触发信号。编码器脉冲信号可由内部或外部触发模式产生。
|
||||||
|
|
||||||
|
### ENCODER寄存器说明
|
||||||
|
|
||||||
|
ENCODER模块的寄存器主要有控制寄存器 (ENCODER_CR)、阀触发分频寄存器 (ENCODER_VDIVR)和相机触发分频寄存器 (ENCODER_CDIVR)。控制寄存器 (ENCODER_CR)用于进行触发模式选择以及复位清空，阀触发分频寄存器 (ENCODER_VDIVR)用于寄存输入的分频系数，将编码器脉冲除以分频系数得到触发脉冲。
|
||||||
|
|
||||||
|
**Base Address: 0x43c10000**
|
||||||
|
|
||||||
|
#### ENCODER控制寄存器 (ENCODER_CR)
|
||||||
|
|
||||||
|
偏移地址: 0x00<br/>复位值: 0x0000 0000
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
| **Field** | **Description** |
|
||||||
|
| :---------- | :----------------------------------------------------------- |
|
||||||
|
| 位31:3 保留 | 必须保持复位值 |
|
||||||
|
| 位2 **VTS** | 内部触发信号 (Virtual Triggle Signal)<br /> **MOD**位置1时，由上位机软件写入，将该位信号作为触发信号 |
|
||||||
|
| 位1 **MOD** | 模式选择 (Mode)<br /> 0: 外部触发模式，外部触发编码器转动<br /> 1: 内部触发模式，上位机软件模拟触发信号 |
|
||||||
|
| 位0 **CLR** | 清除缓存 (Clear)<br /> 清除编码和分频控制器内部的分频计数值，不影响VDIV和CDIV |
|
||||||
|
|
||||||
|
#### ENCODER阀触发分频寄存器 (ENCODER_VDIVR)
|
||||||
|
|
||||||
|
偏移地址: 0x04<br/>复位值: 0x0000 0000
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
| **Field** | **Description** |
|
||||||
|
| :-------------- | :----------------------------------------------------------- |
|
||||||
|
| 位31:0 **VDIV** | 阀触发分频值<br /> 写入数据后编码和分频控制器自动清除缓存并应用新的数值 <br /> 注意：0表示不间断触发，即PL端每个时钟周期均触发阀模块 |
|
||||||
|
|
||||||
|
#### ENCODER相机触发分频寄存器 (ENCODER_CDIVR)
|
||||||
|
|
||||||
|
偏移地址: 0x08<br/>复位值: 0x0000 0000
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
| **Field** | **Description** |
|
||||||
|
| :-------------- | :----------------------------------------------------------- |
|
||||||
|
| 位31:0 **CDIV** | 相机触发分频值<br /> 写入数据后编码和分频控制器自动清除缓存并应用新的数值 <br /> 注意：0表示不间断触发，即PL端每个时钟周期均触发相机 |
|
||||||
|
|
||||||
|
#### ENCODER寄存器映射
|
||||||
|
|
||||||
|
ENCODER寄存器可映射为32位可寻址寄存器，如下表所述：
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
## 先入先出队列 (FIFO)
|
||||||
|
|
||||||
|
### FIFO简介
|
||||||
|
|
||||||
|
FIFO模块为下位机的核心模块，用于接收控制喷阀的信号，以先入先出原则，按顺序由encoder模块控制输出给阀板。
|
||||||
|
|
||||||
|
### FIFO主要特性
|
||||||
|
|
||||||
|
- 384bit数据位宽，最大4096深度
|
||||||
|
- 实时计算存储数据数量，提供队列满，队列空等信号
|
||||||
|
- 指示队列输出状态
|
||||||
|
- 清空功能
|
||||||
|
|
||||||
|
### FIFO功能说明
|
||||||
|
|
||||||
|
下图给出了FIFO的主要信号：
|
||||||
|
|
||||||
|
<img src="pl_reference_mannual.assets/fifo_block.svg" alt="fifo_block" style="zoom: 20%;" />
|
||||||
|
|
||||||
|
FIFO模块在写同步信号拉高后接收用于控制喷阀的384bit位宽的数据，并在读使能拉高后将数据加载到AXI数据总线上，当队列读空后，empty信号拉高，不输出有效数据，表示关闭喷阀。复位信号拉高后将整个队列清空。COUNT信号表示当前在FIFO内存在多少个有效数据。
|
||||||
|
|
||||||
|
### FIFO寄存器说明
|
||||||
|
|
||||||
|
FIFO模块寄存器主要包括数据寄存器x (FIFO_DATx)(x=0...11) 、状态寄存器 (FIFO_SR) 、控制寄存器 (FIFO_CR) 。数据寄存器x (FIFO_DATx)(x=0...11) 用于寄存写入的384bit数据，并保持该数据。状态寄存器 (FIFO_SR)用于反映FIFO内部数据的寄存状态，标志FIFO是否被读空、写满以及FIFO内当前存在多少有效数据。控制寄存器 (FIFO_CR) 用于控制AXI总线上的数据被写入FIFO，以及实现复位清空操作。
|
||||||
|
|
||||||
|
**Base Address: 0x43c00000**
|
||||||
|
|
||||||
|
#### FIFO数据寄存器x (FIFO_DATx) (x=0...11)
|
||||||
|
|
||||||
|
FIFO的写宽度为384bit，因此需12个32位寄存器**FIFO_DAT0**-**FIFO_DAT11**，按小端字节序共同组成384bit位宽。将数据写入这12个寄存器后，应对位**WS**写入1，此时数据寄存器组中的数据写入到FIFO中。
|
||||||
|
|
||||||
|
偏移地址: 0x00...0x2C<br/>复位值: 0x0000 0000
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
| **Field** | **Description** |
|
||||||
|
| :------------------------------ | :----------------------------------------------------------- |
|
||||||
|
| 位31:0 **DTIN[x\*32+31:x\*32]** | FIFO数据寄存器x写入数据位[x\*32+31:x\*32]<br />写入数据后该寄存器将保持写入的值，直到对**WS**位写入1，数据才会进入FIFO队列。不要读取该寄存器。结合VALVE外设可得 <br /> 0: 对应喷阀关闭 <br /> 1: 对应喷阀打开 |
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#### FIFO状态寄存器 (FIFO_SR)
|
||||||
|
|
||||||
|
状态寄存器指示FIFO的内部状态，数据数量等，为只读寄存器，不可写
|
||||||
|
|
||||||
|
偏移地址: 0x30<br/>复位值: 0x0000 0000
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
| **Field** | **Description** |
|
||||||
|
| :------------- | :----------------------------------------------------------- |
|
||||||
|
| 位31:17 保留 | 必须保持复位值 |
|
||||||
|
| 位16 **VLD** | 数据输出有效标志 (Valid)<br /> 0: 当前无有效输出，输出保持上一状态<br /> 1: 当前队列正在输出有效数据 |
|
||||||
|
| 位15 **AMEM** | 队列将空标志 (Almost Empty)<br /> 0: 队列没有被读空<br /> 1: 队列在一个读时钟周期后会被读空 |
|
||||||
|
| 位14 **EM** | 队列空标志 (Empty)<br /> 0: 队列中存在有效数据，没有被读空<br /> 1: 队列中已经没有有效数据 |
|
||||||
|
| 位13 **AMFU** | 队列将满标志 (Almost Full)<br /> 0: 队列没有被写满<br /> 1: 队列在一个写时钟周期后会被写满 |
|
||||||
|
| 位12 **FU** | 队列满标志 (Almost Full)<br /> 0: 队列中的有效数据小于FIFO数据深度<br /> 1: 队列中的有效数据达到FIFO数据深度 |
|
||||||
|
| 位11:0 **CNT** | 队列数据数量 (Data Count)<br />该值指示队列中的数据数量<br />注意：一个数据位384位宽 |
|
||||||
|
|
||||||
|
#### FIFO控制寄存器 (FIFO_CR)
|
||||||
|
|
||||||
|
偏移地址: 0x38<br/>复位值: 0x0000 00xx
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
| **Field** | **Description** |
|
||||||
|
| :---------- | :----------------------------------------------------------- |
|
||||||
|
| 位31:2 保留 | 必须保持复位值 |
|
||||||
|
| 位1 **CLR** | 清空队列 (Clear)<br />对该位写入1，队列将清空，同时队列输出为全0。<br />注意：不要写入除1以外的任何值。 |
|
||||||
|
| 位0 **WS** | 写入同步 (Write Synchronization)<br />对该位写入1，**FIFO_DATx**的数据按字节小端序进入队列。<br />注意：不要写入除1以外的任何值。 |
|
||||||
|
|
||||||
|
#### FIFO寄存器映射
|
||||||
|
|
||||||
|
FIFO寄存器可映射为32位可寻址寄存器，如下表所述：
|
||||||
|
|
||||||
|
<img src="pl_reference_mannual.assets/fifo_regs.png" alt="image-20220613220214064" />
|
||||||
1
hardware/pl_platform/README.md
Normal file
1
hardware/pl_platform/README.md
Normal file
@ -0,0 +1 @@
|
|||||||
|
PL端的fpga工程待补充
|
||||||
@ -1,555 +0,0 @@
|
|||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 22:01:10 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 23) to (Rev. 24)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 21:22:43 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 22) to (Rev. 23)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 21:17:10 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 21) to (Rev. 22)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 20:54:40 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 20) to (Rev. 21)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 14:00:19 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
CAUTION (success, with warnings) in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 19) to (Rev. 20)
|
|
||||||
|
|
||||||
After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
|
|
||||||
|
|
||||||
2. Connection Warnings
|
|
||||||
----------------------
|
|
||||||
|
|
||||||
Detected external port differences while upgrading 'system_ip_fifo_0_0'. These changes may impact your design.
|
|
||||||
|
|
||||||
|
|
||||||
-Upgraded port 'data_count' width 12 differs from original width 14
|
|
||||||
|
|
||||||
-Upgrade has added port 'fifo_valid'
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 13:32:41 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
CAUTION (success, with warnings) in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 18) to (Rev. 19)
|
|
||||||
|
|
||||||
After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
|
|
||||||
|
|
||||||
2. Connection Warnings
|
|
||||||
----------------------
|
|
||||||
|
|
||||||
Detected external port differences while upgrading 'system_ip_fifo_0_0'. These changes may impact your design.
|
|
||||||
|
|
||||||
|
|
||||||
-Upgraded port 'data_count' width 14 differs from original width 10
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 13:30:55 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 17) to (Rev. 18)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 13:26:18 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 16) to (Rev. 17)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 13:13:41 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 15) to (Rev. 16)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 13:02:46 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'valve_interface_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of valve_interface_0 (user.org:user:valve_interface:1.0) from (Rev. 2) to (Rev. 3)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Thu Apr 21 12:52:37 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 14) to (Rev. 15)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Wed Apr 20 20:51:39 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_encoder_0_1'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_encoder_0_1 (user.org:user:ip_encoder:1.0) from (Rev. 2) to (Rev. 3)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Wed Apr 20 16:50:39 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_encoder_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
CAUTION (success, with warnings) in the upgrade of system_ip_encoder_0_0 (user.org:user:ip_encoder:1.0) from (Rev. 1) to (Rev. 3)
|
|
||||||
|
|
||||||
After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
|
|
||||||
|
|
||||||
2. Connection Warnings
|
|
||||||
----------------------
|
|
||||||
|
|
||||||
Detected external port differences while upgrading 'system_ip_encoder_0_0'. These changes may impact your design.
|
|
||||||
|
|
||||||
|
|
||||||
-Upgrade has removed port 'out_signal'
|
|
||||||
|
|
||||||
-Upgrade has removed port 'out_signal_posedge'
|
|
||||||
|
|
||||||
-Upgrade has added port 'out_signal_camera'
|
|
||||||
|
|
||||||
-Upgrade has added port 'out_signal_camera_posedge'
|
|
||||||
|
|
||||||
-Upgrade has added port 'out_signal_valve'
|
|
||||||
|
|
||||||
-Upgrade has added port 'out_signal_valve_posedge'
|
|
||||||
|
|
||||||
|
|
||||||
3. Customization warnings
|
|
||||||
-------------------------
|
|
||||||
|
|
||||||
Parameter 'DIVIDER' is no longer present on the upgraded IP 'system_ip_encoder_0_0', and cannot be set to '10'
|
|
||||||
|
|
||||||
|
|
||||||
4. Debug Commands
|
|
||||||
-----------------
|
|
||||||
|
|
||||||
The following debug information can be passed to Vivado as Tcl commands,
|
|
||||||
in order to validate or debug the output of the upgrade flow.
|
|
||||||
You may consult any warnings from within this upgrade, and alter or remove
|
|
||||||
the configuration parameter(s) which caused the warning; then execute the Tcl
|
|
||||||
commands, and use the IP Customization GUI to verify the IP configuration.
|
|
||||||
|
|
||||||
create_ip -vlnv user.org:user:ip_encoder:1.0 -user_name system_ip_encoder_0_0
|
|
||||||
set_property -dict "\
|
|
||||||
CONFIG.Component_Name {system_ip_encoder_0_0} \
|
|
||||||
CONFIG.rst_n.INSERT_VIP {0} \
|
|
||||||
CONFIG.rst_n.POLARITY {ACTIVE_LOW} \
|
|
||||||
CONFIG.sys_clk.ASSOCIATED_BUSIF {} \
|
|
||||||
CONFIG.sys_clk.ASSOCIATED_PORT {} \
|
|
||||||
CONFIG.sys_clk.ASSOCIATED_RESET {} \
|
|
||||||
CONFIG.sys_clk.CLK_DOMAIN {} \
|
|
||||||
CONFIG.sys_clk.FREQ_HZ {100000000} \
|
|
||||||
CONFIG.sys_clk.FREQ_TOLERANCE_HZ {0} \
|
|
||||||
CONFIG.sys_clk.INSERT_VIP {0} \
|
|
||||||
CONFIG.sys_clk.PHASE {0.0} " [get_ips system_ip_encoder_0_0]
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Tue Apr 19 17:23:51 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
CAUTION (success, with warnings) in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 13) to (Rev. 14)
|
|
||||||
|
|
||||||
After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.
|
|
||||||
|
|
||||||
2. Connection Warnings
|
|
||||||
----------------------
|
|
||||||
|
|
||||||
Detected external port differences while upgrading 'system_ip_fifo_0_0'. These changes may impact your design.
|
|
||||||
|
|
||||||
|
|
||||||
-Upgrade has added port 'almost_empty'
|
|
||||||
|
|
||||||
-Upgrade has added port 'almost_full'
|
|
||||||
|
|
||||||
-Upgrade has added port 'data_count'
|
|
||||||
|
|
||||||
-Upgrade has added port 'dout'
|
|
||||||
|
|
||||||
-Upgrade has added port 'empty'
|
|
||||||
|
|
||||||
-Upgrade has added port 'full'
|
|
||||||
|
|
||||||
-Upgrade has added port 'rd_en'
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Mon Apr 18 20:50:40 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 12) to (Rev. 13)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Mon Apr 18 20:31:17 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 11) to (Rev. 12)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Mon Apr 18 20:02:55 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 10) to (Rev. 11)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Mon Apr 18 17:08:30 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 6) to (Rev. 10)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Mon Apr 18 16:46:01 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 5) to (Rev. 6)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Tue Apr 5 20:36:21 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 4) to (Rev. 5)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Tue Apr 5 20:28:59 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 3) to (Rev. 4)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
| Date : Tue Apr 5 18:58:47 2022
|
|
||||||
| Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
| Command : upgrade_ip
|
|
||||||
| Device : xc7z010clg400-1
|
|
||||||
------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
Upgrade Log for IP 'system_ip_fifo_0_0'
|
|
||||||
|
|
||||||
1. Summary
|
|
||||||
----------
|
|
||||||
|
|
||||||
SUCCESS in the upgrade of system_ip_fifo_0_0 (user.org:user:ip_fifo:1.0) from (Rev. 2) to (Rev. 3)
|
|
||||||
|
|
||||||
Binary file not shown.
@ -1,286 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
|
||||||
<spirit:library>module_ref</spirit:library>
|
|
||||||
<spirit:name>valve_interfaces</spirit:name>
|
|
||||||
<spirit:version>1.0</spirit:version>
|
|
||||||
<spirit:busInterfaces>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>rst_n</spirit:name>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>rst_n</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST_N.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>sys_clk</spirit:name>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>CLK</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>sys_clk</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
</spirit:busInterface>
|
|
||||||
</spirit:busInterfaces>
|
|
||||||
<spirit:model>
|
|
||||||
<spirit:views>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
|
||||||
<spirit:displayName>Synthesis</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
|
||||||
<spirit:language>Verilog</spirit:language>
|
|
||||||
<spirit:modelName>valve_interfaces</spirit:modelName>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>viewChecksum</spirit:name>
|
|
||||||
<spirit:value>52d9f4f7</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
|
||||||
<spirit:displayName>Simulation</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
|
||||||
<spirit:language>Verilog</spirit:language>
|
|
||||||
<spirit:modelName>valve_interfaces</spirit:modelName>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>viewChecksum</spirit:name>
|
|
||||||
<spirit:value>52d9f4f7</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_xpgui</spirit:name>
|
|
||||||
<spirit:displayName>UI Layout</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
</spirit:view>
|
|
||||||
</spirit:views>
|
|
||||||
<spirit:ports>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>total_valve_data</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH')) - 1)">383</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>sys_clk</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>rst_n</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>valve_en</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>empty</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>sclk</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.VALVE_PORT_NUM')) - 1)">5</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>sen</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.VALVE_PORT_NUM')) - 1)">5</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>sdata</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.VALVE_PORT_NUM')) - 1)">5</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
</spirit:ports>
|
|
||||||
<spirit:modelParameters>
|
|
||||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
|
||||||
<spirit:name>VALVE_PORT_NUM</spirit:name>
|
|
||||||
<spirit:displayName>Valve Port Num</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VALVE_PORT_NUM">6</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>TOTAL_VALVE_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Total Valve Data Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>VALVE_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Valve Data Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
</spirit:modelParameters>
|
|
||||||
</spirit:model>
|
|
||||||
<spirit:choices>
|
|
||||||
<spirit:choice>
|
|
||||||
<spirit:name>choice_list_74b5137e</spirit:name>
|
|
||||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
||||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
||||||
</spirit:choice>
|
|
||||||
</spirit:choices>
|
|
||||||
<spirit:fileSets>
|
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>xgui/valve_interfaces_v1_0.tcl</spirit:name>
|
|
||||||
<spirit:fileType>tclSource</spirit:fileType>
|
|
||||||
<spirit:userFileType>CHECKSUM_a55fb5f0</spirit:userFileType>
|
|
||||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
</spirit:fileSets>
|
|
||||||
<spirit:description>xilinx.com:module_ref:valve_interfaces:1.0</spirit:description>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>VALVE_PORT_NUM</spirit:name>
|
|
||||||
<spirit:displayName>Valve Port Num</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VALVE_PORT_NUM">6</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>TOTAL_VALVE_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Total Valve Data Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>VALVE_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Valve Data Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>Component_Name</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">valve_interfaces_v1_0</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:coreExtensions>
|
|
||||||
<xilinx:supportedFamilies>
|
|
||||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
|
||||||
</xilinx:supportedFamilies>
|
|
||||||
<xilinx:taxonomies>
|
|
||||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
|
||||||
</xilinx:taxonomies>
|
|
||||||
<xilinx:displayName>valve_interfaces_v1_0</xilinx:displayName>
|
|
||||||
<xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
|
|
||||||
<xilinx:supportsAutoXDC>dynamic_params</xilinx:supportsAutoXDC>
|
|
||||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
|
||||||
<xilinx:designToolContexts>
|
|
||||||
<xilinx:designToolContext>IPI</xilinx:designToolContext>
|
|
||||||
</xilinx:designToolContexts>
|
|
||||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
|
||||||
<xilinx:coreCreationDateTime>2022-04-21T12:40:59Z</xilinx:coreCreationDateTime>
|
|
||||||
</xilinx:coreExtensions>
|
|
||||||
<xilinx:packagingInfo>
|
|
||||||
<xilinx:xilinxVersion>2021.2</xilinx:xilinxVersion>
|
|
||||||
</xilinx:packagingInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:component>
|
|
||||||
@ -1,55 +0,0 @@
|
|||||||
# Definitional proc to organize widgets for parameters.
|
|
||||||
proc init_gui { IPINST } {
|
|
||||||
ipgui::add_param $IPINST -name "Component_Name"
|
|
||||||
#Adding Page
|
|
||||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
|
||||||
ipgui::add_param $IPINST -name "TOTAL_VALVE_DATA_WIDTH" -parent ${Page_0}
|
|
||||||
ipgui::add_param $IPINST -name "VALVE_DATA_WIDTH" -parent ${Page_0}
|
|
||||||
ipgui::add_param $IPINST -name "VALVE_PORT_NUM" -parent ${Page_0}
|
|
||||||
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH { PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH } {
|
|
||||||
# Procedure called to update TOTAL_VALVE_DATA_WIDTH when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH { PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH } {
|
|
||||||
# Procedure called to validate TOTAL_VALVE_DATA_WIDTH
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.VALVE_DATA_WIDTH { PARAM_VALUE.VALVE_DATA_WIDTH } {
|
|
||||||
# Procedure called to update VALVE_DATA_WIDTH when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.VALVE_DATA_WIDTH { PARAM_VALUE.VALVE_DATA_WIDTH } {
|
|
||||||
# Procedure called to validate VALVE_DATA_WIDTH
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.VALVE_PORT_NUM { PARAM_VALUE.VALVE_PORT_NUM } {
|
|
||||||
# Procedure called to update VALVE_PORT_NUM when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.VALVE_PORT_NUM { PARAM_VALUE.VALVE_PORT_NUM } {
|
|
||||||
# Procedure called to validate VALVE_PORT_NUM
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.VALVE_PORT_NUM { MODELPARAM_VALUE.VALVE_PORT_NUM PARAM_VALUE.VALVE_PORT_NUM } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.VALVE_PORT_NUM}] ${MODELPARAM_VALUE.VALVE_PORT_NUM}
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH { MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH}] ${MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH}
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.VALVE_DATA_WIDTH { MODELPARAM_VALUE.VALVE_DATA_WIDTH PARAM_VALUE.VALVE_DATA_WIDTH } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.VALVE_DATA_WIDTH}] ${MODELPARAM_VALUE.VALVE_DATA_WIDTH}
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,120 +0,0 @@
|
|||||||
//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
|
||||||
//--------------------------------------------------------------------------------
|
|
||||||
//Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
|
|
||||||
//Date : Thu Apr 21 22:01:23 2022
|
|
||||||
//Host : miaow-zdyz running 64-bit Ubuntu 20.04.2 LTS
|
|
||||||
//Command : generate_target system_wrapper.bd
|
|
||||||
//Design : system_wrapper
|
|
||||||
//Purpose : IP block netlist
|
|
||||||
//--------------------------------------------------------------------------------
|
|
||||||
`timescale 1 ps / 1 ps
|
|
||||||
|
|
||||||
module system_wrapper
|
|
||||||
(DDR_addr,
|
|
||||||
DDR_ba,
|
|
||||||
DDR_cas_n,
|
|
||||||
DDR_ck_n,
|
|
||||||
DDR_ck_p,
|
|
||||||
DDR_cke,
|
|
||||||
DDR_cs_n,
|
|
||||||
DDR_dm,
|
|
||||||
DDR_dq,
|
|
||||||
DDR_dqs_n,
|
|
||||||
DDR_dqs_p,
|
|
||||||
DDR_odt,
|
|
||||||
DDR_ras_n,
|
|
||||||
DDR_reset_n,
|
|
||||||
DDR_we_n,
|
|
||||||
FIXED_IO_ddr_vrn,
|
|
||||||
FIXED_IO_ddr_vrp,
|
|
||||||
FIXED_IO_mio,
|
|
||||||
FIXED_IO_ps_clk,
|
|
||||||
FIXED_IO_ps_porb,
|
|
||||||
FIXED_IO_ps_srstb,
|
|
||||||
encoder_signal,
|
|
||||||
out_signal_camera_0,
|
|
||||||
sclk_0,
|
|
||||||
sdata_0,
|
|
||||||
sen_0);
|
|
||||||
inout [14:0]DDR_addr;
|
|
||||||
inout [2:0]DDR_ba;
|
|
||||||
inout DDR_cas_n;
|
|
||||||
inout DDR_ck_n;
|
|
||||||
inout DDR_ck_p;
|
|
||||||
inout DDR_cke;
|
|
||||||
inout DDR_cs_n;
|
|
||||||
inout [3:0]DDR_dm;
|
|
||||||
inout [31:0]DDR_dq;
|
|
||||||
inout [3:0]DDR_dqs_n;
|
|
||||||
inout [3:0]DDR_dqs_p;
|
|
||||||
inout DDR_odt;
|
|
||||||
inout DDR_ras_n;
|
|
||||||
inout DDR_reset_n;
|
|
||||||
inout DDR_we_n;
|
|
||||||
inout FIXED_IO_ddr_vrn;
|
|
||||||
inout FIXED_IO_ddr_vrp;
|
|
||||||
inout [53:0]FIXED_IO_mio;
|
|
||||||
inout FIXED_IO_ps_clk;
|
|
||||||
inout FIXED_IO_ps_porb;
|
|
||||||
inout FIXED_IO_ps_srstb;
|
|
||||||
input encoder_signal;
|
|
||||||
output out_signal_camera_0;
|
|
||||||
output [5:0]sclk_0;
|
|
||||||
output [5:0]sdata_0;
|
|
||||||
output [5:0]sen_0;
|
|
||||||
|
|
||||||
wire [14:0]DDR_addr;
|
|
||||||
wire [2:0]DDR_ba;
|
|
||||||
wire DDR_cas_n;
|
|
||||||
wire DDR_ck_n;
|
|
||||||
wire DDR_ck_p;
|
|
||||||
wire DDR_cke;
|
|
||||||
wire DDR_cs_n;
|
|
||||||
wire [3:0]DDR_dm;
|
|
||||||
wire [31:0]DDR_dq;
|
|
||||||
wire [3:0]DDR_dqs_n;
|
|
||||||
wire [3:0]DDR_dqs_p;
|
|
||||||
wire DDR_odt;
|
|
||||||
wire DDR_ras_n;
|
|
||||||
wire DDR_reset_n;
|
|
||||||
wire DDR_we_n;
|
|
||||||
wire FIXED_IO_ddr_vrn;
|
|
||||||
wire FIXED_IO_ddr_vrp;
|
|
||||||
wire [53:0]FIXED_IO_mio;
|
|
||||||
wire FIXED_IO_ps_clk;
|
|
||||||
wire FIXED_IO_ps_porb;
|
|
||||||
wire FIXED_IO_ps_srstb;
|
|
||||||
wire encoder_signal;
|
|
||||||
wire out_signal_camera_0;
|
|
||||||
wire [5:0]sclk_0;
|
|
||||||
wire [5:0]sdata_0;
|
|
||||||
wire [5:0]sen_0;
|
|
||||||
|
|
||||||
system system_i
|
|
||||||
(.DDR_addr(DDR_addr),
|
|
||||||
.DDR_ba(DDR_ba),
|
|
||||||
.DDR_cas_n(DDR_cas_n),
|
|
||||||
.DDR_ck_n(DDR_ck_n),
|
|
||||||
.DDR_ck_p(DDR_ck_p),
|
|
||||||
.DDR_cke(DDR_cke),
|
|
||||||
.DDR_cs_n(DDR_cs_n),
|
|
||||||
.DDR_dm(DDR_dm),
|
|
||||||
.DDR_dq(DDR_dq),
|
|
||||||
.DDR_dqs_n(DDR_dqs_n),
|
|
||||||
.DDR_dqs_p(DDR_dqs_p),
|
|
||||||
.DDR_odt(DDR_odt),
|
|
||||||
.DDR_ras_n(DDR_ras_n),
|
|
||||||
.DDR_reset_n(DDR_reset_n),
|
|
||||||
.DDR_we_n(DDR_we_n),
|
|
||||||
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
|
|
||||||
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
|
|
||||||
.FIXED_IO_mio(FIXED_IO_mio),
|
|
||||||
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
|
|
||||||
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
|
|
||||||
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
|
|
||||||
.encoder_signal(encoder_signal),
|
|
||||||
.out_signal_camera_0(out_signal_camera_0),
|
|
||||||
.sclk_0(sclk_0),
|
|
||||||
.sdata_0(sdata_0),
|
|
||||||
.sen_0(sen_0));
|
|
||||||
endmodule
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,643 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8" ?>
|
|
||||||
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
|
|
||||||
<designInfo version="1.0" >
|
|
||||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
|
||||||
<PARAMETERS >
|
|
||||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
|
||||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666" />
|
|
||||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
|
|
||||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
|
|
||||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
|
|
||||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
|
||||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
|
|
||||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
|
||||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
|
|
||||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
|
|
||||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
|
||||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
|
|
||||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
|
|
||||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
|
|
||||||
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
|
||||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
|
||||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="4" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
|
|
||||||
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
|
|
||||||
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="200" />
|
|
||||||
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50" />
|
|
||||||
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
|
|
||||||
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
|
|
||||||
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
|
||||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="48" />
|
|
||||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1600.000" />
|
|
||||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="in" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="out" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="8" />
|
|
||||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
|
||||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
|
|
||||||
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 3.3V" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
|
||||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
|
|
||||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
|
|
||||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
|
|
||||||
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
|
|
||||||
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
|
|
||||||
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
|
|
||||||
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
|
|
||||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
|
|
||||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
|
|
||||||
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
|
|
||||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 14 .. 15" />
|
|
||||||
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
|
|
||||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
|
||||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="16" />
|
|
||||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="54.563" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="54.563" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="54.563" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="54.563" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="2048 MBits" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="101.239" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="79.5025" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="60.536" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="71.7715" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="104.5365" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="70.676" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="59.1615" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="81.319" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41J128M16 HA-125" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="14" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
|
|
||||||
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
|
|
||||||
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
|
|
||||||
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
|
|
||||||
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" />
|
|
||||||
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
|
||||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
|
|
||||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
|
|
||||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
|
||||||
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
|
|
||||||
</PARAMETERS>
|
|
||||||
<BUSINTERFACES >
|
|
||||||
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
|
|
||||||
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
|
|
||||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
|
|
||||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
|
|
||||||
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
|
|
||||||
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
|
||||||
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
|
|
||||||
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
|
||||||
</BUSINTERFACES>
|
|
||||||
<CLOCKOUTS >
|
|
||||||
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="200.000000" />
|
|
||||||
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="10.000000" />
|
|
||||||
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
|
|
||||||
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
|
|
||||||
</CLOCKOUTS>
|
|
||||||
</MODULE>
|
|
||||||
</designInfo>
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,700 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
|
||||||
<spirit:library>customized_ip</spirit:library>
|
|
||||||
<spirit:name>system_rst_ps7_0_200M_0</spirit:name>
|
|
||||||
<spirit:version>1.0</spirit:version>
|
|
||||||
<spirit:busInterfaces>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>clock</spirit:name>
|
|
||||||
<spirit:displayName>Clock</spirit:displayName>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>CLK</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>slowest_sync_clk</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>FREQ_HZ</spirit:name>
|
|
||||||
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
|
|
||||||
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">2e+08</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>PHASE</spirit:name>
|
|
||||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>ext_reset</spirit:name>
|
|
||||||
<spirit:displayName>Ext_Reset</spirit:displayName>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>ext_reset_in</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:enablement>
|
|
||||||
<xilinx:presence>required</xilinx:presence>
|
|
||||||
</xilinx:enablement>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>aux_reset</spirit:name>
|
|
||||||
<spirit:displayName>aux_reset</spirit:displayName>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>aux_reset_in</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>dbg_reset</spirit:name>
|
|
||||||
<spirit:displayName>DBG_Reset</spirit:displayName>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>mb_rst</spirit:name>
|
|
||||||
<spirit:displayName>MB_rst</spirit:displayName>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:master/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>mb_reset</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>TYPE</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>bus_struct_reset</spirit:name>
|
|
||||||
<spirit:displayName>bus_struct_reset</spirit:displayName>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:master/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>bus_struct_reset</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>TYPE</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE">INTERCONNECT</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>interconnect_low_rst</spirit:name>
|
|
||||||
<spirit:displayName>interconnect_low_rst</spirit:displayName>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:master/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>interconnect_aresetn</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>TYPE</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>peripheral_high_rst</spirit:name>
|
|
||||||
<spirit:displayName>peripheral_high_rst</spirit:displayName>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:master/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>peripheral_reset</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>TYPE</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>peripheral_low_rst</spirit:name>
|
|
||||||
<spirit:displayName>peripheral_low_rst</spirit:displayName>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:master/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>peripheral_aresetn</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>TYPE</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE">PERIPHERAL</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
</spirit:busInterfaces>
|
|
||||||
<spirit:model>
|
|
||||||
<spirit:ports>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>slowest_sync_clk</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>ext_reset_in</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>aux_reset_in</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
<spirit:driver>
|
|
||||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
||||||
</spirit:driver>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
<spirit:driver>
|
|
||||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
||||||
</spirit:driver>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>dcm_locked</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
<spirit:driver>
|
|
||||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
|
|
||||||
</spirit:driver>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>mb_reset</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
<spirit:driver>
|
|
||||||
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x0</spirit:defaultValue>
|
|
||||||
</spirit:driver>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>bus_struct_reset</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long">0</spirit:left>
|
|
||||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_BUS_RST')) - 1)">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
<spirit:driver>
|
|
||||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
||||||
</spirit:driver>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>peripheral_reset</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long">0</spirit:left>
|
|
||||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_RST')) - 1)">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
<spirit:driver>
|
|
||||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
||||||
</spirit:driver>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>interconnect_aresetn</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long">0</spirit:left>
|
|
||||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN')) - 1)">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
<spirit:driver>
|
|
||||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
||||||
</spirit:driver>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>peripheral_aresetn</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long">0</spirit:left>
|
|
||||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_ARESETN')) - 1)">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
<spirit:driver>
|
|
||||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
|
||||||
</spirit:driver>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
</spirit:ports>
|
|
||||||
<spirit:modelParameters>
|
|
||||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
|
|
||||||
<spirit:name>C_FAMILY</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="std_logic">
|
|
||||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
|
||||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="std_logic">
|
|
||||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
|
||||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
|
||||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
|
||||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
|
||||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
|
||||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
</spirit:modelParameters>
|
|
||||||
</spirit:model>
|
|
||||||
<spirit:choices>
|
|
||||||
<spirit:choice>
|
|
||||||
<spirit:name>choice_list_ac75ef1e</spirit:name>
|
|
||||||
<spirit:enumeration>Custom</spirit:enumeration>
|
|
||||||
</spirit:choice>
|
|
||||||
</spirit:choices>
|
|
||||||
<spirit:description>Processor Reset System</spirit:description>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
|
||||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
|
||||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
|
||||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
|
||||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
|
||||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
|
||||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>Component_Name</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_rst_ps7_0_200M_0</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
|
||||||
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:coreExtensions>
|
|
||||||
<xilinx:displayName>Processor System Reset</xilinx:displayName>
|
|
||||||
<xilinx:coreRevision>13</xilinx:coreRevision>
|
|
||||||
<xilinx:configElementInfos>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
</xilinx:configElementInfos>
|
|
||||||
</xilinx:coreExtensions>
|
|
||||||
<xilinx:packagingInfo>
|
|
||||||
<xilinx:xilinxVersion>2021.2</xilinx:xilinxVersion>
|
|
||||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
|
||||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
|
|
||||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
|
||||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
|
|
||||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
|
|
||||||
</xilinx:packagingInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:component>
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,312 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
|
||||||
<spirit:library>customized_ip</spirit:library>
|
|
||||||
<spirit:name>system_valve_interfaces_0_0</spirit:name>
|
|
||||||
<spirit:version>1.0</spirit:version>
|
|
||||||
<spirit:busInterfaces>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>rst_n</spirit:name>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>rst_n</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RST_N.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST_N.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>sys_clk</spirit:name>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>CLK</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>sys_clk</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>FREQ_HZ</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.FREQ_HZ">2e+08</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>PHASE</spirit:name>
|
|
||||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.PHASE">0.0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_BUSIF"/>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>ASSOCIATED_PORT</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_PORT"/>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_RESET"/>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>INSERT_VIP</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SYS_CLK.INSERT_VIP">0</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
</spirit:busInterfaces>
|
|
||||||
<spirit:model>
|
|
||||||
<spirit:ports>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>total_valve_data</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH')) - 1)">383</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>sys_clk</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>rst_n</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>valve_en</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>empty</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>sclk</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.VALVE_PORT_NUM')) - 1)">5</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>sen</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.VALVE_PORT_NUM')) - 1)">5</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>sdata</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.VALVE_PORT_NUM')) - 1)">5</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
</spirit:ports>
|
|
||||||
<spirit:modelParameters>
|
|
||||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
|
||||||
<spirit:name>VALVE_PORT_NUM</spirit:name>
|
|
||||||
<spirit:displayName>Valve Port Num</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VALVE_PORT_NUM">6</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>TOTAL_VALVE_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Total Valve Data Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>VALVE_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Valve Data Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
</spirit:modelParameters>
|
|
||||||
</spirit:model>
|
|
||||||
<spirit:choices>
|
|
||||||
<spirit:choice>
|
|
||||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
|
||||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
||||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
||||||
</spirit:choice>
|
|
||||||
</spirit:choices>
|
|
||||||
<spirit:description>xilinx.com:module_ref:valve_interfaces:1.0</spirit:description>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>VALVE_PORT_NUM</spirit:name>
|
|
||||||
<spirit:displayName>Valve Port Num</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VALVE_PORT_NUM">6</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>TOTAL_VALVE_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Total Valve Data Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TOTAL_VALVE_DATA_WIDTH">384</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>VALVE_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>Valve Data Width</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.VALVE_DATA_WIDTH">48</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>Component_Name</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_valve_interfaces_0_0</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:coreExtensions>
|
|
||||||
<xilinx:displayName>valve_interfaces_v1_0</xilinx:displayName>
|
|
||||||
<xilinx:definitionSource>module_ref</xilinx:definitionSource>
|
|
||||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
|
||||||
<xilinx:configElementInfos>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST_N.POLARITY" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
</xilinx:configElementInfos>
|
|
||||||
</xilinx:coreExtensions>
|
|
||||||
<xilinx:packagingInfo>
|
|
||||||
<xilinx:xilinxVersion>2021.2</xilinx:xilinxVersion>
|
|
||||||
</xilinx:packagingInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:component>
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,11 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<Root MajorVersion="0" MinorVersion="39">
|
|
||||||
<CompositeFile CompositeFileTopName="system" CanBeSetAsTop="false" CanDisplayChildGraph="true">
|
|
||||||
<Description>Composite Fileset</Description>
|
|
||||||
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1652624652"/>
|
|
||||||
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1652624652"/>
|
|
||||||
<Generation Name="SIMULATION" State="RESET" Timestamp="1652624652"/>
|
|
||||||
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1652624652"/>
|
|
||||||
<FileCollection Name="SOURCES" Type="SOURCES"/>
|
|
||||||
</CompositeFile>
|
|
||||||
</Root>
|
|
||||||
@ -1,59 +0,0 @@
|
|||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[5]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[4]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[3]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[2]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[1]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sclk_0[0]}]
|
|
||||||
set_property PACKAGE_PIN E17 [get_ports {sclk_0[0]}]
|
|
||||||
set_property PACKAGE_PIN J18 [get_ports {sclk_0[1]}]
|
|
||||||
set_property PACKAGE_PIN B20 [get_ports {sclk_0[2]}]
|
|
||||||
set_property PACKAGE_PIN B19 [get_ports {sclk_0[3]}]
|
|
||||||
set_property PACKAGE_PIN H15 [get_ports {sclk_0[4]}]
|
|
||||||
set_property PACKAGE_PIN L17 [get_ports {sclk_0[5]}]
|
|
||||||
set_property SLEW FAST [get_ports {sclk_0[5]}]
|
|
||||||
set_property SLEW FAST [get_ports {sclk_0[4]}]
|
|
||||||
set_property SLEW FAST [get_ports {sclk_0[3]}]
|
|
||||||
set_property SLEW FAST [get_ports {sclk_0[2]}]
|
|
||||||
set_property SLEW FAST [get_ports {sclk_0[1]}]
|
|
||||||
set_property SLEW FAST [get_ports {sclk_0[0]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[5]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[4]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[3]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[2]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[1]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sdata_0[0]}]
|
|
||||||
set_property SLEW FAST [get_ports {sdata_0[5]}]
|
|
||||||
set_property SLEW FAST [get_ports {sdata_0[4]}]
|
|
||||||
set_property SLEW FAST [get_ports {sdata_0[3]}]
|
|
||||||
set_property SLEW FAST [get_ports {sdata_0[2]}]
|
|
||||||
set_property SLEW FAST [get_ports {sdata_0[1]}]
|
|
||||||
set_property SLEW FAST [get_ports {sdata_0[0]}]
|
|
||||||
set_property PACKAGE_PIN H18 [get_ports {sdata_0[0]}]
|
|
||||||
set_property PACKAGE_PIN E18 [get_ports {sdata_0[1]}]
|
|
||||||
set_property PACKAGE_PIN C20 [get_ports {sdata_0[2]}]
|
|
||||||
set_property PACKAGE_PIN K14 [get_ports {sdata_0[3]}]
|
|
||||||
set_property PACKAGE_PIN G15 [get_ports {sdata_0[4]}]
|
|
||||||
set_property PACKAGE_PIN D20 [get_ports {sdata_0[5]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[5]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[4]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[3]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[2]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[1]}]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports {sen_0[0]}]
|
|
||||||
set_property SLEW FAST [get_ports {sen_0[5]}]
|
|
||||||
set_property SLEW FAST [get_ports {sen_0[4]}]
|
|
||||||
set_property SLEW FAST [get_ports {sen_0[3]}]
|
|
||||||
set_property SLEW FAST [get_ports {sen_0[2]}]
|
|
||||||
set_property SLEW FAST [get_ports {sen_0[1]}]
|
|
||||||
set_property SLEW FAST [get_ports {sen_0[0]}]
|
|
||||||
set_property PACKAGE_PIN D18 [get_ports {sen_0[0]}]
|
|
||||||
set_property PACKAGE_PIN E19 [get_ports {sen_0[1]}]
|
|
||||||
set_property PACKAGE_PIN J14 [get_ports {sen_0[2]}]
|
|
||||||
set_property PACKAGE_PIN A20 [get_ports {sen_0[3]}]
|
|
||||||
set_property PACKAGE_PIN D19 [get_ports {sen_0[4]}]
|
|
||||||
set_property PACKAGE_PIN L16 [get_ports {sen_0[5]}]
|
|
||||||
set_property PACKAGE_PIN W19 [get_ports encoder_signal]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports encoder_signal]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports out_signal_camera_0]
|
|
||||||
set_property PACKAGE_PIN T10 [get_ports out_signal_camera_0]
|
|
||||||
set_property SLEW FAST [get_ports out_signal_camera_0]
|
|
||||||
@ -1,260 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
|
||||||
<spirit:library>xci</spirit:library>
|
|
||||||
<spirit:name>unknown</spirit:name>
|
|
||||||
<spirit:version>1.0</spirit:version>
|
|
||||||
<spirit:componentInstances>
|
|
||||||
<spirit:componentInstance>
|
|
||||||
<spirit:instanceName>system_auto_pc_0</spirit:instanceName>
|
|
||||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_protocol_converter" spirit:version="2.1"/>
|
|
||||||
<spirit:configurableElementValues>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">ARESETN</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">2e+08</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">2e+08</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.TYPE">INTERCONNECT</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">2e+08</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">12</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">16</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI3</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">12</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_READ">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_USER_SIGNALS">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_WRITE">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IGNORE_ID">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_PROTOCOL">2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_PROTOCOL">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRANSLATION_MODE">2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_auto_pc_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">12</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SI_PROTOCOL">AXI3</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRANSLATION_MODE">2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">25</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../test_lower_machine.gen/sources_1/bd/system/ip/system_auto_pc_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL">rtl</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
|
||||||
</spirit:configurableElementValues>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:componentInstanceExtensions>
|
|
||||||
<xilinx:configElementInfos>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
</xilinx:configElementInfos>
|
|
||||||
<xilinx:boundaryDescriptionInfo>
|
|
||||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"aclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"aresetn":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_araddr":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"m_axi_arprot":[{"direction":"out","physical_left":"2","physical_right":"0","is_vector":"true"}],"m_axi_arready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_arvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_awaddr":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"m_axi_awprot":[{"direction":"out","physical_left":"2","physical_right":"0","is_vector":"true"}],"m_axi_awready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_awvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_br
|
|
||||||
eady":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_bresp":[{"direction":"in","physical_left":"1","physical_right":"0","is_vector":"true"}],"m_axi_bvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_rdata":[{"direction":"in","physical_left":"31","physical_right":"0","is_vector":"true"}],"m_axi_rready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_rresp":[{"direction":"in","physical_left":"1","physical_right":"0","is_vector":"true"}],"m_axi_rvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_wdata":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"m_axi_wready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_wstrb":[{"direction":"out","physical_left":"3","physical_right":"0","is_vector":"true"}],"m_axi_wvalid":[{"direction":"out","physic
|
|
||||||
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:"16","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_OUTSTANDING":[{"value":"8","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_THREADS":[{"value":"4","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_WRITE_OUTSTANDING":[{"value":"8","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_WRITE_THREADS":[{"value":"4","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"PHASE"
|
|
||||||
:[{"value":"0.0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"float","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"PROTOCOL":[{"value":"AXI3","value_src":"user_prop","value_permission":"bd","resolve_type":"generated","format":"string","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"READ_WRITE_MODE":[{"value":"READ_WRITE","value_src":"auto_prop","value_permission":"bd","resolve_type":"generated","format":"string","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"RUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"RUSER_WIDTH":[{"value":"0","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"SUPPORTS_NARR
|
|
||||||
OW_BURST":[{"value":"0","value_src":"user_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"WUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"WUSER_WIDTH":[{"value":"0","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"ARADDR":[{"physical_name":"s_axi_araddr","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"ARBURST":[{"physical_name":"s_axi_arburst","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"ARCACHE":[{"physical_name":"s_axi_arcache","physical_left":"3","physical_right":"0","logical_lef
|
|
||||||
t":"3","logical_right":"0","port_maps_used":"none"}],"ARID":[{"physical_name":"s_axi_arid","physical_left":"11","physical_right":"0","logical_left":"11","logical_right":"0","port_maps_used":"none"}],"ARLEN":[{"physical_name":"s_axi_arlen","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"ARLOCK":[{"physical_name":"s_axi_arlock","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"ARPROT":[{"physical_name":"s_axi_arprot","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"ARQOS":[{"physical_name":"s_axi_arqos","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"ARREADY":[{"physical_name":"s_axi_arready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARREGION":[{"physical_name":"s_axi_arregion","physical_left":
|
|
||||||
"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"ARSIZE":[{"physical_name":"s_axi_arsize","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"ARUSER":[{"physical_name":"s_axi_aruser","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARVALID":[{"physical_name":"s_axi_arvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWADDR":[{"physical_name":"s_axi_awaddr","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"AWBURST":[{"physical_name":"s_axi_awburst","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"AWCACHE":[{"physical_name":"s_axi_awcache","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"AWID":[{"phy
|
|
||||||
sical_name":"s_axi_awid","physical_left":"11","physical_right":"0","logical_left":"11","logical_right":"0","port_maps_used":"none"}],"AWLEN":[{"physical_name":"s_axi_awlen","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"AWLOCK":[{"physical_name":"s_axi_awlock","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"AWPROT":[{"physical_name":"s_axi_awprot","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"AWQOS":[{"physical_name":"s_axi_awqos","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"AWREADY":[{"physical_name":"s_axi_awready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWREGION":[{"physical_name":"s_axi_awregion","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","p
|
|
||||||
ort_maps_used":"none"}],"AWSIZE":[{"physical_name":"s_axi_awsize","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"AWUSER":[{"physical_name":"s_axi_awuser","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWVALID":[{"physical_name":"s_axi_awvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BID":[{"physical_name":"s_axi_bid","physical_left":"11","physical_right":"0","logical_left":"11","logical_right":"0","port_maps_used":"none"}],"BREADY":[{"physical_name":"s_axi_bready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BRESP":[{"physical_name":"s_axi_bresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"BUSER":[{"physical_name":"s_axi_buser","physical_left":"0","physical_right":"0","logical_l
|
|
||||||
eft":"0","logical_right":"0","port_maps_used":"none"}],"BVALID":[{"physical_name":"s_axi_bvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RDATA":[{"physical_name":"s_axi_rdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"RID":[{"physical_name":"s_axi_rid","physical_left":"11","physical_right":"0","logical_left":"11","logical_right":"0","port_maps_used":"none"}],"RLAST":[{"physical_name":"s_axi_rlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RREADY":[{"physical_name":"s_axi_rready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RRESP":[{"physical_name":"s_axi_rresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"RUSER":[{"physical_name":"s_axi_ruser","physical_left":"0","phy
|
|
||||||
sical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RVALID":[{"physical_name":"s_axi_rvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WDATA":[{"physical_name":"s_axi_wdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"WID":[{"physical_name":"s_axi_wid","physical_left":"11","physical_right":"0","logical_left":"11","logical_right":"0","port_maps_used":"none"}],"WLAST":[{"physical_name":"s_axi_wlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WREADY":[{"physical_name":"s_axi_wready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WSTRB":[{"physical_name":"s_axi_wstrb","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"WUSER":[{"physical_name":"s_axi_wuse
|
|
||||||
r","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WVALID":[{"physical_name":"s_axi_wvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
|
||||||
</xilinx:boundaryDescriptionInfo>
|
|
||||||
</xilinx:componentInstanceExtensions>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:componentInstance>
|
|
||||||
</spirit:componentInstances>
|
|
||||||
</spirit:design>
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,138 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
|
||||||
<spirit:library>xci</spirit:library>
|
|
||||||
<spirit:name>unknown</spirit:name>
|
|
||||||
<spirit:version>1.0</spirit:version>
|
|
||||||
<spirit:componentInstances>
|
|
||||||
<spirit:componentInstance>
|
|
||||||
<spirit:instanceName>system_ip_encoder_0_1</spirit:instanceName>
|
|
||||||
<spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="ip_encoder" spirit:version="1.0"/>
|
|
||||||
<spirit:configurableElementValues>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_BASE_ADDRESS.S00_AXI.S00_AXI_reg">0</spirit:configurableElementValue>
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|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ">2e+08</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP">1</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE">0</spirit:configurableElementValue>
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|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK">0</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT">1</spirit:configurableElementValue>
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||||||
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|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION">0</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ID_WIDTH">0</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
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|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_PORT"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_HZ">2e+08</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_BASEADDR">0xFFFFFFFF</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_HIGHADDR">0x00000000</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_ip_encoder_0_1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../test_lower_machine.gen/sources_1/bd/system/ip/system_ip_encoder_0_1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
|
||||||
</spirit:configurableElementValues>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:componentInstanceExtensions>
|
|
||||||
<xilinx:configElementInfos>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
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|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
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</xilinx:configElementInfos>
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<xilinx:boundaryDescriptionInfo>
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|
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|
|
||||||
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|
|
||||||
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|
||||||
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|
||||||
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|
|
||||||
</xilinx:boundaryDescriptionInfo>
|
|
||||||
</xilinx:componentInstanceExtensions>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:componentInstance>
|
|
||||||
</spirit:componentInstances>
|
|
||||||
</spirit:design>
|
|
||||||
@ -1,138 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
|
||||||
<spirit:library>xci</spirit:library>
|
|
||||||
<spirit:name>unknown</spirit:name>
|
|
||||||
<spirit:version>1.0</spirit:version>
|
|
||||||
<spirit:componentInstances>
|
|
||||||
<spirit:componentInstance>
|
|
||||||
<spirit:instanceName>system_ip_fifo_0_0</spirit:instanceName>
|
|
||||||
<spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="ip_fifo" spirit:version="1.0"/>
|
|
||||||
<spirit:configurableElementValues>
|
|
||||||
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||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
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||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ">2e+08</spirit:configurableElementValue>
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|
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||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_PORT"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_HZ">2e+08</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH">6</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH">6</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_BASEADDR">0xFFFFFFFF</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_HIGHADDR">0x00000000</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_ip_fifo_0_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">24</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../test_lower_machine.gen/sources_1/bd/system/ip/system_ip_fifo_0_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
|
||||||
</spirit:configurableElementValues>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:componentInstanceExtensions>
|
|
||||||
<xilinx:configElementInfos>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_CLK.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
</xilinx:configElementInfos>
|
|
||||||
<xilinx:boundaryDescriptionInfo>
|
|
||||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"almost_empty":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"almost_full":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"data_count":[{"direction":"out","physical_left":"11","physical_right":"0","is_vector":"true"}],"dout":[{"direction":"out","physical_left":"383","physical_right":"0","is_vector":"true"}],"empty":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"fifo_valid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"full":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_en":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_aclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_araddr":[{"direction":"in","physical_left":"5","physical_right":"0","is_vector":"true"}],"s00_axi_aresetn":[{"direction
|
|
||||||
":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_arprot":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"s00_axi_arready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_arvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_awaddr":[{"direction":"in","physical_left":"5","physical_right":"0","is_vector":"true"}],"s00_axi_awprot":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"s00_axi_awready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_awvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_bready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_bresp":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"s00_axi_bvalid":[{"direction":"out"
|
|
||||||
,"physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_rdata":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"s00_axi_rready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_rresp":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"s00_axi_rvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_wdata":[{"direction":"in","physical_left":"31","physical_right":"0","is_vector":"true"}],"s00_axi_wready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s00_axi_wstrb":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"s00_axi_wvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"S00_AXI":{"vlnv":"xilinx.com:interface:aximm:1.0","abstraction_type":"xilinx.com:interface:aximm_rtl:1.0","mode":"slave","memory_
|
|
||||||
map_ref":"S00_AXI","parameters":{"ADDR_WIDTH":[{"value":"6","value_src":"auto","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ARUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"AWUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"BUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"system_processing_system7_0_0_FCLK_CLK0","value_src":"default_prop","value_permission":"bd","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"DATA_WIDTH
|
|
||||||
":[{"value":"32","value_src":"auto","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"2e+08","value_src":"user_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_BRESP":[{"value":"1","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_BURST":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_CACHE":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_LOCK":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","form
|
|
||||||
at":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_PROT":[{"value":"1","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_QOS":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_REGION":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_RRESP":[{"value":"1","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_WSTRB":[{"value":"1","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ID_WIDTH":[{"value"
|
|
||||||
:"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"MAX_BURST_LENGTH":[{"value":"1","value_src":"ip_propagated","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_OUTSTANDING":[{"value":"2","value_src":"default_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_THREADS":[{"value":"1","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_WRITE_OUTSTANDING":[{"value":"2","value_src":"default_prop","value_per
|
|
||||||
mission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_WRITE_THREADS":[{"value":"1","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PROTOCOL":[{"value":"AXI4LITE","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"READ_WRITE_MODE":[{"value":"READ_WRITE","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"RUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long
|
|
||||||
","usage":"none","is_ips_inferred":true,"is_static_object":false}],"RUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SUPPORTS_NARROW_BURST":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"WIZ_DATA_WIDTH":[{"value":"32","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"WIZ_NUM_REG":[{"value":"15","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"WUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}
|
|
||||||
],"WUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"ARADDR":[{"physical_name":"s00_axi_araddr","physical_left":"5","physical_right":"0","logical_left":"5","logical_right":"0","port_maps_used":"none"}],"ARPROT":[{"physical_name":"s00_axi_arprot","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"ARREADY":[{"physical_name":"s00_axi_arready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARVALID":[{"physical_name":"s00_axi_arvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWADDR":[{"physical_name":"s00_axi_awaddr","physical_left":"5","physical_right":"0","logical_left":"5","logical_right":"0","port_maps_used":"none"}],"AWPROT":[{"physical_name":"s00_axi_awprot","p
|
|
||||||
hysical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"AWREADY":[{"physical_name":"s00_axi_awready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWVALID":[{"physical_name":"s00_axi_awvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BREADY":[{"physical_name":"s00_axi_bready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BRESP":[{"physical_name":"s00_axi_bresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"BVALID":[{"physical_name":"s00_axi_bvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RDATA":[{"physical_name":"s00_axi_rdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"n
|
|
||||||
one"}],"RREADY":[{"physical_name":"s00_axi_rready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RRESP":[{"physical_name":"s00_axi_rresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"RVALID":[{"physical_name":"s00_axi_rvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WDATA":[{"physical_name":"s00_axi_wdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"WREADY":[{"physical_name":"s00_axi_wready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WSTRB":[{"physical_name":"s00_axi_wstrb","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"WVALID":[{"physical_name":"s00_axi_wvalid","physical_left":"0","physical_right":"0","logical_le
|
|
||||||
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File diff suppressed because it is too large
Load Diff
@ -1,362 +0,0 @@
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|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator_AppCore</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">26</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../test_lower_machine.gen/sources_1/bd/system/ip/system_ps7_0_axi_periph_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
|
||||||
</spirit:configurableElementValues>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:componentInstanceExtensions>
|
|
||||||
<xilinx:configElementInfos>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_MI" xilinx:valueSource="user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.S00_HAS_DATA_FIFO" xilinx:valueSource="user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.STRATEGY" xilinx:valueSource="user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.XBAR_DATA_WIDTH" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
</xilinx:configElementInfos>
|
|
||||||
</xilinx:componentInstanceExtensions>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:componentInstance>
|
|
||||||
</spirit:componentInstances>
|
|
||||||
</spirit:design>
|
|
||||||
@ -1,101 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
|
||||||
<spirit:library>xci</spirit:library>
|
|
||||||
<spirit:name>unknown</spirit:name>
|
|
||||||
<spirit:version>1.0</spirit:version>
|
|
||||||
<spirit:componentInstances>
|
|
||||||
<spirit:componentInstance>
|
|
||||||
<spirit:instanceName>system_rst_ps7_0_200M_0</spirit:instanceName>
|
|
||||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
|
|
||||||
<spirit:configurableElementValues>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">2e+08</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_rst_ps7_0_200M_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../test_lower_machine.gen/sources_1/bd/system/ip/system_rst_ps7_0_200M_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
|
||||||
</spirit:configurableElementValues>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:componentInstanceExtensions>
|
|
||||||
<xilinx:configElementInfos>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
</xilinx:configElementInfos>
|
|
||||||
<xilinx:boundaryDescriptionInfo>
|
|
||||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"aux_reset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"bus_struct_reset":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"dcm_locked":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"ext_reset_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"interconnect_aresetn":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"mb_debug_sys_rst":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"mb_reset":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"peripheral_aresetn":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"peripheral_reset":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"slowest_sync_clk":[{"direction":"in","physical_left":"0","physical_right":"0","
|
|
||||||
is_vector":"false"}]},"interfaces":{"aux_reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":false,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"propagated","value_permission":"bd","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":false,"is_static_object":false}]},"port_maps":{"RST":[{"physical_name":"aux_reset_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"bus_struct_reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_i
|
|
||||||
nferred":false,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"TYPE":[{"value":"INTERCONNECT","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"bus_struct_reset","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"clock":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":false,"is_static_object":false}],"ASSOCIATED_PORT":[{"value":"","value_src":"default","value_permission":"bd","resolve_type":"gen
|
|
||||||
erated","format":"string","usage":"none","is_ips_inferred":false,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"system_processing_system7_0_0_FCLK_CLK0","value_src":"default_prop","value_permission":"bd","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":false,"is_static_object":false}],"FREQ_HZ":[{"value":"2e+08","value_src":"user_prop","value_permission":"bd","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":false,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"def
|
|
||||||
ault","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":false,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":false,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"slowest_sync_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"dbg_reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":false,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":tru
|
|
||||||
e}]},"port_maps":{"RST":[{"physical_name":"mb_debug_sys_rst","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"ext_reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"BOARD.ASSOCIATED_PARAM":[{"value":"RESET_BOARD_INTERFACE","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":false,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":false,"is_static_object":false}]},"port_maps":{"RST":[{"physical_name":"ext_reset_in","physical_left":"0","physical_right":"0","logical_
|
|
||||||
left":"0","logical_right":"0","port_maps_used":"none"}]}},"interconnect_low_rst":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":false,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"TYPE":[{"value":"INTERCONNECT","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"interconnect_aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"mb_rst":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_t
|
|
||||||
ype":"xilinx.com:signal:reset_rtl:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":false,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"TYPE":[{"value":"PROCESSOR","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"mb_reset","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"peripheral_high_rst":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permissio
|
|
||||||
n":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":false,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"TYPE":[{"value":"PERIPHERAL","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"peripheral_reset","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"peripheral_low_rst":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":false,"is_static_object":false}],"P
|
|
||||||
OLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"TYPE":[{"value":"PERIPHERAL","value_src":"constant","value_permission":"bd","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"peripheral_aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
|
||||||
</xilinx:boundaryDescriptionInfo>
|
|
||||||
</xilinx:componentInstanceExtensions>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:componentInstance>
|
|
||||||
</spirit:componentInstances>
|
|
||||||
</spirit:design>
|
|
||||||
@ -1,264 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
|
||||||
<spirit:library>xci</spirit:library>
|
|
||||||
<spirit:name>unknown</spirit:name>
|
|
||||||
<spirit:version>1.0</spirit:version>
|
|
||||||
<spirit:componentInstances>
|
|
||||||
<spirit:componentInstance>
|
|
||||||
<spirit:instanceName>system_s00_data_fifo_0</spirit:instanceName>
|
|
||||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_data_fifo" spirit:version="2.1"/>
|
|
||||||
<spirit:configurableElementValues>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">ARESETN</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">2e+08</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">2e+08</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.TYPE">INTERCONNECT</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">2e+08</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_PROTOCOL">2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_READ_FIFO_DELAY">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_READ_FIFO_DEPTH">512</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_READ_FIFO_TYPE">bram</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_USER_SIGNALS">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WRITE_FIFO_DELAY">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WRITE_FIFO_DEPTH">512</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WRITE_FIFO_TYPE">bram</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_s00_data_fifo_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_FIFO_DELAY">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_FIFO_DEPTH">512</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_FIFO_DELAY">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_FIFO_DEPTH">512</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">24</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../test_lower_machine.gen/sources_1/bd/system/ip/system_s00_data_fifo_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL">rtl</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
|
||||||
</spirit:configurableElementValues>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:componentInstanceExtensions>
|
|
||||||
<xilinx:configElementInfos>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROTOCOL" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_FIFO_DELAY" xilinx:valueSource="propagated"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_FIFO_DEPTH" xilinx:valueSource="propagated"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WRITE_FIFO_DELAY" xilinx:valueSource="propagated"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WRITE_FIFO_DEPTH" xilinx:valueSource="propagated"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
</xilinx:configElementInfos>
|
|
||||||
<xilinx:boundaryDescriptionInfo>
|
|
||||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"aclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"aresetn":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_araddr":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"m_axi_arprot":[{"direction":"out","physical_left":"2","physical_right":"0","is_vector":"true"}],"m_axi_arready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_arvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_awaddr":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"m_axi_awprot":[{"direction":"out","physical_left":"2","physical_right":"0","is_vector":"true"}],"m_axi_awready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_awvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axi_br
|
|
||||||
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|
|
||||||
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|
|
||||||
ght":"0","is_vector":"true"}],"s_axi_bvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_rdata":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"s_axi_rready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_rresp":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"s_axi_rvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_wdata":[{"direction":"in","physical_left":"31","physical_right":"0","is_vector":"true"}],"s_axi_wready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_wstrb":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"s_axi_wvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"CLK":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:
|
|
||||||
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|
|
||||||
lse,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"M_AXI":{"vlnv":"xilinx.com:interface:aximm:1.0","abstraction_type":"xilinx.com:interface:aximm_rtl:1.0","mode":"master","parameters":{"ADDR_WIDTH":[{"value":"32","value_src":"user_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage"
|
|
||||||
:"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"ARUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"AWUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"BUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"system_processing_system7_0_0_FCLK_CLK0","value_src":"default_prop","value_permission":"bd","resolve_type":"generated","format":"string","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"DATA_WIDTH":[{"value":"32","value_src":"user_prop","value_permission":"bd","resolve_type":"generated","format":"l
|
|
||||||
ong","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"2e+08","value_src":"user_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_BRESP":[{"value":"1","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_BURST":[{"value":"0","value_src":"propagated","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_CACHE":[{"value":"0","value_src":"propagated","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_LOCK":[{"value":"0","value_src":"propagated","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","
|
|
||||||
is_ips_inferred":true,"is_static_object":false}],"HAS_PROT":[{"value":"1","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_QOS":[{"value":"0","value_src":"propagated","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_REGION":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_RRESP":[{"value":"1","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_WSTRB":[{"value":"1","value_src":"constant_prop","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_sta
|
|
||||||
tic_object":false}],"ID_WIDTH":[{"value":"0","value_src":"propagated","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"MAX_BURST_LENGTH":[{"value":"1","value_src":"propagated","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_OUTSTANDING":[{"value":"8","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_THREADS":[{"value":"4","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}]
|
|
||||||
,"NUM_WRITE_OUTSTANDING":[{"value":"8","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_WRITE_THREADS":[{"value":"4","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"float","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"PROTOCOL":[{"value":"AXI4LITE","value_src":"user_prop","value_permission":"bd","resolve_type":"generated","format":"string","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"READ_WRITE_MODE":[{"value":"READ_WRITE","value_src":"user_prop","value_permission":"bd","resolve_type":"generated","format":"string","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}
|
|
||||||
],"RUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"RUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"SUPPORTS_NARROW_BURST":[{"value":"0","value_src":"propagated","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"WUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"WUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"bd","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}]},"port
|
|
||||||
_maps":{"ARADDR":[{"physical_name":"m_axi_araddr","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"ARBURST":[{"physical_name":"m_axi_arburst","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"ARCACHE":[{"physical_name":"m_axi_arcache","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"ARID":[{"physical_name":"m_axi_arid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARLEN":[{"physical_name":"m_axi_arlen","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"ARLOCK":[{"physical_name":"m_axi_arlock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARPROT":[{"physical_name":"m_axi_arprot","physical_left":"2","physical_right":"0","logical_left":"2","
|
|
||||||
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</xilinx:boundaryDescriptionInfo>
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|
||||||
</xilinx:componentInstanceExtensions>
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|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:componentInstance>
|
|
||||||
</spirit:componentInstances>
|
|
||||||
</spirit:design>
|
|
||||||
@ -1,71 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>xilinx.com</spirit:vendor>
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|
||||||
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|
||||||
<spirit:name>unknown</spirit:name>
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|
||||||
<spirit:version>1.0</spirit:version>
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|
||||||
<spirit:componentInstances>
|
|
||||||
<spirit:componentInstance>
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|
||||||
<spirit:instanceName>system_valve_interfaces_0_0</spirit:instanceName>
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|
||||||
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_RESET"/>
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|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg400</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../test_lower_machine.gen/sources_1/bd/system/ip/system_valve_interfaces_0_0</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
|
|
||||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OOC_HIERARCHICAL</spirit:configurableElementValue>
|
|
||||||
</spirit:configurableElementValues>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:componentInstanceExtensions>
|
|
||||||
<xilinx:configElementInfos>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SYS_CLK.PHASE" xilinx:valuePermission="bd_and_user"/>
|
|
||||||
</xilinx:configElementInfos>
|
|
||||||
<xilinx:boundaryDescriptionInfo>
|
|
||||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"empty":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rst_n":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"sclk":[{"direction":"out","physical_left":"5","physical_right":"0","is_vector":"true"}],"sdata":[{"direction":"out","physical_left":"5","physical_right":"0","is_vector":"true"}],"sen":[{"direction":"out","physical_left":"5","physical_right":"0","is_vector":"true"}],"sys_clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"total_valve_data":[{"direction":"in","physical_left":"383","physical_right":"0","is_vector":"true"}],"valve_en":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"rst_n":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user",
|
|
||||||
"format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"bd_and_user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"rst_n","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"sys_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"bd_and_user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_PORT":[{"value":"","value_src":"default","value_permission":"bd_and_user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"",
|
|
||||||
"value_src":"default","value_permission":"bd_and_user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"system_processing_system7_0_0_FCLK_CLK0","value_src":"default_prop","value_permission":"bd_and_user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"2e+08","value_src":"user_prop","value_permission":"bd_and_user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"bd_and_user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.
|
|
||||||
0","value_src":"default","value_permission":"bd_and_user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"sys_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
|
||||||
</xilinx:boundaryDescriptionInfo>
|
|
||||||
</xilinx:componentInstanceExtensions>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:componentInstance>
|
|
||||||
</spirit:componentInstances>
|
|
||||||
</spirit:design>
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,82 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="utf-8"?>
|
|
||||||
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
|
|
||||||
<key id="BA" for="node" attr.name="base_addr" attr.type="string"/>
|
|
||||||
<key id="BP" for="node" attr.name="base_param" attr.type="string"/>
|
|
||||||
<key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/>
|
|
||||||
<key id="HA" for="node" attr.name="high_addr" attr.type="string"/>
|
|
||||||
<key id="HP" for="node" attr.name="high_param" attr.type="string"/>
|
|
||||||
<key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/>
|
|
||||||
<key id="MX" for="node" attr.name="master_instance" attr.type="string"/>
|
|
||||||
<key id="MI" for="node" attr.name="master_interface" attr.type="string"/>
|
|
||||||
<key id="MS" for="node" attr.name="master_segment" attr.type="string"/>
|
|
||||||
<key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/>
|
|
||||||
<key id="TM" for="node" attr.name="memory_type" attr.type="string"/>
|
|
||||||
<key id="SX" for="node" attr.name="slave_instance" attr.type="string"/>
|
|
||||||
<key id="SI" for="node" attr.name="slave_interface" attr.type="string"/>
|
|
||||||
<key id="SS" for="node" attr.name="slave_segment" attr.type="string"/>
|
|
||||||
<key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/>
|
|
||||||
<key id="TU" for="node" attr.name="usage_type" attr.type="string"/>
|
|
||||||
<key id="VH" for="node" attr.name="vert_hid" attr.type="int"/>
|
|
||||||
<key id="VM" for="node" attr.name="vert_name" attr.type="string"/>
|
|
||||||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
|
||||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
|
||||||
<node id="n0">
|
|
||||||
<data key="BA">0x43C10000</data>
|
|
||||||
<data key="BP">C_S00_AXI_BASEADDR</data>
|
|
||||||
<data key="HA">0x43C1FFFF</data>
|
|
||||||
<data key="HP">C_S00_AXI_HIGHADDR</data>
|
|
||||||
<data key="MA">Data</data>
|
|
||||||
<data key="MX">/processing_system7_0</data>
|
|
||||||
<data key="MI">M_AXI_GP0</data>
|
|
||||||
<data key="MS">SEG_ip_encoder_0_S00_AXI_reg</data>
|
|
||||||
<data key="MV">xilinx.com:ip:processing_system7:5.5</data>
|
|
||||||
<data key="TM">both</data>
|
|
||||||
<data key="SX">/ip_encoder_0</data>
|
|
||||||
<data key="SI">S00_AXI</data>
|
|
||||||
<data key="SS">S00_AXI_reg</data>
|
|
||||||
<data key="SV">user.org:user:ip_encoder:1.0</data>
|
|
||||||
<data key="TU">register</data>
|
|
||||||
<data key="VT">AC</data>
|
|
||||||
</node>
|
|
||||||
<node id="n1">
|
|
||||||
<data key="VH">2</data>
|
|
||||||
<data key="VM">system</data>
|
|
||||||
<data key="VT">VR</data>
|
|
||||||
</node>
|
|
||||||
<node id="n2">
|
|
||||||
<data key="TU">active</data>
|
|
||||||
<data key="VH">2</data>
|
|
||||||
<data key="VT">PM</data>
|
|
||||||
</node>
|
|
||||||
<node id="n3">
|
|
||||||
<data key="VM">system</data>
|
|
||||||
<data key="VT">BC</data>
|
|
||||||
</node>
|
|
||||||
<node id="n4">
|
|
||||||
<data key="BA">0x43C00000</data>
|
|
||||||
<data key="BP">C_S00_AXI_BASEADDR</data>
|
|
||||||
<data key="HA">0x43C0FFFF</data>
|
|
||||||
<data key="HP">C_S00_AXI_HIGHADDR</data>
|
|
||||||
<data key="MA">Data</data>
|
|
||||||
<data key="MX">/processing_system7_0</data>
|
|
||||||
<data key="MI">M_AXI_GP0</data>
|
|
||||||
<data key="MS">SEG_ip_fifo_0_S00_AXI_reg</data>
|
|
||||||
<data key="MV">xilinx.com:ip:processing_system7:5.5</data>
|
|
||||||
<data key="TM">both</data>
|
|
||||||
<data key="SX">/ip_fifo_0</data>
|
|
||||||
<data key="SI">S00_AXI</data>
|
|
||||||
<data key="SS">S00_AXI_reg</data>
|
|
||||||
<data key="SV">user.org:user:ip_fifo:1.0</data>
|
|
||||||
<data key="TU">register</data>
|
|
||||||
<data key="VT">AC</data>
|
|
||||||
</node>
|
|
||||||
<edge id="e0" source="n3" target="n1"/>
|
|
||||||
<edge id="e1" source="n1" target="n2"/>
|
|
||||||
<edge id="e2" source="n0" target="n2">
|
|
||||||
<data key="EH">2</data>
|
|
||||||
</edge>
|
|
||||||
<edge id="e3" source="n4" target="n2">
|
|
||||||
<data key="EH">2</data>
|
|
||||||
</edge>
|
|
||||||
</graph>
|
|
||||||
</graphml>
|
|
||||||
@ -1,49 +0,0 @@
|
|||||||
{
|
|
||||||
"ActiveEmotionalView":"Default View",
|
|
||||||
"Default View_ScaleFactor":"0.926657",
|
|
||||||
"Default View_TopLeft":"-156,-150",
|
|
||||||
"ExpandedHierarchyInLayout":"",
|
|
||||||
"guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
|
|
||||||
# -string -flagsOSRD
|
|
||||||
preplace port DDR -pg 1 -lvl 5 -x 1620 -y 320 -defaultsOSRD
|
|
||||||
preplace port FIXED_IO -pg 1 -lvl 5 -x 1620 -y 340 -defaultsOSRD
|
|
||||||
preplace port port-id_encoder_signal -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD
|
|
||||||
preplace port port-id_out_signal_camera_0 -pg 1 -lvl 5 -x 1620 -y 520 -defaultsOSRD
|
|
||||||
preplace portBus sen_0 -pg 1 -lvl 5 -x 1620 -y 120 -defaultsOSRD
|
|
||||||
preplace portBus sclk_0 -pg 1 -lvl 5 -x 1620 -y 100 -defaultsOSRD
|
|
||||||
preplace portBus sdata_0 -pg 1 -lvl 5 -x 1620 -y 140 -defaultsOSRD
|
|
||||||
preplace inst processing_system7_0 -pg 1 -lvl 1 -x 230 -y 360 -defaultsOSRD
|
|
||||||
preplace inst ps7_0_axi_periph -pg 1 -lvl 2 -x 640 -y 140 -defaultsOSRD
|
|
||||||
preplace inst rst_ps7_0_200M -pg 1 -lvl 1 -x 230 -y 160 -defaultsOSRD
|
|
||||||
preplace inst ip_encoder_0 -pg 1 -lvl 3 -x 1010 -y 430 -defaultsOSRD
|
|
||||||
preplace inst ila_0 -pg 1 -lvl 4 -x 1410 -y 430 -defaultsOSRD
|
|
||||||
preplace inst valve_interfaces_0 -pg 1 -lvl 4 -x 1410 -y 120 -defaultsOSRD
|
|
||||||
preplace inst ip_fifo_0 -pg 1 -lvl 3 -x 1010 -y 160 -defaultsOSRD
|
|
||||||
preplace netloc in_signal_0_1 1 0 3 NJ 260 470J 420 NJ
|
|
||||||
preplace netloc ip_encoder_0_out_signal_camera 1 3 2 1230J 300 1590J
|
|
||||||
preplace netloc ip_fifo_0_dout 1 3 1 1220 80n
|
|
||||||
preplace netloc ip_fifo_0_empty 1 3 1 N 160
|
|
||||||
preplace netloc processing_system7_0_FCLK_CLK0 1 0 4 20 60 440 290 820 280 1240
|
|
||||||
preplace netloc rst_ps7_0_200M_peripheral_aresetn 1 1 2 430 280 800
|
|
||||||
preplace netloc valve_interfaces_0_sclk 1 4 1 NJ 100
|
|
||||||
preplace netloc valve_interfaces_0_sdata 1 4 1 NJ 140
|
|
||||||
preplace netloc valve_interfaces_0_sen 1 4 1 NJ 120
|
|
||||||
preplace netloc ip_encoder_0_out_signal_valve_posedge 1 3 1 1210 140n
|
|
||||||
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 4 30 460 490 330 790J 40 1230J
|
|
||||||
preplace netloc ip_encoder_0_out_signal_camera_posedge 1 2 2 830 520 1200
|
|
||||||
preplace netloc ip_encoder_0_out_signal_valve 1 3 1 1190 420n
|
|
||||||
preplace netloc processing_system7_0_DDR 1 1 4 460J 310 NJ 310 NJ 310 1600J
|
|
||||||
preplace netloc processing_system7_0_FIXED_IO 1 1 4 480J 320 NJ 320 NJ 320 1580J
|
|
||||||
preplace netloc processing_system7_0_M_AXI_GP0 1 1 1 450 60n
|
|
||||||
preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 N 130
|
|
||||||
preplace netloc ps7_0_axi_periph_M01_AXI 1 2 1 810 150n
|
|
||||||
levelinfo -pg 1 0 230 640 1010 1410 1620
|
|
||||||
pagesize -pg 1 -db -bbox -sgen -160 0 1820 540
|
|
||||||
"
|
|
||||||
}
|
|
||||||
{
|
|
||||||
"da_axi4_cnt":"2",
|
|
||||||
"da_board_cnt":"1",
|
|
||||||
"da_clkrst_cnt":"2",
|
|
||||||
"da_ps7_cnt":"1"
|
|
||||||
}
|
|
||||||
Binary file not shown.
@ -1,46 +0,0 @@
|
|||||||
module valve_interfaces#(
|
|
||||||
parameter VALVE_PORT_NUM = 6,
|
|
||||||
parameter TOTAL_VALVE_DATA_WIDTH = 384,
|
|
||||||
parameter VALVE_DATA_WIDTH = 48
|
|
||||||
)(
|
|
||||||
input [TOTAL_VALVE_DATA_WIDTH - 1:0] total_valve_data,
|
|
||||||
input sys_clk,
|
|
||||||
input rst_n,
|
|
||||||
input valve_en,
|
|
||||||
input empty,
|
|
||||||
output [VALVE_PORT_NUM - 1:0] sclk,
|
|
||||||
output [VALVE_PORT_NUM - 1:0] sen,
|
|
||||||
output [VALVE_PORT_NUM - 1:0] sdata
|
|
||||||
);
|
|
||||||
|
|
||||||
reg [1:0] valve_en_buf;
|
|
||||||
wire [TOTAL_VALVE_DATA_WIDTH - 1:0] total_valve_data_safe = empty ? 'b0 : total_valve_data;
|
|
||||||
wire valve_en_delayed = valve_en_buf[1];
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n) begin
|
|
||||||
valve_en_buf <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
valve_en_buf[0] <= valve_en;
|
|
||||||
valve_en_buf[1] <= valve_en_buf[0];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
generate
|
|
||||||
genvar i;
|
|
||||||
for(i=0; i<VALVE_PORT_NUM; i=i+1) begin: valve_interface_inst
|
|
||||||
valve_interface_0 valve_interface_inst (
|
|
||||||
.input_data(total_valve_data_safe[i * VALVE_DATA_WIDTH + : VALVE_DATA_WIDTH]), // input wire [47 : 0] input_data
|
|
||||||
.sys_clk(sys_clk), // input wire sys_clk
|
|
||||||
.rst_n(rst_n), // input wire rst_n
|
|
||||||
.valve_en(valve_en_delayed), // input wire valve_en
|
|
||||||
.sclk(sclk[i]), // output wire sclk
|
|
||||||
.sen(sen[i]), // output wire sen
|
|
||||||
.sdata(sdata[i]) // output wire sdata
|
|
||||||
);
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
Binary file not shown.
@ -1,3 +0,0 @@
|
|||||||
version:1
|
|
||||||
6d6f64655f636f756e7465727c4755494d6f6465:3
|
|
||||||
eof:
|
|
||||||
@ -1,6 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<!-- Product Version: Vivado v2021.2 (64-bit) -->
|
|
||||||
<!-- -->
|
|
||||||
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
|
|
||||||
|
|
||||||
<labtools version="1" minor="0"/>
|
|
||||||
@ -1,233 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<!-- Product Version: Vivado v2021.2 (64-bit) -->
|
|
||||||
<!-- -->
|
|
||||||
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
|
|
||||||
|
|
||||||
<Project Version="7" Minor="56" Path="/home/miaow/zynq/test_lower_machine/test_lower_machine.tmp/ip_encoder_v1_0_project/ip_encoder_v1_0_project.xpr">
|
|
||||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
|
||||||
<Configuration>
|
|
||||||
<Option Name="Id" Val="be1d97afcb2144ffb3f5d0c96ef1bebc"/>
|
|
||||||
<Option Name="Part" Val="xc7z010clg400-1"/>
|
|
||||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
|
||||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
|
||||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
|
||||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
|
||||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
|
||||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
|
||||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
|
||||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
|
||||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
|
||||||
<Option Name="SimulatorVersionXsim" Val="2021.2"/>
|
|
||||||
<Option Name="SimulatorVersionModelSim" Val="2020.4"/>
|
|
||||||
<Option Name="SimulatorVersionQuesta" Val="2020.4"/>
|
|
||||||
<Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
|
|
||||||
<Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
|
|
||||||
<Option Name="SimulatorVersionRiviera" Val="2020.10"/>
|
|
||||||
<Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
|
|
||||||
<Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
|
|
||||||
<Option Name="BoardPart" Val=""/>
|
|
||||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
||||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
||||||
<Option Name="ProjectType" Val="Default"/>
|
|
||||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ip_repo"/>
|
|
||||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
|
||||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
|
||||||
<Option Name="IPCachePermission" Val="read"/>
|
|
||||||
<Option Name="IPCachePermission" Val="write"/>
|
|
||||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
|
||||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
|
||||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
|
||||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
|
||||||
<Option Name="EnableBDX" Val="FALSE"/>
|
|
||||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTXSimExportSim" Val="0"/>
|
|
||||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
|
||||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
|
||||||
<Option Name="WTIesExportSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsExportSim" Val="0"/>
|
|
||||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
|
||||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
|
||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
|
||||||
<Option Name="XSimRadix" Val="hex"/>
|
|
||||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
|
||||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
|
||||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
|
||||||
<Option Name="SimTypes" Val="rtl"/>
|
|
||||||
<Option Name="SimTypes" Val="bfm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
|
||||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
|
||||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
|
||||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
|
||||||
</Configuration>
|
|
||||||
<FileSets Version="1" Minor="31">
|
|
||||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
|
||||||
<Filter Type="Srcs"/>
|
|
||||||
<File Path="$PPRDIR/../../../ip_repo/ip_encoder_1.0/src/encoder.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="Library" Val=""/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../../ip_repo/ip_encoder_1.0/hdl/ip_encoder_v1_0_S00_AXI.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="Library" Val=""/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../../ip_repo/ip_encoder_1.0/hdl/ip_encoder_v1_0.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="Library" Val=""/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../../ip_repo/ip_encoder_1.0/component.xml">
|
|
||||||
<FileInfo SFType="IPXACT"/>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="ip_encoder_v1_0"/>
|
|
||||||
<Option Name="TopRTLFile" Val="$PPRDIR/../../../ip_repo/ip_encoder_1.0/hdl/ip_encoder_v1_0.v"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
|
||||||
<Filter Type="Constrs"/>
|
|
||||||
<Config>
|
|
||||||
<Option Name="ConstrsType" Val="XDC"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="ip_encoder_v1_0"/>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
<Option Name="TransportPathDelay" Val="0"/>
|
|
||||||
<Option Name="TransportIntDelay" Val="0"/>
|
|
||||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
|
||||||
<Option Name="PamDesignTestbench" Val=""/>
|
|
||||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
|
||||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
|
||||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
|
||||||
<Option Name="SrcSet" Val="sources_1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
|
||||||
<Filter Type="Utils"/>
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
</FileSets>
|
|
||||||
<Simulators>
|
|
||||||
<Simulator Name="XSim">
|
|
||||||
<Option Name="Description" Val="Vivado Simulator"/>
|
|
||||||
<Option Name="CompiledLib" Val="0"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="ModelSim">
|
|
||||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Questa">
|
|
||||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Xcelium">
|
|
||||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="VCS">
|
|
||||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Riviera">
|
|
||||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
</Simulators>
|
|
||||||
<Runs Version="1" Minor="15">
|
|
||||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
|
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
|
|
||||||
<Desc>Default settings for Implementation.</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
</Runs>
|
|
||||||
<Board/>
|
|
||||||
<DashboardSummary Version="1" Minor="0">
|
|
||||||
<Dashboards>
|
|
||||||
<Dashboard Name="default_dashboard">
|
|
||||||
<Gadgets>
|
|
||||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
|
||||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
|
||||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
</Gadgets>
|
|
||||||
</Dashboard>
|
|
||||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
|
||||||
</Dashboards>
|
|
||||||
</DashboardSummary>
|
|
||||||
</Project>
|
|
||||||
@ -1,361 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<!-- Product Version: Vivado v2021.2 (64-bit) -->
|
|
||||||
<!-- -->
|
|
||||||
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
|
|
||||||
|
|
||||||
<Project Version="7" Minor="56" Path="/home/miaow/zynq/test_lower_machine/test_lower_machine.xpr">
|
|
||||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
|
||||||
<Configuration>
|
|
||||||
<Option Name="Id" Val="25b0c33abe3a4dd19f352e7b795735b7"/>
|
|
||||||
<Option Name="Part" Val="xc7z010clg400-1"/>
|
|
||||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
|
||||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
|
||||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
|
||||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
|
||||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
|
||||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
|
||||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
|
||||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
|
||||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
|
||||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
|
||||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
|
||||||
<Option Name="SimulatorVersionXsim" Val="2021.2"/>
|
|
||||||
<Option Name="SimulatorVersionModelSim" Val="2020.4"/>
|
|
||||||
<Option Name="SimulatorVersionQuesta" Val="2020.4"/>
|
|
||||||
<Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
|
|
||||||
<Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
|
|
||||||
<Option Name="SimulatorVersionRiviera" Val="2020.10"/>
|
|
||||||
<Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
|
|
||||||
<Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
|
|
||||||
<Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
|
|
||||||
<Option Name="BoardPart" Val=""/>
|
|
||||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
||||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
||||||
<Option Name="ProjectType" Val="Default"/>
|
|
||||||
<Option Name="IPRepoPath" Val="$PPRDIR/../ip_repo"/>
|
|
||||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
|
||||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
|
||||||
<Option Name="IPCachePermission" Val="read"/>
|
|
||||||
<Option Name="IPCachePermission" Val="write"/>
|
|
||||||
<Option Name="EnableCoreContainer" Val="TRUE"/>
|
|
||||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
|
||||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
|
||||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
|
||||||
<Option Name="EnableBDX" Val="FALSE"/>
|
|
||||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
|
||||||
<Option Name="WTXSimExportSim" Val="39"/>
|
|
||||||
<Option Name="WTModelSimExportSim" Val="39"/>
|
|
||||||
<Option Name="WTQuestaExportSim" Val="39"/>
|
|
||||||
<Option Name="WTIesExportSim" Val="0"/>
|
|
||||||
<Option Name="WTVcsExportSim" Val="39"/>
|
|
||||||
<Option Name="WTRivieraExportSim" Val="39"/>
|
|
||||||
<Option Name="WTActivehdlExportSim" Val="39"/>
|
|
||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
|
||||||
<Option Name="XSimRadix" Val="hex"/>
|
|
||||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
|
||||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
|
||||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
|
||||||
<Option Name="SimTypes" Val="rtl"/>
|
|
||||||
<Option Name="SimTypes" Val="bfm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm"/>
|
|
||||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
|
||||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
|
||||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
|
||||||
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
|
||||||
</Configuration>
|
|
||||||
<FileSets Version="1" Minor="31">
|
|
||||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
|
||||||
<Filter Type="Srcs"/>
|
|
||||||
<File Path="$PSRCDIR/sources_1/ip/valve_interface_0.xcix">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/ip/valve_interface_0/valve_interface_0.xci">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/ip/valve_interface_0/valve_interface_0.xci"/>
|
|
||||||
<Attr Name="ImportTime" Val="1650517366"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/new/valve_interfaces.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PSRCDIR/sources_1/bd/system/system.bd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
<CompFileExtendedInfo CompFileName="system.bd" FileRelPathName="ip/system_ila_0_0/system_ila_0_0.xci">
|
|
||||||
<Proxy FileSetName="system_ila_0_0"/>
|
|
||||||
</CompFileExtendedInfo>
|
|
||||||
<CompFileExtendedInfo CompFileName="system.bd" FileRelPathName="ip/system_valve_interfaces_0_0/system_valve_interfaces_0_0.xci">
|
|
||||||
<Proxy FileSetName="system_valve_interfaces_0_0"/>
|
|
||||||
</CompFileExtendedInfo>
|
|
||||||
<CompFileExtendedInfo CompFileName="system.bd" FileRelPathName="ip/system_ip_fifo_0_0/system_ip_fifo_0_0.xci">
|
|
||||||
<Proxy FileSetName="system_ip_fifo_0_0"/>
|
|
||||||
</CompFileExtendedInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PGENDIR/sources_1/bd/system/hdl/system_wrapper.v">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="system_wrapper"/>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
|
||||||
<Filter Type="Constrs"/>
|
|
||||||
<File Path="$PSRCDIR/constrs_1/new/test_lower_machine.xdc">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/test_lower_machine.xdc"/>
|
|
||||||
<Option Name="ConstrsType" Val="XDC"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
|
||||||
<Filter Type="Srcs"/>
|
|
||||||
<Config>
|
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
|
||||||
<Option Name="TopModule" Val="system_wrapper"/>
|
|
||||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
<Option Name="TransportPathDelay" Val="0"/>
|
|
||||||
<Option Name="TransportIntDelay" Val="0"/>
|
|
||||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
|
||||||
<Option Name="PamDesignTestbench" Val=""/>
|
|
||||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
|
||||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
|
||||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
|
||||||
<Option Name="SrcSet" Val="sources_1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
|
||||||
<Filter Type="Utils"/>
|
|
||||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/system_wrapper.dcp">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
|
||||||
<Attr Name="UsedInSteps" Val="synth_1"/>
|
|
||||||
<Attr Name="AutoDcp" Val="1"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="system_valve_interfaces_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_valve_interfaces_0_0" RelGenDir="$PGENDIR/system_valve_interfaces_0_0">
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopModule" Val="system_valve_interfaces_0_0"/>
|
|
||||||
<Option Name="UseBlackboxStub" Val="1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ila_0_0" RelGenDir="$PGENDIR/system_ila_0_0">
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopModule" Val="system_ila_0_0"/>
|
|
||||||
<Option Name="UseBlackboxStub" Val="1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
<FileSet Name="system_ip_fifo_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_ip_fifo_0_0" RelGenDir="$PGENDIR/system_ip_fifo_0_0">
|
|
||||||
<Config>
|
|
||||||
<Option Name="TopModule" Val="system_ip_fifo_0_0"/>
|
|
||||||
<Option Name="UseBlackboxStub" Val="1"/>
|
|
||||||
</Config>
|
|
||||||
</FileSet>
|
|
||||||
</FileSets>
|
|
||||||
<Simulators>
|
|
||||||
<Simulator Name="XSim">
|
|
||||||
<Option Name="Description" Val="Vivado Simulator"/>
|
|
||||||
<Option Name="CompiledLib" Val="0"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="ModelSim">
|
|
||||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Questa">
|
|
||||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Xcelium">
|
|
||||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="VCS">
|
|
||||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
|
||||||
</Simulator>
|
|
||||||
<Simulator Name="Riviera">
|
|
||||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
|
||||||
</Simulator>
|
|
||||||
</Simulators>
|
|
||||||
<Runs Version="1" Minor="15">
|
|
||||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/system_wrapper.dcp" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="system_valve_interfaces_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_valve_interfaces_0_0" Part="xc7z010clg400-1" ConstrsSet="system_valve_interfaces_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_valve_interfaces_0_0_synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ila_0_0" Part="xc7z010clg400-1" ConstrsSet="system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ila_0_0_synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="system_ip_fifo_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_ip_fifo_0_0" Part="xc7z010clg400-1" ConstrsSet="system_ip_fifo_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ip_fifo_0_0_synth_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Step Id="synth_design"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="system_valve_interfaces_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="system_valve_interfaces_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_valve_interfaces_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_valve_interfaces_0_0_impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ila_0_0_impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
<Run Id="system_ip_fifo_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="system_ip_fifo_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_ip_fifo_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_ip_fifo_0_0_impl_1">
|
|
||||||
<Strategy Version="1" Minor="2">
|
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Step Id="init_design"/>
|
|
||||||
<Step Id="opt_design"/>
|
|
||||||
<Step Id="power_opt_design"/>
|
|
||||||
<Step Id="place_design"/>
|
|
||||||
<Step Id="post_place_power_opt_design"/>
|
|
||||||
<Step Id="phys_opt_design"/>
|
|
||||||
<Step Id="route_design"/>
|
|
||||||
<Step Id="post_route_phys_opt_design"/>
|
|
||||||
<Step Id="write_bitstream"/>
|
|
||||||
</Strategy>
|
|
||||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
|
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
|
||||||
<RQSFiles/>
|
|
||||||
</Run>
|
|
||||||
</Runs>
|
|
||||||
<Board/>
|
|
||||||
<DashboardSummary Version="1" Minor="0">
|
|
||||||
<Dashboards>
|
|
||||||
<Dashboard Name="default_dashboard">
|
|
||||||
<Gadgets>
|
|
||||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
|
||||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
|
||||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
|
||||||
</Gadget>
|
|
||||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
|
||||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
|
||||||
</Gadget>
|
|
||||||
</Gadgets>
|
|
||||||
</Dashboard>
|
|
||||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
|
||||||
</Dashboards>
|
|
||||||
</DashboardSummary>
|
|
||||||
</Project>
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,29 +1,34 @@
|
|||||||
|
# 下位机和上位机通信协议 V1.1
|
||||||
|
|
||||||
| 起始 | 长度高 | 长度低 | 类型高 | 类型低 | 数据字节1 | ... | 数据字节n | 校验低 | 校验高 | 结束 |
|
| 起始 | 长度高 | 长度低 | 类型高 | 类型低 | 数据字节1 | ... | 数据字节n | 校验低 | 校验高 | 结束 |
|
||||||
| ---- | ------ | ------ | ------ | ------ | --------- | ---- | --------- | ------ | ------ | ---- |
|
| ---- | ------ | ------ | ------ | ------ | --------- | ---- | --------- | ------ | ------ | ---- |
|
||||||
| 0xAA | 0x00 | 0x03 | 's' | 't' | | | | 0xFF | 0xFF | 0xBB |
|
| 0xAA | 0x00 | 0x0A | 's' | 't' | | | | 0xFF | 0xFF | 0xBB |
|
||||||
|
|
||||||
长度=数据字节数+2，组成一个无符号16位数，校验字节随意给值即可
|
**长度**=数据字节数+2，组成一个无符号16位数，校验字节随意给值即可
|
||||||
|
|
||||||
类型
|
**类型**
|
||||||
|
|
||||||
- 命令
|
- 命令
|
||||||
|
|
||||||
- 开始命令 st，长度3，数据0xFF
|
- 开始命令 st，**长度**3，**数据**0xFF
|
||||||
- 停止命令sp，长度3，数据0xFF
|
- 停止命令sp，**长度**3，**数据**0xFF
|
||||||
- 测试命令te，长度3，数据0xFF
|
- 测试命令te，**长度**10，数据为十进制字符串，'0''0''0''0''0''0''5''0'表示值50，'5'在前，'0'在后
|
||||||
- poweron命令po，长度3，数据0xFF
|
- 停止测试tt，**长度**3，**数据**0xFF
|
||||||
- 设置相机触发周期对应的脉冲数sc，长度4，数据位十进制字符串'5''0'表示值50，'5'在前，'0'在后
|
- poweron命令po，**长度**3，**数据**0xFF
|
||||||
- 设置阀板动作对应的脉冲数sv，长度4，数据位十进制字符串'5''0'表示值50，'5'在前，'0'在后
|
- 设置相机触发周期对应的脉冲数sc，**长度**10，数据为十进制字符串，'0''0''0''0''0''0''5''0'表示值50，'5'在前，'0'在后 // 1234
|
||||||
- 设置相机触发到阀板动作的延迟脉冲数sd，长度4，数据位十进制字符串'5''0'表示值100，'5'在前，'0'在后
|
- 设置阀板动作对应的脉冲数sv，**长度**10，数据为十进制字符串，'0''0''0''0''0''0''5''0'表示值50，'5'在前，'0'在后 //1000
|
||||||
- 数据命令da， 长度为3002，数据要有3000个
|
- 设置相机触发到阀板动作的延迟脉冲数sd，**长度**10，数据为十进制字符串，'0''0''0''0''0''0''5''0'表示值50，'5'在前，'0'在后 //200
|
||||||
|
- 数据命令da， **长度**为视需求而定，数据要有（**长度**-2）个字节
|
||||||
|
|
||||||
- 数据
|
- 数据
|
||||||
|
|
||||||
数据就是阀数据，其实这是一个命令，也就是数据命令'da'，分到数据这一节写是因为它的参数格式和其他命令不同，下表为字节排序，接收时从左往右，也就是数据字节1先接收到，然后是数据字节2，最后是数据字节6。阀1代表面向阀板，最靠近右边的阀，所以最左边的为阀48
|
数据就是阀数据，其实这是一个命令，也就是数据命令'da'，分到数据这一节写是因为它的参数格式和其他命令不同，下表为字节排序，接收时从右往左，也就是数据字节1先接收到，然后是数据字节2，最后是数据字节(m-1)。
|
||||||
|
|
||||||
|
阀1代表面向各块阀板，最靠近右边的阀，所以最左边的为阀n
|
||||||
|
|
||||||
| 数据字节1 | 数据字节2 | 数据字节3 | 数据字节4 | 数据字节5 | 数据字节6 |
|
| 数据字节(m-1) | 数据字节(m-2) | ... | 数据字节2 | 数据字节1 | 数据字节0 |
|
||||||
| --------- | --------- | --------- | --------- | --------- | --------- |
|
| ------------- | -------------- | ---- | --------- | --------- | --------- |
|
||||||
| 阀48-41 | 阀40-33 | 阀32-25 | 阀24-17 | 阀16-9 | 阀8-1 |
|
| 阀n~(n-7) | 阀(n-8)~(n-15) | ... | 阀24-17 | 阀16-9 | 阀8-1 |
|
||||||
|
|
||||||
对于各个字节，其中的位是这么对应的，以数据字节2为例
|
对于各个字节，其中的位是这么对应的，以数据字节2为例
|
||||||
|
|
||||||
@ -31,4 +36,4 @@
|
|||||||
| ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---- |
|
| ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---- |
|
||||||
| 阀8 | 阀7 | 阀6 | 阀5 | 阀4 | 阀3 | 阀2 | 阀1 |
|
| 阀8 | 阀7 | 阀6 | 阀5 | 阀4 | 阀3 | 阀2 | 阀1 |
|
||||||
|
|
||||||
需要注意的是，这里的数据不是ascii编码的，是直接的数据字节。上面描述字节排序的表为hostcomputer图像中的一行对应的阀动作，一共500行，发送完一行后接着发送下一行，直到最后一行。因此一共有3000个字节的数据。
|
需要注意的是，这里的数据不是ascii编码的，是直接的数据字节。上面描述字节排序的表为hostcomputer图像中的一行对应的阀动作，一共若干行，发送完一行后接着发送下一行，直到最后一行。因此一共有(行数*m)个字节的数据。
|
||||||
108
script/.bashrc
Normal file
108
script/.bashrc
Normal file
@ -0,0 +1,108 @@
|
|||||||
|
|
||||||
|
# If not running interactively, don't do anything
|
||||||
|
case $- in
|
||||||
|
*i*) ;;
|
||||||
|
*) return;;
|
||||||
|
esac
|
||||||
|
|
||||||
|
# don't put duplicate lines or lines starting with space in the history.
|
||||||
|
# See bash(1) for more options
|
||||||
|
HISTCONTROL=ignoreboth
|
||||||
|
|
||||||
|
# append to the history file, don't overwrite it
|
||||||
|
shopt -s histappend
|
||||||
|
|
||||||
|
# for setting history length see HISTSIZE and HISTFILESIZE in bash(1)
|
||||||
|
HISTSIZE=1000
|
||||||
|
HISTFILESIZE=2000
|
||||||
|
|
||||||
|
# check the window size after each command and, if necessary,
|
||||||
|
# update the values of LINES and COLUMNS.
|
||||||
|
shopt -s checkwinsize
|
||||||
|
|
||||||
|
# If set, the pattern "**" used in a pathname expansion context will
|
||||||
|
# match all files and zero or more directories and subdirectories.
|
||||||
|
#shopt -s globstar
|
||||||
|
|
||||||
|
# make less more friendly for non-text input files, see lesspipe(1)
|
||||||
|
[ -x /usr/bin/lesspipe ] && eval "$(SHELL=/bin/sh lesspipe)"
|
||||||
|
|
||||||
|
# set a fancy prompt (non-color, unless we know we "want" color)
|
||||||
|
case "$TERM" in
|
||||||
|
xterm-color|*-256color) color_prompt=yes;;
|
||||||
|
esac
|
||||||
|
|
||||||
|
# uncomment for a colored prompt, if the terminal has the capability; turned
|
||||||
|
# off by default to not distract the user: the focus in a terminal window
|
||||||
|
# should be on the output of commands, not on the prompt
|
||||||
|
force_color_prompt=yes
|
||||||
|
|
||||||
|
if [ -n "$force_color_prompt" ]; then
|
||||||
|
if [ -x /usr/bin/tput ] && tput setaf 1 >&/dev/null; then
|
||||||
|
# We have color support; assume it's compliant with Ecma-48
|
||||||
|
# (ISO/IEC-6429). (Lack of such support is extremely rare, and such
|
||||||
|
# a case would tend to support setf rather than setaf.)
|
||||||
|
color_prompt=yes
|
||||||
|
else
|
||||||
|
color_prompt=
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
|
||||||
|
if [ "$color_prompt" = yes ]; then
|
||||||
|
PS1='\[\033[01;32m\]\u@\h\[\033[00m\]:\[\033[01;34m\]\w\[\033[00m\]\$ '
|
||||||
|
else
|
||||||
|
PS1='\u@\h:\w\$ '
|
||||||
|
fi
|
||||||
|
unset color_prompt force_color_prompt
|
||||||
|
|
||||||
|
# If this is an xterm set the title to user@host:dir
|
||||||
|
case "$TERM" in
|
||||||
|
xterm*|rxvt*)
|
||||||
|
PS1="\[\e]0;${debian_chroot:+($debian_chroot)}\u@\h: \w\a\]$PS1"
|
||||||
|
;;
|
||||||
|
*)
|
||||||
|
;;
|
||||||
|
esac
|
||||||
|
|
||||||
|
# enable color support of ls and also add handy aliases
|
||||||
|
|
||||||
|
alias ls='ls --color=auto'
|
||||||
|
#alias dir='dir --color=auto'
|
||||||
|
#alias vdir='vdir --color=auto'
|
||||||
|
|
||||||
|
alias grep='grep --color=auto'
|
||||||
|
alias fgrep='fgrep --color=auto'
|
||||||
|
alias egrep='egrep --color=auto'
|
||||||
|
|
||||||
|
|
||||||
|
# colored GCC warnings and errors
|
||||||
|
#export GCC_COLORS='error=01;31:warning=01;35:note=01;36:caret=01;32:locus=01:quote=01'
|
||||||
|
|
||||||
|
# some more ls aliases
|
||||||
|
alias ll='ls -alF'
|
||||||
|
alias la='ls -A'
|
||||||
|
alias l='ls -CF'
|
||||||
|
|
||||||
|
# Add an "alert" alias for long running commands. Use like so:
|
||||||
|
# sleep 10; alert
|
||||||
|
alias alert='notify-send --urgency=low -i "$([ $? = 0 ] && echo terminal || echo error)" "$(history|tail -n1|sed -e '\''s/^\s*[0-9]\+\s*//;s/[;&|]\s*alert$//'\'')"'
|
||||||
|
|
||||||
|
# Alias definitions.
|
||||||
|
# You may want to put all your additions into a separate file like
|
||||||
|
# ~/.bash_aliases, instead of adding them here directly.
|
||||||
|
# See /usr/share/doc/bash-doc/examples in the bash-doc package.
|
||||||
|
|
||||||
|
if [ -f ~/.bash_aliases ]; then
|
||||||
|
. ~/.bash_aliases
|
||||||
|
fi
|
||||||
|
|
||||||
|
# enable programmable completion features (you don't need to enable
|
||||||
|
# this, if it's already enabled in /etc/bash.bashrc and /etc/profile
|
||||||
|
# sources /etc/bash.bashrc).
|
||||||
|
if [ -f /usr/share/bash-completion/bash_completion ]; then
|
||||||
|
. /usr/share/bash-completion/bash_completion
|
||||||
|
elif [ -f /etc/bash_completion ]; then
|
||||||
|
. /etc/bash_completion
|
||||||
|
fi
|
||||||
|
|
||||||
|
|
||||||
11
script/.profile
Normal file
11
script/.profile
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
# ~/.profile: executed by Bourne-compatible login shells.
|
||||||
|
|
||||||
|
if [ -f ~/.bashrc ]; then
|
||||||
|
. ~/.bashrc
|
||||||
|
fi
|
||||||
|
|
||||||
|
# path set by /etc/profile
|
||||||
|
# export PATH
|
||||||
|
|
||||||
|
# Might fail after "su - myuser" when /dev/tty* is not writable by "myuser".
|
||||||
|
mesg n 2>/dev/null
|
||||||
@ -1,2 +0,0 @@
|
|||||||
待补充
|
|
||||||
|
|
||||||
3
script/loadencoder.sh
Normal file
3
script/loadencoder.sh
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
#!/bin/sh
|
||||||
|
|
||||||
|
modprobe encoder
|
||||||
3
script/loadfifo.sh
Normal file
3
script/loadfifo.sh
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
#!/bin/sh
|
||||||
|
|
||||||
|
modprobe fifo
|
||||||
5
script/target.sh
Normal file
5
script/target.sh
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
#!/bin/sh
|
||||||
|
|
||||||
|
if [ -x /home/root/target ]; then
|
||||||
|
/home/root/target
|
||||||
|
fi
|
||||||
66
source/linux_app/.gitignore
vendored
Normal file
66
source/linux_app/.gitignore
vendored
Normal file
@ -0,0 +1,66 @@
|
|||||||
|
# Prerequisites
|
||||||
|
*.d
|
||||||
|
|
||||||
|
.vscode/*
|
||||||
|
!.vscode/settings.json
|
||||||
|
!.vscode/tasks.json
|
||||||
|
!.vscode/launch.json
|
||||||
|
!.vscode/extensions.json
|
||||||
|
!.vscode/c_cpp_properties.json
|
||||||
|
!.vscode/*.code-snippets
|
||||||
|
build/
|
||||||
|
|
||||||
|
# Local History for Visual Studio Code
|
||||||
|
.history/
|
||||||
|
|
||||||
|
# Built Visual Studio Code Extensions
|
||||||
|
*.vsix
|
||||||
|
# Object files
|
||||||
|
*.o
|
||||||
|
*.ko
|
||||||
|
*.obj
|
||||||
|
*.elf
|
||||||
|
|
||||||
|
# Linker output
|
||||||
|
*.ilk
|
||||||
|
*.map
|
||||||
|
*.exp
|
||||||
|
|
||||||
|
# Precompiled Headers
|
||||||
|
*.gch
|
||||||
|
*.pch
|
||||||
|
|
||||||
|
# Libraries
|
||||||
|
*.lib
|
||||||
|
*.a
|
||||||
|
*.la
|
||||||
|
*.lo
|
||||||
|
|
||||||
|
# Shared objects (inc. Windows DLLs)
|
||||||
|
*.dll
|
||||||
|
*.so
|
||||||
|
*.so.*
|
||||||
|
*.dylib
|
||||||
|
|
||||||
|
# Executables
|
||||||
|
*.exe
|
||||||
|
*.out
|
||||||
|
*.app
|
||||||
|
*.i*86
|
||||||
|
*.x86_64
|
||||||
|
*.hex
|
||||||
|
|
||||||
|
# Debug files
|
||||||
|
*.dSYM/
|
||||||
|
*.su
|
||||||
|
*.idb
|
||||||
|
*.pdb
|
||||||
|
|
||||||
|
# Kernel Module Compile Results
|
||||||
|
*.mod*
|
||||||
|
*.cmd
|
||||||
|
.tmp_versions/
|
||||||
|
modules.order
|
||||||
|
Module.symvers
|
||||||
|
Mkfile.old
|
||||||
|
dkms.conf
|
||||||
86
source/linux_app/Makefile
Normal file
86
source/linux_app/Makefile
Normal file
@ -0,0 +1,86 @@
|
|||||||
|
#makefile for file_ioctl
|
||||||
|
CROSS_COMPILE ?= /home/miaow/software/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/bin/arm-none-linux-gnueabihf-
|
||||||
|
TARGET := target
|
||||||
|
BUILD_DIR := build
|
||||||
|
|
||||||
|
ifeq ("$(origin V)", "command line")
|
||||||
|
KBUILD_VERBOSE = $(V)
|
||||||
|
endif
|
||||||
|
ifndef KBUILD_VERBOSE
|
||||||
|
KBUILD_VERBOSE = 0
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(KBUILD_VERBOSE),1)
|
||||||
|
quiet =
|
||||||
|
Q =
|
||||||
|
else
|
||||||
|
quiet=quiet_
|
||||||
|
Q = @
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4
|
||||||
|
ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
|
||||||
|
quiet=silent_
|
||||||
|
endif
|
||||||
|
else # make-3.8x
|
||||||
|
ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
|
||||||
|
quiet=silent_
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
|
||||||
|
SRC := $(wildcard *.c)
|
||||||
|
ASM_SRC := $(wildcard *.s)
|
||||||
|
OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.o)))
|
||||||
|
ASM_OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.o)))
|
||||||
|
DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.dis)))
|
||||||
|
ASM_DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.dis)))
|
||||||
|
|
||||||
|
_TARGET := $(BUILD_DIR)/$(TARGET)
|
||||||
|
TARGET_DIS := $(BUILD_DIR)/$(TARGET).dis
|
||||||
|
|
||||||
|
LD = $(CROSS_COMPILE)ld
|
||||||
|
CC = $(CROSS_COMPILE)gcc
|
||||||
|
CPP = $(CC) -E
|
||||||
|
AR = $(CROSS_COMPILE)ar
|
||||||
|
LDR = $(CROSS_COMPILE)ldr
|
||||||
|
STRIP = $(CROSS_COMPILE)strip
|
||||||
|
OBJCOPY = $(CROSS_COMPILE)objcopy
|
||||||
|
OBJDUMP = $(CROSS_COMPILE)objdump
|
||||||
|
CFLAGS = -g -std=gnu99 -Wall -I.
|
||||||
|
LDFLAGS = -lpthread -lc -lm -lrt
|
||||||
|
|
||||||
|
.SECONDARY:
|
||||||
|
|
||||||
|
.PHONY:all
|
||||||
|
all: $(_TARGET) $(DIS) $(ASM_DIS) $(TARGET_DIS)
|
||||||
|
|
||||||
|
$(BUILD_DIR)/%.i:%.c %.h Makefile | $(BUILD_DIR)
|
||||||
|
$(Q)$(CC) -E $(CFLAGS) $< -o $@
|
||||||
|
$(BUILD_DIR)/%.s:$(BUILD_DIR)/%.i Makefile | $(BUILD_DIR)
|
||||||
|
$(Q)$(CC) -S $(CFLAGS) $< -o $@
|
||||||
|
$(BUILD_DIR)/%.o:$(BUILD_DIR)/%.s Makefile | $(BUILD_DIR)
|
||||||
|
$(Q)$(CC) -c $(CFLAGS) $< -o $@
|
||||||
|
$(BUILD_DIR)/%.o:%.s Makefile | $(BUILD_DIR)
|
||||||
|
$(Q)$(CC) -c $(CFLAGS) $< -o $@
|
||||||
|
$(BUILD_DIR)/%.dis:$(BUILD_DIR)/%.o Makefile | $(BUILD_DIR)
|
||||||
|
$(Q)$(OBJDUMP) -s -d $< > $@
|
||||||
|
$(TARGET_DIS):$(_TARGET) Makefile | $(BUILD_DIR)
|
||||||
|
$(Q)$(OBJDUMP) -s -d $< > $@
|
||||||
|
$(_TARGET):$(OBJ) $(ASM_OBJ) Makefile | $(BUILD_DIR)
|
||||||
|
$(Q)$(CC) $(OBJ) $(ASM_OBJ) $(LDFLAGS) -o $@
|
||||||
|
|
||||||
|
|
||||||
|
.PHONY:clean
|
||||||
|
clean:
|
||||||
|
$(Q)$(RM) $(BUILD_DIR)/* -f
|
||||||
|
|
||||||
|
.PHONY:install
|
||||||
|
install:$(TARGET)
|
||||||
|
$(Q)chmod 777 $(TARGET)
|
||||||
|
|
||||||
|
.PHONY:$(BUILD_DIR)
|
||||||
|
$(BUILD_DIR):
|
||||||
|
$(Q)if [ ! -d $(BUILD_DIR) ]; then mkdir -p $@; fi
|
||||||
|
|
||||||
|
|
||||||
46
source/linux_app/common.h
Normal file
46
source/linux_app/common.h
Normal file
@ -0,0 +1,46 @@
|
|||||||
|
/**
|
||||||
|
* @file common.h
|
||||||
|
* @brief Common macros.
|
||||||
|
* @author miaow (3703781@qq.com)
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2022/06/12
|
||||||
|
* @mainpage github.com/NanjingForestryUniversity
|
||||||
|
*
|
||||||
|
* @copyright Copyright (c) 2022 miaow
|
||||||
|
*
|
||||||
|
* @par Changelog:
|
||||||
|
* <table>
|
||||||
|
* <tr><th>Date <th>Version <th>Author <th>Description
|
||||||
|
* <tr><td>2022/06/12 <td>1.0 <td>miaow <td>Write this file
|
||||||
|
* </table>
|
||||||
|
*/
|
||||||
|
#ifndef __COMMON_H
|
||||||
|
#define __COMMON_H
|
||||||
|
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <errno.h>
|
||||||
|
|
||||||
|
#define ON_ERROR(res, message1, message2) \
|
||||||
|
if (res < 0) \
|
||||||
|
{ \
|
||||||
|
sprintf(perror_buffer, "error %d at %s:%d, %s, %s", res, __FILE__, __LINE__, message1, message2); \
|
||||||
|
perror(perror_buffer); \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define ON_ERROR_RET_VOID(res, message1, message2) \
|
||||||
|
ON_ERROR(res, message1, message2); \
|
||||||
|
if (res < 0) \
|
||||||
|
{ \
|
||||||
|
res = 0; \
|
||||||
|
return; \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define ON_ERROR_RET(res, message1, message2, retval) \
|
||||||
|
ON_ERROR(res, message1, message2); \
|
||||||
|
if (res < 0) \
|
||||||
|
{ \
|
||||||
|
res = 0; \
|
||||||
|
return retval; \
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
119
source/linux_app/encoder_dev.c
Normal file
119
source/linux_app/encoder_dev.c
Normal file
@ -0,0 +1,119 @@
|
|||||||
|
/**
|
||||||
|
* @file encoder_dev.c
|
||||||
|
* @brief Manage the hardware encoder unit
|
||||||
|
* @author miaow (3703781@qq.com)
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2022/06/11
|
||||||
|
* @mainpage github.com/NanjingForestryUniversity
|
||||||
|
*
|
||||||
|
* @copyright Copyright (c) 2022 miaow
|
||||||
|
*
|
||||||
|
* @par Changelog:
|
||||||
|
* <table>
|
||||||
|
* <tr><th>Date <th>Version <th>Author <th>Description
|
||||||
|
* <tr><td>2022/06/11 <td>0.9 <td>Miaow <td>Write this module
|
||||||
|
* </table>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <encoder_dev.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <fcntl.h>
|
||||||
|
#include <unistd.h>
|
||||||
|
#include <sys/ioctl.h>
|
||||||
|
#include <sys/types.h>
|
||||||
|
#include <sys/stat.h>
|
||||||
|
|
||||||
|
#define ENCODER_CMD_FUNCTION_CLEAR 1
|
||||||
|
#define ENCODER_CMD_FUNCTION_VIRT_INPUT 2
|
||||||
|
|
||||||
|
static int encoder_dev_fd = -1;
|
||||||
|
static char perror_buffer[128];
|
||||||
|
|
||||||
|
static struct {
|
||||||
|
unsigned int valve_divide_value;
|
||||||
|
unsigned int camera_divide_value;
|
||||||
|
} encoder_dev_divide_value_structure;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the hardware encoder unit
|
||||||
|
* @note This function just open the file descriptor of the hardware encoder unit
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int encoder_dev_init()
|
||||||
|
{
|
||||||
|
encoder_dev_fd = open(ENCODER_DEV_PATH, O_RDWR);
|
||||||
|
ON_ERROR_RET(encoder_dev_fd, "", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the two divider in the hareware encoder unit.
|
||||||
|
* @param valve_divide the frequency division factor between the encoder signal and valve output
|
||||||
|
* Set ENCODER_DEV_DIVIDE_NOT_TO_SET to skip changing the division facter
|
||||||
|
* @param camera_divide the frequency division factor between the encoder signal and camera triggle signal
|
||||||
|
* Set ENCODER_DEV_DIVIDE_NOT_TO_SET to skip changing the division facter
|
||||||
|
*
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int encoder_dev_set_divide(int valve_divide, int camera_divide)
|
||||||
|
{
|
||||||
|
encoder_dev_divide_value_structure.valve_divide_value = valve_divide;
|
||||||
|
encoder_dev_divide_value_structure.camera_divide_value = camera_divide;
|
||||||
|
ssize_t size = write(encoder_dev_fd, &encoder_dev_divide_value_structure, sizeof(encoder_dev_divide_value_structure));
|
||||||
|
int res = -(size != sizeof(encoder_dev_divide_value_structure));
|
||||||
|
ON_ERROR_RET(res, "size=", "", -1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the trig signal to internal or external.
|
||||||
|
* @param mode ENCODER_TRIG_MODE_EXTERNEL for externally trig, or ENCODER_TRIG_MODE_INTERNEL for internally trig
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int encoder_dev_virtual_trig(int count)
|
||||||
|
{
|
||||||
|
int res = ioctl(encoder_dev_fd, _IOW('D', ENCODER_CMD_FUNCTION_VIRT_INPUT, 4), count);
|
||||||
|
ON_ERROR_RET(res, "", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the trig signal to internal or external.
|
||||||
|
* @param mode ENCODER_TRIG_MODE_EXTERNEL for externally trig, or ENCODER_TRIG_MODE_INTERNEL for internally trig
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int encoder_dev_set_trigmod(int mode)
|
||||||
|
{
|
||||||
|
int res = ioctl(encoder_dev_fd, _IOW('D', mode, 0));
|
||||||
|
ON_ERROR_RET(res, "", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Claer the cache in hardware encoder unit.
|
||||||
|
* @note The frequency division counters continutly count pluses of external/internal signal.
|
||||||
|
* This functhion clears the counters.
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int encoder_dev_flush()
|
||||||
|
{
|
||||||
|
int res = ioctl(encoder_dev_fd, _IOW('D', ENCODER_CMD_FUNCTION_CLEAR, 0));
|
||||||
|
ON_ERROR_RET(res, "", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitialize the hardware encoder unit.
|
||||||
|
* @note This function just close the file descriptor of the encoder unit.
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int encoder_dev_deinit()
|
||||||
|
{
|
||||||
|
int res = close(encoder_dev_fd);
|
||||||
|
|
||||||
|
ON_ERROR_RET(res, "", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
35
source/linux_app/encoder_dev.h
Normal file
35
source/linux_app/encoder_dev.h
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
/**
|
||||||
|
* @file encoder_dev.h
|
||||||
|
* @brief Manage the hardware encoder unit
|
||||||
|
* @author miaow (3703781@qq.com)
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2022/06/11
|
||||||
|
*
|
||||||
|
* @copyright Copyright (c) 2022 miaow
|
||||||
|
*
|
||||||
|
* @par Changelog:
|
||||||
|
* <table>
|
||||||
|
* <tr><th>Date <th>Version <th>Author <th>Description
|
||||||
|
* <tr><td>2022/06/11 <td>0.9 <td>Miaow <td>Write this module
|
||||||
|
* </table>
|
||||||
|
*/
|
||||||
|
#ifndef __ENCODER_DEV_H
|
||||||
|
#define __ENCODER_DEV_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#define ENCODER_DEV_PATH "/dev/encoder"
|
||||||
|
|
||||||
|
#define ENCODER_DEV_DIVIDE_NOT_TO_SET 0
|
||||||
|
|
||||||
|
#define ENCODER_TRIG_MODE_EXTERNEL 100
|
||||||
|
#define ENCODER_TRIG_MODE_INTERNEL 101
|
||||||
|
|
||||||
|
int encoder_dev_set_divide(int valve_divide, int camera_divide);
|
||||||
|
int encoder_dev_flush(void);
|
||||||
|
int encoder_dev_set_trigmod(int mode);
|
||||||
|
int encoder_dev_virtual_trig(int count);
|
||||||
|
int encoder_dev_init(void);
|
||||||
|
int encoder_dev_deinit(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
120
source/linux_app/fifo_dev.c
Normal file
120
source/linux_app/fifo_dev.c
Normal file
@ -0,0 +1,120 @@
|
|||||||
|
/**
|
||||||
|
* @file fifo_dev.c
|
||||||
|
* @brief Operate the hardware fifo with Linux application
|
||||||
|
* @details Call fifo_dev_init() paired with fifo_dev_deinit() as their names imply, fifo_dev_write() can be executed several times to operate the hardware fifo between fifo_dev_init() and fifo_dev_deinit()
|
||||||
|
* @mainpage github.com/NanjingForestryUniversity
|
||||||
|
* @author miaow
|
||||||
|
* @email 3703781@qq.com
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2022/06/09
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <fifo_dev.h>
|
||||||
|
#include <pthread.h>
|
||||||
|
#include <unistd.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <fcntl.h>
|
||||||
|
#include <sys/ioctl.h>
|
||||||
|
#include <sys/types.h>
|
||||||
|
#include <sys/stat.h>
|
||||||
|
|
||||||
|
#define FIFO_CMD_FUNCTION_CLEAR 1
|
||||||
|
#define FIFO_CMD_FUNCTION_PADDING 2
|
||||||
|
|
||||||
|
|
||||||
|
static int fifo_dev_fd = -1;
|
||||||
|
static char perror_buffer[128];
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the hardware fifo
|
||||||
|
* @note This function just open the file descriptor of the hardware fifo
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int fifo_dev_init()
|
||||||
|
{
|
||||||
|
fifo_dev_fd = open(FIFO_DEV_PATH, O_RDWR);
|
||||||
|
ON_ERROR_RET(fifo_dev_fd, "", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set value to put of a frame.
|
||||||
|
* @param valve_data An array 32bytes * 600rows.
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int fifo_dev_write_frame(void *valve_data)
|
||||||
|
{
|
||||||
|
ssize_t size = write(fifo_dev_fd, valve_data, 32 * 600);
|
||||||
|
int res = -(size < 32 * 600);
|
||||||
|
ON_ERROR_RET(res, "size=", "", -1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set value to put of a row.
|
||||||
|
* @param valve_data An array 32bytes.
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int fifo_dev_write_row(void *valve_data)
|
||||||
|
{
|
||||||
|
ssize_t size = write(fifo_dev_fd, valve_data, 32);
|
||||||
|
int res = -(size < 32);
|
||||||
|
ON_ERROR_RET(res, "size=", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Flush and clear the hardware fifo.
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int fifo_dev_clear()
|
||||||
|
{
|
||||||
|
int res = ioctl(fifo_dev_fd, _IOW('D', FIFO_CMD_FUNCTION_CLEAR, 0));
|
||||||
|
|
||||||
|
ON_ERROR_RET(res, "", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write `count` zero-items to the haredware fifo, which acts as delay time.
|
||||||
|
* @param count Count of zero-items to write.
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int fifo_dev_write_delay(uint32_t count)
|
||||||
|
{
|
||||||
|
int res = ioctl(fifo_dev_fd, _IOW('D', FIFO_CMD_FUNCTION_CLEAR, 0), count);
|
||||||
|
|
||||||
|
ON_ERROR_RET(res, "", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the count of items in the hardware fifo.
|
||||||
|
* @note An item from hardware fifo is of 256 bits in size, aka. 32 bytes, 8 integers
|
||||||
|
* @return 0 - success, other - error
|
||||||
|
*/
|
||||||
|
int fifo_dev_get_count()
|
||||||
|
{
|
||||||
|
uint32_t fifo_item_count;
|
||||||
|
ssize_t size = read(fifo_dev_fd, &fifo_item_count, sizeof(fifo_item_count));
|
||||||
|
|
||||||
|
if (size != sizeof(fifo_item_count))
|
||||||
|
ON_ERROR(-1, "size=", "");
|
||||||
|
|
||||||
|
return fifo_item_count;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitialize the hardware fifo.
|
||||||
|
* @note This function just close the file descriptor of the hardware fifo.
|
||||||
|
* @return 0 - success, -1 - error
|
||||||
|
*/
|
||||||
|
int fifo_dev_deinit()
|
||||||
|
{
|
||||||
|
int res = close(fifo_dev_fd);
|
||||||
|
|
||||||
|
ON_ERROR_RET(res, "", "", -1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
27
source/linux_app/fifo_dev.h
Normal file
27
source/linux_app/fifo_dev.h
Normal file
@ -0,0 +1,27 @@
|
|||||||
|
/**
|
||||||
|
* @file fifo_dev.h
|
||||||
|
* @brief Operate the hardware fifo with Linux application
|
||||||
|
* @details Call fifo_dev_init() paired with fifo_dev_deinit() as their names imply, fifo_dev_write() can be executed several times to operate the hardware fifo between fifo_dev_init() and fifo_dev_deinit()
|
||||||
|
* @mainpage github.com/NanjingForestryUniversity
|
||||||
|
* @author miaow
|
||||||
|
* @email 3703781@qq.com
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2022/06/09
|
||||||
|
*/
|
||||||
|
#ifndef __FIFO_DEV_H
|
||||||
|
#define __FIFO_DEV_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#define FIFO_DEV_PATH "/dev/fifo"
|
||||||
|
|
||||||
|
int fifo_dev_init(void);
|
||||||
|
int fifo_dev_write_frame(void *valve_data);
|
||||||
|
int fifo_dev_clear(void);
|
||||||
|
int fifo_dev_write_delay(uint32_t count);
|
||||||
|
int fifo_dev_write_row(void *valve_data);
|
||||||
|
int fifo_dev_get_count(void);
|
||||||
|
|
||||||
|
int fifo_dev_deinit(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
289
source/linux_app/host_computer.c
Normal file
289
source/linux_app/host_computer.c
Normal file
@ -0,0 +1,289 @@
|
|||||||
|
/**
|
||||||
|
* @file host_computer.c
|
||||||
|
* @brief Commnunicate with host computer. Protocal is described in hostcomputer通信协议.md
|
||||||
|
* @author miaow (3703781@qq.com)
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2022/01/16
|
||||||
|
* @mainpage github.com/NanjingForestryUniversity
|
||||||
|
*
|
||||||
|
* @copyright Copyright (c) 2022 miaow
|
||||||
|
*
|
||||||
|
* @par Changelog:
|
||||||
|
* <table>
|
||||||
|
* <tr><th>Date <th>Version <th>Author <th>Description
|
||||||
|
* <tr><td>2022/01/16 <td>1.0 <td>miaow <td>Write this file
|
||||||
|
* </table>
|
||||||
|
*/
|
||||||
|
#include <host_computer.h>
|
||||||
|
#include <sys/socket.h>
|
||||||
|
#include <netinet/in.h>
|
||||||
|
#include <arpa/inet.h>
|
||||||
|
#include <netinet/tcp.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <pthread.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <unistd.h>
|
||||||
|
#include <fcntl.h>
|
||||||
|
#include <fifo_dev.h>
|
||||||
|
#include <encoder_dev.h>
|
||||||
|
|
||||||
|
#define HOST_COMPUTER_PICTURE_COLUMN_BYTES (HOST_COMPUTER_PICTURE_COLUMN_NUM / 8)
|
||||||
|
#define HOST_COMPUTER_RAW_DATA_BYTES (HOST_COMPUTER_PICTURE_COLUMN_BYTES * HOST_COMPUTER_PICTURE_ROW_NUM)
|
||||||
|
|
||||||
|
static char perror_buffer[128];
|
||||||
|
/**
|
||||||
|
* @brief Queue handle structure
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
queue_uint64_msg_t *cmd_q; // A pointer to the queue for commands
|
||||||
|
int socket_fd; // The socket fd for receiving commands and data
|
||||||
|
int need_exit; // The flag variable to indicate whether to exit the loop_thread in this file
|
||||||
|
pthread_t loop_thread; // The main routine of this module, which parses commands and data from host, puts them into the queue
|
||||||
|
pthread_mutex_t loop_thread_mutex; // The mutex for loop_thread
|
||||||
|
} hostcomputer_t;
|
||||||
|
|
||||||
|
static hostcomputer_t _global_structure;
|
||||||
|
void *loop_thread_func(void *param);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Pre initialize host computer module
|
||||||
|
* @param data_q A pointer to the queue storing the valve data from host computer
|
||||||
|
* @param cmd_q A pointer to the queue storing the cmd from host computer
|
||||||
|
* @return 0 - success
|
||||||
|
*/
|
||||||
|
int hostcomputer_init(queue_uint64_msg_t *cmd_q)
|
||||||
|
{
|
||||||
|
_global_structure.cmd_q = cmd_q;
|
||||||
|
|
||||||
|
pthread_mutex_init(&_global_structure.loop_thread_mutex, NULL);
|
||||||
|
pthread_create(&_global_structure.loop_thread, NULL, loop_thread_func, NULL);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Receive `size` bytes from a socket. If no more bytes are available at the socket, this function return -1 when timeout reaches.
|
||||||
|
* @param fd The socket fd
|
||||||
|
* @param buf Received bytes
|
||||||
|
* @param size Number of bytes to receive
|
||||||
|
* @return These calls return the number of bytes received, or -1 if time out occurred
|
||||||
|
*/
|
||||||
|
static int recvn(int fd, char *buf, int size)
|
||||||
|
{
|
||||||
|
char *pt = buf;
|
||||||
|
int count = size;
|
||||||
|
while (count > 0)
|
||||||
|
{
|
||||||
|
int len = recv(fd, pt, count, 0);
|
||||||
|
// if (len == -1 && (errno == EAGAIN || errno == EWOULDBLOCK))
|
||||||
|
// {
|
||||||
|
// // printf("recv timeout\r\n");
|
||||||
|
// }
|
||||||
|
if (len == -1)
|
||||||
|
return -1;
|
||||||
|
else if (len == 0)
|
||||||
|
return size - count;
|
||||||
|
pt += len;
|
||||||
|
count -= len;
|
||||||
|
}
|
||||||
|
return size;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To inspect the status of TCP connection
|
||||||
|
* @param sock_fd The socket
|
||||||
|
* @return 0 - Not connected, 1 - connected
|
||||||
|
*/
|
||||||
|
static int is_connected(int sock_fd)
|
||||||
|
{
|
||||||
|
struct tcp_info info;
|
||||||
|
int len = sizeof(info);
|
||||||
|
getsockopt(sock_fd, IPPROTO_TCP, TCP_INFO, &info, (socklen_t *)&len);
|
||||||
|
return info.tcpi_state == TCP_ESTABLISHED;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function runs in child thread and handles communication with host computer
|
||||||
|
* @param param NULL
|
||||||
|
* @return NULL
|
||||||
|
*/
|
||||||
|
void *loop_thread_func(void *param)
|
||||||
|
{
|
||||||
|
printf("loop thread in %s start\r\n", __FILE__);
|
||||||
|
int need_exit = 0;
|
||||||
|
char pre;
|
||||||
|
uint16_t n_bytes;
|
||||||
|
char type[2];
|
||||||
|
char data[HOST_COMPUTER_RAW_DATA_BYTES + 1];
|
||||||
|
char check[2];
|
||||||
|
while (!need_exit)
|
||||||
|
{
|
||||||
|
pthread_mutex_lock(&_global_structure.loop_thread_mutex);
|
||||||
|
need_exit = _global_structure.need_exit;
|
||||||
|
pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
|
||||||
|
// reconnect if not connected
|
||||||
|
if (!is_connected(_global_structure.socket_fd))
|
||||||
|
{
|
||||||
|
_global_structure.socket_fd = socket(AF_INET, SOCK_STREAM, 0);
|
||||||
|
struct timeval timeout = {.tv_sec = 10, .tv_usec = 0};
|
||||||
|
setsockopt(_global_structure.socket_fd, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout));
|
||||||
|
ON_ERROR_RET(_global_structure.socket_fd, "hostcomputer_init", "", NULL);
|
||||||
|
struct sockaddr_in serAddr;
|
||||||
|
serAddr.sin_family = AF_INET;
|
||||||
|
// serAddr.sin_addr.s_addr = inet_addr(HOST_COMPUTER_IP);
|
||||||
|
inet_pton(AF_INET, HOST_COMPUTER_IP, &serAddr.sin_addr);
|
||||||
|
serAddr.sin_port = htons(HOST_COMPUTER_PORT);
|
||||||
|
printf("Connecting host computer...");
|
||||||
|
fflush(stdout);
|
||||||
|
if (connect(_global_structure.socket_fd, (struct sockaddr *)&serAddr, sizeof(struct sockaddr_in)) == -1)
|
||||||
|
{
|
||||||
|
sleep(2);
|
||||||
|
close(_global_structure.socket_fd);
|
||||||
|
printf("FAILED\r\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
printf("OK\r\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
// =======================parse the protocol=========================================
|
||||||
|
|
||||||
|
if (recvn(_global_structure.socket_fd, (char *)&pre, 1) > 1)
|
||||||
|
{
|
||||||
|
// close(_global_structure.socket_fd);
|
||||||
|
printf("pre_len!=1\r\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (pre != 0xAA)
|
||||||
|
{
|
||||||
|
// close(_global_structure.socket_fd);
|
||||||
|
// printf("%X ", (int)pre);
|
||||||
|
// fflush(stdout);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (recvn(_global_structure.socket_fd, (char *)&n_bytes, 2) != 2)
|
||||||
|
{
|
||||||
|
// close(_global_structure.socket_fd);
|
||||||
|
printf("n_bytes_len!=2\r\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
n_bytes = ntohs(n_bytes);
|
||||||
|
if (n_bytes != HOST_COMPUTER_RAW_DATA_BYTES + 2 && n_bytes > 10)
|
||||||
|
{
|
||||||
|
// close(_global_structure.socket_fd);
|
||||||
|
printf("n_bytes> 10 and n_bytes!=HOST_COMPUTER_RAW_DATA_BYTES + 2\r\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (recvn(_global_structure.socket_fd, (char *)type, 2) != 2)
|
||||||
|
{
|
||||||
|
// close(_global_structure.socket_fd);
|
||||||
|
printf("type!=2\r\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (recvn(_global_structure.socket_fd, (char *)data, n_bytes - 2) != n_bytes - 2)
|
||||||
|
{
|
||||||
|
// close(_global_structure.socket_fd);
|
||||||
|
printf("data_len!=n_bytes-2\r\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
data[n_bytes - 2] = 0;
|
||||||
|
if (recvn(_global_structure.socket_fd, (char *)check, 2) != 2)
|
||||||
|
{
|
||||||
|
// close(_global_structure.socket_fd);
|
||||||
|
printf("check_len!=2\r\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (recvn(_global_structure.socket_fd, (char *)&pre, 1) != 1)
|
||||||
|
{
|
||||||
|
// close(_global_structure.socket_fd);
|
||||||
|
printf("end_len!=1\r\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (pre != 0xBB)
|
||||||
|
{
|
||||||
|
// close(_global_structure.socket_fd);
|
||||||
|
printf("end!=0xBB\r\n");
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
// =======================parse the commands=========================================
|
||||||
|
// commands are reformed as an uint64_t, 0x--------xxxxxxxx, where `-` refers its paramter and `x` is HOSTCOMPUTER_CMD
|
||||||
|
if (type[0] == 'd' && type[1] == 'a')
|
||||||
|
{
|
||||||
|
// printf("%dbytes of data put to data queue\r\n", (int)n_bytes - 2);
|
||||||
|
if (n_bytes - 2 != HOST_COMPUTER_RAW_DATA_BYTES)
|
||||||
|
{
|
||||||
|
printf("n_bytes-2!=%d\r\n", HOST_COMPUTER_RAW_DATA_BYTES);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
fifo_dev_write_frame(data);
|
||||||
|
}
|
||||||
|
else if (type[0] == 's' && type[1] == 't')
|
||||||
|
{
|
||||||
|
// printf("Start put to cmd queue, param:%d\r\n", (int)atoll(data));
|
||||||
|
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_START);
|
||||||
|
}
|
||||||
|
else if (type[0] == 's' && type[1] == 'p')
|
||||||
|
{
|
||||||
|
// printf("Stop put to cmd queue, param:%d\r\n", (int)atoll(data));
|
||||||
|
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_STOP);
|
||||||
|
}
|
||||||
|
else if (type[0] == 't' && type[1] == 'e')
|
||||||
|
{
|
||||||
|
// printf("Test put to cmd queue, param:%d\r\n", (int)atoll(data));
|
||||||
|
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_TEST);
|
||||||
|
}
|
||||||
|
else if (type[0] == 't' && type[1] == 't')
|
||||||
|
{
|
||||||
|
// printf("Test put to cmd queue, param:%d\r\n", (int)atoll(data));
|
||||||
|
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_STOP_TEST);
|
||||||
|
}
|
||||||
|
else if (type[0] == 'p' && type[1] == 'o')
|
||||||
|
{
|
||||||
|
// printf("Power on put to cmd queue, param:%d\r\n", (int)atoll(data));
|
||||||
|
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_POWERON);
|
||||||
|
}
|
||||||
|
else if (type[0] == 's' && type[1] == 'c')
|
||||||
|
{
|
||||||
|
// printf("Set camera triggle pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
|
||||||
|
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT);
|
||||||
|
}
|
||||||
|
else if (type[0] == 's' && type[1] == 'v')
|
||||||
|
{
|
||||||
|
// printf("Set valve pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
|
||||||
|
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETVALVETRIGPULSECOUNT);
|
||||||
|
}
|
||||||
|
else if (type[0] == 's' && type[1] == 'd')
|
||||||
|
{
|
||||||
|
// printf("Set camera to valve pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
|
||||||
|
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETCAMERATOVALVEPULSECOUNT);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
printf("Unknown command received");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
printf("loop thread in %s exit\r\n", __FILE__);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitialize and release resources used by host computer module
|
||||||
|
* @return int
|
||||||
|
*/
|
||||||
|
int hostcomputer_deinit()
|
||||||
|
{
|
||||||
|
pthread_mutex_lock(&_global_structure.loop_thread_mutex);
|
||||||
|
_global_structure.need_exit = 1;
|
||||||
|
pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
|
||||||
|
pthread_join(_global_structure.loop_thread, NULL);
|
||||||
|
pthread_mutex_destroy(&_global_structure.loop_thread_mutex);
|
||||||
|
|
||||||
|
close(_global_structure.socket_fd);
|
||||||
|
_global_structure.socket_fd = 0;
|
||||||
|
_global_structure.need_exit = 0;
|
||||||
|
_global_structure.cmd_q = NULL;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
47
source/linux_app/host_computer.h
Normal file
47
source/linux_app/host_computer.h
Normal file
@ -0,0 +1,47 @@
|
|||||||
|
/**
|
||||||
|
* @file host_computer.h
|
||||||
|
* @brief Commnunicate with host computer. Protocal is described in hostcomputer通信协议.md
|
||||||
|
* @author miaow (3703781@qq.com)
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2022/01/16
|
||||||
|
*
|
||||||
|
* @copyright Copyright (c) 2022 miaow
|
||||||
|
*
|
||||||
|
* @par Changelog:
|
||||||
|
* <table>
|
||||||
|
* <tr><th>Date <th>Version <th>Author <th>Description
|
||||||
|
* <tr><td>2022/01/16 <td>1.0 <td>miaow <td>Write this file
|
||||||
|
* </table>
|
||||||
|
*/
|
||||||
|
#ifndef __HOST_COMPUTER_H
|
||||||
|
#define __HOST_COMPUTER_H
|
||||||
|
|
||||||
|
#include <queue_uint64.h>
|
||||||
|
#include <pthread.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#define HOST_COMPUTER_IP "192.168.10.8"
|
||||||
|
#define HOST_COMPUTER_PORT 13452
|
||||||
|
#define HOST_COMPUTER_PICTURE_ROW_NUM 600
|
||||||
|
#define HOST_COMPUTER_PICTURE_COLUMN_NUM 256
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief The commonds, ref hostcomputer通信协议 v1.1.md
|
||||||
|
*/
|
||||||
|
enum HOSTCOMPUTER_CMD
|
||||||
|
{
|
||||||
|
HOSTCOMPUTER_CMD_START = 2,
|
||||||
|
HOSTCOMPUTER_CMD_STOP = 3,
|
||||||
|
HOSTCOMPUTER_CMD_TEST = 4,
|
||||||
|
HOSTCOMPUTER_CMD_POWERON = 5,
|
||||||
|
HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT = 6,
|
||||||
|
HOSTCOMPUTER_CMD_SETVALVETRIGPULSECOUNT = 7,
|
||||||
|
HOSTCOMPUTER_CMD_SETCAMERATOVALVEPULSECOUNT = 8,
|
||||||
|
HOSTCOMPUTER_CMD_STOP_TEST = 9
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
int hostcomputer_init(queue_uint64_msg_t *cmd_q);
|
||||||
|
int hostcomputer_deinit(void);
|
||||||
|
|
||||||
|
#endif
|
||||||
180
source/linux_app/main.c
Normal file
180
source/linux_app/main.c
Normal file
@ -0,0 +1,180 @@
|
|||||||
|
/**
|
||||||
|
* @file main.c
|
||||||
|
* @brief Excute the commands from host_computer
|
||||||
|
* @author miaow (3703781@qq.com)
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2022/06/12
|
||||||
|
* @mainpage github.com/NanjingForestryUniversity
|
||||||
|
*
|
||||||
|
* @copyright Copyright (c) 2022 miaow
|
||||||
|
*
|
||||||
|
* @par Changelog:
|
||||||
|
* <table>
|
||||||
|
* <tr><th>Date <th>Version <th>Author <th>Description
|
||||||
|
* <tr><td>2022/06/12 <td>1.0 <td>miaow <td>Write this file
|
||||||
|
* </table>
|
||||||
|
*/
|
||||||
|
#include <fifo_dev.h>
|
||||||
|
#include <sys/socket.h>
|
||||||
|
#include <arpa/inet.h>
|
||||||
|
#include <math.h>
|
||||||
|
#include <queue_uint64.h>
|
||||||
|
#include <encoder_dev.h>
|
||||||
|
#include <host_computer.h>
|
||||||
|
#include <memory.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <unistd.h>
|
||||||
|
|
||||||
|
#define SET_VALVE_ONLY_N_ON(u32_buf, n) bzero(u32_buf, sizeof(u32_buf));SET_VALVE_N_ON(u32_buf, n)
|
||||||
|
#define SET_VALVE_N_ON(u32_buf, n) u32_buf[n / 32] = 1 << (n % 32)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Value of state machine
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
SLEEPING = 0,
|
||||||
|
RUNNING = 1,
|
||||||
|
} status_enum_t;
|
||||||
|
|
||||||
|
queue_uint64_msg_t cmd_queue = {0};
|
||||||
|
|
||||||
|
static status_enum_t status = SLEEPING;
|
||||||
|
static int camera_trigger_pulse_count = 1200;
|
||||||
|
static int valve_trigger_pulse_count = 120;
|
||||||
|
static int camera_to_valve_pulse_count = 5000;
|
||||||
|
|
||||||
|
void process_cmd(uint64_t *cmd);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read from the cmd_queue and excute the command every 100ms.
|
||||||
|
* @param argc not used
|
||||||
|
* @param argv not used
|
||||||
|
* @return int should not return.
|
||||||
|
*/
|
||||||
|
int main(int argc, char *argv[])
|
||||||
|
{
|
||||||
|
queue_uint64_init(&cmd_queue, 9999);
|
||||||
|
|
||||||
|
// Initialize drivers and clear all caches
|
||||||
|
encoder_dev_init();
|
||||||
|
encoder_dev_set_trigmod(ENCODER_TRIG_MODE_INTERNEL);
|
||||||
|
encoder_dev_set_divide(2, 2);
|
||||||
|
fifo_dev_init();
|
||||||
|
hostcomputer_init(&cmd_queue);
|
||||||
|
printf("\r\n>>>>>\r\nstatus==SLEEPING\r\n<<<<<\r\n\r\n");
|
||||||
|
uint64_t cmd;
|
||||||
|
int TRUE = 1;
|
||||||
|
// Read from the cmd_queue and excute the command every 100ms
|
||||||
|
while (TRUE)
|
||||||
|
{
|
||||||
|
if (queue_uint64_get(&cmd_queue, &cmd) == 0)
|
||||||
|
process_cmd(&cmd);
|
||||||
|
usleep(100000);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Never run here
|
||||||
|
hostcomputer_deinit();
|
||||||
|
fifo_dev_clear();
|
||||||
|
encoder_dev_set_divide(2, 2);
|
||||||
|
encoder_dev_virtual_trig(10);
|
||||||
|
|
||||||
|
fifo_dev_deinit();
|
||||||
|
encoder_dev_set_trigmod(ENCODER_TRIG_MODE_INTERNEL);
|
||||||
|
encoder_dev_deinit();
|
||||||
|
queue_uint64_deinit(&cmd_queue);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Excute the command and control the states
|
||||||
|
* @param cmd The command to be excuted
|
||||||
|
*/
|
||||||
|
void process_cmd(uint64_t *cmd)
|
||||||
|
{
|
||||||
|
int tmp_cmd = (int)*cmd;
|
||||||
|
int tmp_data = (int)(*cmd >> 32);
|
||||||
|
|
||||||
|
// Only in the SLEEPING state, it resbonds to START or TEST command.
|
||||||
|
if (status == SLEEPING)
|
||||||
|
{
|
||||||
|
if (tmp_cmd == HOSTCOMPUTER_CMD_START)
|
||||||
|
{
|
||||||
|
// Before running, clear the hardware fifo and hardware encoder. Then, the two dividers and delay value should be set.
|
||||||
|
// Also, the hareware encoder is expected to receiving pluse of encoder: the EXTERNAL mode
|
||||||
|
fifo_dev_clear();
|
||||||
|
fifo_dev_write_delay(camera_to_valve_pulse_count);
|
||||||
|
encoder_dev_flush();
|
||||||
|
encoder_dev_set_divide(valve_trigger_pulse_count, camera_trigger_pulse_count);
|
||||||
|
encoder_dev_set_trigmod(ENCODER_TRIG_MODE_EXTERNEL);
|
||||||
|
printf("\r\n>>>>>\r\nstatus==RUNNING\r\ncamera_trigger_pulse_count=%d\r\nvalve_trigger_pulse_count=%d\r\ncamera_to_valve_pulse_count=%d\r\n<<<<<\r\n\r\n", camera_trigger_pulse_count, valve_trigger_pulse_count, camera_to_valve_pulse_count);
|
||||||
|
status = RUNNING;
|
||||||
|
}
|
||||||
|
else if (tmp_cmd == HOSTCOMPUTER_CMD_TEST)
|
||||||
|
{
|
||||||
|
uint32_t row_data[8] = {0};
|
||||||
|
// When to excute TEST cmd (aka testing the valve), hardware fifo and hardware encoder should be cleared.
|
||||||
|
// A new combination of divider is set: 2 for both valve and camera, for less virtual pluse is needed to triggle valve in INTERNAL mode.
|
||||||
|
// Note that camera can be triggled during testing.
|
||||||
|
fifo_dev_clear();
|
||||||
|
encoder_dev_flush();
|
||||||
|
encoder_dev_set_trigmod(ENCODER_TRIG_MODE_INTERNEL);
|
||||||
|
encoder_dev_set_divide(2, 2);
|
||||||
|
|
||||||
|
// A parameter below 256 represents a single shot, the value of parameter indicates the valve to triggle.
|
||||||
|
if (tmp_data < 256)
|
||||||
|
{
|
||||||
|
SET_VALVE_ONLY_N_ON(row_data, tmp_data);
|
||||||
|
fifo_dev_write_row(row_data);
|
||||||
|
// delay for 100 ms and turn off the valve
|
||||||
|
encoder_dev_virtual_trig(2);
|
||||||
|
usleep(100000);
|
||||||
|
encoder_dev_virtual_trig(2);
|
||||||
|
}
|
||||||
|
// 257 represents triggle valve from NO.1 to 256 sequenctially. This loop blocks for 25.7s.
|
||||||
|
else if (tmp_data == 257)
|
||||||
|
{
|
||||||
|
for (int i = 0; i < 256; i++)
|
||||||
|
{
|
||||||
|
SET_VALVE_ONLY_N_ON(row_data, i);
|
||||||
|
fifo_dev_write_row(row_data);
|
||||||
|
}
|
||||||
|
for (int i = 0; i < 257; i++)
|
||||||
|
{
|
||||||
|
encoder_dev_virtual_trig(2);
|
||||||
|
usleep(100000);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if (tmp_cmd == HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT)
|
||||||
|
{
|
||||||
|
camera_trigger_pulse_count = tmp_data;
|
||||||
|
}
|
||||||
|
else if (tmp_cmd == HOSTCOMPUTER_CMD_SETVALVETRIGPULSECOUNT)
|
||||||
|
{
|
||||||
|
valve_trigger_pulse_count = tmp_data;
|
||||||
|
}
|
||||||
|
else if (tmp_cmd == HOSTCOMPUTER_CMD_SETCAMERATOVALVEPULSECOUNT)
|
||||||
|
{
|
||||||
|
camera_to_valve_pulse_count = tmp_data;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
// Only in RUNNING state, the lower machine responds to STOP command.
|
||||||
|
else if (status == RUNNING)
|
||||||
|
{
|
||||||
|
if (tmp_cmd == HOSTCOMPUTER_CMD_STOP)
|
||||||
|
{
|
||||||
|
// Clear hardware fifo.
|
||||||
|
// 10 virtual triggles in internal mode ensure valve is turned off.
|
||||||
|
// Hardware encoder is flushed for a fresh start.
|
||||||
|
fifo_dev_clear();
|
||||||
|
encoder_dev_set_trigmod(ENCODER_TRIG_MODE_INTERNEL);
|
||||||
|
encoder_dev_set_divide(2, 2);
|
||||||
|
encoder_dev_virtual_trig(10);
|
||||||
|
encoder_dev_flush();
|
||||||
|
status = SLEEPING;
|
||||||
|
printf("\r\n>>>>>\r\nstatus==SLEEPING\r\n<<<<<\r\n\r\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
196
source/linux_app/queue_uint64.c
Normal file
196
source/linux_app/queue_uint64.c
Normal file
@ -0,0 +1,196 @@
|
|||||||
|
|
||||||
|
/**
|
||||||
|
* @file queue_uint64.c
|
||||||
|
* @brief Thread safe queue, which stores uint64_t
|
||||||
|
* @details Call queue_init(queue_uint64_msg_t *q, int max_count) paired with queue_deinit(queue_uint64_msg_t *q) as their names imply, queue_initstruct(queue_uint64_msg_t *q)Initialize the message queue structure,*queue_get(queue_uint64_msg_t *q) and queue_put(queue_uint64_msg_t *q, void *data) In and out of the team operation
|
||||||
|
* @author miaow (3703781@qq.com)
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2021/01/10
|
||||||
|
* @mainpage github.com/NanjingForestryUniversity
|
||||||
|
*
|
||||||
|
* @copyright Copyright (c) 2022 miaow
|
||||||
|
*
|
||||||
|
* @par Changelog:
|
||||||
|
* <table>
|
||||||
|
* <tr><th>Date <th>Version <th>Author <th>Description
|
||||||
|
* <tr><td>2022/01/09 <td>1.0 <td>miaow <td>Write this file
|
||||||
|
* </table>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <pthread.h>
|
||||||
|
#include <queue_uint64.h>
|
||||||
|
#ifdef QUEUE_UINT64_DEBUG
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#endif
|
||||||
|
#include <stdlib.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Take out the first item from the circular queue
|
||||||
|
* @param q The queue handler
|
||||||
|
* @param data A buffer of uint64_t[1] to store the data taken out
|
||||||
|
* @return 0 - success, -1 - failed
|
||||||
|
*/
|
||||||
|
int queue_uint64_get(queue_uint64_msg_t *q, uint64_t *data)
|
||||||
|
{
|
||||||
|
pthread_mutex_lock(&q->_mux);
|
||||||
|
// while (q->lget == q->lput && 0 == q->nData)
|
||||||
|
// {
|
||||||
|
// // The reason program goes here: assuming there are 2 consmer threads block in this function
|
||||||
|
// // One wakes first and consumes 2 data quickly before another wakes
|
||||||
|
// // In the circumstances that the queue contains 2 items formerly, the second thread should not get data from an empty queue
|
||||||
|
// // This may happen when 2 queue_puts was called by producers and at that moment 2 consmer threads have been blocked
|
||||||
|
|
||||||
|
// // It is designed as a circular queue, where lget==lput means:
|
||||||
|
// // 1：nData!=0，a full queue
|
||||||
|
// // 2：nData为0，an empty queue
|
||||||
|
// q->nEmptyThread++;
|
||||||
|
// pthread_cond_wait(&q->_cond_get, &q->_mux);
|
||||||
|
// q->nEmptyThread--;
|
||||||
|
// }
|
||||||
|
if (q->nData == 0)
|
||||||
|
{
|
||||||
|
pthread_mutex_unlock(&q->_mux);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
#ifdef QUEUE_UINT64_DEBUG
|
||||||
|
printf("get data! lget:%d, ", q->lget);
|
||||||
|
#endif
|
||||||
|
*data = (q->buffer)[q->lget++];
|
||||||
|
#ifdef QUEUE_UINT64_DEBUG
|
||||||
|
printf("data:% lld", *data);
|
||||||
|
#endif
|
||||||
|
if (q->lget == q->size)
|
||||||
|
{
|
||||||
|
// this is a circular queue
|
||||||
|
q->lget = 0;
|
||||||
|
}
|
||||||
|
q->nData--;
|
||||||
|
#ifdef QUEUE_UINT64_DEBUG
|
||||||
|
printf(", nData:%d\r\n", q->nData);
|
||||||
|
#endif
|
||||||
|
// if (q->nFullThread)
|
||||||
|
// {
|
||||||
|
// // call pthread_cond_signal only when necessary, enter the kernel state as little as possible
|
||||||
|
// pthread_cond_signal(&q->_cond_put);
|
||||||
|
// }
|
||||||
|
pthread_mutex_unlock(&q->_mux);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the queue with a size (maximum count of items) specified in q->size
|
||||||
|
* @param q The queue hander to be initialized
|
||||||
|
* @return 0 - success, -1 - failed
|
||||||
|
* @note q->size should be set before calling this function
|
||||||
|
*/
|
||||||
|
int queue_uint64_initstruct(queue_uint64_msg_t *q)
|
||||||
|
{
|
||||||
|
q->buffer = malloc(q->size * sizeof(uint64_t));
|
||||||
|
if (q->buffer == NULL)
|
||||||
|
return -1;
|
||||||
|
pthread_mutex_init(&q->_mux, NULL);
|
||||||
|
// pthread_cond_init(&q->_cond_get, NULL);
|
||||||
|
// pthread_cond_init(&q->_cond_put, NULL);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the queue
|
||||||
|
* @param q The queue hander to be initialized
|
||||||
|
* @param max_count Maximum count of items in the queue
|
||||||
|
* @return 0 - success, -1 - failed
|
||||||
|
*/
|
||||||
|
int queue_uint64_init(queue_uint64_msg_t *q, int max_count)
|
||||||
|
{
|
||||||
|
q->size = max_count;
|
||||||
|
return queue_uint64_initstruct(q);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitialize the queue
|
||||||
|
* @param q The queue handle
|
||||||
|
* @return 0 - success
|
||||||
|
*/
|
||||||
|
int queue_uint64_deinit(queue_uint64_msg_t *q)
|
||||||
|
{
|
||||||
|
free(q->buffer);
|
||||||
|
q->buffer = NULL;
|
||||||
|
pthread_mutex_destroy(&q->_mux);
|
||||||
|
// pthread_cond_destroy(&q->_cond_get);
|
||||||
|
// pthread_cond_destroy(&q->_cond_put);
|
||||||
|
q->size = 0;
|
||||||
|
q->nData = 0;
|
||||||
|
q->lget = 0;
|
||||||
|
q->lput = 0;
|
||||||
|
// q->nEmptyThread = 0;
|
||||||
|
// q->nFullThread = 0;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Put one item into the circular queue
|
||||||
|
* @param q The queue handle
|
||||||
|
* @param data The item to put
|
||||||
|
* @return 0 - success, -1 - failed
|
||||||
|
*/
|
||||||
|
int queue_uint64_put(queue_uint64_msg_t *q, uint64_t data)
|
||||||
|
{
|
||||||
|
pthread_mutex_lock(&q->_mux);
|
||||||
|
// while (q->lget == q->lput && q->nData)
|
||||||
|
// {
|
||||||
|
// q->nFullThread++;
|
||||||
|
// pthread_cond_wait(&q->_cond_put, &q->_mux);
|
||||||
|
// q->nFullThread--;
|
||||||
|
// }
|
||||||
|
if (q->lget == q->lput && q->nData)
|
||||||
|
{
|
||||||
|
pthread_mutex_unlock(&q->_mux);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
#ifdef QUEUE_UINT64_DEBUG
|
||||||
|
printf("put data! lput:%d, data:%lld", q->lput, data);
|
||||||
|
#endif
|
||||||
|
(q->buffer)[q->lput++] = data;
|
||||||
|
if (q->lput == q->size)
|
||||||
|
{
|
||||||
|
q->lput = 0;
|
||||||
|
}
|
||||||
|
q->nData++;
|
||||||
|
#ifdef QUEUE_UINT64_DEBUG
|
||||||
|
printf(" nData:%d\n", q->nData);
|
||||||
|
#endif
|
||||||
|
// if (q->nEmptyThread)
|
||||||
|
// {
|
||||||
|
// pthread_cond_signal(&q->_cond_get);
|
||||||
|
// }
|
||||||
|
pthread_mutex_unlock(&q->_mux);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the circular queue
|
||||||
|
* @param q The queue handle
|
||||||
|
* @return 0 - success, -1 - failed
|
||||||
|
*/
|
||||||
|
int queue_uint64_clear(queue_uint64_msg_t *q)
|
||||||
|
{
|
||||||
|
pthread_mutex_lock(&q->_mux);
|
||||||
|
// while (q->lget == q->lput && q->nData)
|
||||||
|
// {
|
||||||
|
// q->nFullThread++;
|
||||||
|
// pthread_cond_wait(&q->_cond_put, &q->_mux);
|
||||||
|
// q->nFullThread--;
|
||||||
|
// }
|
||||||
|
q->lget = q->lput = q->nData = 0;
|
||||||
|
#ifdef QUEUE_UINT64_DEBUG
|
||||||
|
printf("clear!\r\n");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// if (q->nEmptyThread)
|
||||||
|
// {
|
||||||
|
// pthread_cond_signal(&q->_cond_get);
|
||||||
|
// }
|
||||||
|
pthread_mutex_unlock(&q->_mux);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
49
source/linux_app/queue_uint64.h
Normal file
49
source/linux_app/queue_uint64.h
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
/**
|
||||||
|
* @file queue_uint64.h
|
||||||
|
* @brief Thread safe queue, which stores uint64_t
|
||||||
|
* @details Call queue_init(queue_uint64_msg_t *q, int max_count) paired with queue_deinit(queue_uint64_msg_t *q) as their names imply, queue_initstruct(queue_uint64_msg_t *q)Initialize the message queue structure,*queue_get(queue_uint64_msg_t *q) and queue_put(queue_uint64_msg_t *q, void *data) In and out of the team operation
|
||||||
|
* @author miaow (3703781@qq.com)
|
||||||
|
* @version 1.0
|
||||||
|
* @date 2021/01/10
|
||||||
|
* @mainpage github.com/NanjingForestryUniversity
|
||||||
|
*
|
||||||
|
* @copyright Copyright (c) 2022 miaow
|
||||||
|
*
|
||||||
|
* @par Changelog:
|
||||||
|
* <table>
|
||||||
|
* <tr><th>Date <th>Version <th>Author <th>Description
|
||||||
|
* <tr><td>2022/01/09 <td>1.0 <td>miaow <td>Write this file
|
||||||
|
* </table>
|
||||||
|
*/
|
||||||
|
#if !defined(__QUEUE_UINT64_H)
|
||||||
|
#define __QUEUE_UINT64_H
|
||||||
|
|
||||||
|
#include <pthread.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Queue handle structure
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint64_t *buffer; // 缓冲数据, .buffer = msg
|
||||||
|
int size; // 队列大小，使用的时候给出稍大的size，可以减少进入内核态的操作
|
||||||
|
int lget; // 取队列数据的偏移量
|
||||||
|
int lput; // 放队列数据的偏移量
|
||||||
|
int nData; // 队列中数据的个数,用来判断队列满/空
|
||||||
|
// int nFullThread; // 由于队列满而阻塞在put_queue的线程个数
|
||||||
|
// int nEmptyThread; // 由于队列空而阻塞在get_queue的线程个数
|
||||||
|
pthread_mutex_t _mux;
|
||||||
|
// pthread_cond_t _cond_get, _cond_put;
|
||||||
|
} queue_uint64_msg_t;
|
||||||
|
|
||||||
|
// #define QUEUE_UINT64_DEBUG
|
||||||
|
|
||||||
|
int queue_uint64_get(queue_uint64_msg_t *q, uint64_t *data);
|
||||||
|
int queue_uint64_put(queue_uint64_msg_t *q, uint64_t data);
|
||||||
|
int queue_uint64_initstruct(queue_uint64_msg_t *q);
|
||||||
|
int queue_uint64_init(queue_uint64_msg_t *q, int max_count);
|
||||||
|
int queue_uint64_clear(queue_uint64_msg_t *q);
|
||||||
|
int queue_uint64_deinit(queue_uint64_msg_t *q);
|
||||||
|
|
||||||
|
#endif // __QUEUE_UINT64_H
|
||||||
277
source/linux_driver/encoder.c
Normal file
277
source/linux_driver/encoder.c
Normal file
@ -0,0 +1,277 @@
|
|||||||
|
#include <linux/types.h>
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/errno.h>
|
||||||
|
#include <linux/gpio.h>
|
||||||
|
#include <asm/mach/map.h>
|
||||||
|
#include <asm/uaccess.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <linux/cdev.h>
|
||||||
|
|
||||||
|
#define ENCODER_CNT 1 /* 主设备号 */
|
||||||
|
#define ENCODER_NAME "encoder" /* 设备名字 */
|
||||||
|
|
||||||
|
#define ENCODER_CMD_FUNCTION_CLEAR 1
|
||||||
|
#define ENCODER_CMD_FUNCTION_VIRT_INPUT 2
|
||||||
|
|
||||||
|
#define ENCODER_CMD_INPUT_MODE_EXTERNEL 100
|
||||||
|
#define ENCODER_CMD_INPUT_MODE_INTERNEL 101
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 相关寄存器地址定义
|
||||||
|
*/
|
||||||
|
#define ENCODER_REG_BASE 0x43C10000
|
||||||
|
#define ENCODER_REG_0_OFFSET 0x00000000
|
||||||
|
#define ENCODER_REG_1_OFFSET 0x00000004
|
||||||
|
#define ENCODER_REG_2_OFFSET 0x00000008
|
||||||
|
#define ENCODER_REG_3_OFFSET 0x0000000C
|
||||||
|
|
||||||
|
/* 映射后的寄存器虚拟地址指针 */
|
||||||
|
static void __iomem *encoder_reg_0_addr;
|
||||||
|
static void __iomem *encoder_reg_1_addr;
|
||||||
|
static void __iomem *encoder_reg_2_addr;
|
||||||
|
static void __iomem *encoder_reg_3_addr;
|
||||||
|
|
||||||
|
struct encoder_dev
|
||||||
|
{
|
||||||
|
dev_t devid; /* 设备号 */
|
||||||
|
struct cdev cdev; /* cdev */
|
||||||
|
struct class *class; /* 类 */
|
||||||
|
struct device *device; /* 设备 */
|
||||||
|
int major; /* 主设备号 */
|
||||||
|
int minor; /* 次设备号 */
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
u32 valve_divide_value;
|
||||||
|
u32 camera_divide_value;
|
||||||
|
} kernelbuf_typedef;
|
||||||
|
|
||||||
|
static struct encoder_dev encoder;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* @description : 打开设备
|
||||||
|
* @param – inode : 传递给驱动的inode
|
||||||
|
* @param - filp : 设备文件，file结构体有个叫做private_data的成员变量
|
||||||
|
* 一般在open的时候将private_data指向设备结构体。
|
||||||
|
* @return : 0 成功;其他 失败
|
||||||
|
*/
|
||||||
|
static int encoder_open(struct inode *inode, struct file *filp)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* @description : 向设备写数据
|
||||||
|
* @param - filp : 设备文件，表示打开的文件描述符
|
||||||
|
* @param - buf : 要写给设备写入的数据
|
||||||
|
* @param - cnt : 要写入的数据长度
|
||||||
|
* @param - offt : 相对于文件首地址的偏移
|
||||||
|
* @return : 写入的字节数，如果为负值，表示写入失败
|
||||||
|
*/
|
||||||
|
static ssize_t encoder_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
u32 data;
|
||||||
|
kernelbuf_typedef kern_buf = {
|
||||||
|
.valve_divide_value = 0,
|
||||||
|
.camera_divide_value = 0,
|
||||||
|
};
|
||||||
|
if (cnt != sizeof(kern_buf))
|
||||||
|
{
|
||||||
|
printk(KERN_ERR "encoder write: cnt error, cnt=%d", cnt);
|
||||||
|
return -EFAULT;
|
||||||
|
}
|
||||||
|
ret = copy_from_user(&kern_buf, buf, cnt); // 得到应用层传递过来的数据
|
||||||
|
if (ret < 0)
|
||||||
|
{
|
||||||
|
printk(KERN_ERR "kernel write failed!\r\n");
|
||||||
|
return -EFAULT;
|
||||||
|
}
|
||||||
|
if (!(kern_buf.valve_divide_value || kern_buf.camera_divide_value))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
data = readl(encoder_reg_0_addr);
|
||||||
|
writel(data & ~(u32)(1 << 0), encoder_reg_0_addr);
|
||||||
|
|
||||||
|
if (kern_buf.valve_divide_value != 0)
|
||||||
|
writel(kern_buf.valve_divide_value, encoder_reg_1_addr);
|
||||||
|
if (kern_buf.camera_divide_value != 0)
|
||||||
|
writel(kern_buf.camera_divide_value, encoder_reg_2_addr);
|
||||||
|
|
||||||
|
writel(data | (u32)(1 << 0), encoder_reg_0_addr);
|
||||||
|
|
||||||
|
return cnt;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* @description : 关闭/释放设备
|
||||||
|
* @param – filp : 要关闭的设备文件(文件描述符)
|
||||||
|
* @return : 0 成功;其他 失败
|
||||||
|
*/
|
||||||
|
static int encoder_release(struct inode *inode, struct file *filp)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static long encoder_ioctl(struct file *fp, unsigned int cmd, unsigned long tmp)
|
||||||
|
{
|
||||||
|
u32 data, cmd_parsed;
|
||||||
|
if (_IOC_TYPE(cmd) != 'D' || _IOC_DIR(cmd) != _IOC_WRITE)
|
||||||
|
{
|
||||||
|
printk(KERN_ERR "IOC_TYPE or IOC_WRITE error: IOC_TYPE=%c, IOC_WRITE=%d\r\n", _IOC_TYPE(cmd), _IOC_DIR(cmd));
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
cmd_parsed = _IOC_NR(cmd);
|
||||||
|
data = readl(encoder_reg_0_addr);
|
||||||
|
if (cmd_parsed == ENCODER_CMD_FUNCTION_CLEAR)
|
||||||
|
{
|
||||||
|
writel(data & ~(u32)(1 << 0), encoder_reg_0_addr);
|
||||||
|
writel(data | (u32)(1 << 0), encoder_reg_0_addr);
|
||||||
|
}
|
||||||
|
else if (cmd_parsed == ENCODER_CMD_INPUT_MODE_EXTERNEL)
|
||||||
|
{
|
||||||
|
writel(data & ~(u32)(1 << 1), encoder_reg_0_addr);
|
||||||
|
}
|
||||||
|
else if (cmd_parsed == ENCODER_CMD_INPUT_MODE_INTERNEL)
|
||||||
|
{
|
||||||
|
writel(data | (u32)(1 << 1), encoder_reg_0_addr);
|
||||||
|
}
|
||||||
|
else if (cmd_parsed == ENCODER_CMD_FUNCTION_VIRT_INPUT)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
// 1. ENCODER_CMD_INPUT_MODE_INTERNEL
|
||||||
|
writel(data | (u32)(1 << 1), encoder_reg_0_addr);
|
||||||
|
// 2. Generate pluses
|
||||||
|
for (i = 0; i < tmp; i++)
|
||||||
|
{
|
||||||
|
writel(data & ~(u32)(1 << 2), encoder_reg_0_addr);
|
||||||
|
writel(data | (u32)(1 << 2), encoder_reg_0_addr);
|
||||||
|
}
|
||||||
|
// 3. Recover the original configuration
|
||||||
|
writel(data, encoder_reg_0_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* 设备操作函数 */
|
||||||
|
static struct file_operations encoder_fops = {
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.open = encoder_open,
|
||||||
|
.write = encoder_write,
|
||||||
|
.release = encoder_release,
|
||||||
|
.unlocked_ioctl = encoder_ioctl,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init encoder_init(void)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
u32 data;
|
||||||
|
/* 寄存器地址映射 */
|
||||||
|
encoder_reg_0_addr = ioremap(ENCODER_REG_BASE + ENCODER_REG_0_OFFSET, 4);
|
||||||
|
encoder_reg_1_addr = ioremap(ENCODER_REG_BASE + ENCODER_REG_1_OFFSET, 4);
|
||||||
|
encoder_reg_2_addr = ioremap(ENCODER_REG_BASE + ENCODER_REG_2_OFFSET, 4);
|
||||||
|
encoder_reg_3_addr = ioremap(ENCODER_REG_BASE + ENCODER_REG_3_OFFSET, 4);
|
||||||
|
|
||||||
|
/* 注册字符设备驱动 */
|
||||||
|
//(1)创建设备号
|
||||||
|
if (encoder.major)
|
||||||
|
{
|
||||||
|
encoder.devid = MKDEV(encoder.major, 0);
|
||||||
|
ret = register_chrdev_region(encoder.devid, ENCODER_CNT, ENCODER_NAME);
|
||||||
|
if (ret)
|
||||||
|
goto FAIL_REGISTER_CHR_DEV;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ret = alloc_chrdev_region(&encoder.devid, 0, ENCODER_CNT, ENCODER_NAME);
|
||||||
|
if (ret)
|
||||||
|
goto FAIL_REGISTER_CHR_DEV;
|
||||||
|
encoder.major = MAJOR(encoder.devid);
|
||||||
|
encoder.minor = MINOR(encoder.devid);
|
||||||
|
}
|
||||||
|
|
||||||
|
//(2)初始化cdev
|
||||||
|
encoder.cdev.owner = THIS_MODULE;
|
||||||
|
cdev_init(&encoder.cdev, &encoder_fops);
|
||||||
|
|
||||||
|
//(3)添加cdev
|
||||||
|
ret = cdev_add(&encoder.cdev, encoder.devid, ENCODER_CNT);
|
||||||
|
if (ret)
|
||||||
|
goto FAIL_ADD_CDEV;
|
||||||
|
|
||||||
|
//(4)创建类
|
||||||
|
encoder.class = class_create(THIS_MODULE, ENCODER_NAME);
|
||||||
|
if (IS_ERR(encoder.class))
|
||||||
|
{
|
||||||
|
ret = PTR_ERR(encoder.class);
|
||||||
|
goto FAIL_CREATE_CLASS;
|
||||||
|
}
|
||||||
|
|
||||||
|
//(5)创建设备
|
||||||
|
encoder.device = device_create(encoder.class, NULL, encoder.devid, NULL, ENCODER_NAME);
|
||||||
|
if (IS_ERR(encoder.device))
|
||||||
|
{
|
||||||
|
ret = PTR_ERR(encoder.device);
|
||||||
|
goto FAIL_CREATE_DEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
//默认分频系数1000
|
||||||
|
data = readl(encoder_reg_0_addr);
|
||||||
|
writel(data & ~(u32)(1 << 0), encoder_reg_0_addr);
|
||||||
|
writel(1000, encoder_reg_1_addr);
|
||||||
|
writel(1000, encoder_reg_2_addr);
|
||||||
|
writel(data | (u32)(1 << 0), encoder_reg_0_addr);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
FAIL_CREATE_DEV:
|
||||||
|
class_destroy(encoder.class);
|
||||||
|
|
||||||
|
FAIL_CREATE_CLASS:
|
||||||
|
cdev_del(&encoder.cdev);
|
||||||
|
|
||||||
|
FAIL_ADD_CDEV:
|
||||||
|
unregister_chrdev_region(encoder.devid, ENCODER_CNT);
|
||||||
|
|
||||||
|
FAIL_REGISTER_CHR_DEV:
|
||||||
|
iounmap(encoder_reg_0_addr);
|
||||||
|
iounmap(encoder_reg_1_addr);
|
||||||
|
iounmap(encoder_reg_2_addr);
|
||||||
|
iounmap(encoder_reg_3_addr);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __exit encoder_exit(void)
|
||||||
|
{
|
||||||
|
//(1)注销设备
|
||||||
|
device_destroy(encoder.class, encoder.devid);
|
||||||
|
|
||||||
|
//(2)注销类
|
||||||
|
class_destroy(encoder.class);
|
||||||
|
|
||||||
|
//(3)删除cdev
|
||||||
|
cdev_del(&encoder.cdev);
|
||||||
|
|
||||||
|
//(4)注销设备号
|
||||||
|
unregister_chrdev_region(encoder.devid, ENCODER_CNT);
|
||||||
|
|
||||||
|
//(5)取消内存映射
|
||||||
|
iounmap(encoder_reg_0_addr);
|
||||||
|
iounmap(encoder_reg_1_addr);
|
||||||
|
iounmap(encoder_reg_2_addr);
|
||||||
|
iounmap(encoder_reg_3_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* 驱动模块入口和出口函数注册 */
|
||||||
|
module_init(encoder_init);
|
||||||
|
module_exit(encoder_exit);
|
||||||
|
MODULE_AUTHOR("DingKun");
|
||||||
|
MODULE_DESCRIPTION("driver for hardware encoder in the platform");
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
329
source/linux_driver/fifo.c
Normal file
329
source/linux_driver/fifo.c
Normal file
@ -0,0 +1,329 @@
|
|||||||
|
#include <linux/types.h>
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/errno.h>
|
||||||
|
#include <linux/gpio.h>
|
||||||
|
#include <asm/mach/map.h>
|
||||||
|
#include <asm/uaccess.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <linux/cdev.h>
|
||||||
|
|
||||||
|
#define FIFO_CNT 1 /* 设备号个数 */
|
||||||
|
#define FIFO_NAME "fifo" /* 名字 */
|
||||||
|
#define FIFO_CMD_FUNCTION_CLEAR 1
|
||||||
|
#define FIFO_CMD_FUNCTION_PADDING 2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 相关寄存器地址定义
|
||||||
|
*/
|
||||||
|
#define FIFO_REG_BASE 0x43C00000
|
||||||
|
#define FIFO_REG_0_OFFSET 0x00000000
|
||||||
|
#define FIFO_REG_1_OFFSET 0x00000004
|
||||||
|
#define FIFO_REG_2_OFFSET 0x00000008
|
||||||
|
#define FIFO_REG_3_OFFSET 0x0000000C
|
||||||
|
#define FIFO_REG_4_OFFSET 0x00000010
|
||||||
|
#define FIFO_REG_5_OFFSET 0x00000014
|
||||||
|
#define FIFO_REG_6_OFFSET 0x00000018
|
||||||
|
#define FIFO_REG_7_OFFSET 0x0000001C
|
||||||
|
#define FIFO_REG_8_OFFSET 0x00000020
|
||||||
|
#define FIFO_REG_9_OFFSET 0x00000024
|
||||||
|
#define FIFO_REG_10_OFFSET 0x00000028
|
||||||
|
#define FIFO_REG_11_OFFSET 0x0000002C
|
||||||
|
#define FIFO_REG_12_OFFSET 0x00000030 // {16'b0, almost_empty, empty, almost_full, full, data_count[11:0]};
|
||||||
|
#define FIFO_REG_13_OFFSET 0x00000034
|
||||||
|
#define FIFO_REG_14_OFFSET 0x00000038
|
||||||
|
|
||||||
|
/* 映射后的寄存器虚拟地址指针 */
|
||||||
|
static void __iomem *fifo_reg_0_addr;
|
||||||
|
static void __iomem *fifo_reg_1_addr;
|
||||||
|
static void __iomem *fifo_reg_2_addr;
|
||||||
|
static void __iomem *fifo_reg_3_addr;
|
||||||
|
static void __iomem *fifo_reg_4_addr;
|
||||||
|
static void __iomem *fifo_reg_5_addr;
|
||||||
|
static void __iomem *fifo_reg_6_addr;
|
||||||
|
static void __iomem *fifo_reg_7_addr;
|
||||||
|
static void __iomem *fifo_reg_8_addr;
|
||||||
|
static void __iomem *fifo_reg_9_addr;
|
||||||
|
static void __iomem *fifo_reg_10_addr;
|
||||||
|
static void __iomem *fifo_reg_11_addr;
|
||||||
|
static void __iomem *fifo_reg_12_addr;
|
||||||
|
static void __iomem *fifo_reg_13_addr;
|
||||||
|
static void __iomem *fifo_reg_14_addr;
|
||||||
|
|
||||||
|
/* fifo设备结构体 */
|
||||||
|
struct fifo_dev
|
||||||
|
{
|
||||||
|
dev_t devid; /* 设备号 */
|
||||||
|
struct cdev cdev; /* cdev */
|
||||||
|
struct class *class; /* 类 */
|
||||||
|
struct device *device; /* 设备 */
|
||||||
|
int major; /* 主设备号 */
|
||||||
|
int minor; /* 次设备号 */
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct fifo_dev fifo; /* led设备 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* @description : 打开设备
|
||||||
|
* @param – inode : 传递给驱动的inode
|
||||||
|
* @param - filp : 设备文件，file结构体有个叫做private_data的成员变量
|
||||||
|
* 一般在open的时候将private_data指向设备结构体。
|
||||||
|
* @return : 0 成功;其他 失败
|
||||||
|
*/
|
||||||
|
static int fifo_open(struct inode *inode, struct file *filp)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* @description : 从设备读取数据
|
||||||
|
* @param - filp : 要打开的设备文件(文件描述符)
|
||||||
|
* @param - buf : 返回给用户空间的数据缓冲区
|
||||||
|
* @param - cnt : 要读取的数据长度
|
||||||
|
* @param - offt : 相对于文件首地址的偏移
|
||||||
|
* @return : 读取的字节数，如果为负值，表示读取失败
|
||||||
|
*/
|
||||||
|
static ssize_t fifo_read(struct file *filp, char __user *buf, size_t cnt, loff_t *offt)
|
||||||
|
{
|
||||||
|
u32 data = readl(fifo_reg_12_addr) & 0xFFF;
|
||||||
|
copy_to_user(buf, &data, 4);
|
||||||
|
return cnt;
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 kern_buf_u32[8 * 4096];
|
||||||
|
|
||||||
|
/*
|
||||||
|
* @description : 向设备写数据
|
||||||
|
* @param - filp : 设备文件，表示打开的文件描述符
|
||||||
|
* @param - buf : 要写给设备写入的数据
|
||||||
|
* @param - cnt : 要写入的数据长度
|
||||||
|
* @param - offt : 相对于文件首地址的偏移
|
||||||
|
* @return : 写入的字节数，如果为负值，表示写入失败
|
||||||
|
*/
|
||||||
|
static ssize_t fifo_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (cnt % 32 != 0 || cnt > sizeof(kern_buf_u32))
|
||||||
|
{
|
||||||
|
printk(KERN_ERR "cnt error, cnt=%d\r\n", cnt);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = copy_from_user(kern_buf_u32, buf, cnt); // 得到应用层传递过来的数据
|
||||||
|
if (ret < 0)
|
||||||
|
{
|
||||||
|
printk(KERN_ERR "kernel write failed!\r\n");
|
||||||
|
return -EFAULT;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < (cnt / sizeof(u32)); i += 8)
|
||||||
|
{
|
||||||
|
writel(kern_buf_u32[i], fifo_reg_0_addr);
|
||||||
|
writel(kern_buf_u32[i + 1], fifo_reg_1_addr);
|
||||||
|
writel(kern_buf_u32[i + 2], fifo_reg_2_addr);
|
||||||
|
writel(kern_buf_u32[i + 3], fifo_reg_3_addr);
|
||||||
|
writel(kern_buf_u32[i + 4], fifo_reg_4_addr);
|
||||||
|
writel(kern_buf_u32[i + 5], fifo_reg_5_addr);
|
||||||
|
writel(kern_buf_u32[i + 6], fifo_reg_6_addr);
|
||||||
|
writel(kern_buf_u32[i + 7], fifo_reg_7_addr);
|
||||||
|
writel(0, fifo_reg_8_addr);
|
||||||
|
writel(0, fifo_reg_9_addr);
|
||||||
|
writel(0, fifo_reg_10_addr);
|
||||||
|
writel(0, fifo_reg_11_addr);
|
||||||
|
writel(1, fifo_reg_14_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
return cnt;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* @description : 关闭/释放设备
|
||||||
|
* @param – filp : 要关闭的设备文件(文件描述符)
|
||||||
|
* @return : 0 成功;其他 失败
|
||||||
|
*/
|
||||||
|
static int fifo_release(struct inode *inode, struct file *filp)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static long fifo_ioctl(struct file *fp, unsigned int cmd, unsigned long tmp)
|
||||||
|
{
|
||||||
|
if (_IOC_TYPE(cmd) != 'D' || _IOC_DIR(cmd) != _IOC_WRITE)
|
||||||
|
{
|
||||||
|
printk(KERN_ERR "IOC_TYPE or IOC_WRITE error: IOC_TYPE=%c, IOC_WRITE=%d\r\n", _IOC_TYPE(cmd), _IOC_DIR(cmd));
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
if (_IOC_NR(cmd) == FIFO_CMD_FUNCTION_CLEAR)
|
||||||
|
{
|
||||||
|
writel(((u32)1 << 1), fifo_reg_14_addr);
|
||||||
|
}
|
||||||
|
else if (_IOC_NR(cmd) == FIFO_CMD_FUNCTION_PADDING)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
for (i = 0; i < tmp; i ++)
|
||||||
|
{
|
||||||
|
writel((u32)0, fifo_reg_0_addr);
|
||||||
|
writel((u32)0, fifo_reg_1_addr);
|
||||||
|
writel((u32)0, fifo_reg_2_addr);
|
||||||
|
writel((u32)0, fifo_reg_3_addr);
|
||||||
|
writel((u32)0, fifo_reg_4_addr);
|
||||||
|
writel((u32)0, fifo_reg_5_addr);
|
||||||
|
writel((u32)0, fifo_reg_6_addr);
|
||||||
|
writel((u32)0, fifo_reg_7_addr);
|
||||||
|
writel((u32)0, fifo_reg_8_addr);
|
||||||
|
writel((u32)0, fifo_reg_9_addr);
|
||||||
|
writel((u32)0, fifo_reg_10_addr);
|
||||||
|
writel((u32)0, fifo_reg_11_addr);
|
||||||
|
writel((u32)1, fifo_reg_14_addr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* 设备操作函数 */
|
||||||
|
static struct file_operations fifo_fops = {
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.open = fifo_open,
|
||||||
|
.read = fifo_read,
|
||||||
|
.write = fifo_write,
|
||||||
|
.release = fifo_release,
|
||||||
|
.unlocked_ioctl = fifo_ioctl,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init fifo_init(void)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
/* 寄存器地址映射 */
|
||||||
|
fifo_reg_0_addr = ioremap(FIFO_REG_BASE + FIFO_REG_0_OFFSET, 4);
|
||||||
|
fifo_reg_1_addr = ioremap(FIFO_REG_BASE + FIFO_REG_1_OFFSET, 4);
|
||||||
|
fifo_reg_2_addr = ioremap(FIFO_REG_BASE + FIFO_REG_2_OFFSET, 4);
|
||||||
|
fifo_reg_3_addr = ioremap(FIFO_REG_BASE + FIFO_REG_3_OFFSET, 4);
|
||||||
|
fifo_reg_4_addr = ioremap(FIFO_REG_BASE + FIFO_REG_4_OFFSET, 4);
|
||||||
|
fifo_reg_5_addr = ioremap(FIFO_REG_BASE + FIFO_REG_5_OFFSET, 4);
|
||||||
|
fifo_reg_6_addr = ioremap(FIFO_REG_BASE + FIFO_REG_6_OFFSET, 4);
|
||||||
|
fifo_reg_7_addr = ioremap(FIFO_REG_BASE + FIFO_REG_7_OFFSET, 4);
|
||||||
|
fifo_reg_8_addr = ioremap(FIFO_REG_BASE + FIFO_REG_8_OFFSET, 4);
|
||||||
|
fifo_reg_9_addr = ioremap(FIFO_REG_BASE + FIFO_REG_9_OFFSET, 4);
|
||||||
|
fifo_reg_10_addr = ioremap(FIFO_REG_BASE + FIFO_REG_10_OFFSET, 4);
|
||||||
|
fifo_reg_11_addr = ioremap(FIFO_REG_BASE + FIFO_REG_11_OFFSET, 4);
|
||||||
|
fifo_reg_12_addr = ioremap(FIFO_REG_BASE + FIFO_REG_12_OFFSET, 4);
|
||||||
|
fifo_reg_13_addr = ioremap(FIFO_REG_BASE + FIFO_REG_13_OFFSET, 4);
|
||||||
|
fifo_reg_14_addr = ioremap(FIFO_REG_BASE + FIFO_REG_14_OFFSET, 4);
|
||||||
|
|
||||||
|
/* 注册字符设备驱动 */
|
||||||
|
//(1)创建设备号
|
||||||
|
if (fifo.major)
|
||||||
|
{
|
||||||
|
fifo.devid = MKDEV(fifo.major, 0);
|
||||||
|
ret = register_chrdev_region(fifo.devid, FIFO_CNT, FIFO_NAME);
|
||||||
|
if (ret)
|
||||||
|
goto FAIL_REGISTER_CHR_DEV;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ret = alloc_chrdev_region(&fifo.devid, 0, FIFO_CNT, FIFO_NAME);
|
||||||
|
if (ret)
|
||||||
|
goto FAIL_REGISTER_CHR_DEV;
|
||||||
|
fifo.major = MAJOR(fifo.devid);
|
||||||
|
fifo.minor = MINOR(fifo.devid);
|
||||||
|
}
|
||||||
|
|
||||||
|
//(2)初始化cdev
|
||||||
|
fifo.cdev.owner = THIS_MODULE;
|
||||||
|
cdev_init(&fifo.cdev, &fifo_fops);
|
||||||
|
|
||||||
|
//(3)添加cdev
|
||||||
|
ret = cdev_add(&fifo.cdev, fifo.devid, FIFO_CNT);
|
||||||
|
if (ret)
|
||||||
|
goto FAIL_ADD_CDEV;
|
||||||
|
|
||||||
|
//(4)创建类
|
||||||
|
fifo.class = class_create(THIS_MODULE, FIFO_NAME);
|
||||||
|
if (IS_ERR(fifo.class))
|
||||||
|
{
|
||||||
|
ret = PTR_ERR(fifo.class);
|
||||||
|
goto FAIL_CREATE_CLASS;
|
||||||
|
}
|
||||||
|
|
||||||
|
//(5)创建设备
|
||||||
|
fifo.device = device_create(fifo.class, NULL, fifo.devid, NULL, FIFO_NAME);
|
||||||
|
if (IS_ERR(fifo.device))
|
||||||
|
{
|
||||||
|
ret = PTR_ERR(fifo.device);
|
||||||
|
goto FAIL_CREATE_DEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
FAIL_CREATE_DEV:
|
||||||
|
class_destroy(fifo.class);
|
||||||
|
|
||||||
|
FAIL_CREATE_CLASS:
|
||||||
|
cdev_del(&fifo.cdev);
|
||||||
|
|
||||||
|
FAIL_ADD_CDEV:
|
||||||
|
unregister_chrdev_region(fifo.devid, FIFO_CNT);
|
||||||
|
|
||||||
|
FAIL_REGISTER_CHR_DEV:
|
||||||
|
iounmap(fifo_reg_0_addr);
|
||||||
|
iounmap(fifo_reg_1_addr);
|
||||||
|
iounmap(fifo_reg_2_addr);
|
||||||
|
iounmap(fifo_reg_3_addr);
|
||||||
|
iounmap(fifo_reg_4_addr);
|
||||||
|
iounmap(fifo_reg_5_addr);
|
||||||
|
iounmap(fifo_reg_6_addr);
|
||||||
|
iounmap(fifo_reg_7_addr);
|
||||||
|
iounmap(fifo_reg_8_addr);
|
||||||
|
iounmap(fifo_reg_9_addr);
|
||||||
|
iounmap(fifo_reg_10_addr);
|
||||||
|
iounmap(fifo_reg_11_addr);
|
||||||
|
iounmap(fifo_reg_12_addr);
|
||||||
|
iounmap(fifo_reg_13_addr);
|
||||||
|
iounmap(fifo_reg_14_addr);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __exit fifo_exit(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
//(1)注销设备
|
||||||
|
device_destroy(fifo.class, fifo.devid);
|
||||||
|
|
||||||
|
//(2)注销类
|
||||||
|
class_destroy(fifo.class);
|
||||||
|
|
||||||
|
//(3)删除cdev
|
||||||
|
cdev_del(&fifo.cdev);
|
||||||
|
|
||||||
|
//(4)注销设备号
|
||||||
|
unregister_chrdev_region(fifo.devid, FIFO_CNT);
|
||||||
|
|
||||||
|
//(5)取消内存映射
|
||||||
|
iounmap(fifo_reg_0_addr);
|
||||||
|
iounmap(fifo_reg_1_addr);
|
||||||
|
iounmap(fifo_reg_2_addr);
|
||||||
|
iounmap(fifo_reg_3_addr);
|
||||||
|
iounmap(fifo_reg_4_addr);
|
||||||
|
iounmap(fifo_reg_5_addr);
|
||||||
|
iounmap(fifo_reg_6_addr);
|
||||||
|
iounmap(fifo_reg_7_addr);
|
||||||
|
iounmap(fifo_reg_8_addr);
|
||||||
|
iounmap(fifo_reg_9_addr);
|
||||||
|
iounmap(fifo_reg_10_addr);
|
||||||
|
iounmap(fifo_reg_11_addr);
|
||||||
|
iounmap(fifo_reg_12_addr);
|
||||||
|
iounmap(fifo_reg_13_addr);
|
||||||
|
iounmap(fifo_reg_14_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* 驱动模块入口和出口函数注册 */
|
||||||
|
module_init(fifo_init);
|
||||||
|
module_exit(fifo_exit);
|
||||||
|
MODULE_AUTHOR("Dingkun");
|
||||||
|
MODULE_DESCRIPTION("driver for hardware fifo in the platform");
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
8
source/petalinux_config/kernel.cfg
Normal file
8
source/petalinux_config/kernel.cfg
Normal file
@ -0,0 +1,8 @@
|
|||||||
|
CONFIG_FS_POSIX_ACL=y
|
||||||
|
CONFIG_FUSE_FS=y
|
||||||
|
CONFIG_USB_OTG=y
|
||||||
|
CONFIG_FAT_DEFAULT_UTF8=y
|
||||||
|
CONFIG_EXFAT_FS=y
|
||||||
|
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
|
||||||
|
CONFIG_NTFS_FS=y
|
||||||
|
CONFIG_NTFS_RW=y
|
||||||
262
source/petalinux_config/petalinux_config
Normal file
262
source/petalinux_config/petalinux_config
Normal file
@ -0,0 +1,262 @@
|
|||||||
|
#
|
||||||
|
# Automatically generated file; DO NOT EDIT.
|
||||||
|
# misc/config System Configuration
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_TYPE_LINUX=y
|
||||||
|
CONFIG_SYSTEM_ZYNQ=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Linux Components Selection
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y
|
||||||
|
CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y
|
||||||
|
CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQ_FSBL=y
|
||||||
|
CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y
|
||||||
|
CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y
|
||||||
|
# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set
|
||||||
|
# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set
|
||||||
|
CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX=y
|
||||||
|
# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set
|
||||||
|
# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Auto Config Settings
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y
|
||||||
|
# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set
|
||||||
|
CONFIG_SUBSYSTEM_HARDWARE_AUTO=y
|
||||||
|
CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="ps7_cortexa9_0"
|
||||||
|
CONFIG_SUBSYSTEM_PROCESSOR_ps7_cortexa9_0_SELECT=y
|
||||||
|
CONFIG_SUBSYSTEM_ARCH_ARM=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Memory Settings
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SELECT=y
|
||||||
|
# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set
|
||||||
|
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_BASEADDR=0x0
|
||||||
|
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SIZE=0x20000000
|
||||||
|
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0
|
||||||
|
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x400000
|
||||||
|
CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PS7_DDR_0"
|
||||||
|
|
||||||
|
#
|
||||||
|
# Serial Settings
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_0_SELECT=y
|
||||||
|
# CONFIG_SUBSYSTEM_FSBL_SERIAL_MANUAL_SELECT is not set
|
||||||
|
CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT=y
|
||||||
|
# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set
|
||||||
|
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_600 is not set
|
||||||
|
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_9600 is not set
|
||||||
|
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_28800 is not set
|
||||||
|
CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_115200=y
|
||||||
|
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_230400 is not set
|
||||||
|
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_460800 is not set
|
||||||
|
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_921600 is not set
|
||||||
|
CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="ps7_uart_0"
|
||||||
|
CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_0"
|
||||||
|
|
||||||
|
#
|
||||||
|
# Ethernet Settings
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_SELECT=y
|
||||||
|
# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set
|
||||||
|
# CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC_AUTO is not set
|
||||||
|
CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC="00:0a:35:00:1e:53"
|
||||||
|
# CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_USE_DHCP is not set
|
||||||
|
CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_IP_ADDRESS="192.168.10.10"
|
||||||
|
CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_IP_NETMASK="255.255.255.0"
|
||||||
|
CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_IP_GATEWAY="192.168.10.1"
|
||||||
|
|
||||||
|
#
|
||||||
|
# Flash Settings
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_SELECT=y
|
||||||
|
# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set
|
||||||
|
# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# partition 0
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_NAME="boot"
|
||||||
|
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_SIZE=0x400000
|
||||||
|
|
||||||
|
#
|
||||||
|
# partition 1
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART1_NAME="kernel"
|
||||||
|
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART1_SIZE=0x1400000
|
||||||
|
|
||||||
|
#
|
||||||
|
# partition 2
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_NAME="bootenv"
|
||||||
|
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_SIZE=0x400000
|
||||||
|
|
||||||
|
#
|
||||||
|
# partition 3
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_NAME=""
|
||||||
|
CONFIG_SUBSYSTEM_FLASH_IP_NAME="ps7_qspi_0"
|
||||||
|
|
||||||
|
#
|
||||||
|
# SD/SDIO Settings
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_PRIMARY_SD_PS7_SD_0_SELECT=y
|
||||||
|
# CONFIG_SUBSYSTEM_PRIMARY_SD_PS7_SD_1_SELECT is not set
|
||||||
|
# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set
|
||||||
|
CONFIG_SUBSYSTEM_SD_PS7_SD_0_SELECT=y
|
||||||
|
CONFIG_SUBSYSTEM_SD_PS7_SD_1_SELECT=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# RTC Settings
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT=y
|
||||||
|
CONFIG_SUBSYSTEM_USB_PS7_USB_0_SELECT=y
|
||||||
|
CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# DTG Settings
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_MACHINE_NAME="template"
|
||||||
|
CONFIG_SUBSYSTEM_EXTRA_DT_FILES=""
|
||||||
|
|
||||||
|
#
|
||||||
|
# Kernel Bootargs
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y
|
||||||
|
CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y
|
||||||
|
|
||||||
|
CONFIG_SUBSYSTEM_DEVICETREE_COMPILER_FLAGS="-@"
|
||||||
|
# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set
|
||||||
|
# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set
|
||||||
|
# CONFIG_SUBSYSTEM_ENABLE_NO_ALIAS is not set
|
||||||
|
# CONFIG_SUBSYSTEM_ENABLE_DT_VERBOSE is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# FSBL Configuration
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_FSBL_BSPCOMPILER_FLAGS=""
|
||||||
|
CONFIG_SUBSYSTEM_FSBL_COMPILER_EXTRA_FLAGS=""
|
||||||
|
|
||||||
|
#
|
||||||
|
# FPGA Manager
|
||||||
|
#
|
||||||
|
# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# u-boot Configuration
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET="xilinx_zynq_virt_defconfig"
|
||||||
|
|
||||||
|
#
|
||||||
|
# u-boot script configuration
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_APPEND_BASEADDR=y
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_PRE_BOOTENV=""
|
||||||
|
|
||||||
|
#
|
||||||
|
# JTAG/DDR image offsets
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_DEVICETREE_OFFSET=0x100000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_KERNEL_OFFSET=0x200000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_RAMDISK_IMAGE_OFFSET=0x4000000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_FIT_IMAGE_OFFSET=0x10000000
|
||||||
|
|
||||||
|
#
|
||||||
|
# QSPI/OSPI image offsets
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_QSPI_KERNEL_OFFSET=0xA00000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_QSPI_KERNEL_SIZE=0x600000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_QSPI_RAMDISK_OFFSET=0x1000000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_QSPI_RAMDISK_SIZE=0xF80000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_OFFSET=0xA80000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_SIZE=0x1500000
|
||||||
|
|
||||||
|
#
|
||||||
|
# NAND image offsets
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_NAND_KERNEL_OFFSET=0x1000000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_NAND_KERNEL_SIZE=0x3200000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_NAND_RAMDISK_OFFSET=0x4600000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_NAND_RAMDISK_SIZE=0x3200000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_NAND_FIT_IMAGE_OFFSET=0x1080000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_NAND_FIT_IMAGE_SIZE=0x6400000
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_KERNEL_IMAGE="uImage"
|
||||||
|
CONFIG_SUBSYSTEM_UBOOT_FIT_IMAGE="image.ub"
|
||||||
|
# CONFIG_SUBSYSTEM_UBOOT_EXT_DTB is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Linux Configuration
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_LINUX_CONFIG_TARGET=""
|
||||||
|
|
||||||
|
#
|
||||||
|
# Image Packaging Configuration
|
||||||
|
#
|
||||||
|
# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
|
||||||
|
# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set
|
||||||
|
# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set
|
||||||
|
# CONFIG_SUBSYSTEM_ROOTFS_UBIFS is not set
|
||||||
|
# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set
|
||||||
|
CONFIG_SUBSYSTEM_ROOTFS_EXT4=y
|
||||||
|
# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
|
||||||
|
CONFIG_SUBSYSTEM_SDROOT_DEV="/dev/mmcblk0p2"
|
||||||
|
CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub"
|
||||||
|
CONFIG_SUBSYSTEM_RFS_FORMATS="ext4 tar.gz"
|
||||||
|
CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000
|
||||||
|
# CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Firmware Version Configuration
|
||||||
|
#
|
||||||
|
CONFIG_SUBSYSTEM_HOSTNAME="ps-linux"
|
||||||
|
CONFIG_SUBSYSTEM_PRODUCT="ps-linux"
|
||||||
|
CONFIG_SUBSYSTEM_FW_VERSION="1.00"
|
||||||
|
|
||||||
|
#
|
||||||
|
# Yocto Settings
|
||||||
|
#
|
||||||
|
CONFIG_YOCTO_MACHINE_NAME="zynq-generic"
|
||||||
|
|
||||||
|
#
|
||||||
|
# TMPDIR Location
|
||||||
|
#
|
||||||
|
CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp"
|
||||||
|
|
||||||
|
#
|
||||||
|
# Devtool Workspace Location
|
||||||
|
#
|
||||||
|
CONFIG_DEVTOOL_WORKSPACE_LOCATION="${PROOT}/components/yocto/workspace"
|
||||||
|
|
||||||
|
#
|
||||||
|
# Parallel thread execution
|
||||||
|
#
|
||||||
|
CONFIG_YOCTO_BB_NUMBER_THREADS=""
|
||||||
|
CONFIG_YOCTO_PARALLEL_MAKE=""
|
||||||
|
|
||||||
|
#
|
||||||
|
# Add pre-mirror url
|
||||||
|
#
|
||||||
|
CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_MAJOR_VER}/downloads"
|
||||||
|
|
||||||
|
#
|
||||||
|
# Local sstate feeds settings
|
||||||
|
#
|
||||||
|
CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL=""
|
||||||
|
CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Network sstate feeds URL
|
||||||
|
#
|
||||||
|
CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_MAJOR_VER}/arm/sstate-cache"
|
||||||
|
# CONFIG_YOCTO_BB_NO_NETWORK is not set
|
||||||
|
# CONFIG_YOCTO_BUILDTOOLS_EXTENDED is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# User Layers
|
||||||
|
#
|
||||||
|
CONFIG_USER_LAYER_0=""
|
||||||
|
|
||||||
|
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="console=ttyPS0,115200 earlycon root=/dev/mmcblk0p2 rw rootwait"
|
||||||
3903
source/petalinux_config/rootfs_config
Normal file
3903
source/petalinux_config/rootfs_config
Normal file
File diff suppressed because it is too large
Load Diff
26
source/petalinux_devicetree/system-user.dtsi
Normal file
26
source/petalinux_devicetree/system-user.dtsi
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
/include/ "system-conf.dtsi"
|
||||||
|
/ {
|
||||||
|
};
|
||||||
|
|
||||||
|
/ {
|
||||||
|
usb_phy0: usb_phy@0 {
|
||||||
|
compatible = "ulpi-phy";
|
||||||
|
reg = <0xe0002000 0x1000>;
|
||||||
|
view-port = <0x170>;
|
||||||
|
reset-gpios = <&gpio0 8 1>;
|
||||||
|
drv-vbus;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
&usb0 {
|
||||||
|
status = "okay";
|
||||||
|
dr_mode = "host";
|
||||||
|
usb-phy = <&usb_phy0>;
|
||||||
|
};
|
||||||
|
&flash0 {
|
||||||
|
compatible = "micron,w25q256";
|
||||||
|
reg = <0x0>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
spi-max-frequency = <50000000>;
|
||||||
|
};
|
||||||
|
|
||||||
1
source/petalinux_hwdescription/README.md
Normal file
1
source/petalinux_hwdescription/README.md
Normal file
@ -0,0 +1 @@
|
|||||||
|
关于生成硬件描述文件，见[doc/hardware_description.md](../../doc/hardware_description.md)
|
||||||
@ -1,24 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
|
||||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
|
||||||
|
|
||||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
|
||||||
|
|
||||||
<cconfiguration id="org.eclipse.cdt.core.default.config.2070356241">
|
|
||||||
|
|
||||||
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.2070356241" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
|
|
||||||
|
|
||||||
<externalSettings/>
|
|
||||||
|
|
||||||
<extensions/>
|
|
||||||
|
|
||||||
</storageModule>
|
|
||||||
|
|
||||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
|
||||||
|
|
||||||
</cconfiguration>
|
|
||||||
|
|
||||||
</storageModule>
|
|
||||||
|
|
||||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
|
||||||
|
|
||||||
</cproject>
|
|
||||||
3
source/test_lower_machine/.gitignore
vendored
3
source/test_lower_machine/.gitignore
vendored
@ -1,3 +0,0 @@
|
|||||||
/export/
|
|
||||||
*.o
|
|
||||||
*.d
|
|
||||||
@ -1,72 +0,0 @@
|
|||||||
2022-05-15T22:17:26.941896 0 0 255 - 22:17:26 **** Clean-only build of project test_lower_machine ****
|
|
||||||
0 0 0 - buildplatform.sh 36625 test_lower_machine clean
|
|
||||||
0 0 0 - XSDB Server Channel: tcfchan#5
|
|
||||||
0 0 0 - Cleaning the zynq_fsbl application.
|
|
||||||
0 0 0 - rm -rf pcap.o qspi.o nor.o rsa.o main.o fsbl_hooks.o md5.o image_mover.o ps7_init.o nand.o sd.o fsbl_handoff.o zyn
|
|
||||||
0 0 0 - q_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a fsbl.elf *.o
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - Cleaning the zynq_fsbl application, bsp
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/ip_encoder_v1_0/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/ip_fifo_v1_0/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - rm -f ps7_cortexa9_0/lib/libxil.a
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - Cleaning the BSP for domain - standalone_domain
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/ip_encoder_v1_0/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/ip_fifo_v1_0/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s clean
|
|
||||||
0 0 0 -
|
|
||||||
0 0 0 - rm -f ps7_cortexa9_0/lib/libxil.a
|
|
||||||
0 0 0 -
|
|
||||||
0 0 255 -
|
|
||||||
22:17:32 Build Finished (took 5s.534ms)
|
|
||||||
|
|
||||||
@ -1,18 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<projectDescription>
|
|
||||||
<name>test_lower_machine</name>
|
|
||||||
<comment>Created by Vitis v2021.2</comment>
|
|
||||||
<projects>
|
|
||||||
</projects>
|
|
||||||
<buildSpec>
|
|
||||||
<buildCommand>
|
|
||||||
<name>com.xilinx.sdx.scw.PlatformProjectBuilder</name>
|
|
||||||
<arguments>
|
|
||||||
</arguments>
|
|
||||||
</buildCommand>
|
|
||||||
</buildSpec>
|
|
||||||
<natures>
|
|
||||||
<nature>com.xilinx.sdx.scw.platformProject</nature>
|
|
||||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
|
||||||
</natures>
|
|
||||||
</projectDescription>
|
|
||||||
@ -1,10 +0,0 @@
|
|||||||
|
|
||||||
|
|
||||||
OPTION psf_version = 2.1;
|
|
||||||
|
|
||||||
BEGIN DRIVER ip_encoder
|
|
||||||
OPTION supported_peripherals = (ip_encoder);
|
|
||||||
OPTION copyfiles = all;
|
|
||||||
OPTION VERSION = 1.0;
|
|
||||||
OPTION NAME = ip_encoder;
|
|
||||||
END DRIVER
|
|
||||||
@ -1,5 +0,0 @@
|
|||||||
|
|
||||||
|
|
||||||
proc generate {drv_handle} {
|
|
||||||
xdefine_include_file $drv_handle "xparameters.h" "ip_encoder" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
|
||||||
}
|
|
||||||
@ -1,26 +0,0 @@
|
|||||||
COMPILER=
|
|
||||||
ARCHIVER=
|
|
||||||
CP=cp
|
|
||||||
COMPILER_FLAGS=
|
|
||||||
EXTRA_COMPILER_FLAGS=
|
|
||||||
LIB=libxil.a
|
|
||||||
|
|
||||||
RELEASEDIR=../../../lib
|
|
||||||
INCLUDEDIR=../../../include
|
|
||||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
|
||||||
|
|
||||||
INCLUDEFILES=*.h
|
|
||||||
LIBSOURCES=*.c
|
|
||||||
OUTS = *.o
|
|
||||||
|
|
||||||
libs:
|
|
||||||
echo "Compiling ip_encoder..."
|
|
||||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
|
||||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
|
||||||
make clean
|
|
||||||
|
|
||||||
include:
|
|
||||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
|
||||||
|
|
||||||
clean:
|
|
||||||
rm -rf ${OUTS}
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user