feat: migrate from the wood project to form the framework of this cotton project
readme.md needs to be improved
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README.md
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README.md
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# 下位机
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# 下位机
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下位机按上位机指令根据传送带脉冲等触发相机，完成刨花板的缺陷分选任务。本次下位机不连接阀板，是由PLC翻板机的机械装置作为执行器，对木板进行分选。采用的硬件是[Microphase](https://www.microphase.cn/)的XME0724CB ZYNQ开发板，具体核心板型号为XME0724-10，到手后记得把各排插针焊一下，如左图：
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下位机按上位机指令根据传送带脉冲等触发相机，完成刨花板的缺陷分选任务。本次下位机不连接阀板，是由PLC翻板机的机械装置作为执行器，对木板进行分选。采用的硬件是[Alinx](https://www.alinx.com/)的AC7Z100C ZYNQ开发板。
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本IO扩展版提供了
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为了供电稳定，采用叠板给底板5V供电，由底板输出3.3V供回给叠板，叠板就是IO扩展板，将IO扩展板插在底板排针上，叠起来，因此称为叠板，如上图中和上图右。
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- xxxxxx
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IO扩展版提供了
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- 1个12V电源输入
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- 4个相机触发，本次项目为2个相机触发，其余冗余
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- 1个ZYNQ散热风扇接口
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- 6个编码器或IO输入，本次项目为1个编码器输入、1个物体传感器输入，其余冗余
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- 8个阀板接口，本次项目没有用到
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接线时，12V电源连接到IO扩展板的电源接口，相机线应连接相机触发接口`TRIG1`、`TRIG2`和对应的`GND`接口，编码器线应连接在编码器输入接口`E1`和对应的`GND`接口，物体传感器应连接输入接口`E3`和对应的`GND`接口。注意底板不连接任何外部电源。
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接线时，12V电源连接到IO扩展板的电源接口，相机线应连接相机触发接口`TRIG1`、`TRIG2`和对应的`GND`接口，编码器线应连接在编码器输入接口`E1`和对应的`GND`接口，物体传感器应连接输入接口`E3`和对应的`GND`接口。注意底板不连接任何外部电源。
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@ -43,7 +35,7 @@ IO扩展版提供了
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- pl_platform为PL端硬件设计
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- pl_platform为PL端硬件设计
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- xme0724ioextend为IO叠板的原理图和PCB
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- xme0724ioextend为IO叠板的原理图和PCB
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- source为XME0724板子上运行的源程序和模拟上位机程序
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- source为AC7Z100C板子上运行的源程序和模拟上位机程序
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- liunx_app为Linux上运行的应用程序，即业务逻辑
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- liunx_app为Linux上运行的应用程序，即业务逻辑
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- linux_driver为Linux上的驱动，用于控制自定义的PL端硬件，其中drv_test结尾的目录为相应驱动模块的测试应用程序
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- linux_driver为Linux上的驱动，用于控制自定义的PL端硬件，其中drv_test结尾的目录为相应驱动模块的测试应用程序
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@ -76,4 +68,4 @@ b分支编号-d文档版本-hPCB设计版本-lFPGA设计版本-p协议版本-s
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## 作者
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## 作者
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作者觉得还是不说明是谁比较好，免得毕业后有提着示波器的师弟师妹来问问题
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作者徐耀，不管有没有毕业，7x24欢迎提着示波器的师弟师妹来问问题
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@ -1,365 +0,0 @@
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# 开发和部署
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## 开发
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本次开发基于zynq `xc7z010-1clg400`芯片，因此FPGA设计软件为Vitis中包含的[Vivado 2022.1](https://china.xilinx.com/support/download/index.html/content/xilinx/zh/downloadNav/vitis.html)，Linux编译工具为[petalinux 2022.2](https://china.xilinx.com/support/download/index.html/content/xilinx/zh/downloadNav/embedded-design-tools.html)，Linux应用程序编译工具为linaro的[arm-linux-gnueabihf-gcc 12.2.1](https://snapshots.linaro.org/gnu-toolchain/12.2-2023.04-1/)。
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### 生成硬件描述文件
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1. 下载[hardware/pl_platform](../hardware/pl_platform)文件夹到家目录，这里假设用户为miaow<br />在vivado 2022.1中执行tcl脚本，复原工程
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```tcl
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source /home/miaow/pl_platform/lower_machine.tcl
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```
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2. 重新生成`block design`的`output products`
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3. 生成`bitstream`后创建硬件描述文件，命令为
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```tcl
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# 下面命令中32为计算机逻辑内核数，按实际设定
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launch_runs impl_1 -to_step write_bitstream -jobs 32
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# 生成硬件描述文件
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write_hw_platform -fixed -include_bit -force -file /home/miaow/zynq/vivado_git/lower_machine/system_wrapper.xsa
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```
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硬件描述文件为`system_wrapper.xsa`
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### 创建PETALINUX工程
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1. 创建名为`ps-linux`的工程
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```shell
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$ cd ~
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$ petalinux-create -t project --template zynq -n ps-linux
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```
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2. 上传release中的硬件描述文件`system_wrapper.xsa`到`ps-linux`目录中并config
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```shell
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system_wrapper.xsa上传到~/ps-linux
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$ petalinux-config --get-hw-description system_wrapper.xsa
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```
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在`petalinux-config`时候，按下面提示配置
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```shell
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# Subsystem AUTO Hardware Settings
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# ├─Serial Settings
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# | ├─FSBL Serial stdin/stdout (设为ps7_uart_0)
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# | ├─DTG Serial stdin/stdout (设为ps7_uart_0)
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# | └─System stdin/stdout baudrate for ps7_uart_0 (设为115200)
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# ├─Ethernet Settings
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# | ├─Randomise MAC address (不选)
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# | ├─Primary Ethernet (设为ps7_ethernet_0)
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# | ├─Obtain IP address automatically (不选)
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# | ├─Static IP address (设为192.168.10.10)
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# | ├─Static IP netmask (设为255.255.255.0)
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# | └─Static IP gateway (设为192.168.10.1)
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# ├─Flash Settings
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# | └─Primary Flash (设为ps7_qspi_0)
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# ├─Flash Settings
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# | └─Primary Flash (设为ps7_qspi_0)
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# ├─SD/SDIO Settings
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# | └─Primary SD/SDIO (设为ps7_sd_0)
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# Image Packaging Configuration
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# └─Image Packaging Configuration
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# ├─Root filesystem type (设为EXT4 (SD/eMMC/SATA/USB))
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# ├─name for bootable kernel image (设为image.ub)
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# ├─Root filesystem formats (设为tar.gz)
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# └─Copy final images to tftpboot (不选)
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```
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4. 创建一个模块
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```shell
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$ petalinux-create -t modules --name encoder --enable
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```
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1. 上传驱动代码[source/linux_driver/encoder.c](../source/linux_driver/encoder.c)到下面的目录中
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```shell
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~/ps-linux/project-spec/meta-user/recipes-modules/encoder/files
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```
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1. 修改设备树，需要修改的文件为`project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi`，先删除该文件，然后上传新的自定义设备树文件[source/petalinux_devicetree/system-user.dtsi](../source/petalinux_devicetree/system-user.dtsi)
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```shell
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$ cd ~/ps-linux/project-spec/meta-user/recipes-bsp/device-tree/files
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$ rm system-user.dtsi
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上传source/petalinux_devicetree/system-user.dtsi
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```
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2. 配置`kernel`，使用命令`petalinux-config -c kernel`，按下面提示或[source/petalinux_config/kernel.cfg](../source/petalinux_config/kernel.cfg)配置
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```shell
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# File systems
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# ├─FUSE (Filesystem in Userspace) support (勾选为星号)
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# └─DOS/FAT/EXFAT/NT Filesystems
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# ├─Enable FAT UTF-8 option by default (勾选为星号)
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# ├─exFAT filesystem support (勾选为星号)
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# ├─NTFS file system support (勾选为星号)
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# └─NTFS write support (勾选为星号)
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# Device Drivers
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# └─USB support
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# └─OTG support (勾选为星号)
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```
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3. 配置`rootfs`，使用命令`petalinux-config -c rootfs`，按下面提示或[source/petalinux_config/rootfs_config](../source/petalinux_config/rootfs_config)配置
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```shell
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# Filesystem Packages
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# ├─base
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# | ├─shell
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# | | └─bash
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# | | └─bash (勾选为星号)
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# | ├─tar
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# | | └─tar (勾选为星号)
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# | ├─util-linux
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# | | ├─util-linux-blkid (勾选为星号)
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# | | ├─util-linux-lscpu (勾选为星号)
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# | | ├─util-linux-umount (勾选为星号)
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# | | └─util-linux-mount (勾选为星号)
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# | └─xz
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# | ├─xz (勾选为星号)
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# | └─liblzma (勾选为星号)
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# ├─console
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# | ├─network
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# | | ├─curl
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# | | | ├─curl (勾选为星号)
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# | | | └─libcurl (勾选为星号)
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# | | ├─dropbear
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# | | | └─dropbear (不选)
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# | | ├─ethtool
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# | | | └─ethtool (勾选为星号)
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# | | ├─lrzsz
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# | | | └─lrzsz (勾选为星号)
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# | | ├─minicom
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# | | | └─minicom (勾选为星号)
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# | | ├─openssh
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# | | | ├─openssh (勾选为星号)
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# | | | ├─openssh-misc (勾选为星号)
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# | | | ├─openssh-sshd (勾选为星号)
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# | | | ├─openssh-keygen (勾选为星号)
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# | | | ├─openssh-ssh (勾选为星号)
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# | | | ├─openssh-sftp (勾选为星号)
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# | | | ├─openssh-sftp-server (勾选为星号)
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# | | | └─openssh-scp (勾选为星号)
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# | | └─wget
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# | | └─wget (勾选为星号)
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# | ├─utils
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# | | ├─bash-completion
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# | | | ├─bash-completion (勾选为星号)
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# | | | └─bash-completion-extra (勾选为星号)
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# | ├─bzip2
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# | | ├─bzip2 (勾选为星号)
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# | | └─libbz2 (勾选为星号)
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# | ├─file
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# | | └─file (勾选为星号)
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# | ├─findutils
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# | | └─findutils (勾选为星号)
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# | ├─gawk
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# | | └─gawk (勾选为星号)
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# | ├─grep
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# | | └─grep (勾选为星号)
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# | ├─gzip
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# | | └─gzip (勾选为星号)
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# | ├─less
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# | | └─less (勾选为星号)
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# | ├─man
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# | | └─man (勾选为星号)
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# | ├─man-pages
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# | | └─man-pages (勾选为星号)
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# | ├─screen
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# | | └─screen (勾选为星号)
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# | ├─sed
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# | | └─sed (勾选为星号)
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# | ├─unzip
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# | | └─unzip (勾选为星号)
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# | ├─vim
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# | | ├─vim (勾选为星号)
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# | | ├─vim-syntax (勾选为星号)
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# | | └─vim-common (勾选为星号)
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# | └─zip
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# | └─zip (勾选为星号)
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# ├─devel
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# | └─lsof
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# | └─lsof (勾选为星号)
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# ├─libs
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# | ├─ncurses
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# | | ├─ncurses (勾选为星号)
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# | | ├─ncurses-terminfo-base (勾选为星号)
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# | | ├─ncurses-tools (勾选为星号)
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# | | └─ncurses-terminfo (勾选为星号)
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# | └─which
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# | └─which (勾选为星号)
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# ├─misc
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# | ├─perf
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# | | └─perf (勾选为星号)
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# | └─packagegroup-core-ssh-dropbear
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# | └─packagegroup-core-ssh-dropbear (不选)
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# Image Features
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# ├─imagefeature-ssh-server-dropbear (不选)
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# ├─imagefeature-ssh-server-openssh (勾选为星号)
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# ├─imagefeature-hwcodecs (勾选为星号)
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# ├─imagefeature-package-management (勾选为星号)
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# modules
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# ├─encoder (不选)
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# PetaLinux RootFS Settings
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# ├─ADD_EXTRA_USERS (root:3703;petalinux:3703;)
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# ├─ADD_USERS_TO_GROUPS (petalinux:audio,video;)
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# └─ADD_USERS_TO_SUDOERS (petalinux)
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```
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8. 替换`~/ps-linux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h`为[platform-top.h](../source/petalinux_config/platform-top.h)，用于添加u-boot所需的环境变量，实现动态加载比特流文件
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### 编译系统
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1. 编译工程，使用命令`petalinux-build`。编译完成，在当前工程目录下生成`images`文件夹，该命令将生成设备树文件、`FSBL`文件、`U-Boot`文件，`Linux Kernel`文件和`rootfs`文件镜像
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2. 制作BOOT.BIN启动文件，具体命令如下：
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```shell
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$ cd ~/ps-linux/images/linux/ # 生成的BOOT.BIN在该路径下
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$ petalinux-package --boot --fsbl ./zynq_fsbl.elf --u-boot ./u-boot.elf --force
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```
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### 编译驱动
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依次运行如下命令，编译驱动程序
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||||||
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```shell
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|
||||||
$ petalinux-build -c encoder
|
|
||||||
```
|
|
||||||
|
|
||||||
编译后的模块文件为`ps-linux/build/tmp/sysroots-components/zynq_generic/encoder/lib/modules/5.15.36-xilinx-v2022.2/extra/encoder.ko`
|
|
||||||
|
|
||||||
### 编译应用程序
|
|
||||||
|
|
||||||
在运行make时要设置好交叉编译工具链前缀，命令如下
|
|
||||||
```shell
|
|
||||||
$ make CROSS_COMPILE=交叉编译工具链前缀
|
|
||||||
例如 make CROSS_COMPILE=/home/miaow/software/gcc-linaro-12.2.1-2023.04-x86_64_arm-linux-gnueabihf/bin/arm-none-linux-gnueabihf-
|
|
||||||
```
|
|
||||||
|
|
||||||
编译后的可执行文件为工程目录的`build/target`，交叉编译工具链前缀也可以在Makefile中修改设定
|
|
||||||
|
|
||||||
## 部署
|
|
||||||
|
|
||||||
有两种方式部署，一种是修改文件系统，这也是我第一次构建这个系统时的操作；另一种是直接写入镜像，推荐使用这种方式，省时省力不易出错
|
|
||||||
|
|
||||||
> 注意：修改文件系统方法所需的文件按上一章节编译得到或者从github的release中下载；直接写入镜像所需的文件在release中
|
|
||||||
|
|
||||||
|
|
||||||
### 修改文件系统
|
|
||||||
|
|
||||||
1. 给SD卡创建DOS分区表，然后分2个区并创建文件系统，细节如下表：
|
|
||||||
|
|
||||||
| 扇区 | 大小 | 分区类型 | 文件系统 | 卷标 |
|
|
||||||
| -------------- | -------------- | ----------------- | -------- | ------ |
|
|
||||||
| 2048~x扇区 | 100M | C W95 FAT32 (LBA) | FAT32 | boot |
|
|
||||||
| x扇区~最后扇区 | ≈SD卡大小-100M | 83 Linux | ext4 | rootfs |
|
|
||||||
|
|
||||||
2. 将打包和编译得到的`BOOT.BIN`、`boot.scr`、`system.bit`和`image.ub`复制到`boot`分区；将`rootfs.tar.gz`解压到`rootfs`分区
|
|
||||||
|
|
||||||
这里的`system.bit`为比特流文件，可以由`petalinux`从`XSA`文件中提取，也可以是`vivado`生成的，注意重命名为`system.bit`。
|
|
||||||
|
|
||||||
3. 拨码开关拨到SD卡启动，插入SD卡到XME0724底板上，上电启动。
|
|
||||||
|
|
||||||
4. 终端软件连接底板上的串口，波特率115200，8位，1停止位，无校验
|
|
||||||
|
|
||||||
> 注意：github的release中包含了修改完成的`rootfs.tar.gz`，因此无需重复下面的步骤，这里仅用作记录修改步骤
|
|
||||||
|
|
||||||
5. 修改`/etc/shadow`文件，将`root`用户的密码删除，切换到`root`用户并设定密码为`3703`，具体命令如下:
|
|
||||||
|
|
||||||
```shell
|
|
||||||
$ sudo sed "1c root::15069:0:99999:7:::" /etc/shadow
|
|
||||||
# 如果没有sed命令，用任何其他方式都可以，比如vim
|
|
||||||
$ su root
|
|
||||||
$ passwd
|
|
||||||
```
|
|
||||||
|
|
||||||
|
|
||||||
6. 配置网络和`ssh`服务，用`root`登录：
|
|
||||||
|
|
||||||
```shell
|
|
||||||
$ vi /etc/network/interfaces
|
|
||||||
添加或确认内容如下：
|
|
||||||
auto eth0
|
|
||||||
iface eth0 inet static
|
|
||||||
address 192.168.10.10
|
|
||||||
netmask 255.255.255.0
|
|
||||||
gateway 192.168.10.1
|
|
||||||
$ vi /etc/ssh/sshd_config
|
|
||||||
确认修改如下选项：
|
|
||||||
PermitRootLogin yes
|
|
||||||
PermitEmptyPasswords yes
|
|
||||||
PasswordAuthentication yes
|
|
||||||
$ reboot
|
|
||||||
```
|
|
||||||
|
|
||||||
7. 电脑网卡设置到开发板同一网段 SSH连接信息如下
|
|
||||||
|
|
||||||
```shell
|
|
||||||
在电脑上执行下面命令
|
|
||||||
$ sshpass -p "3703" ssh root@192.168.10.10 -p 22
|
|
||||||
```
|
|
||||||
|
|
||||||
8. 安装编译得到的驱动文件`encode.ko`，并设置自动加载，对应自启脚本可以如下方式写入，也可以直接上传[script/loadencoder.sh](../script/loadencoder.sh)，ssh方式，`root`登录:
|
|
||||||
|
|
||||||
```shell
|
|
||||||
上传encoder.ko到/lib/modules/[内核版本]/extra/
|
|
||||||
$ cd /lib/modules/[内核版本]/extra/; depmod
|
|
||||||
$ set +H
|
|
||||||
$ echo -e "#!/bin/sh\nmodprobe encoder" > /etc/init.d/loadencoder.sh
|
|
||||||
$ chmod 755 /etc/init.d/loadencoder.sh
|
|
||||||
$ cd /etc/rc5.d
|
|
||||||
$ ln -s ../init.d/loadencoder.sh S20loadencoder.sh
|
|
||||||
```
|
|
||||||
|
|
||||||
9. 安装编译得到的应用程序target，并设置自启动，对应脚本见[script/target.sh](../script/target.sh)
|
|
||||||
|
|
||||||
ssh方式，root登录:
|
|
||||||
|
|
||||||
```shell
|
|
||||||
上传target到/home/root
|
|
||||||
$ cd ~
|
|
||||||
$ chmod 755 target
|
|
||||||
$ set +H
|
|
||||||
$ echo -e "#!/bin/sh\nif [ -x /home/root/target ]; then\n /home/root/target\nfi" > /etc/init.d/target.sh
|
|
||||||
$ chmod 755 /etc/init.d/target.sh
|
|
||||||
$ cd /etc/rc5.d
|
|
||||||
$ ln -s ../init.d/target.sh S99target.sh
|
|
||||||
```
|
|
||||||
|
|
||||||
10. \[可选\] 设置`.bashrc`，修改`PS1`，对应脚本见[script/.profile](../script/.profile)和[script/.bashrc](../script/.bashrc)
|
|
||||||
|
|
||||||
```shell
|
|
||||||
$ cd ~; rm .bashrc .profile
|
|
||||||
上传.bashrc和.profile到/home/root
|
|
||||||
$ if [ ! -a /home/petalinux/.profile ]; then cp /home/ root/.profile /home/petalinux/ fi
|
|
||||||
$ if [ ! -a /home/petalinux/.bashrc ]; then cp /home/root/. bashrc /home/petalinux/ & chown petalinux:petalinux -R / home/petalinux fi
|
|
||||||
$ source ~/.profile
|
|
||||||
```
|
|
||||||
|
|
||||||
11. \[可选\] 安装`ncurses-6.3`和`htop`
|
|
||||||
|
|
||||||
```shell
|
|
||||||
$ cd ~; rz # 上传ncurses-6.3.tar.gz
|
|
||||||
$ tar xmzf /home/root/ncurses-6.3.tar.gz -C /usr/
|
|
||||||
$ rz # 上传htop.tar.gz
|
|
||||||
$ tar xmzf /home/root/htop.tar.gz -C /usr/
|
|
||||||
$ echo "export TERMINFO=/usr/share/terminfo" >> /etc/profile
|
|
||||||
$ reboot
|
|
||||||
```
|
|
||||||
|
|
||||||
### 直接写入镜像
|
|
||||||
|
|
||||||
强烈推荐的傻瓜式的方法，在windows上准备好正版[DiskGenius标准版或专业版](https://www.diskgenius.cn/)，盗版有概率写入错误数据，从release中下载`sdimage.pmfx`文件
|
|
||||||
|
|
||||||
1. 在windows上插入16G的TF卡
|
|
||||||
2. 打开`DiskGenius`
|
|
||||||
3. 左侧栏选中TF卡，右键，从镜像文件还原磁盘
|
|
||||||
4. 选`sdimage.pmfx`文件
|
|
||||||
5. 点击开始
|
|
||||||
|
|
||||||
把TF卡插回板子，启动方式拨到SD卡启动，上电。要进入系统，参考修改文件系统章节的第7步。
|
|
||||||
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|
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@ -1,46 +0,0 @@
|
|||||||
# 硬件平台
|
|
||||||
|
|
||||||
PL端主要由2个外设组成，分别时**风扇控制器**(FAN)，**编码和分频控制器**(ENCODER)，各个控制器的连接关系如下图所示。
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
由于开发板的PL端没有自带晶振，所以2个外设由统一的同步时钟驱动，时钟源来自PS端，为200MHz，软件不可修改。外部编码器信号和物体检测传感器信号输入**编码和分频控制器**，控制器根据软件设置的阀触发分频值和相机触发分频值对编码器信号进行分频，分频后的信号用于触发相机拍照。
|
|
||||||
|
|
||||||
**风扇控制器**用于驱动风扇的启停，给ZYNQ芯片进行降温，防止芯片过热导致工作中出现问题。由于风扇寿命短，因此目前采用散热片方案，风扇不开。
|
|
||||||
|
|
||||||
## PS模块
|
|
||||||
|
|
||||||
下面列出需要开启的外设和采用的IO口，BANK0为LVCMOS3.3V，BANK1为LVCOMS1.8V
|
|
||||||
|
|
||||||
| 外设 | IO | 备注 |
|
|
||||||
| --------------------------------------------------- | ---------------------- | -------------------------------------- |
|
|
||||||
| Quad SPI Flash | 1~6 | Single SS 4bit IO，Fast , ss_b pullup |
|
|
||||||
| Ethernet 0<br />MDIO | 16~27<br /> 52~53 | Fast, all pullup |
|
|
||||||
| USB0 | 28~39 | Fast, all pullup |
|
|
||||||
| SD0 | 40~45 | Fast, all pullup |
|
|
||||||
| SD1 | 46~51 | Fast, all pullup |
|
|
||||||
| UART0 | 14~15 | all pullup, baud 115200, 8bits, 1 stop |
|
|
||||||
| TTC0 | EMIO | |
|
|
||||||
| GPIO MIO<br />Ethernet PHY Reset<br />USB PHY Reset | 所有剩下的<br/>7<br/>8 | Fast, all pullup |
|
|
||||||
|
|
||||||
时钟配置上，ARM为666.66MHz，DDR为533.33MHz，用IOPLL给PL端提供200MHz的FCLK_CLK0。
|
|
||||||
|
|
||||||
如果用的是7010的板子，内存选忽略下面这一段：内存配置上，选择DDR3，数据位宽32bit=16bit/chip \* 2chip, 4096Mbits/chip，频率533.33，速度等级为1066F，行/列/Bank地址宽度为15/10/3，CL=7，CWL=6，RCD=7，RP=7，RC=51ns，FAW=40ns
|
|
||||||
|
|
||||||
ARM核上还开启AXI GP0接口与PL通信
|
|
||||||
|
|
||||||
## ENCODER模块
|
|
||||||
|
|
||||||
encoder模块主要接口为in_signal、out_signal_camera_a_posedge、out_signal_camera_b_posedge、out_signal_camera_c_posedge、out_signal_camera_d_posedge、out_signal_valve_posedge、out_signal_camera_a、out_signal_camera_b、out_signal_camera_c、out_signal_camera_d、out_signal_valve、exrst_n
|
|
||||||
|
|
||||||
终于，我们重新实现了被老倪乱起八糟的需求搞的几乎奔溃的模块，现在这个模块已经比较简洁了
|
|
||||||
|
|
||||||
1. in_signal接口与外部编码器相连，接收外部编码器信号
|
|
||||||
2. out_signal_camera_a到d最多课用于触发共4个相机
|
|
||||||
3. out_signal_camera_posedge_a到d为上述信号的上升沿，固定不连接。
|
|
||||||
4. out_signal_valve_posedge为out_signal_valve的上升沿，固定不连接。
|
|
||||||
5. exrst_n为可选的外部复位清零信号，可用于连接物体传感器，根据需要屏蔽相机触发输出
|
|
||||||
|
|
||||||
|
|
||||||
ENCODER模块输入输出频率的详细计算方式和寄存器说明见[doc/pl_reference_mannual.md](pl_reference_mannual.md)中的ENCODER控制器部分
|
|
||||||
|
|
||||||
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|
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|
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|
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|
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|
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@ -1 +0,0 @@
|
|||||||
<svg width="1226" height="662" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xml:space="preserve" overflow="hidden"><defs><clipPath id="clip0"><rect x="1440" y="922" width="1226" height="662"/></clipPath></defs><g clip-path="url(#clip0)" transform="translate(-1440 -922)"><path d="M1440 1415 1594.99 1415" stroke="#B4C7E7" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1467 1140 1621.66 1140" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2504 1228 2658.66 1228" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1551.5 984.391C1551.5 951.866 1577.87 925.5 1610.39 925.5L2503.61 925.5C2536.13 925.5 2562.5 951.866 2562.5 984.391L2562.5 1521.61C2562.5 1554.13 2536.13 1580.5 2503.61 1580.5L1610.39 1580.5C1577.87 1580.5 1551.5 1554.13 1551.5 1521.61Z" stroke="#2F5597" stroke-width="6.875" stroke-miterlimit="8" fill="#DAE3F3" fill-rule="evenodd"/><text font-family="Arial,Arial_MSFontService,sans-serif" font-weight="700" font-size="73" transform="matrix(1 0 0 1 2378.67 1268)">SPD<tspan font-size="73" x="-800.976" y="-85">EN</tspan><tspan fill="#767171" font-size="73" x="-800.976" y="162">FAN</tspan></text></g></svg>
|
|
||||||
|
Before Width: | Height: | Size: 1.3 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 4.9 KiB |
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|
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|
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@ -1 +0,0 @@
|
|||||||
<svg width="1398" height="862" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xml:space="preserve" overflow="hidden"><defs><clipPath id="clip0"><rect x="1180" y="712" width="1398" height="862"/></clipPath></defs><g clip-path="url(#clip0)" transform="translate(-1180 -712)"><path d="M1180 1330 1356.99 1330" stroke="#2F5597" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1180 1214 1356.99 1214" stroke="#2F5597" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1180 1087 1356.99 1087" stroke="#2F5597" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385.5 855.5 2562.49 855.5" stroke="#B4C7E7" stroke-width="20.625" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385 973 2561.99 973.001" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385 1093 2561.99 1093" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385 1214 2561.99 1214" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385 1330 2561.99 1330" stroke="#2F5597" stroke-width="10.3125" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M2385.5 1447.5 2562.49 1447.5" stroke="#2F5597" stroke-width="20.625" stroke-linecap="square" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1180 844 1334.99 844" stroke="#B4C7E7" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1180 962 1356.99 962.001" stroke="#B4C7E7" stroke-width="10.3125" stroke-miterlimit="8" fill="none" fill-rule="evenodd"/><path d="M1289.5 792.373C1289.5 749.917 1323.92 715.5 1366.37 715.5L2369.63 715.5C2412.08 715.5 2446.5 749.917 2446.5 792.373L2446.5 1493.63C2446.5 1536.08 2412.08 1570.5 2369.63 1570.5L1366.37 1570.5C1323.92 1570.5 1289.5 1536.08 1289.5 1493.63Z" stroke="#2F5597" stroke-width="6.875" stroke-miterlimit="8" fill="#DAE3F3" fill-rule="evenodd"/><text fill="#767171" font-family="Arial,Arial_MSFontService,sans-serif" font-weight="700" font-size="73" transform="matrix(1 0 0 1 1874.98 867)">DT_OUT<tspan font-size="73" x="292.76" y="0">[</tspan><tspan font-size="73" x="317.396" y="0">383:0</tspan><tspan font-size="73" x="504.74" y="0">]</tspan><tspan fill="#000000" font-size="73" x="236.615" y="124">xEMPTY</tspan><tspan fill="#000000" font-size="73" x="342.604" y="247">FULL</tspan><tspan fill="#000000" font-size="73" x="-72.7605" y="370">ALMOST_EMPTY</tspan><tspan fill="#000000" font-size="73" x="-7.448" y="493">ALMOST_FULL</tspan><tspan fill="#000000" font-size="73" x="73.3333" y="616">COUNT[11:0]</tspan><tspan font-size="73" x="-518.112" y="0">FIFO_VALID</tspan><tspan font-size="73" x="-518.112" y="124">RD_SYN</tspan><tspan fill="#000000" font-size="73" x="-518.112" y="247">WR_SYN</tspan><tspan fill="#000000" font-size="73" x="-518.112" y="370">CLEAR</tspan><tspan fill="#000000" font-size="73" x="-518.112" y="493">DT_IN</tspan><tspan fill="#000000" font-size="73" x="-306.705" y="493">[383:0]</tspan></text></g></svg>
|
|
||||||
|
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|
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@ -1,139 +0,0 @@
|
|||||||
# PL 端自定义外设参考手册
|
|
||||||
|
|
||||||
## 存储器和总线架构
|
|
||||||
|
|
||||||
### 系统架构
|
|
||||||
|
|
||||||
PL端主要由2个外设组成，分别时**风扇控制器**(FAN)，**编码和分频控制器**(ENCODER)。各个控制器的连接关系如下图所示。
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
2个外设由统一的同步时钟驱动，时钟源来自PS端，为200MHz，软件不可修改。外部编码器信号和物体传感器信号输入**编码和分频控制器**，控制器根据软件设置的相机触发分频值对编码器信号进行分频。为同步触发相机。
|
|
||||||
|
|
||||||
具体的硬件设计和信号说明见[doc/hardware_description.md](hardware_description.md)
|
|
||||||
|
|
||||||
各控制器的边界地址和所属总线等信息如下表所示
|
|
||||||
|
|
||||||
| 边界地址 | 外设 | 总线 |
|
|
||||||
| ----------------------- | ---------------- | --------- |
|
|
||||||
| 0x43c10000 - 0x43c1ffff | 编码和分频控制器 | M_AXI_GP0 |
|
|
||||||
| 0x43c20000 - 0x43c2ffff | 风扇控制器 | M_AXI_GP0 |
|
|
||||||
|
|
||||||
## 风扇控制器 (FAN)
|
|
||||||
|
|
||||||
### FAN简介
|
|
||||||
|
|
||||||
FAN模块用于控 制散热风扇的启停以及通过PWM调整风扇速度。通过对寄存器写入值，该模块能正常启停散热风扇，但由于代码与硬件兼容问题，导致无法观察到调速现象。
|
|
||||||
|
|
||||||
### FAN主要特性
|
|
||||||
|
|
||||||
- 能控制风扇的启停
|
|
||||||
- 自定义占空比，调整风扇转速
|
|
||||||
|
|
||||||
### FAN功能说明
|
|
||||||
|
|
||||||
<img src="pl_reference_mannual.assets/fan_block.svg" alt="fan_block" style="zoom:20%;" />
|
|
||||||
|
|
||||||
通过将开启使能拉高，开启风扇。通过向风速寄存器写入PWM占空值，控制风扇减少或提高风速。
|
|
||||||
|
|
||||||
### FAN寄存器说明
|
|
||||||
|
|
||||||
FAN模块寄存器主要包括控制寄存器 (FAN_CR)、风速寄存器 (FAN_SPDR)。控制寄存器 (FAN_CR)用于控制风扇开启或关闭的状态，风速寄存器 (FAN_SPDR)通过PWM技术设置风扇转动的速度。
|
|
||||||
|
|
||||||
**Base Address: 0x43c20000**
|
|
||||||
|
|
||||||
#### FAN控制寄存器 (FAN_CR)
|
|
||||||
|
|
||||||
偏移地址: 0x00<br/>复位值: 0x0000 0000
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
| **Field** | **Description** |
|
|
||||||
| :----------- | :----------------------------------------------------------- |
|
|
||||||
| 位31:16 保留 | 必须保持复位值 |
|
|
||||||
| 位0 **EN** | 内部触发信号 (Virtual Triggle Signal)<br /> 0: 停止风扇<br/> 1: 开启风扇 |
|
|
||||||
|
|
||||||
#### FAN风速寄存器 (FAN_SPDR)
|
|
||||||
|
|
||||||
偏移地址: 0x04<br/>复位值: 0x0000 0000
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
| **Field** | **Description** |
|
|
||||||
| :------------- | :----------------------------------------------------------- |
|
|
||||||
| 位31:0 **SPD** | 该寄存器值表示设置的风扇PWM占空值，占空比转换公式如下。<br />占空比% = SPD / (2 ^ 32 - 1) * 100% |
|
|
||||||
|
|
||||||
#### FAN寄存器映射
|
|
||||||
|
|
||||||
FAN寄存器可映射为32位可寻址寄存器，如下表所述：
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
## 编码和分频控制器 (ENCODER)
|
|
||||||
|
|
||||||
### ENCODER简介
|
|
||||||
|
|
||||||
ENCODER模块主要用于实现编码器计数以及对编码器脉冲进行分频，分频后的脉冲信号输出给相机。该模块包括1个控制寄存器 (ENCODER_CR)、阀触发分频寄存器 (ENCODER_VDIVR)、相机触发分频寄存器 (ENCODER_CDIVR)。
|
|
||||||
|
|
||||||
### ENCODER主要特性
|
|
||||||
|
|
||||||
- 独立设置对相机和喷阀的分频系数
|
|
||||||
- 内外两种触发模式选择
|
|
||||||
- 可选的外部清零方式
|
|
||||||
|
|
||||||
### ENCODER功能说明
|
|
||||||
|
|
||||||
下图给出了ENCODER的主要信号：
|
|
||||||
|
|
||||||
<img src="pl_reference_mannual.assets/encoder_block.svg" alt="图片1" style="zoom: 20%;" />
|
|
||||||
|
|
||||||
ENCODER模块接收编码器脉冲信号，通过设置的相机和喷阀分频系数，生成对应的触发信号。编码器脉冲信号可由内部或外部触发模式产生。
|
|
||||||
|
|
||||||
### ENCODER寄存器说明
|
|
||||||
|
|
||||||
ENCODER模块的寄存器主要有控制寄存器 (ENCODER_CR)、阀触发分频寄存器 (ENCODER_VDIVR)和相机触发分频寄存器 (ENCODER_CDIVR)。控制寄存器 (ENCODER_CR)用于进行触发模式选择以及复位清空，阀触发分频寄存器 (ENCODER_VDIVR)用于寄存输入的分频系数，将编码器脉冲除以分频系数得到触发脉冲。
|
|
||||||
|
|
||||||
**Base Address: 0x43c10000**
|
|
||||||
|
|
||||||
#### ENCODER控制寄存器 (ENCODER_CR)
|
|
||||||
|
|
||||||
偏移地址: 0x00<br/>复位值: 0x0000 0008
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
| **Field** | **Description** |
|
|
||||||
| :---------- | :----------------------------------------------------------- |
|
|
||||||
| 位31:4 保留 | 必须保持复位值 |
|
|
||||||
| 位3 **ICO** | 仅限内部清除缓存 (Internal Clear Only)<br /> 0: 同时允许由外部输入**Ex CLR**和清除缓存位**CLR**控制进入清零状态<br /> 清零状态见位**CLR**的描述；外部输入为高时，退出清零状态<br /> 1: 仅限内部信号清除缓存 |
|
|
||||||
| 位2 **VTS** | 内部触发信号 (Virtual Triggle Signal)<br /> **MOD**位置1时，由软件写入，将该位信号直接充当触发信号<br /> 0: 低电平<br /> 1: 高电平 |
|
|
||||||
| 位1 **MOD** | 模式选择 (Mode)<br /> 0: 外部触发模式，外部触发编码器转动<br /> 1: 内部触发模式，软件模拟触发信号 |
|
|
||||||
| 位0 **CLR** | 清除缓存 (Clear)<br /> 0: 清除编码和分频控制器内部的分频计数值，不影响ENCODER_VDIVR和ENCODER_CDIVRx<br /> 注意: 程序清零该位后需再写入1，使计数器退出清零状态，正常工作 <br /> 1: 正常工作 |
|
|
||||||
|
|
||||||
#### ENCODER阀触发分频寄存器 (ENCODER_VDIVR)
|
|
||||||
|
|
||||||
偏移地址: 0x04<br/>复位值: 0x0000 0000
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
| **Field** | **Description** |
|
|
||||||
| :-------------- | :----------------------------------------------------------- |
|
|
||||||
| 位31:0 **VDIV** | 阀触发分频值<br /> 阀控制器重采样频率和编码器脉冲的分频值， 写入数据后编码和分频控制器自动清除缓存并应用新的数值 <br /> 注意：0表示不间断触发，即PL端每个时钟周期均触发阀模块 |
|
|
||||||
|
|
||||||
#### ENCODER相机触发分频寄存器 (ENCODER_CDIVRx) (x=A...D)
|
|
||||||
|
|
||||||
用于设定相机A到相机D的分频系数，各相机可独立设置
|
|
||||||
|
|
||||||
偏移地址: 0x08<br/>复位值: 0x0000 0000
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
| **Field** | **Description** |
|
|
||||||
| :-------------- | :----------------------------------------------------------- |
|
|
||||||
| 位31:0 **CDIV** | 相机触发分频值<br /> 写入数据后编码和分频控制器自动清除缓存并应用新的数值 <br /> 注意：0表示不间断触发，即PL端每个时钟周期均触发相机 |
|
|
||||||
|
|
||||||
#### ENCODER寄存器映射
|
|
||||||
|
|
||||||
ENCODER寄存器可映射为32位可寻址寄存器，如下表所述：
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
Binary file not shown.
|
Before Width: | Height: | Size: 73 KiB |
@ -1,11 +0,0 @@
|
|||||||
# 模拟上位机说明文档
|
|
||||||
|
|
||||||
## 模拟上位机连接下位机
|
|
||||||
|
|
||||||
模拟上位机使用python编写，如下图所示，实现显示界面并与下位机通信发送四个相机的分频值。运行程序后，出现显示界面，连接网线并选择Server IP为运行模拟上位机程序的本机系统中手动设定的IP地址，Server Port端号为13452(默认)。选择完成后等待连接，当界面下方出现本机与下位机的IP地址时即为连接成功。
|
|
||||||
|
|
||||||
## 模拟上位机发送指令
|
|
||||||
|
|
||||||
模拟上位机与下位机连接成功后，可在MANUAL栏中发送通信协议中对应的命令，在PRESET栏中填写四个相机触发所需的分频值，在发送分频值前，需要先点击停止按钮，然后点击对应的A、B、C、D按钮即可发送各相机对应的分频值，最后点击Start按钮即可将分频值发送给下位机。
|
|
||||||
|
|
||||||
|
|
||||||
@ -1 +0,0 @@
|
|||||||
1.7
|
|
||||||
|
Before Width: | Height: | Size: 9.3 KiB After Width: | Height: | Size: 9.3 KiB |
|
Before Width: | Height: | Size: 8.6 KiB After Width: | Height: | Size: 8.6 KiB |
|
Before Width: | Height: | Size: 4.1 KiB After Width: | Height: | Size: 4.1 KiB |
|
Before Width: | Height: | Size: 6.5 KiB After Width: | Height: | Size: 6.5 KiB |
|
Before Width: | Height: | Size: 9.4 KiB After Width: | Height: | Size: 9.4 KiB |
|
Before Width: | Height: | Size: 12 KiB After Width: | Height: | Size: 12 KiB |
|
Before Width: | Height: | Size: 5.7 KiB After Width: | Height: | Size: 5.7 KiB |
|
Before Width: | Height: | Size: 8.8 KiB After Width: | Height: | Size: 8.8 KiB |
|
Before Width: | Height: | Size: 6.5 KiB After Width: | Height: | Size: 6.5 KiB |
|
Before Width: | Height: | Size: 6.7 KiB After Width: | Height: | Size: 6.7 KiB |
|
Before Width: | Height: | Size: 9.6 KiB After Width: | Height: | Size: 9.6 KiB |
|
Before Width: | Height: | Size: 8.5 KiB After Width: | Height: | Size: 8.5 KiB |
|
Before Width: | Height: | Size: 5.3 KiB After Width: | Height: | Size: 5.3 KiB |
|
Before Width: | Height: | Size: 5.9 KiB After Width: | Height: | Size: 5.9 KiB |
@ -1,648 +0,0 @@
|
|||||||
|
|
||||||
################################################################
|
|
||||||
# This is a generated script based on design: system
|
|
||||||
#
|
|
||||||
# Though there are limitations about the generated script,
|
|
||||||
# the main purpose of this utility is to make learning
|
|
||||||
# IP Integrator Tcl commands easier.
|
|
||||||
################################################################
|
|
||||||
|
|
||||||
namespace eval _tcl {
|
|
||||||
proc get_script_folder {} {
|
|
||||||
set script_path [file normalize [info script]]
|
|
||||||
set script_folder [file dirname $script_path]
|
|
||||||
return $script_folder
|
|
||||||
}
|
|
||||||
}
|
|
||||||
variable script_folder
|
|
||||||
set script_folder [_tcl::get_script_folder]
|
|
||||||
|
|
||||||
################################################################
|
|
||||||
# Check if script is running in correct Vivado version.
|
|
||||||
################################################################
|
|
||||||
set scripts_vivado_version 2022.1
|
|
||||||
set current_vivado_version [version -short]
|
|
||||||
|
|
||||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
|
||||||
puts ""
|
|
||||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
|
||||||
|
|
||||||
return 1
|
|
||||||
}
|
|
||||||
|
|
||||||
################################################################
|
|
||||||
# START
|
|
||||||
################################################################
|
|
||||||
|
|
||||||
# To test this script, run the following commands from Vivado Tcl console:
|
|
||||||
# source system_script.tcl
|
|
||||||
|
|
||||||
# If there is no project opened, this script will create a
|
|
||||||
# project, but make sure you do not have an existing project
|
|
||||||
# <./myproj/project_1.xpr> in the current working folder.
|
|
||||||
|
|
||||||
set list_projs [get_projects -quiet]
|
|
||||||
if { $list_projs eq "" } {
|
|
||||||
create_project project_1 myproj -part xc7z010clg400-1
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
# CHANGE DESIGN NAME HERE
|
|
||||||
variable design_name
|
|
||||||
set design_name system
|
|
||||||
|
|
||||||
# If you do not already have an existing IP Integrator design open,
|
|
||||||
# you can create a design using the following command:
|
|
||||||
# create_bd_design $design_name
|
|
||||||
|
|
||||||
# Creating design if needed
|
|
||||||
set errMsg ""
|
|
||||||
set nRet 0
|
|
||||||
|
|
||||||
set cur_design [current_bd_design -quiet]
|
|
||||||
set list_cells [get_bd_cells -quiet]
|
|
||||||
|
|
||||||
if { ${design_name} eq "" } {
|
|
||||||
# USE CASES:
|
|
||||||
# 1) Design_name not set
|
|
||||||
|
|
||||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
|
||||||
set nRet 1
|
|
||||||
|
|
||||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
|
||||||
# USE CASES:
|
|
||||||
# 2): Current design opened AND is empty AND names same.
|
|
||||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
|
||||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
|
||||||
|
|
||||||
if { $cur_design ne $design_name } {
|
|
||||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
|
||||||
set design_name [get_property NAME $cur_design]
|
|
||||||
}
|
|
||||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
|
||||||
|
|
||||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
|
||||||
# USE CASES:
|
|
||||||
# 5) Current design opened AND has components AND same names.
|
|
||||||
|
|
||||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|
||||||
set nRet 1
|
|
||||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
|
||||||
# USE CASES:
|
|
||||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
|
||||||
# 7) No opened design, design_name exists in project.
|
|
||||||
|
|
||||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
|
||||||
set nRet 2
|
|
||||||
|
|
||||||
} else {
|
|
||||||
# USE CASES:
|
|
||||||
# 8) No opened design, design_name not in project.
|
|
||||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
|
||||||
|
|
||||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
|
||||||
|
|
||||||
create_bd_design $design_name
|
|
||||||
|
|
||||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
|
||||||
current_bd_design $design_name
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
|
||||||
|
|
||||||
if { $nRet != 0 } {
|
|
||||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
|
||||||
return $nRet
|
|
||||||
}
|
|
||||||
|
|
||||||
set bCheckIPsPassed 1
|
|
||||||
##################################################################
|
|
||||||
# CHECK IPs
|
|
||||||
##################################################################
|
|
||||||
set bCheckIPs 1
|
|
||||||
if { $bCheckIPs == 1 } {
|
|
||||||
set list_check_ips "\
|
|
||||||
user.org:user:ip_encoder:1.1\
|
|
||||||
user.org:user:ip_fan:1.0\
|
|
||||||
xilinx.com:ip:processing_system7:5.5\
|
|
||||||
xilinx.com:ip:proc_sys_reset:5.0\
|
|
||||||
"
|
|
||||||
|
|
||||||
set list_ips_missing ""
|
|
||||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
|
||||||
|
|
||||||
foreach ip_vlnv $list_check_ips {
|
|
||||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
|
||||||
if { $ip_obj eq "" } {
|
|
||||||
lappend list_ips_missing $ip_vlnv
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if { $list_ips_missing ne "" } {
|
|
||||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
|
||||||
set bCheckIPsPassed 0
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
if { $bCheckIPsPassed != 1 } {
|
|
||||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
|
||||||
return 3
|
|
||||||
}
|
|
||||||
|
|
||||||
##################################################################
|
|
||||||
# DESIGN PROCs
|
|
||||||
##################################################################
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
# Procedure to create entire design; Provide argument to make
|
|
||||||
# procedure reusable. If parentCell is "", will use root.
|
|
||||||
proc create_root_design { parentCell } {
|
|
||||||
|
|
||||||
variable script_folder
|
|
||||||
variable design_name
|
|
||||||
|
|
||||||
if { $parentCell eq "" } {
|
|
||||||
set parentCell [get_bd_cells /]
|
|
||||||
}
|
|
||||||
|
|
||||||
# Get object for parentCell
|
|
||||||
set parentObj [get_bd_cells $parentCell]
|
|
||||||
if { $parentObj == "" } {
|
|
||||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
|
||||||
return
|
|
||||||
}
|
|
||||||
|
|
||||||
# Make sure parentObj is hier blk
|
|
||||||
set parentType [get_property TYPE $parentObj]
|
|
||||||
if { $parentType ne "hier" } {
|
|
||||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
|
||||||
return
|
|
||||||
}
|
|
||||||
|
|
||||||
# Save current instance; Restore later
|
|
||||||
set oldCurInst [current_bd_instance .]
|
|
||||||
|
|
||||||
# Set parent object as current
|
|
||||||
current_bd_instance $parentObj
|
|
||||||
|
|
||||||
|
|
||||||
# Create interface ports
|
|
||||||
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
|
|
||||||
|
|
||||||
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
|
|
||||||
|
|
||||||
|
|
||||||
# Create ports
|
|
||||||
set encoder_signal [ create_bd_port -dir I encoder_signal ]
|
|
||||||
set exrst_n [ create_bd_port -dir I exrst_n ]
|
|
||||||
set fan [ create_bd_port -dir O fan ]
|
|
||||||
set out_signal_camera_a [ create_bd_port -dir O out_signal_camera_a ]
|
|
||||||
set out_signal_camera_b [ create_bd_port -dir O out_signal_camera_b ]
|
|
||||||
set out_signal_camera_c [ create_bd_port -dir O out_signal_camera_c ]
|
|
||||||
set out_signal_camera_d [ create_bd_port -dir O out_signal_camera_d ]
|
|
||||||
|
|
||||||
# Create instance: ip_encoder_0, and set properties
|
|
||||||
set ip_encoder_0 [ create_bd_cell -type ip -vlnv user.org:user:ip_encoder:1.1 ip_encoder_0 ]
|
|
||||||
|
|
||||||
# Create instance: ip_fan_0, and set properties
|
|
||||||
set ip_fan_0 [ create_bd_cell -type ip -vlnv user.org:user:ip_fan:1.0 ip_fan_0 ]
|
|
||||||
|
|
||||||
# Create instance: processing_system7_0, and set properties
|
|
||||||
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
|
|
||||||
set_property -dict [ list \
|
|
||||||
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
|
|
||||||
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
|
|
||||||
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
|
|
||||||
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
|
|
||||||
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
|
|
||||||
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {200.000000} \
|
|
||||||
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
|
|
||||||
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
|
|
||||||
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
|
|
||||||
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
|
|
||||||
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
|
|
||||||
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \
|
|
||||||
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
|
|
||||||
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
|
|
||||||
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
|
|
||||||
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
|
||||||
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
|
||||||
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
|
||||||
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
|
||||||
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
|
||||||
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
|
||||||
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
|
|
||||||
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
|
|
||||||
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
|
|
||||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
|
|
||||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
|
|
||||||
CONFIG.PCW_CLK0_FREQ {200000000} \
|
|
||||||
CONFIG.PCW_CLK1_FREQ {10000000} \
|
|
||||||
CONFIG.PCW_CLK2_FREQ {10000000} \
|
|
||||||
CONFIG.PCW_CLK3_FREQ {10000000} \
|
|
||||||
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
|
|
||||||
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
|
|
||||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
|
|
||||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
|
|
||||||
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
|
|
||||||
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
|
|
||||||
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
|
|
||||||
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
|
|
||||||
CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
|
|
||||||
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
|
|
||||||
CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
|
|
||||||
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
|
|
||||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
|
|
||||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
|
|
||||||
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
|
|
||||||
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
|
|
||||||
CONFIG.PCW_ENET0_RESET_ENABLE {1} \
|
|
||||||
CONFIG.PCW_ENET0_RESET_IO {MIO 7} \
|
|
||||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
|
|
||||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
|
|
||||||
CONFIG.PCW_ENET1_RESET_ENABLE {0} \
|
|
||||||
CONFIG.PCW_ENET_RESET_ENABLE {1} \
|
|
||||||
CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
|
|
||||||
CONFIG.PCW_EN_EMIO_ENET0 {0} \
|
|
||||||
CONFIG.PCW_EN_EMIO_SDIO1 {0} \
|
|
||||||
CONFIG.PCW_EN_EMIO_TTC0 {1} \
|
|
||||||
CONFIG.PCW_EN_EMIO_UART0 {0} \
|
|
||||||
CONFIG.PCW_EN_ENET0 {1} \
|
|
||||||
CONFIG.PCW_EN_GPIO {1} \
|
|
||||||
CONFIG.PCW_EN_QSPI {1} \
|
|
||||||
CONFIG.PCW_EN_SDIO0 {1} \
|
|
||||||
CONFIG.PCW_EN_SDIO1 {1} \
|
|
||||||
CONFIG.PCW_EN_TTC0 {1} \
|
|
||||||
CONFIG.PCW_EN_UART0 {1} \
|
|
||||||
CONFIG.PCW_EN_USB0 {1} \
|
|
||||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
|
|
||||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {1} \
|
|
||||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
|
|
||||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
|
|
||||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
|
|
||||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
|
|
||||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
|
|
||||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
|
|
||||||
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {200} \
|
|
||||||
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
|
|
||||||
CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
|
|
||||||
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
|
|
||||||
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
|
|
||||||
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
|
|
||||||
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
|
|
||||||
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
|
|
||||||
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
|
|
||||||
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
|
|
||||||
CONFIG.PCW_I2C_RESET_ENABLE {1} \
|
|
||||||
CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
|
|
||||||
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
|
|
||||||
CONFIG.PCW_MIO_0_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_0_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_0_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_10_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_10_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_10_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_11_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_11_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_11_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_12_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_12_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_12_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_13_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_13_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_13_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_14_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_14_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_14_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_15_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_15_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_15_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_16_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_16_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_16_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_17_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_17_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_17_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_18_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_18_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_18_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_19_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_19_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_19_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_1_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_1_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_1_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_20_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_20_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_20_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_21_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_21_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_21_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_22_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_22_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_22_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_23_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_23_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_23_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_24_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_24_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_24_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_25_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_25_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_25_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_26_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_26_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_26_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_27_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_27_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_27_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_28_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_28_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_28_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_29_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_29_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_29_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_2_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_2_PULLUP {disabled} \
|
|
||||||
CONFIG.PCW_MIO_2_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_30_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_30_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_30_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_31_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_31_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_31_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_32_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_32_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_32_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_33_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_33_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_33_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_34_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_34_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_34_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_35_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_35_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_35_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_36_DIRECTION {in} \
|
|
||||||
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_36_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_36_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_37_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_37_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_37_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_38_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_38_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_38_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_39_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_39_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_39_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_3_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_3_PULLUP {disabled} \
|
|
||||||
CONFIG.PCW_MIO_3_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_40_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_40_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_40_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_41_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_41_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_41_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_42_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_42_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_42_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_43_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_43_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_43_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_44_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_44_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_44_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_45_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_45_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_45_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_46_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_46_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_46_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_47_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_47_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_47_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_48_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_48_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_48_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_49_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_49_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_49_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_4_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_4_PULLUP {disabled} \
|
|
||||||
CONFIG.PCW_MIO_4_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_50_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_50_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_50_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_51_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_51_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_51_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_52_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_52_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_52_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_53_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_MIO_53_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_53_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_5_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_5_PULLUP {disabled} \
|
|
||||||
CONFIG.PCW_MIO_5_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_6_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_6_PULLUP {disabled} \
|
|
||||||
CONFIG.PCW_MIO_6_SLEW {fast} \
|
|
||||||
CONFIG.PCW_MIO_7_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_7_PULLUP {disabled} \
|
|
||||||
CONFIG.PCW_MIO_7_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_8_DIRECTION {out} \
|
|
||||||
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_8_PULLUP {disabled} \
|
|
||||||
CONFIG.PCW_MIO_8_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_9_DIRECTION {inout} \
|
|
||||||
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
|
|
||||||
CONFIG.PCW_MIO_9_PULLUP {enabled} \
|
|
||||||
CONFIG.PCW_MIO_9_SLEW {slow} \
|
|
||||||
CONFIG.PCW_MIO_TREE_PERIPHERALS {\
|
|
||||||
GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI\
|
|
||||||
Flash#Quad SPI Flash#ENET Reset#USB Reset#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART\
|
|
||||||
0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet\
|
|
||||||
0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\
|
|
||||||
0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0} \
|
|
||||||
CONFIG.PCW_MIO_TREE_SIGNALS {\
|
|
||||||
gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#reset#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#data[0]#cmd#clk#data[1]#data[2]#data[3]#mdc#mdio} \
|
|
||||||
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
|
|
||||||
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
|
|
||||||
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
|
|
||||||
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
|
|
||||||
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
|
|
||||||
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
|
|
||||||
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
|
|
||||||
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
|
|
||||||
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
|
|
||||||
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
|
|
||||||
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
|
|
||||||
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
|
|
||||||
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
|
||||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
|
||||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
|
||||||
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
|
||||||
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
|
|
||||||
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
|
||||||
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
|
||||||
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
|
||||||
CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \
|
|
||||||
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
|
|
||||||
CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
|
|
||||||
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
|
|
||||||
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
|
|
||||||
CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
|
|
||||||
CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
|
|
||||||
CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
|
|
||||||
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
|
|
||||||
CONFIG.PCW_SD1_SD1_IO {MIO 46 .. 51} \
|
|
||||||
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \
|
|
||||||
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
|
|
||||||
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
|
|
||||||
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
|
|
||||||
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
|
|
||||||
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
|
|
||||||
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
|
|
||||||
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
|
|
||||||
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
|
|
||||||
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
|
|
||||||
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
|
|
||||||
CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
|
|
||||||
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
|
|
||||||
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
|
|
||||||
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
|
|
||||||
CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
|
|
||||||
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \
|
|
||||||
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
|
||||||
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
|
|
||||||
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_CL {7} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-125} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
|
|
||||||
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
|
|
||||||
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
|
|
||||||
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
|
|
||||||
CONFIG.PCW_USB0_RESET_ENABLE {1} \
|
|
||||||
CONFIG.PCW_USB0_RESET_IO {MIO 8} \
|
|
||||||
CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
|
|
||||||
CONFIG.PCW_USB1_RESET_ENABLE {0} \
|
|
||||||
CONFIG.PCW_USB_RESET_ENABLE {1} \
|
|
||||||
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
|
|
||||||
] $processing_system7_0
|
|
||||||
|
|
||||||
# Create instance: ps7_0_axi_periph, and set properties
|
|
||||||
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
|
|
||||||
set_property -dict [ list \
|
|
||||||
CONFIG.NUM_MI {2} \
|
|
||||||
] $ps7_0_axi_periph
|
|
||||||
|
|
||||||
# Create instance: rst_ps7_0_200M, and set properties
|
|
||||||
set rst_ps7_0_200M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_200M ]
|
|
||||||
|
|
||||||
# Create interface connections
|
|
||||||
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
|
|
||||||
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
|
|
||||||
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
|
|
||||||
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ip_encoder_0/S00_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
|
|
||||||
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ip_fan_0/S00_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
|
|
||||||
|
|
||||||
# Create port connections
|
|
||||||
connect_bd_net -net exrst_n_0_1 [get_bd_ports exrst_n] [get_bd_pins ip_encoder_0/exrst_n]
|
|
||||||
connect_bd_net -net in_signal_0_1 [get_bd_ports encoder_signal] [get_bd_pins ip_encoder_0/in_signal]
|
|
||||||
connect_bd_net -net ip_encoder_0_out_signal_camera_a [get_bd_ports out_signal_camera_a] [get_bd_pins ip_encoder_0/out_signal_camera_a]
|
|
||||||
connect_bd_net -net ip_encoder_0_out_signal_camera_b [get_bd_ports out_signal_camera_b] [get_bd_pins ip_encoder_0/out_signal_camera_b]
|
|
||||||
connect_bd_net -net ip_encoder_0_out_signal_camera_c [get_bd_ports out_signal_camera_c] [get_bd_pins ip_encoder_0/out_signal_camera_c]
|
|
||||||
connect_bd_net -net ip_encoder_0_out_signal_camera_d [get_bd_ports out_signal_camera_d] [get_bd_pins ip_encoder_0/out_signal_camera_d]
|
|
||||||
connect_bd_net -net ip_fan_0_fan [get_bd_ports fan] [get_bd_pins ip_fan_0/fan]
|
|
||||||
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins ip_encoder_0/s00_axi_aclk] [get_bd_pins ip_fan_0/s00_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_200M/slowest_sync_clk]
|
|
||||||
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_200M/ext_reset_in]
|
|
||||||
connect_bd_net -net rst_ps7_0_200M_peripheral_aresetn [get_bd_pins ip_encoder_0/s00_axi_aresetn] [get_bd_pins ip_fan_0/s00_axi_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_200M/peripheral_aresetn]
|
|
||||||
|
|
||||||
# Create address segments
|
|
||||||
assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs ip_encoder_0/S00_AXI/S00_AXI_reg] -force
|
|
||||||
assign_bd_address -offset 0x43C20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs ip_fan_0/S00_AXI/S00_AXI_reg] -force
|
|
||||||
|
|
||||||
|
|
||||||
# Restore current instance
|
|
||||||
current_bd_instance $oldCurInst
|
|
||||||
|
|
||||||
validate_bd_design
|
|
||||||
save_bd_design
|
|
||||||
}
|
|
||||||
# End of create_root_design()
|
|
||||||
|
|
||||||
|
|
||||||
##################################################################
|
|
||||||
# MAIN FLOW
|
|
||||||
##################################################################
|
|
||||||
|
|
||||||
create_root_design ""
|
|
||||||
|
|
||||||
|
|
||||||
@ -1,30 +0,0 @@
|
|||||||
|
|
||||||
set_property PACKAGE_PIN R14 [get_ports encoder_signal]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports encoder_signal]
|
|
||||||
|
|
||||||
|
|
||||||
set_property PACKAGE_PIN J20 [get_ports fan]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports fan]
|
|
||||||
set_property SLEW SLOW [get_ports fan]
|
|
||||||
|
|
||||||
|
|
||||||
set_property PACKAGE_PIN T10 [get_ports out_signal_camera_a]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports out_signal_camera_a]
|
|
||||||
set_property SLEW FAST [get_ports out_signal_camera_a]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports out_signal_camera_b]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports out_signal_camera_c]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports out_signal_camera_d]
|
|
||||||
set_property PACKAGE_PIN U12 [get_ports out_signal_camera_b]
|
|
||||||
set_property PACKAGE_PIN V12 [get_ports out_signal_camera_c]
|
|
||||||
set_property PACKAGE_PIN W13 [get_ports out_signal_camera_d]
|
|
||||||
set_property SLEW FAST [get_ports out_signal_camera_b]
|
|
||||||
set_property SLEW FAST [get_ports out_signal_camera_c]
|
|
||||||
set_property SLEW FAST [get_ports out_signal_camera_d]
|
|
||||||
|
|
||||||
set_property OFFCHIP_TERM NONE [get_ports fan]
|
|
||||||
set_property OFFCHIP_TERM NONE [get_ports out_signal_camera_a]
|
|
||||||
set_property OFFCHIP_TERM NONE [get_ports out_signal_camera_b]
|
|
||||||
set_property OFFCHIP_TERM NONE [get_ports out_signal_camera_c]
|
|
||||||
set_property OFFCHIP_TERM NONE [get_ports out_signal_camera_d]
|
|
||||||
set_property IOSTANDARD LVCMOS33 [get_ports exrst_n]
|
|
||||||
set_property PACKAGE_PIN T12 [get_ports exrst_n]
|
|
||||||
@ -1,86 +0,0 @@
|
|||||||
|
|
||||||
proc init { cellpath otherInfo } {
|
|
||||||
|
|
||||||
set cell_handle [get_bd_cells $cellpath]
|
|
||||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
|
||||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
|
||||||
set full_sbusif_list [list ]
|
|
||||||
|
|
||||||
foreach busif $all_busif {
|
|
||||||
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
|
|
||||||
set busif_param_list [list]
|
|
||||||
set busif_name [get_property NAME $busif]
|
|
||||||
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
foreach tparam $axi_standard_param_list {
|
|
||||||
lappend busif_param_list "C_${busif_name}_${tparam}"
|
|
||||||
}
|
|
||||||
bd::mark_propagate_only $cell_handle $busif_param_list
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
proc pre_propagate {cellpath otherInfo } {
|
|
||||||
|
|
||||||
set cell_handle [get_bd_cells $cellpath]
|
|
||||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
|
||||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
|
||||||
|
|
||||||
foreach busif $all_busif {
|
|
||||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
|
|
||||||
set busif_name [get_property NAME $busif]
|
|
||||||
foreach tparam $axi_standard_param_list {
|
|
||||||
set busif_param_name "C_${busif_name}_${tparam}"
|
|
||||||
|
|
||||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
|
||||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
|
||||||
|
|
||||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
|
||||||
if { $val_on_cell != "" } {
|
|
||||||
set_property CONFIG.${tparam} $val_on_cell $busif
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
proc propagate {cellpath otherInfo } {
|
|
||||||
|
|
||||||
set cell_handle [get_bd_cells $cellpath]
|
|
||||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
|
||||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
|
||||||
|
|
||||||
foreach busif $all_busif {
|
|
||||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
|
|
||||||
set busif_name [get_property NAME $busif]
|
|
||||||
foreach tparam $axi_standard_param_list {
|
|
||||||
set busif_param_name "C_${busif_name}_${tparam}"
|
|
||||||
|
|
||||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
|
||||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
|
||||||
|
|
||||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
|
||||||
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
|
|
||||||
if { $val_on_cell_intf_pin != "" } {
|
|
||||||
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,10 +0,0 @@
|
|||||||
|
|
||||||
|
|
||||||
OPTION psf_version = 2.1;
|
|
||||||
|
|
||||||
BEGIN DRIVER ip_encoder
|
|
||||||
OPTION supported_peripherals = (ip_encoder);
|
|
||||||
OPTION copyfiles = all;
|
|
||||||
OPTION VERSION = 1.0;
|
|
||||||
OPTION NAME = ip_encoder;
|
|
||||||
END DRIVER
|
|
||||||
@ -1,5 +0,0 @@
|
|||||||
|
|
||||||
|
|
||||||
proc generate {drv_handle} {
|
|
||||||
xdefine_include_file $drv_handle "xparameters.h" "ip_encoder" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
|
||||||
}
|
|
||||||
@ -1,26 +0,0 @@
|
|||||||
COMPILER=
|
|
||||||
ARCHIVER=
|
|
||||||
CP=cp
|
|
||||||
COMPILER_FLAGS=
|
|
||||||
EXTRA_COMPILER_FLAGS=
|
|
||||||
LIB=libxil.a
|
|
||||||
|
|
||||||
RELEASEDIR=../../../lib
|
|
||||||
INCLUDEDIR=../../../include
|
|
||||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
|
||||||
|
|
||||||
INCLUDEFILES=*.h
|
|
||||||
LIBSOURCES=*.c
|
|
||||||
OUTS = *.o
|
|
||||||
|
|
||||||
libs:
|
|
||||||
echo "Compiling ip_encoder..."
|
|
||||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
|
||||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
|
||||||
make clean
|
|
||||||
|
|
||||||
include:
|
|
||||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
|
||||||
|
|
||||||
clean:
|
|
||||||
rm -rf ${OUTS}
|
|
||||||
@ -1,6 +0,0 @@
|
|||||||
|
|
||||||
|
|
||||||
/***************************** Include Files *******************************/
|
|
||||||
#include "ip_encoder.h"
|
|
||||||
|
|
||||||
/************************** Function Definitions ***************************/
|
|
||||||
@ -1,79 +0,0 @@
|
|||||||
|
|
||||||
#ifndef IP_ENCODER_H
|
|
||||||
#define IP_ENCODER_H
|
|
||||||
|
|
||||||
|
|
||||||
/****************** Include Files ********************/
|
|
||||||
#include "xil_types.h"
|
|
||||||
#include "xstatus.h"
|
|
||||||
|
|
||||||
#define IP_ENCODER_S00_AXI_SLV_REG0_OFFSET 0
|
|
||||||
#define IP_ENCODER_S00_AXI_SLV_REG1_OFFSET 4
|
|
||||||
#define IP_ENCODER_S00_AXI_SLV_REG2_OFFSET 8
|
|
||||||
#define IP_ENCODER_S00_AXI_SLV_REG3_OFFSET 12
|
|
||||||
|
|
||||||
|
|
||||||
/**************************** Type Definitions *****************************/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* Write a value to a IP_ENCODER register. A 32 bit write is performed.
|
|
||||||
* If the component is implemented in a smaller width, only the least
|
|
||||||
* significant data is written.
|
|
||||||
*
|
|
||||||
* @param BaseAddress is the base address of the IP_ENCODERdevice.
|
|
||||||
* @param RegOffset is the register offset from the base to write to.
|
|
||||||
* @param Data is the data written to the register.
|
|
||||||
*
|
|
||||||
* @return None.
|
|
||||||
*
|
|
||||||
* @note
|
|
||||||
* C-style signature:
|
|
||||||
* void IP_ENCODER_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define IP_ENCODER_mWriteReg(BaseAddress, RegOffset, Data) \
|
|
||||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
|
||||||
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* Read a value from a IP_ENCODER register. A 32 bit read is performed.
|
|
||||||
* If the component is implemented in a smaller width, only the least
|
|
||||||
* significant data is read from the register. The most significant data
|
|
||||||
* will be read as 0.
|
|
||||||
*
|
|
||||||
* @param BaseAddress is the base address of the IP_ENCODER device.
|
|
||||||
* @param RegOffset is the register offset from the base to write to.
|
|
||||||
*
|
|
||||||
* @return Data is the data from the register.
|
|
||||||
*
|
|
||||||
* @note
|
|
||||||
* C-style signature:
|
|
||||||
* u32 IP_ENCODER_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define IP_ENCODER_mReadReg(BaseAddress, RegOffset) \
|
|
||||||
Xil_In32((BaseAddress) + (RegOffset))
|
|
||||||
|
|
||||||
/************************** Function Prototypes ****************************/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
|
||||||
* resets of the device are performed.
|
|
||||||
*
|
|
||||||
* If the hardware system is not built correctly, this function may never
|
|
||||||
* return to the caller.
|
|
||||||
*
|
|
||||||
* @param baseaddr_p is the base address of the IP_ENCODER instance to be worked on.
|
|
||||||
*
|
|
||||||
* @return
|
|
||||||
*
|
|
||||||
* - XST_SUCCESS if all self-test code passed
|
|
||||||
* - XST_FAILURE if any self-test code failed
|
|
||||||
*
|
|
||||||
* @note Caching must be turned off for this function to work.
|
|
||||||
* @note Self test may fail if data memory and device are not on the same bus.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
XStatus IP_ENCODER_Reg_SelfTest(void * baseaddr_p);
|
|
||||||
|
|
||||||
#endif // IP_ENCODER_H
|
|
||||||
@ -1,60 +0,0 @@
|
|||||||
|
|
||||||
/***************************** Include Files *******************************/
|
|
||||||
#include "ip_encoder.h"
|
|
||||||
#include "xparameters.h"
|
|
||||||
#include "stdio.h"
|
|
||||||
#include "xil_io.h"
|
|
||||||
|
|
||||||
/************************** Constant Definitions ***************************/
|
|
||||||
#define READ_WRITE_MUL_FACTOR 0x10
|
|
||||||
|
|
||||||
/************************** Function Definitions ***************************/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
|
||||||
* resets of the device are performed.
|
|
||||||
*
|
|
||||||
* If the hardware system is not built correctly, this function may never
|
|
||||||
* return to the caller.
|
|
||||||
*
|
|
||||||
* @param baseaddr_p is the base address of the IP_ENCODERinstance to be worked on.
|
|
||||||
*
|
|
||||||
* @return
|
|
||||||
*
|
|
||||||
* - XST_SUCCESS if all self-test code passed
|
|
||||||
* - XST_FAILURE if any self-test code failed
|
|
||||||
*
|
|
||||||
* @note Caching must be turned off for this function to work.
|
|
||||||
* @note Self test may fail if data memory and device are not on the same bus.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
XStatus IP_ENCODER_Reg_SelfTest(void * baseaddr_p)
|
|
||||||
{
|
|
||||||
u32 baseaddr;
|
|
||||||
int write_loop_index;
|
|
||||||
int read_loop_index;
|
|
||||||
int Index;
|
|
||||||
|
|
||||||
baseaddr = (u32) baseaddr_p;
|
|
||||||
|
|
||||||
xil_printf("******************************\n\r");
|
|
||||||
xil_printf("* User Peripheral Self Test\n\r");
|
|
||||||
xil_printf("******************************\n\n\r");
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write to user logic slave module register(s) and read back
|
|
||||||
*/
|
|
||||||
xil_printf("User logic slave module test...\n\r");
|
|
||||||
|
|
||||||
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
|
|
||||||
IP_ENCODER_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
|
|
||||||
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
|
|
||||||
if ( IP_ENCODER_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
|
|
||||||
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
|
|
||||||
return XST_FAILURE;
|
|
||||||
}
|
|
||||||
|
|
||||||
xil_printf(" - slave register write/read passed\n\n\r");
|
|
||||||
|
|
||||||
return XST_SUCCESS;
|
|
||||||
}
|
|
||||||
@ -1,88 +0,0 @@
|
|||||||
proc create_ipi_design { offsetfile design_name } {
|
|
||||||
create_bd_design $design_name
|
|
||||||
open_bd_design $design_name
|
|
||||||
|
|
||||||
# Create Clock and Reset Ports
|
|
||||||
set ACLK [ create_bd_port -dir I -type clk ACLK ]
|
|
||||||
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
|
|
||||||
set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
|
|
||||||
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
|
|
||||||
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
|
|
||||||
|
|
||||||
# Create instance: ip_encoder_0, and set properties
|
|
||||||
set ip_encoder_0 [ create_bd_cell -type ip -vlnv user.org:user:ip_encoder:1.0 ip_encoder_0]
|
|
||||||
|
|
||||||
# Create instance: master_0, and set properties
|
|
||||||
set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0]
|
|
||||||
set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
|
|
||||||
|
|
||||||
# Create interface connections
|
|
||||||
connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins ip_encoder_0/S00_AXI]
|
|
||||||
|
|
||||||
# Create port connections
|
|
||||||
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins ip_encoder_0/S00_AXI_ACLK]
|
|
||||||
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins ip_encoder_0/S00_AXI_ARESETN]
|
|
||||||
set_property target_simulator XSim [current_project]
|
|
||||||
set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
|
|
||||||
|
|
||||||
# Auto assign address
|
|
||||||
assign_bd_address
|
|
||||||
|
|
||||||
# Copy all address to interface_address.vh file
|
|
||||||
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
|
|
||||||
upvar 1 $offsetfile offset_file
|
|
||||||
set offset_file "${bd_path}/ip_encoder_v1_0_tb_include.svh"
|
|
||||||
set fp [open $offset_file "w"]
|
|
||||||
puts $fp "`ifndef ip_encoder_v1_0_tb_include_vh_"
|
|
||||||
puts $fp "`define ip_encoder_v1_0_tb_include_vh_\n"
|
|
||||||
puts $fp "//Configuration current bd names"
|
|
||||||
puts $fp "`define BD_NAME ${design_name}"
|
|
||||||
puts $fp "`define BD_INST_NAME ${design_name}_i"
|
|
||||||
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
|
|
||||||
puts $fp "//Configuration address parameters"
|
|
||||||
|
|
||||||
puts $fp "`endif"
|
|
||||||
close $fp
|
|
||||||
}
|
|
||||||
|
|
||||||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:ip_encoder:1.0]]]]
|
|
||||||
set test_bench_file ${ip_path}/example_designs/bfm_design/ip_encoder_v1_0_tb.sv
|
|
||||||
set interface_address_vh_file ""
|
|
||||||
|
|
||||||
# Set IP Repository and Update IP Catalogue
|
|
||||||
set repo_paths [get_property ip_repo_paths [current_fileset]]
|
|
||||||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
|
|
||||||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
|
|
||||||
update_ip_catalog
|
|
||||||
}
|
|
||||||
|
|
||||||
set design_name ""
|
|
||||||
set all_bd {}
|
|
||||||
set all_bd_files [get_files *.bd -quiet]
|
|
||||||
foreach file $all_bd_files {
|
|
||||||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
|
|
||||||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
|
|
||||||
lappend all_bd $bd_name
|
|
||||||
}
|
|
||||||
|
|
||||||
for { set i 1 } { 1 } { incr i } {
|
|
||||||
set design_name "ip_encoder_v1_0_bfm_${i}"
|
|
||||||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
|
|
||||||
break
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
create_ipi_design interface_address_vh_file ${design_name}
|
|
||||||
validate_bd_design
|
|
||||||
|
|
||||||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
|
|
||||||
import_files -force -norecurse $wrapper_file
|
|
||||||
|
|
||||||
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
|
||||||
import_files -fileset sim_1 -norecurse -force $test_bench_file
|
|
||||||
remove_files -quiet -fileset sim_1 ip_encoder_v1_0_tb_include.vh
|
|
||||||
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
|
|
||||||
set_property top ip_encoder_v1_0_tb [get_filesets sim_1]
|
|
||||||
set_property top_lib {} [get_filesets sim_1]
|
|
||||||
set_property top_file {} [get_filesets sim_1]
|
|
||||||
launch_simulation -simset sim_1 -mode behavioral
|
|
||||||
@ -1,197 +0,0 @@
|
|||||||
|
|
||||||
`timescale 1ns / 1ps
|
|
||||||
`include "ip_encoder_v1_0_tb_include.svh"
|
|
||||||
|
|
||||||
import axi_vip_pkg::*;
|
|
||||||
import ip_encoder_v1_0_bfm_1_master_0_0_pkg::*;
|
|
||||||
|
|
||||||
module ip_encoder_v1_0_tb();
|
|
||||||
|
|
||||||
|
|
||||||
xil_axi_uint error_cnt = 0;
|
|
||||||
xil_axi_uint comparison_cnt = 0;
|
|
||||||
axi_transaction wr_transaction;
|
|
||||||
axi_transaction rd_transaction;
|
|
||||||
axi_monitor_transaction mst_monitor_transaction;
|
|
||||||
axi_monitor_transaction master_moniter_transaction_queue[$];
|
|
||||||
xil_axi_uint master_moniter_transaction_queue_size =0;
|
|
||||||
axi_monitor_transaction mst_scb_transaction;
|
|
||||||
axi_monitor_transaction passthrough_monitor_transaction;
|
|
||||||
axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
|
|
||||||
xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
|
|
||||||
axi_monitor_transaction passthrough_mst_scb_transaction;
|
|
||||||
axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
|
|
||||||
xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
|
|
||||||
axi_monitor_transaction passthrough_slv_scb_transaction;
|
|
||||||
axi_monitor_transaction slv_monitor_transaction;
|
|
||||||
axi_monitor_transaction slave_moniter_transaction_queue[$];
|
|
||||||
xil_axi_uint slave_moniter_transaction_queue_size =0;
|
|
||||||
axi_monitor_transaction slv_scb_transaction;
|
|
||||||
xil_axi_uint mst_agent_verbosity = 0;
|
|
||||||
xil_axi_uint slv_agent_verbosity = 0;
|
|
||||||
xil_axi_uint passthrough_agent_verbosity = 0;
|
|
||||||
bit clock;
|
|
||||||
bit reset;
|
|
||||||
integer result_slave;
|
|
||||||
bit [31:0] S00_AXI_test_data[3:0];
|
|
||||||
localparam LC_AXI_BURST_LENGTH = 8;
|
|
||||||
localparam LC_AXI_DATA_WIDTH = 32;
|
|
||||||
task automatic COMPARE_DATA;
|
|
||||||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected;
|
|
||||||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual;
|
|
||||||
begin
|
|
||||||
if (expected === 'hx || actual === 'hx) begin
|
|
||||||
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
|
|
||||||
result_slave = 0; $stop;
|
|
||||||
end
|
|
||||||
if (actual != expected) begin
|
|
||||||
$display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual);
|
|
||||||
result_slave = 0;
|
|
||||||
$stop;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
$display("TESTBENCH Passed! Data expected is equal to actual.",
|
|
||||||
" expected = 0x%h",expected, " actual = 0x%h",actual);
|
|
||||||
end
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
integer i;
|
|
||||||
integer j;
|
|
||||||
xil_axi_uint trans_cnt_before_switch = 48;
|
|
||||||
xil_axi_uint passthrough_cmd_switch_cnt = 0;
|
|
||||||
event passthrough_mastermode_start_event;
|
|
||||||
event passthrough_mastermode_end_event;
|
|
||||||
event passthrough_slavemode_end_event;
|
|
||||||
xil_axi_uint mtestID;
|
|
||||||
xil_axi_ulong mtestADDR;
|
|
||||||
xil_axi_len_t mtestBurstLength;
|
|
||||||
xil_axi_size_t mtestDataSize;
|
|
||||||
xil_axi_burst_t mtestBurstType;
|
|
||||||
xil_axi_lock_t mtestLOCK;
|
|
||||||
xil_axi_cache_t mtestCacheType = 0;
|
|
||||||
xil_axi_prot_t mtestProtectionType = 3'b000;
|
|
||||||
xil_axi_region_t mtestRegion = 4'b000;
|
|
||||||
xil_axi_qos_t mtestQOS = 4'b000;
|
|
||||||
xil_axi_data_beat dbeat;
|
|
||||||
xil_axi_data_beat [255:0] mtestWUSER;
|
|
||||||
xil_axi_data_beat mtestAWUSER = 'h0;
|
|
||||||
xil_axi_data_beat mtestARUSER = 0;
|
|
||||||
xil_axi_data_beat [255:0] mtestRUSER;
|
|
||||||
xil_axi_uint mtestBUSER = 0;
|
|
||||||
xil_axi_resp_t mtestBresp;
|
|
||||||
xil_axi_resp_t[255:0] mtestRresp;
|
|
||||||
bit [63:0] mtestWDataL;
|
|
||||||
bit [63:0] mtestRDataL;
|
|
||||||
axi_transaction pss_wr_transaction;
|
|
||||||
axi_transaction pss_rd_transaction;
|
|
||||||
axi_transaction reactive_transaction;
|
|
||||||
axi_transaction rd_payload_transaction;
|
|
||||||
axi_transaction wr_rand;
|
|
||||||
axi_transaction rd_rand;
|
|
||||||
axi_transaction wr_reactive;
|
|
||||||
axi_transaction rd_reactive;
|
|
||||||
axi_transaction wr_reactive2;
|
|
||||||
axi_transaction rd_reactive2;
|
|
||||||
axi_ready_gen bready_gen;
|
|
||||||
axi_ready_gen rready_gen;
|
|
||||||
axi_ready_gen awready_gen;
|
|
||||||
axi_ready_gen wready_gen;
|
|
||||||
axi_ready_gen arready_gen;
|
|
||||||
axi_ready_gen bready_gen2;
|
|
||||||
axi_ready_gen rready_gen2;
|
|
||||||
axi_ready_gen awready_gen2;
|
|
||||||
axi_ready_gen wready_gen2;
|
|
||||||
axi_ready_gen arready_gen2;
|
|
||||||
xil_axi_payload_byte data_mem[xil_axi_ulong];
|
|
||||||
ip_encoder_v1_0_bfm_1_master_0_0_mst_t mst_agent_0;
|
|
||||||
|
|
||||||
`BD_WRAPPER DUT(
|
|
||||||
.ARESETN(reset),
|
|
||||||
.ACLK(clock)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms
|
|
||||||
mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
|
|
||||||
mst_agent_0.set_agent_tag("Master VIP");
|
|
||||||
mst_agent_0.set_verbosity(mst_agent_verbosity);
|
|
||||||
mst_agent_0.start_master();
|
|
||||||
$timeformat (-12, 1, " ps", 1);
|
|
||||||
end
|
|
||||||
initial begin
|
|
||||||
reset <= 1'b0;
|
|
||||||
#200ns;
|
|
||||||
reset <= 1'b1;
|
|
||||||
repeat (5) @(negedge clock);
|
|
||||||
end
|
|
||||||
always #5 clock <= ~clock;
|
|
||||||
initial begin
|
|
||||||
S_AXI_TEST ( );
|
|
||||||
|
|
||||||
#1ns;
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
task automatic S_AXI_TEST;
|
|
||||||
begin
|
|
||||||
#1;
|
|
||||||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts");
|
|
||||||
mtestID = 0;
|
|
||||||
mtestADDR = 64'h00000000;
|
|
||||||
mtestBurstLength = 0;
|
|
||||||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
|
|
||||||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
|
|
||||||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
|
|
||||||
mtestCacheType = 0;
|
|
||||||
mtestProtectionType = 0;
|
|
||||||
mtestRegion = 0;
|
|
||||||
mtestQOS = 0;
|
|
||||||
result_slave = 1;
|
|
||||||
mtestWDataL[31:0] = 32'h00000001;
|
|
||||||
for(int i = 0; i < 4;i++) begin
|
|
||||||
S00_AXI_test_data[i] <= mtestWDataL[31:0];
|
|
||||||
mst_agent_0.AXI4LITE_WRITE_BURST(
|
|
||||||
mtestADDR,
|
|
||||||
mtestProtectionType,
|
|
||||||
mtestWDataL,
|
|
||||||
mtestBresp
|
|
||||||
);
|
|
||||||
mtestWDataL[31:0] = mtestWDataL[31:0] + 1;
|
|
||||||
mtestADDR = mtestADDR + 64'h4;
|
|
||||||
end
|
|
||||||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes");
|
|
||||||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method starts");
|
|
||||||
mtestID = 0;
|
|
||||||
mtestADDR = 64'h00000000;
|
|
||||||
mtestBurstLength = 0;
|
|
||||||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
|
|
||||||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
|
|
||||||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
|
|
||||||
mtestCacheType = 0;
|
|
||||||
mtestProtectionType = 0;
|
|
||||||
mtestRegion = 0;
|
|
||||||
mtestQOS = 0;
|
|
||||||
for(int i = 0; i < 4;i++) begin
|
|
||||||
mst_agent_0.AXI4LITE_READ_BURST(
|
|
||||||
mtestADDR,
|
|
||||||
mtestProtectionType,
|
|
||||||
mtestRDataL,
|
|
||||||
mtestRresp
|
|
||||||
);
|
|
||||||
mtestADDR = mtestADDR + 64'h4;
|
|
||||||
COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL);
|
|
||||||
end
|
|
||||||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method completes");
|
|
||||||
$display("Sequential read transfers example similar to AXI VIP READ_BURST method completes");
|
|
||||||
$display("---------------------------------------------------------");
|
|
||||||
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
|
|
||||||
if ( result_slave ) begin
|
|
||||||
$display("PTGEN_TEST: PASSED!");
|
|
||||||
end else begin
|
|
||||||
$display("PTGEN_TEST: FAILED!");
|
|
||||||
end
|
|
||||||
$display("---------------------------------------------------------");
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,118 +0,0 @@
|
|||||||
|
|
||||||
proc create_ipi_design { offsetfile design_name } {
|
|
||||||
|
|
||||||
create_bd_design $design_name
|
|
||||||
open_bd_design $design_name
|
|
||||||
|
|
||||||
# Create and configure Clock/Reset
|
|
||||||
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
|
|
||||||
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
|
|
||||||
|
|
||||||
#Constraints will be provided manually while pin planning.
|
|
||||||
create_bd_port -dir I -type rst reset_rtl
|
|
||||||
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
|
|
||||||
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
|
|
||||||
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
|
|
||||||
set external_reset_port reset_rtl
|
|
||||||
create_bd_port -dir I -type clk clock_rtl
|
|
||||||
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
|
|
||||||
set external_clock_port clock_rtl
|
|
||||||
|
|
||||||
#Avoid IPI DRC, make clock port synchronous to reset
|
|
||||||
if { $external_clock_port ne "" && $external_reset_port ne "" } {
|
|
||||||
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
|
|
||||||
}
|
|
||||||
|
|
||||||
# Connect other sys_reset pins
|
|
||||||
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
|
|
||||||
|
|
||||||
# Create instance: ip_encoder_0, and set properties
|
|
||||||
set ip_encoder_0 [ create_bd_cell -type ip -vlnv user.org:user:ip_encoder:1.0 ip_encoder_0 ]
|
|
||||||
|
|
||||||
# Create instance: jtag_axi_0, and set properties
|
|
||||||
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
|
|
||||||
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
|
|
||||||
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
|
||||||
|
|
||||||
# Create instance: axi_peri_interconnect, and set properties
|
|
||||||
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
|
|
||||||
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
|
||||||
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
|
|
||||||
|
|
||||||
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
|
||||||
|
|
||||||
# Connect all clock & reset of ip_encoder_0 slave interfaces..
|
|
||||||
connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins ip_encoder_0/S00_AXI]
|
|
||||||
connect_bd_net [get_bd_pins ip_encoder_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins ip_encoder_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
|
||||||
|
|
||||||
|
|
||||||
# Auto assign address
|
|
||||||
assign_bd_address
|
|
||||||
|
|
||||||
# Copy all address to ip_encoder_v1_0_include.tcl file
|
|
||||||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
|
|
||||||
upvar 1 $offsetfile offset_file
|
|
||||||
set offset_file "${bd_path}/ip_encoder_v1_0_include.tcl"
|
|
||||||
set fp [open $offset_file "w"]
|
|
||||||
puts $fp "# Configuration address parameters"
|
|
||||||
|
|
||||||
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_ip_encoder_0_S00_AXI_* ]]
|
|
||||||
puts $fp "set s00_axi_addr ${offset}"
|
|
||||||
|
|
||||||
close $fp
|
|
||||||
}
|
|
||||||
|
|
||||||
# Set IP Repository and Update IP Catalogue
|
|
||||||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:ip_encoder:1.0]]]]
|
|
||||||
set hw_test_file ${ip_path}/example_designs/debug_hw_design/ip_encoder_v1_0_hw_test.tcl
|
|
||||||
|
|
||||||
set repo_paths [get_property ip_repo_paths [current_fileset]]
|
|
||||||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
|
|
||||||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
|
|
||||||
update_ip_catalog
|
|
||||||
}
|
|
||||||
|
|
||||||
set design_name ""
|
|
||||||
set all_bd {}
|
|
||||||
set all_bd_files [get_files *.bd -quiet]
|
|
||||||
foreach file $all_bd_files {
|
|
||||||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
|
|
||||||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
|
|
||||||
lappend all_bd $bd_name
|
|
||||||
}
|
|
||||||
|
|
||||||
for { set i 1 } { 1 } { incr i } {
|
|
||||||
set design_name "ip_encoder_v1_0_hw_${i}"
|
|
||||||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
|
|
||||||
break
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
set intf_address_include_file ""
|
|
||||||
create_ipi_design intf_address_include_file ${design_name}
|
|
||||||
save_bd_design
|
|
||||||
validate_bd_design
|
|
||||||
|
|
||||||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
|
|
||||||
import_files -force -norecurse $wrapper_file
|
|
||||||
|
|
||||||
puts "-------------------------------------------------------------------------------------------------"
|
|
||||||
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
|
|
||||||
puts " please perform following steps to test design in targeted board."
|
|
||||||
puts "1. Generate bitstream"
|
|
||||||
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
|
|
||||||
puts "3. Download generated bitstream"
|
|
||||||
puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
|
|
||||||
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
|
|
||||||
puts " : source -notrace ${hw_test_file}"
|
|
||||||
puts "-------------------------------------------------------------------------------------------------"
|
|
||||||
|
|
||||||
@ -1,45 +0,0 @@
|
|||||||
# Runtime Tcl commands to interact with - ip_encoder_v1_0
|
|
||||||
|
|
||||||
# Sourcing design address info tcl
|
|
||||||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
|
|
||||||
source ${bd_path}/ip_encoder_v1_0_include.tcl
|
|
||||||
|
|
||||||
# jtag axi master interface hardware name, change as per your design.
|
|
||||||
set jtag_axi_master hw_axi_1
|
|
||||||
set ec 0
|
|
||||||
|
|
||||||
# hw test script
|
|
||||||
# Delete all previous axis transactions
|
|
||||||
if { [llength [get_hw_axi_txns -quiet]] } {
|
|
||||||
delete_hw_axi_txn [get_hw_axi_txns -quiet]
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
# Test all lite slaves.
|
|
||||||
set wdata_1 abcd1234
|
|
||||||
|
|
||||||
# Test: S00_AXI
|
|
||||||
# Create a write transaction at s00_axi_addr address
|
|
||||||
create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
|
|
||||||
# Create a read transaction at s00_axi_addr address
|
|
||||||
create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
|
|
||||||
# Initiate transactions
|
|
||||||
run_hw_axi r_s00_axi_addr
|
|
||||||
run_hw_axi w_s00_axi_addr
|
|
||||||
run_hw_axi r_s00_axi_addr
|
|
||||||
set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
|
|
||||||
# Compare read data
|
|
||||||
if { $rdata_tmp == $wdata_1 } {
|
|
||||||
puts "Data comparison test pass for - S00_AXI"
|
|
||||||
} else {
|
|
||||||
puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
|
|
||||||
inc ec
|
|
||||||
}
|
|
||||||
|
|
||||||
# Check error flag
|
|
||||||
if { $ec == 0 } {
|
|
||||||
puts "PTGEN_TEST: PASSED!"
|
|
||||||
} else {
|
|
||||||
puts "PTGEN_TEST: FAILED!"
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,102 +0,0 @@
|
|||||||
|
|
||||||
`timescale 1 ns / 1 ps
|
|
||||||
|
|
||||||
module ip_encoder_v1_0 #
|
|
||||||
(
|
|
||||||
// Users to add parameters here
|
|
||||||
|
|
||||||
// User parameters ends
|
|
||||||
// Do not modify the parameters beyond this line
|
|
||||||
|
|
||||||
|
|
||||||
// Parameters of Axi Slave Bus Interface S00_AXI
|
|
||||||
parameter integer C_S00_AXI_DATA_WIDTH = 32,
|
|
||||||
parameter integer C_S00_AXI_ADDR_WIDTH = 5
|
|
||||||
)
|
|
||||||
(
|
|
||||||
// Users to add ports here
|
|
||||||
input in_signal,
|
|
||||||
input exrst_n,
|
|
||||||
output out_signal_valve_posedge,
|
|
||||||
output out_signal_valve,
|
|
||||||
output out_signal_camera_a_posedge,
|
|
||||||
output out_signal_camera_b_posedge,
|
|
||||||
output out_signal_camera_c_posedge,
|
|
||||||
output out_signal_camera_d_posedge,
|
|
||||||
output out_signal_camera_a,
|
|
||||||
output out_signal_camera_b,
|
|
||||||
output out_signal_camera_c,
|
|
||||||
output out_signal_camera_d,
|
|
||||||
|
|
||||||
// User ports ends
|
|
||||||
// Do not modify the ports beyond this line
|
|
||||||
|
|
||||||
|
|
||||||
// Ports of Axi Slave Bus Interface S00_AXI
|
|
||||||
input wire s00_axi_aclk,
|
|
||||||
input wire s00_axi_aresetn,
|
|
||||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
|
|
||||||
input wire [2 : 0] s00_axi_awprot,
|
|
||||||
input wire s00_axi_awvalid,
|
|
||||||
output wire s00_axi_awready,
|
|
||||||
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
|
|
||||||
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
|
|
||||||
input wire s00_axi_wvalid,
|
|
||||||
output wire s00_axi_wready,
|
|
||||||
output wire [1 : 0] s00_axi_bresp,
|
|
||||||
output wire s00_axi_bvalid,
|
|
||||||
input wire s00_axi_bready,
|
|
||||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
|
|
||||||
input wire [2 : 0] s00_axi_arprot,
|
|
||||||
input wire s00_axi_arvalid,
|
|
||||||
output wire s00_axi_arready,
|
|
||||||
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
|
|
||||||
output wire [1 : 0] s00_axi_rresp,
|
|
||||||
output wire s00_axi_rvalid,
|
|
||||||
input wire s00_axi_rready
|
|
||||||
);
|
|
||||||
// Instantiation of Axi Bus Interface S00_AXI
|
|
||||||
ip_encoder_v1_0_S00_AXI # (
|
|
||||||
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
|
|
||||||
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
|
|
||||||
) ip_encoder_v1_0_S00_AXI_inst (
|
|
||||||
.in_signal(in_signal),
|
|
||||||
.exrst_n (exrst_n),
|
|
||||||
.out_signal_valve_posedge(out_signal_valve_posedge),
|
|
||||||
.out_signal_valve(out_signal_valve),
|
|
||||||
.out_signal_camera_a_posedge(out_signal_camera_a_posedge),
|
|
||||||
.out_signal_camera_b_posedge(out_signal_camera_b_posedge),
|
|
||||||
.out_signal_camera_c_posedge(out_signal_camera_c_posedge),
|
|
||||||
.out_signal_camera_d_posedge(out_signal_camera_d_posedge),
|
|
||||||
.out_signal_camera_a(out_signal_camera_a),
|
|
||||||
.out_signal_camera_b(out_signal_camera_b),
|
|
||||||
.out_signal_camera_c(out_signal_camera_c),
|
|
||||||
.out_signal_camera_d(out_signal_camera_d),
|
|
||||||
.S_AXI_ACLK(s00_axi_aclk),
|
|
||||||
.S_AXI_ARESETN(s00_axi_aresetn),
|
|
||||||
.S_AXI_AWADDR(s00_axi_awaddr),
|
|
||||||
.S_AXI_AWPROT(s00_axi_awprot),
|
|
||||||
.S_AXI_AWVALID(s00_axi_awvalid),
|
|
||||||
.S_AXI_AWREADY(s00_axi_awready),
|
|
||||||
.S_AXI_WDATA(s00_axi_wdata),
|
|
||||||
.S_AXI_WSTRB(s00_axi_wstrb),
|
|
||||||
.S_AXI_WVALID(s00_axi_wvalid),
|
|
||||||
.S_AXI_WREADY(s00_axi_wready),
|
|
||||||
.S_AXI_BRESP(s00_axi_bresp),
|
|
||||||
.S_AXI_BVALID(s00_axi_bvalid),
|
|
||||||
.S_AXI_BREADY(s00_axi_bready),
|
|
||||||
.S_AXI_ARADDR(s00_axi_araddr),
|
|
||||||
.S_AXI_ARPROT(s00_axi_arprot),
|
|
||||||
.S_AXI_ARVALID(s00_axi_arvalid),
|
|
||||||
.S_AXI_ARREADY(s00_axi_arready),
|
|
||||||
.S_AXI_RDATA(s00_axi_rdata),
|
|
||||||
.S_AXI_RRESP(s00_axi_rresp),
|
|
||||||
.S_AXI_RVALID(s00_axi_rvalid),
|
|
||||||
.S_AXI_RREADY(s00_axi_rready)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Add user logic here
|
|
||||||
|
|
||||||
// User logic ends
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,482 +0,0 @@
|
|||||||
|
|
||||||
`timescale 1 ns / 1 ps
|
|
||||||
|
|
||||||
module ip_encoder_v1_0_S00_AXI #
|
|
||||||
(
|
|
||||||
// Users to add parameters here
|
|
||||||
|
|
||||||
// User parameters ends
|
|
||||||
// Do not modify the parameters beyond this line
|
|
||||||
|
|
||||||
// Width of S_AXI data bus
|
|
||||||
parameter integer C_S_AXI_DATA_WIDTH = 32,
|
|
||||||
// Width of S_AXI address bus
|
|
||||||
parameter integer C_S_AXI_ADDR_WIDTH = 5
|
|
||||||
)
|
|
||||||
(
|
|
||||||
// Users to add ports here
|
|
||||||
input in_signal,
|
|
||||||
input exrst_n,
|
|
||||||
output out_signal_valve_posedge,
|
|
||||||
output out_signal_valve,
|
|
||||||
output out_signal_camera_a_posedge,
|
|
||||||
output out_signal_camera_b_posedge,
|
|
||||||
output out_signal_camera_c_posedge,
|
|
||||||
output out_signal_camera_d_posedge,
|
|
||||||
output out_signal_camera_a,
|
|
||||||
output out_signal_camera_b,
|
|
||||||
output out_signal_camera_c,
|
|
||||||
output out_signal_camera_d,
|
|
||||||
|
|
||||||
// User ports ends
|
|
||||||
// Do not modify the ports beyond this line
|
|
||||||
|
|
||||||
// Global Clock Signal
|
|
||||||
input wire S_AXI_ACLK,
|
|
||||||
// Global Reset Signal. This Signal is Active LOW
|
|
||||||
input wire S_AXI_ARESETN,
|
|
||||||
// Write address (issued by master, acceped by Slave)
|
|
||||||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
|
|
||||||
// Write channel Protection type. This signal indicates the
|
|
||||||
// privilege and security level of the transaction, and whether
|
|
||||||
// the transaction is a data access or an instruction access.
|
|
||||||
input wire [2 : 0] S_AXI_AWPROT,
|
|
||||||
// Write address valid. This signal indicates that the master signaling
|
|
||||||
// valid write address and control information.
|
|
||||||
input wire S_AXI_AWVALID,
|
|
||||||
// Write address ready. This signal indicates that the slave is ready
|
|
||||||
// to accept an address and associated control signals.
|
|
||||||
output wire S_AXI_AWREADY,
|
|
||||||
// Write data (issued by master, acceped by Slave)
|
|
||||||
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
|
|
||||||
// Write strobes. This signal indicates which byte lanes hold
|
|
||||||
// valid data. There is one write strobe bit for each eight
|
|
||||||
// bits of the write data bus.
|
|
||||||
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
|
|
||||||
// Write valid. This signal indicates that valid write
|
|
||||||
// data and strobes are available.
|
|
||||||
input wire S_AXI_WVALID,
|
|
||||||
// Write ready. This signal indicates that the slave
|
|
||||||
// can accept the write data.
|
|
||||||
output wire S_AXI_WREADY,
|
|
||||||
// Write response. This signal indicates the status
|
|
||||||
// of the write transaction.
|
|
||||||
output wire [1 : 0] S_AXI_BRESP,
|
|
||||||
// Write response valid. This signal indicates that the channel
|
|
||||||
// is signaling a valid write response.
|
|
||||||
output wire S_AXI_BVALID,
|
|
||||||
// Response ready. This signal indicates that the master
|
|
||||||
// can accept a write response.
|
|
||||||
input wire S_AXI_BREADY,
|
|
||||||
// Read address (issued by master, acceped by Slave)
|
|
||||||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
|
|
||||||
// Protection type. This signal indicates the privilege
|
|
||||||
// and security level of the transaction, and whether the
|
|
||||||
// transaction is a data access or an instruction access.
|
|
||||||
input wire [2 : 0] S_AXI_ARPROT,
|
|
||||||
// Read address valid. This signal indicates that the channel
|
|
||||||
// is signaling valid read address and control information.
|
|
||||||
input wire S_AXI_ARVALID,
|
|
||||||
// Read address ready. This signal indicates that the slave is
|
|
||||||
// ready to accept an address and associated control signals.
|
|
||||||
output wire S_AXI_ARREADY,
|
|
||||||
// Read data (issued by slave)
|
|
||||||
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
|
|
||||||
// Read response. This signal indicates the status of the
|
|
||||||
// read transfer.
|
|
||||||
output wire [1 : 0] S_AXI_RRESP,
|
|
||||||
// Read valid. This signal indicates that the channel is
|
|
||||||
// signaling the required read data.
|
|
||||||
output wire S_AXI_RVALID,
|
|
||||||
// Read ready. This signal indicates that the master can
|
|
||||||
// accept the read data and response information.
|
|
||||||
input wire S_AXI_RREADY
|
|
||||||
);
|
|
||||||
|
|
||||||
// AXI4LITE signals
|
|
||||||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
|
|
||||||
reg axi_awready;
|
|
||||||
reg axi_wready;
|
|
||||||
reg [1 : 0] axi_bresp;
|
|
||||||
reg axi_bvalid;
|
|
||||||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
|
|
||||||
reg axi_arready;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
|
|
||||||
reg [1 : 0] axi_rresp;
|
|
||||||
reg axi_rvalid;
|
|
||||||
|
|
||||||
// Example-specific design signals
|
|
||||||
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
|
||||||
// ADDR_LSB is used for addressing 32/64 bit registers/memories
|
|
||||||
// ADDR_LSB = 2 for 32 bits (n downto 2)
|
|
||||||
// ADDR_LSB = 3 for 64 bits (n downto 3)
|
|
||||||
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
|
|
||||||
localparam integer OPT_MEM_ADDR_BITS = 2;
|
|
||||||
//----------------------------------------------
|
|
||||||
//-- Signals for user logic register space example
|
|
||||||
//------------------------------------------------
|
|
||||||
//-- Number of Slave Registers 8
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
|
|
||||||
wire slv_reg_rden;
|
|
||||||
wire slv_reg_wren;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
|
|
||||||
integer byte_index;
|
|
||||||
reg aw_en;
|
|
||||||
|
|
||||||
// I/O Connections assignments
|
|
||||||
|
|
||||||
assign S_AXI_AWREADY = axi_awready;
|
|
||||||
assign S_AXI_WREADY = axi_wready;
|
|
||||||
assign S_AXI_BRESP = axi_bresp;
|
|
||||||
assign S_AXI_BVALID = axi_bvalid;
|
|
||||||
assign S_AXI_ARREADY = axi_arready;
|
|
||||||
assign S_AXI_RDATA = axi_rdata;
|
|
||||||
assign S_AXI_RRESP = axi_rresp;
|
|
||||||
assign S_AXI_RVALID = axi_rvalid;
|
|
||||||
// Implement axi_awready generation
|
|
||||||
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
|
||||||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
|
||||||
// de-asserted when reset is low.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_awready <= 1'b0;
|
|
||||||
aw_en <= 1'b1;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
|
||||||
begin
|
|
||||||
// slave is ready to accept write address when
|
|
||||||
// there is a valid write address and write data
|
|
||||||
// on the write address and data bus. This design
|
|
||||||
// expects no outstanding transactions.
|
|
||||||
axi_awready <= 1'b1;
|
|
||||||
aw_en <= 1'b0;
|
|
||||||
end
|
|
||||||
else if (S_AXI_BREADY && axi_bvalid)
|
|
||||||
begin
|
|
||||||
aw_en <= 1'b1;
|
|
||||||
axi_awready <= 1'b0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
axi_awready <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement axi_awaddr latching
|
|
||||||
// This process is used to latch the address when both
|
|
||||||
// S_AXI_AWVALID and S_AXI_WVALID are valid.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_awaddr <= 0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
|
||||||
begin
|
|
||||||
// Write Address latching
|
|
||||||
axi_awaddr <= S_AXI_AWADDR;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement axi_wready generation
|
|
||||||
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
|
||||||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
|
||||||
// de-asserted when reset is low.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_wready <= 1'b0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
|
|
||||||
begin
|
|
||||||
// slave is ready to accept write data when
|
|
||||||
// there is a valid write address and write data
|
|
||||||
// on the write address and data bus. This design
|
|
||||||
// expects no outstanding transactions.
|
|
||||||
axi_wready <= 1'b1;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
axi_wready <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement memory mapped register select and write logic generation
|
|
||||||
// The write data is accepted and written to memory mapped registers when
|
|
||||||
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
|
||||||
// select byte enables of slave registers while writing.
|
|
||||||
// These registers are cleared when reset (active low) is applied.
|
|
||||||
// Slave register write enable is asserted when valid address and data are available
|
|
||||||
// and the slave is ready to accept the write address and write data.
|
|
||||||
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
slv_reg0 <= 32'h9;
|
|
||||||
slv_reg1 <= 0;
|
|
||||||
slv_reg2 <= 0;
|
|
||||||
slv_reg3 <= 0;
|
|
||||||
slv_reg4 <= 0;
|
|
||||||
slv_reg5 <= 0;
|
|
||||||
slv_reg6 <= 0;
|
|
||||||
slv_reg7 <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
if (slv_reg_wren)
|
|
||||||
begin
|
|
||||||
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
|
|
||||||
3'h0:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 0
|
|
||||||
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
3'h1:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 1
|
|
||||||
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
3'h2:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 2
|
|
||||||
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
3'h3:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 3
|
|
||||||
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
3'h4:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 3
|
|
||||||
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
3'h5:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 3
|
|
||||||
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
3'h6:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 3
|
|
||||||
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
3'h7:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 3
|
|
||||||
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
default : begin
|
|
||||||
slv_reg0 <= slv_reg0;
|
|
||||||
slv_reg1 <= slv_reg1;
|
|
||||||
slv_reg2 <= slv_reg2;
|
|
||||||
slv_reg3 <= slv_reg3;
|
|
||||||
slv_reg4 <= slv_reg4;
|
|
||||||
slv_reg5 <= slv_reg5;
|
|
||||||
slv_reg6 <= slv_reg6;
|
|
||||||
slv_reg7 <= slv_reg7;
|
|
||||||
end
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement write response logic generation
|
|
||||||
// The write response and response valid signals are asserted by the slave
|
|
||||||
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
|
||||||
// This marks the acceptance of address and indicates the status of
|
|
||||||
// write transaction.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_bvalid <= 0;
|
|
||||||
axi_bresp <= 2'b0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
|
|
||||||
begin
|
|
||||||
// indicates a valid write response is available
|
|
||||||
axi_bvalid <= 1'b1;
|
|
||||||
axi_bresp <= 2'b0; // 'OKAY' response
|
|
||||||
end // work error responses in future
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (S_AXI_BREADY && axi_bvalid)
|
|
||||||
//check if bready is asserted while bvalid is high)
|
|
||||||
//(there is a possibility that bready is always asserted high)
|
|
||||||
begin
|
|
||||||
axi_bvalid <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement axi_arready generation
|
|
||||||
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
|
||||||
// S_AXI_ARVALID is asserted. axi_awready is
|
|
||||||
// de-asserted when reset (active low) is asserted.
|
|
||||||
// The read address is also latched when S_AXI_ARVALID is
|
|
||||||
// asserted. axi_araddr is reset to zero on reset assertion.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_arready <= 1'b0;
|
|
||||||
axi_araddr <= 32'b0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (~axi_arready && S_AXI_ARVALID)
|
|
||||||
begin
|
|
||||||
// indicates that the slave has acceped the valid read address
|
|
||||||
axi_arready <= 1'b1;
|
|
||||||
// Read address latching
|
|
||||||
axi_araddr <= S_AXI_ARADDR;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
axi_arready <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement axi_arvalid generation
|
|
||||||
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
|
||||||
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
|
||||||
// data are available on the axi_rdata bus at this instance. The
|
|
||||||
// assertion of axi_rvalid marks the validity of read data on the
|
|
||||||
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
|
||||||
// is deasserted on reset (active low). axi_rresp and axi_rdata are
|
|
||||||
// cleared to zero on reset (active low).
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_rvalid <= 0;
|
|
||||||
axi_rresp <= 0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
|
|
||||||
begin
|
|
||||||
// Valid read data is available at the read data bus
|
|
||||||
axi_rvalid <= 1'b1;
|
|
||||||
axi_rresp <= 2'b0; // 'OKAY' response
|
|
||||||
end
|
|
||||||
else if (axi_rvalid && S_AXI_RREADY)
|
|
||||||
begin
|
|
||||||
// Read data is accepted by the master
|
|
||||||
axi_rvalid <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement memory mapped register select and read logic generation
|
|
||||||
// Slave register read enable is asserted when valid address is available
|
|
||||||
// and the slave is ready to accept the read address.
|
|
||||||
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
|
|
||||||
always @(*)
|
|
||||||
begin
|
|
||||||
// Address decoding for reading registers
|
|
||||||
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
|
|
||||||
3'h0 : reg_data_out <= slv_reg0;
|
|
||||||
3'h1 : reg_data_out <= slv_reg1;
|
|
||||||
3'h2 : reg_data_out <= slv_reg2;
|
|
||||||
3'h3 : reg_data_out <= slv_reg3;
|
|
||||||
3'h4 : reg_data_out <= slv_reg4;
|
|
||||||
3'h5 : reg_data_out <= slv_reg5;
|
|
||||||
3'h6 : reg_data_out <= slv_reg6;
|
|
||||||
3'h7 : reg_data_out <= slv_reg7;
|
|
||||||
default : reg_data_out <= 0;
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
|
|
||||||
// Output register or memory read data
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_rdata <= 0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
// When there is a valid read address (S_AXI_ARVALID) with
|
|
||||||
// acceptance of read address by the slave (axi_arready),
|
|
||||||
// output the read dada
|
|
||||||
if (slv_reg_rden)
|
|
||||||
begin
|
|
||||||
axi_rdata <= reg_data_out; // register read data
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
wire in_signal_tmp = slv_reg0[1] ? slv_reg0[2] : in_signal; //0:external 1:internal
|
|
||||||
wire encoder_rst_n = slv_reg0[0] & S_AXI_ARESETN & (slv_reg0[3] | exrst_n);
|
|
||||||
// Add user logic here
|
|
||||||
encoder encoder_inst(
|
|
||||||
.sys_clk(S_AXI_ACLK),
|
|
||||||
.rst_n(encoder_rst_n),
|
|
||||||
.in_signal(in_signal_tmp),
|
|
||||||
.valve_signal_divider(slv_reg1),
|
|
||||||
.camera_signal_divider_a(slv_reg2),
|
|
||||||
.camera_signal_divider_b(slv_reg3),
|
|
||||||
.camera_signal_divider_c(slv_reg4),
|
|
||||||
.camera_signal_divider_d(slv_reg5),
|
|
||||||
|
|
||||||
.out_signal_valve_posedge(out_signal_valve_posedge),
|
|
||||||
.out_signal_valve(out_signal_valve),
|
|
||||||
.out_signal_camera_a_posedge(out_signal_camera_a_posedge),
|
|
||||||
.out_signal_camera_b_posedge(out_signal_camera_b_posedge),
|
|
||||||
.out_signal_camera_c_posedge(out_signal_camera_c_posedge),
|
|
||||||
.out_signal_camera_d_posedge(out_signal_camera_d_posedge),
|
|
||||||
.out_signal_camera_a(out_signal_camera_a),
|
|
||||||
.out_signal_camera_b(out_signal_camera_b),
|
|
||||||
.out_signal_camera_c(out_signal_camera_c),
|
|
||||||
.out_signal_camera_d(out_signal_camera_d)
|
|
||||||
);
|
|
||||||
// User logic ends
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
Binary file not shown.
@ -1,226 +0,0 @@
|
|||||||
module encoder(
|
|
||||||
input sys_clk,
|
|
||||||
input rst_n,
|
|
||||||
input in_signal,
|
|
||||||
input [31:0] valve_signal_divider,
|
|
||||||
input [31:0] camera_signal_divider_a,
|
|
||||||
input [31:0] camera_signal_divider_b,
|
|
||||||
input [31:0] camera_signal_divider_c,
|
|
||||||
input [31:0] camera_signal_divider_d,
|
|
||||||
output out_signal_valve_posedge,
|
|
||||||
output reg out_signal_valve,
|
|
||||||
output out_signal_camera_a_posedge,
|
|
||||||
output out_signal_camera_b_posedge,
|
|
||||||
output out_signal_camera_c_posedge,
|
|
||||||
output out_signal_camera_d_posedge,
|
|
||||||
output reg out_signal_camera_a,
|
|
||||||
output reg out_signal_camera_b,
|
|
||||||
output reg out_signal_camera_c,
|
|
||||||
output reg out_signal_camera_d
|
|
||||||
);
|
|
||||||
|
|
||||||
wire [31:0] valve_signal_divider_div_2 = {1'b0, valve_signal_divider[31:1]};
|
|
||||||
wire [31:0] camera_signal_divider_a_div_2 = {1'b0, camera_signal_divider_a[31:1]};
|
|
||||||
wire [31:0] camera_signal_divider_b_div_2 = {1'b0, camera_signal_divider_b[31:1]};
|
|
||||||
wire [31:0] camera_signal_divider_c_div_2 = {1'b0, camera_signal_divider_c[31:1]};
|
|
||||||
wire [31:0] camera_signal_divider_d_div_2 = {1'b0, camera_signal_divider_d[31:1]};
|
|
||||||
|
|
||||||
reg [31:0] valve_signal_divider_tmp;
|
|
||||||
reg [31:0] camera_signal_divider_a_tmp;
|
|
||||||
reg [31:0] camera_signal_divider_b_tmp;
|
|
||||||
reg [31:0] camera_signal_divider_c_tmp;
|
|
||||||
reg [31:0] camera_signal_divider_d_tmp;
|
|
||||||
|
|
||||||
wire rst_n_inter = (valve_signal_divider_tmp == valve_signal_divider) && (camera_signal_divider_a_tmp == camera_signal_divider_a) && (camera_signal_divider_b_tmp == camera_signal_divider_b)&& (camera_signal_divider_c_tmp == camera_signal_divider_c)&& (camera_signal_divider_d_tmp == camera_signal_divider_d)&& rst_n;
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
valve_signal_divider_tmp <= valve_signal_divider;
|
|
||||||
camera_signal_divider_a_tmp <= camera_signal_divider_a;
|
|
||||||
camera_signal_divider_b_tmp <= camera_signal_divider_b;
|
|
||||||
camera_signal_divider_c_tmp <= camera_signal_divider_c;
|
|
||||||
camera_signal_divider_d_tmp <= camera_signal_divider_d;
|
|
||||||
end
|
|
||||||
|
|
||||||
reg [1:0] in_signal_buffer;
|
|
||||||
wire in_signal_posedge = in_signal_buffer[0] && !in_signal_buffer[1];
|
|
||||||
wire in_signal_negedge = !in_signal_buffer[0] && in_signal_buffer[1];
|
|
||||||
wire in_signal_edge = in_signal_posedge || in_signal_negedge;
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
in_signal_buffer <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
in_signal_buffer[0] <= in_signal;
|
|
||||||
in_signal_buffer[1] <= in_signal_buffer[0];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
reg [1:0] out_signal_valve_buffer;
|
|
||||||
// Actually, !out_signal_valve_buffer[0] && out_signal_valve_buffer[1] is the negedge, it is name posedge because I accidentally made a mistake.
|
|
||||||
// When I found the mistake, It's too much trouble to change the name, so it was not changed.
|
|
||||||
assign out_signal_valve_posedge = !out_signal_valve_buffer[0] && out_signal_valve_buffer[1];//实际为下降沿
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_valve_buffer <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
out_signal_valve_buffer[0] <= out_signal_valve;
|
|
||||||
out_signal_valve_buffer[1] <= out_signal_valve_buffer[0];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
reg[1:0] out_signal_camera_a_buffer;
|
|
||||||
reg[1:0] out_signal_camera_b_buffer;
|
|
||||||
reg[1:0] out_signal_camera_c_buffer;
|
|
||||||
reg[1:0] out_signal_camera_d_buffer;
|
|
||||||
assign out_signal_camera_a_posedge = out_signal_camera_a_buffer[0] && !out_signal_camera_a_buffer[1];
|
|
||||||
assign out_signal_camera_b_posedge = out_signal_camera_b_buffer[0] && !out_signal_camera_b_buffer[1];
|
|
||||||
assign out_signal_camera_c_posedge = out_signal_camera_c_buffer[0] && !out_signal_camera_c_buffer[1];
|
|
||||||
assign out_signal_camera_d_posedge = out_signal_camera_d_buffer[0] && !out_signal_camera_d_buffer[1];
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_camera_a_buffer <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
out_signal_camera_a_buffer[0] <= out_signal_camera_a;
|
|
||||||
out_signal_camera_a_buffer[1] <= out_signal_camera_a_buffer[0];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_camera_b_buffer <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
out_signal_camera_b_buffer[0] <= out_signal_camera_b;
|
|
||||||
out_signal_camera_b_buffer[1] <= out_signal_camera_b_buffer[0];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_camera_c_buffer <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
out_signal_camera_c_buffer[0] <= out_signal_camera_c;
|
|
||||||
out_signal_camera_c_buffer[1] <= out_signal_camera_c_buffer[0];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_camera_d_buffer <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
out_signal_camera_d_buffer[0] <= out_signal_camera_d;
|
|
||||||
out_signal_camera_d_buffer[1] <= out_signal_camera_d_buffer[0];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
reg [31:0] counter_valve;
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
counter_valve <= 0;
|
|
||||||
end
|
|
||||||
else if (counter_valve == valve_signal_divider_div_2) begin
|
|
||||||
counter_valve <= 0;
|
|
||||||
end
|
|
||||||
else if (in_signal_posedge) begin
|
|
||||||
counter_valve <= counter_valve + 1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
reg [31:0] counter_camera_a;
|
|
||||||
reg [31:0] counter_camera_b;
|
|
||||||
reg [31:0] counter_camera_c;
|
|
||||||
reg [31:0] counter_camera_d;
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
counter_camera_a <= 0;
|
|
||||||
end
|
|
||||||
else if (counter_camera_a == camera_signal_divider_a_div_2) begin
|
|
||||||
counter_camera_a <= 0;
|
|
||||||
end
|
|
||||||
else if (in_signal_posedge) begin
|
|
||||||
counter_camera_a <= counter_camera_a + 1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
counter_camera_b <= 0;
|
|
||||||
end
|
|
||||||
else if (counter_camera_b == camera_signal_divider_b_div_2) begin
|
|
||||||
counter_camera_b <= 0;
|
|
||||||
end
|
|
||||||
else if (in_signal_posedge) begin
|
|
||||||
counter_camera_b <= counter_camera_b + 1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
counter_camera_c <= 0;
|
|
||||||
end
|
|
||||||
else if (counter_camera_c == camera_signal_divider_c_div_2) begin
|
|
||||||
counter_camera_c <= 0;
|
|
||||||
end
|
|
||||||
else if (in_signal_posedge) begin
|
|
||||||
counter_camera_c <= counter_camera_c + 1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
counter_camera_d <= 0;
|
|
||||||
end
|
|
||||||
else if (counter_camera_d == camera_signal_divider_d_div_2) begin
|
|
||||||
counter_camera_d <= 0;
|
|
||||||
end
|
|
||||||
else if (in_signal_posedge) begin
|
|
||||||
counter_camera_d <= counter_camera_d + 1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_valve <= 0;
|
|
||||||
end
|
|
||||||
else if (counter_valve == valve_signal_divider_div_2) begin
|
|
||||||
out_signal_valve <= !out_signal_valve;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_camera_a <= 1; // Please set the camera to posedge trig mode, in case of trig at half period of the first cycle.
|
|
||||||
end
|
|
||||||
else if (counter_camera_a == camera_signal_divider_a_div_2) begin
|
|
||||||
out_signal_camera_a <= !out_signal_camera_a;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_camera_b <= 1; // Please set the camera to posedge trig mode, in case of trig at half period of the first cycle.
|
|
||||||
end
|
|
||||||
else if (counter_camera_b == camera_signal_divider_b_div_2) begin
|
|
||||||
out_signal_camera_b <= !out_signal_camera_b;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_camera_c <= 1; // Please set the camera to posedge trig mode, in case of trig at half period of the first cycle.
|
|
||||||
end
|
|
||||||
else if (counter_camera_c == camera_signal_divider_c_div_2) begin
|
|
||||||
out_signal_camera_c <= !out_signal_camera_c;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge sys_clk) begin
|
|
||||||
if (!rst_n_inter) begin
|
|
||||||
out_signal_camera_d <= 1; // Please set the camera to posedge trig mode, in case of trig at half period of the first cycle.
|
|
||||||
end
|
|
||||||
else if (counter_camera_d == camera_signal_divider_d_div_2) begin
|
|
||||||
out_signal_camera_d <= !out_signal_camera_d;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,56 +0,0 @@
|
|||||||
# Definitional proc to organize widgets for parameters.
|
|
||||||
proc init_gui { IPINST } {
|
|
||||||
ipgui::add_param $IPINST -name "Component_Name"
|
|
||||||
#Adding Page
|
|
||||||
ipgui::add_page $IPINST -name "Page 0"
|
|
||||||
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
|
||||||
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
|
||||||
# Procedure called to validate C_S00_AXI_DATA_WIDTH
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
|
||||||
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
|
||||||
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
|
||||||
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
|
||||||
# Procedure called to validate C_S00_AXI_BASEADDR
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
|
||||||
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
|
||||||
# Procedure called to validate C_S00_AXI_HIGHADDR
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,53 +0,0 @@
|
|||||||
# Definitional proc to organize widgets for parameters.
|
|
||||||
proc init_gui { IPINST } {
|
|
||||||
ipgui::add_param $IPINST -name "Component_Name"
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
|
||||||
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
|
||||||
# Procedure called to validate C_S00_AXI_DATA_WIDTH
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
|
||||||
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
|
||||||
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
|
||||||
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
|
||||||
# Procedure called to validate C_S00_AXI_BASEADDR
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
|
||||||
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
|
||||||
# Procedure called to validate C_S00_AXI_HIGHADDR
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,86 +0,0 @@
|
|||||||
|
|
||||||
proc init { cellpath otherInfo } {
|
|
||||||
|
|
||||||
set cell_handle [get_bd_cells $cellpath]
|
|
||||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
|
||||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
|
||||||
set full_sbusif_list [list ]
|
|
||||||
|
|
||||||
foreach busif $all_busif {
|
|
||||||
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
|
|
||||||
set busif_param_list [list]
|
|
||||||
set busif_name [get_property NAME $busif]
|
|
||||||
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
foreach tparam $axi_standard_param_list {
|
|
||||||
lappend busif_param_list "C_${busif_name}_${tparam}"
|
|
||||||
}
|
|
||||||
bd::mark_propagate_only $cell_handle $busif_param_list
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
proc pre_propagate {cellpath otherInfo } {
|
|
||||||
|
|
||||||
set cell_handle [get_bd_cells $cellpath]
|
|
||||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
|
||||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
|
||||||
|
|
||||||
foreach busif $all_busif {
|
|
||||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
|
|
||||||
set busif_name [get_property NAME $busif]
|
|
||||||
foreach tparam $axi_standard_param_list {
|
|
||||||
set busif_param_name "C_${busif_name}_${tparam}"
|
|
||||||
|
|
||||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
|
||||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
|
||||||
|
|
||||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
|
||||||
if { $val_on_cell != "" } {
|
|
||||||
set_property CONFIG.${tparam} $val_on_cell $busif
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
proc propagate {cellpath otherInfo } {
|
|
||||||
|
|
||||||
set cell_handle [get_bd_cells $cellpath]
|
|
||||||
set all_busif [get_bd_intf_pins $cellpath/*]
|
|
||||||
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
|
|
||||||
|
|
||||||
foreach busif $all_busif {
|
|
||||||
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
|
|
||||||
continue
|
|
||||||
}
|
|
||||||
|
|
||||||
set busif_name [get_property NAME $busif]
|
|
||||||
foreach tparam $axi_standard_param_list {
|
|
||||||
set busif_param_name "C_${busif_name}_${tparam}"
|
|
||||||
|
|
||||||
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
|
|
||||||
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
|
|
||||||
|
|
||||||
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
|
|
||||||
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
|
|
||||||
if { $val_on_cell_intf_pin != "" } {
|
|
||||||
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,993 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
||||||
<spirit:vendor>user.org</spirit:vendor>
|
|
||||||
<spirit:library>user</spirit:library>
|
|
||||||
<spirit:name>ip_fan</spirit:name>
|
|
||||||
<spirit:version>1.0</spirit:version>
|
|
||||||
<spirit:busInterfaces>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>S00_AXI</spirit:name>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave>
|
|
||||||
<spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
|
|
||||||
</spirit:slave>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>AWADDR</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_awaddr</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>AWPROT</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_awprot</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>AWVALID</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_awvalid</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>AWREADY</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_awready</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>WDATA</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_wdata</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>WSTRB</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_wstrb</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>WVALID</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_wvalid</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>WREADY</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_wready</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>BRESP</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_bresp</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>BVALID</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_bvalid</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>BREADY</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_bready</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>ARADDR</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_araddr</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>ARPROT</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_arprot</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>ARVALID</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_arvalid</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>ARREADY</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_arready</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RDATA</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_rdata</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RRESP</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_rresp</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RVALID</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_rvalid</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RREADY</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_rready</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>WIZ_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>WIZ_NUM_REG</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">4</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
|
|
||||||
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>S00_AXI_RST</spirit:name>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>RST</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_aresetn</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>POLARITY</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
<spirit:busInterface>
|
|
||||||
<spirit:name>S00_AXI_CLK</spirit:name>
|
|
||||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
||||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
||||||
<spirit:slave/>
|
|
||||||
<spirit:portMaps>
|
|
||||||
<spirit:portMap>
|
|
||||||
<spirit:logicalPort>
|
|
||||||
<spirit:name>CLK</spirit:name>
|
|
||||||
</spirit:logicalPort>
|
|
||||||
<spirit:physicalPort>
|
|
||||||
<spirit:name>s00_axi_aclk</spirit:name>
|
|
||||||
</spirit:physicalPort>
|
|
||||||
</spirit:portMap>
|
|
||||||
</spirit:portMaps>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
||||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:busInterface>
|
|
||||||
</spirit:busInterfaces>
|
|
||||||
<spirit:memoryMaps>
|
|
||||||
<spirit:memoryMap>
|
|
||||||
<spirit:name>S00_AXI</spirit:name>
|
|
||||||
<spirit:addressBlock>
|
|
||||||
<spirit:name>S00_AXI_reg</spirit:name>
|
|
||||||
<spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
|
|
||||||
<spirit:range spirit:format="long">4096</spirit:range>
|
|
||||||
<spirit:width spirit:format="long">32</spirit:width>
|
|
||||||
<spirit:usage>register</spirit:usage>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
||||||
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
||||||
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:addressBlock>
|
|
||||||
</spirit:memoryMap>
|
|
||||||
</spirit:memoryMaps>
|
|
||||||
<spirit:model>
|
|
||||||
<spirit:views>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
|
||||||
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
|
||||||
<spirit:language>verilog</spirit:language>
|
|
||||||
<spirit:modelName>ip_fan_v1_0</spirit:modelName>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>viewChecksum</spirit:name>
|
|
||||||
<spirit:value>728a76ba</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
|
||||||
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
|
||||||
<spirit:language>verilog</spirit:language>
|
|
||||||
<spirit:modelName>ip_fan_v1_0</spirit:modelName>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>viewChecksum</spirit:name>
|
|
||||||
<spirit:value>728a76ba</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_softwaredriver</spirit:name>
|
|
||||||
<spirit:displayName>Software Driver</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>viewChecksum</spirit:name>
|
|
||||||
<spirit:value>33320685</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_xpgui</spirit:name>
|
|
||||||
<spirit:displayName>UI Layout</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>viewChecksum</spirit:name>
|
|
||||||
<spirit:value>0e00759d</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>bd_tcl</spirit:name>
|
|
||||||
<spirit:displayName>Block Diagram</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>bd_tcl_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>viewChecksum</spirit:name>
|
|
||||||
<spirit:value>45a2f450</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
</spirit:views>
|
|
||||||
<spirit:ports>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>fan</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_aclk</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_aresetn</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_awaddr</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_awprot</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long">2</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_awvalid</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_awready</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_wdata</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_wstrb</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) / 8) - 1)">3</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_wvalid</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_wready</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_bresp</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long">1</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_bvalid</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_bready</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_araddr</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_arprot</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long">2</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_arvalid</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_arready</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_rdata</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_rresp</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:vector>
|
|
||||||
<spirit:left spirit:format="long">1</spirit:left>
|
|
||||||
<spirit:right spirit:format="long">0</spirit:right>
|
|
||||||
</spirit:vector>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_rvalid</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>out</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
<spirit:port>
|
|
||||||
<spirit:name>s00_axi_rready</spirit:name>
|
|
||||||
<spirit:wire>
|
|
||||||
<spirit:direction>in</spirit:direction>
|
|
||||||
<spirit:wireTypeDefs>
|
|
||||||
<spirit:wireTypeDef>
|
|
||||||
<spirit:typeName>wire</spirit:typeName>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
||||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
||||||
</spirit:wireTypeDef>
|
|
||||||
</spirit:wireTypeDefs>
|
|
||||||
</spirit:wire>
|
|
||||||
</spirit:port>
|
|
||||||
</spirit:ports>
|
|
||||||
<spirit:modelParameters>
|
|
||||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
|
||||||
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
|
|
||||||
<spirit:description>Width of S_AXI data bus</spirit:description>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
|
|
||||||
<spirit:description>Width of S_AXI address bus</spirit:description>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">4</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>FAN_PWM_FREQ</spirit:name>
|
|
||||||
<spirit:displayName>Fan Pwm Freq</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FAN_PWM_FREQ">10</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
<spirit:modelParameter spirit:dataType="integer">
|
|
||||||
<spirit:name>SYS_CLK_FREQ</spirit:name>
|
|
||||||
<spirit:displayName>Sys Clk Freq</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SYS_CLK_FREQ">200000000</spirit:value>
|
|
||||||
</spirit:modelParameter>
|
|
||||||
</spirit:modelParameters>
|
|
||||||
</spirit:model>
|
|
||||||
<spirit:choices>
|
|
||||||
<spirit:choice>
|
|
||||||
<spirit:name>choice_list_6fc15197</spirit:name>
|
|
||||||
<spirit:enumeration>32</spirit:enumeration>
|
|
||||||
</spirit:choice>
|
|
||||||
<spirit:choice>
|
|
||||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
|
||||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
||||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
||||||
</spirit:choice>
|
|
||||||
<spirit:choice>
|
|
||||||
<spirit:name>choice_pairs_ce1226b1</spirit:name>
|
|
||||||
<spirit:enumeration spirit:text="true">1</spirit:enumeration>
|
|
||||||
<spirit:enumeration spirit:text="false">0</spirit:enumeration>
|
|
||||||
</spirit:choice>
|
|
||||||
</spirit:choices>
|
|
||||||
<spirit:fileSets>
|
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>hdl/ip_fan_v1_0_S00_AXI.v</spirit:name>
|
|
||||||
<spirit:fileType>verilogSource</spirit:fileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>hdl/ip_fan_v1_0.v</spirit:name>
|
|
||||||
<spirit:fileType>verilogSource</spirit:fileType>
|
|
||||||
<spirit:userFileType>CHECKSUM_686eeef6</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>hdl/ip_fan_v1_0_S00_AXI.v</spirit:name>
|
|
||||||
<spirit:fileType>verilogSource</spirit:fileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>hdl/ip_fan_v1_0.v</spirit:name>
|
|
||||||
<spirit:fileType>verilogSource</spirit:fileType>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>drivers/ip_fan_v1_0/data/ip_fan.mdd</spirit:name>
|
|
||||||
<spirit:userFileType>mdd</spirit:userFileType>
|
|
||||||
<spirit:userFileType>driver_mdd</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>drivers/ip_fan_v1_0/data/ip_fan.tcl</spirit:name>
|
|
||||||
<spirit:fileType>tclSource</spirit:fileType>
|
|
||||||
<spirit:userFileType>driver_tcl</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>drivers/ip_fan_v1_0/src/Makefile</spirit:name>
|
|
||||||
<spirit:userFileType>driver_src</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>drivers/ip_fan_v1_0/src/ip_fan.h</spirit:name>
|
|
||||||
<spirit:fileType>cSource</spirit:fileType>
|
|
||||||
<spirit:userFileType>driver_src</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>drivers/ip_fan_v1_0/src/ip_fan.c</spirit:name>
|
|
||||||
<spirit:fileType>cSource</spirit:fileType>
|
|
||||||
<spirit:userFileType>driver_src</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>drivers/ip_fan_v1_0/src/ip_fan_selftest.c</spirit:name>
|
|
||||||
<spirit:fileType>cSource</spirit:fileType>
|
|
||||||
<spirit:userFileType>driver_src</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>xgui/ip_fan_v1_0.tcl</spirit:name>
|
|
||||||
<spirit:fileType>tclSource</spirit:fileType>
|
|
||||||
<spirit:userFileType>CHECKSUM_0e00759d</spirit:userFileType>
|
|
||||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>bd_tcl_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>bd/bd.tcl</spirit:name>
|
|
||||||
<spirit:fileType>tclSource</spirit:fileType>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
</spirit:fileSets>
|
|
||||||
<spirit:description>ip for controlling fan</spirit:description>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
|
|
||||||
<spirit:description>Width of S_AXI data bus</spirit:description>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:enablement>
|
|
||||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
|
|
||||||
</xilinx:enablement>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
|
|
||||||
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
|
|
||||||
<spirit:description>Width of S_AXI address bus</spirit:description>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">4</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:enablement>
|
|
||||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_ADDR_WIDTH">false</xilinx:isEnabled>
|
|
||||||
</xilinx:enablement>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_S00_AXI_BASEADDR</spirit:name>
|
|
||||||
<spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:enablement>
|
|
||||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
|
|
||||||
</xilinx:enablement>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
|
|
||||||
<spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:parameterInfo>
|
|
||||||
<xilinx:enablement>
|
|
||||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
|
|
||||||
</xilinx:enablement>
|
|
||||||
</xilinx:parameterInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>Component_Name</spirit:name>
|
|
||||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ip_fan_v1_0</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>FAN_PWM_FREQ</spirit:name>
|
|
||||||
<spirit:displayName>FAN_PWM_FREQ (HZ)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FAN_PWM_FREQ">10</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>SYS_CLK_FREQ</spirit:name>
|
|
||||||
<spirit:displayName>SYS_CLK_FREQ (HZ)</spirit:displayName>
|
|
||||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SYS_CLK_FREQ">200000000</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
<spirit:vendorExtensions>
|
|
||||||
<xilinx:coreExtensions>
|
|
||||||
<xilinx:supportedFamilies>
|
|
||||||
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
|
|
||||||
<xilinx:family xilinx:lifeCycle="Beta">qzynq</xilinx:family>
|
|
||||||
<xilinx:family xilinx:lifeCycle="Beta">azynq</xilinx:family>
|
|
||||||
</xilinx:supportedFamilies>
|
|
||||||
<xilinx:taxonomies>
|
|
||||||
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
|
|
||||||
</xilinx:taxonomies>
|
|
||||||
<xilinx:displayName>ip_fan_v1.0</xilinx:displayName>
|
|
||||||
<xilinx:coreRevision>13</xilinx:coreRevision>
|
|
||||||
<xilinx:coreCreationDateTime>2022-07-18T09:29:45Z</xilinx:coreCreationDateTime>
|
|
||||||
<xilinx:tags>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@7036eae6_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@58f22a27_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@d868186_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4c2eef57_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@b4e86a4_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4533e21b_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@40a5cbed_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2f562645_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@3e49a6d_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2790bfd8_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@73386b48_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@216dd667_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4aecaebf_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4a551590_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@6e79563d_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@5104d385_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@21593c5c_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@6189e0fc_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@12422869_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@63e76193_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@114f09f1_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@331f1b11_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@536f41ea_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@477ce2fc_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@678e8bed_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@738474fc_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2e3e96b2_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@1ebc3cae_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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<xilinx:tag xilinx:name="ui.data.coregen.df@7cae67d9_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.df@31f1659e_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@31bc4dda_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4579ba33_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@529116b7_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@223ef8e4_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@5a6ca93_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@571c3dbb_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@3dc816aa_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@736c2d75_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@32bcafc0_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@6b64d32_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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<xilinx:tag xilinx:name="ui.data.coregen.df@4cf4d6b0_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@626f7aef_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4613c145_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4ffc10a9_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2bf79702_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@7ecf5c24_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@45548ca8_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4c59aaf3_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@6ec56c95_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4f686fec_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4f2de768_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@503e27dd_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@6d8b6018_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@72de2e57_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@78239028_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@59ab1890_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@62973965_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@1ca9d243_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@5563c136_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@1809d4db_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@59886eaf_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@7d1ea10c_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4ae2dc99_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@3e3239e9_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4a8e83c0_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@27ae9b82_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@25e880ba_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@303fc856_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@5cb31d19_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@41d7f446_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@41551b0_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@6daccddb_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@63cdb99d_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2850da19_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@689d8c93_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@1586531d_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2649a793_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2a2a8cbd_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@49c79f44_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@1c1ffc80_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
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||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@670fb08_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@44765bd6_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@424ecc2_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@79dee093_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@3c813888_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@24179acc_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2e2c9969_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@5a49f9e5_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4853dd31_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@20d62eff_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@608e2a0e_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@1f278196_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@278255f1_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@76f0f70_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@46dc8129_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@34771eb1_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@7d978e81_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2a570351_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@cd5b215_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@5edfac0d_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@5120f524_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@764cf4b_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2cc08c44_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@7f941e9e_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@44e179b8_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@5f8dead7_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@7ac3a59a_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@6c7a5fcd_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@2cbdfa17_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@744ba43f_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@5af208c0_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@760406b_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@16d2e54d_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4692299f_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@1d56c6fd_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@46014b2c_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@1542e926_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@590155b6_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@76ef66aa_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@6a9aeb57_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@52b4bb8d_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@54c410d9_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@7ffb7ee2_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@27718d4b_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@20295b7_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@66af1248_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@76e985c6_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@11a375a0_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@4b4684e_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
<xilinx:tag xilinx:name="ui.data.coregen.df@53143cef_ARCHIVE_LOCATION">/home/miaow/zynq/ip_repo/ip_fan_1.0</xilinx:tag>
|
|
||||||
</xilinx:tags>
|
|
||||||
</xilinx:coreExtensions>
|
|
||||||
<xilinx:packagingInfo>
|
|
||||||
<xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
|
|
||||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="7a63f3fc"/>
|
|
||||||
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
|
|
||||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="15fe8242"/>
|
|
||||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="a5786c5d"/>
|
|
||||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="57f8198d"/>
|
|
||||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="66dfc9a8"/>
|
|
||||||
</xilinx:packagingInfo>
|
|
||||||
</spirit:vendorExtensions>
|
|
||||||
</spirit:component>
|
|
||||||
@ -1,10 +0,0 @@
|
|||||||
|
|
||||||
|
|
||||||
OPTION psf_version = 2.1;
|
|
||||||
|
|
||||||
BEGIN DRIVER ip_fan
|
|
||||||
OPTION supported_peripherals = (ip_fan);
|
|
||||||
OPTION copyfiles = all;
|
|
||||||
OPTION VERSION = 1.0;
|
|
||||||
OPTION NAME = ip_fan;
|
|
||||||
END DRIVER
|
|
||||||
@ -1,5 +0,0 @@
|
|||||||
|
|
||||||
|
|
||||||
proc generate {drv_handle} {
|
|
||||||
xdefine_include_file $drv_handle "xparameters.h" "ip_fan" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
|
|
||||||
}
|
|
||||||
@ -1,26 +0,0 @@
|
|||||||
COMPILER=
|
|
||||||
ARCHIVER=
|
|
||||||
CP=cp
|
|
||||||
COMPILER_FLAGS=
|
|
||||||
EXTRA_COMPILER_FLAGS=
|
|
||||||
LIB=libxil.a
|
|
||||||
|
|
||||||
RELEASEDIR=../../../lib
|
|
||||||
INCLUDEDIR=../../../include
|
|
||||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
|
||||||
|
|
||||||
INCLUDEFILES=*.h
|
|
||||||
LIBSOURCES=*.c
|
|
||||||
OUTS = *.o
|
|
||||||
|
|
||||||
libs:
|
|
||||||
echo "Compiling ip_fan..."
|
|
||||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
|
||||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
|
||||||
make clean
|
|
||||||
|
|
||||||
include:
|
|
||||||
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
|
|
||||||
|
|
||||||
clean:
|
|
||||||
rm -rf ${OUTS}
|
|
||||||
@ -1,6 +0,0 @@
|
|||||||
|
|
||||||
|
|
||||||
/***************************** Include Files *******************************/
|
|
||||||
#include "ip_fan.h"
|
|
||||||
|
|
||||||
/************************** Function Definitions ***************************/
|
|
||||||
@ -1,79 +0,0 @@
|
|||||||
|
|
||||||
#ifndef IP_FAN_H
|
|
||||||
#define IP_FAN_H
|
|
||||||
|
|
||||||
|
|
||||||
/****************** Include Files ********************/
|
|
||||||
#include "xil_types.h"
|
|
||||||
#include "xstatus.h"
|
|
||||||
|
|
||||||
#define IP_FAN_S00_AXI_SLV_REG0_OFFSET 0
|
|
||||||
#define IP_FAN_S00_AXI_SLV_REG1_OFFSET 4
|
|
||||||
#define IP_FAN_S00_AXI_SLV_REG2_OFFSET 8
|
|
||||||
#define IP_FAN_S00_AXI_SLV_REG3_OFFSET 12
|
|
||||||
|
|
||||||
|
|
||||||
/**************************** Type Definitions *****************************/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* Write a value to a IP_FAN register. A 32 bit write is performed.
|
|
||||||
* If the component is implemented in a smaller width, only the least
|
|
||||||
* significant data is written.
|
|
||||||
*
|
|
||||||
* @param BaseAddress is the base address of the IP_FANdevice.
|
|
||||||
* @param RegOffset is the register offset from the base to write to.
|
|
||||||
* @param Data is the data written to the register.
|
|
||||||
*
|
|
||||||
* @return None.
|
|
||||||
*
|
|
||||||
* @note
|
|
||||||
* C-style signature:
|
|
||||||
* void IP_FAN_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define IP_FAN_mWriteReg(BaseAddress, RegOffset, Data) \
|
|
||||||
Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
|
|
||||||
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* Read a value from a IP_FAN register. A 32 bit read is performed.
|
|
||||||
* If the component is implemented in a smaller width, only the least
|
|
||||||
* significant data is read from the register. The most significant data
|
|
||||||
* will be read as 0.
|
|
||||||
*
|
|
||||||
* @param BaseAddress is the base address of the IP_FAN device.
|
|
||||||
* @param RegOffset is the register offset from the base to write to.
|
|
||||||
*
|
|
||||||
* @return Data is the data from the register.
|
|
||||||
*
|
|
||||||
* @note
|
|
||||||
* C-style signature:
|
|
||||||
* u32 IP_FAN_mReadReg(u32 BaseAddress, unsigned RegOffset)
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define IP_FAN_mReadReg(BaseAddress, RegOffset) \
|
|
||||||
Xil_In32((BaseAddress) + (RegOffset))
|
|
||||||
|
|
||||||
/************************** Function Prototypes ****************************/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
|
||||||
* resets of the device are performed.
|
|
||||||
*
|
|
||||||
* If the hardware system is not built correctly, this function may never
|
|
||||||
* return to the caller.
|
|
||||||
*
|
|
||||||
* @param baseaddr_p is the base address of the IP_FAN instance to be worked on.
|
|
||||||
*
|
|
||||||
* @return
|
|
||||||
*
|
|
||||||
* - XST_SUCCESS if all self-test code passed
|
|
||||||
* - XST_FAILURE if any self-test code failed
|
|
||||||
*
|
|
||||||
* @note Caching must be turned off for this function to work.
|
|
||||||
* @note Self test may fail if data memory and device are not on the same bus.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
XStatus IP_FAN_Reg_SelfTest(void * baseaddr_p);
|
|
||||||
|
|
||||||
#endif // IP_FAN_H
|
|
||||||
@ -1,60 +0,0 @@
|
|||||||
|
|
||||||
/***************************** Include Files *******************************/
|
|
||||||
#include "ip_fan.h"
|
|
||||||
#include "xparameters.h"
|
|
||||||
#include "stdio.h"
|
|
||||||
#include "xil_io.h"
|
|
||||||
|
|
||||||
/************************** Constant Definitions ***************************/
|
|
||||||
#define READ_WRITE_MUL_FACTOR 0x10
|
|
||||||
|
|
||||||
/************************** Function Definitions ***************************/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
* Run a self-test on the driver/device. Note this may be a destructive test if
|
|
||||||
* resets of the device are performed.
|
|
||||||
*
|
|
||||||
* If the hardware system is not built correctly, this function may never
|
|
||||||
* return to the caller.
|
|
||||||
*
|
|
||||||
* @param baseaddr_p is the base address of the IP_FANinstance to be worked on.
|
|
||||||
*
|
|
||||||
* @return
|
|
||||||
*
|
|
||||||
* - XST_SUCCESS if all self-test code passed
|
|
||||||
* - XST_FAILURE if any self-test code failed
|
|
||||||
*
|
|
||||||
* @note Caching must be turned off for this function to work.
|
|
||||||
* @note Self test may fail if data memory and device are not on the same bus.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
XStatus IP_FAN_Reg_SelfTest(void * baseaddr_p)
|
|
||||||
{
|
|
||||||
u32 baseaddr;
|
|
||||||
int write_loop_index;
|
|
||||||
int read_loop_index;
|
|
||||||
int Index;
|
|
||||||
|
|
||||||
baseaddr = (u32) baseaddr_p;
|
|
||||||
|
|
||||||
xil_printf("******************************\n\r");
|
|
||||||
xil_printf("* User Peripheral Self Test\n\r");
|
|
||||||
xil_printf("******************************\n\n\r");
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write to user logic slave module register(s) and read back
|
|
||||||
*/
|
|
||||||
xil_printf("User logic slave module test...\n\r");
|
|
||||||
|
|
||||||
for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
|
|
||||||
IP_FAN_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
|
|
||||||
for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
|
|
||||||
if ( IP_FAN_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
|
|
||||||
xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
|
|
||||||
return XST_FAILURE;
|
|
||||||
}
|
|
||||||
|
|
||||||
xil_printf(" - slave register write/read passed\n\n\r");
|
|
||||||
|
|
||||||
return XST_SUCCESS;
|
|
||||||
}
|
|
||||||
@ -1,88 +0,0 @@
|
|||||||
proc create_ipi_design { offsetfile design_name } {
|
|
||||||
create_bd_design $design_name
|
|
||||||
open_bd_design $design_name
|
|
||||||
|
|
||||||
# Create Clock and Reset Ports
|
|
||||||
set ACLK [ create_bd_port -dir I -type clk ACLK ]
|
|
||||||
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
|
|
||||||
set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
|
|
||||||
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
|
|
||||||
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
|
|
||||||
|
|
||||||
# Create instance: ip_fan_0, and set properties
|
|
||||||
set ip_fan_0 [ create_bd_cell -type ip -vlnv user.org:user:ip_fan:1.0 ip_fan_0]
|
|
||||||
|
|
||||||
# Create instance: master_0, and set properties
|
|
||||||
set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0]
|
|
||||||
set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0
|
|
||||||
|
|
||||||
# Create interface connections
|
|
||||||
connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins ip_fan_0/S00_AXI]
|
|
||||||
|
|
||||||
# Create port connections
|
|
||||||
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins ip_fan_0/S00_AXI_ACLK]
|
|
||||||
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins ip_fan_0/S00_AXI_ARESETN]
|
|
||||||
set_property target_simulator XSim [current_project]
|
|
||||||
set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
|
|
||||||
|
|
||||||
# Auto assign address
|
|
||||||
assign_bd_address
|
|
||||||
|
|
||||||
# Copy all address to interface_address.vh file
|
|
||||||
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
|
|
||||||
upvar 1 $offsetfile offset_file
|
|
||||||
set offset_file "${bd_path}/ip_fan_v1_0_tb_include.svh"
|
|
||||||
set fp [open $offset_file "w"]
|
|
||||||
puts $fp "`ifndef ip_fan_v1_0_tb_include_vh_"
|
|
||||||
puts $fp "`define ip_fan_v1_0_tb_include_vh_\n"
|
|
||||||
puts $fp "//Configuration current bd names"
|
|
||||||
puts $fp "`define BD_NAME ${design_name}"
|
|
||||||
puts $fp "`define BD_INST_NAME ${design_name}_i"
|
|
||||||
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
|
|
||||||
puts $fp "//Configuration address parameters"
|
|
||||||
|
|
||||||
puts $fp "`endif"
|
|
||||||
close $fp
|
|
||||||
}
|
|
||||||
|
|
||||||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:ip_fan:1.0]]]]
|
|
||||||
set test_bench_file ${ip_path}/example_designs/bfm_design/ip_fan_v1_0_tb.sv
|
|
||||||
set interface_address_vh_file ""
|
|
||||||
|
|
||||||
# Set IP Repository and Update IP Catalogue
|
|
||||||
set repo_paths [get_property ip_repo_paths [current_fileset]]
|
|
||||||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
|
|
||||||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
|
|
||||||
update_ip_catalog
|
|
||||||
}
|
|
||||||
|
|
||||||
set design_name ""
|
|
||||||
set all_bd {}
|
|
||||||
set all_bd_files [get_files *.bd -quiet]
|
|
||||||
foreach file $all_bd_files {
|
|
||||||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
|
|
||||||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
|
|
||||||
lappend all_bd $bd_name
|
|
||||||
}
|
|
||||||
|
|
||||||
for { set i 1 } { 1 } { incr i } {
|
|
||||||
set design_name "ip_fan_v1_0_bfm_${i}"
|
|
||||||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
|
|
||||||
break
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
create_ipi_design interface_address_vh_file ${design_name}
|
|
||||||
validate_bd_design
|
|
||||||
|
|
||||||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
|
|
||||||
import_files -force -norecurse $wrapper_file
|
|
||||||
|
|
||||||
set_property SOURCE_SET sources_1 [get_filesets sim_1]
|
|
||||||
import_files -fileset sim_1 -norecurse -force $test_bench_file
|
|
||||||
remove_files -quiet -fileset sim_1 ip_fan_v1_0_tb_include.vh
|
|
||||||
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
|
|
||||||
set_property top ip_fan_v1_0_tb [get_filesets sim_1]
|
|
||||||
set_property top_lib {} [get_filesets sim_1]
|
|
||||||
set_property top_file {} [get_filesets sim_1]
|
|
||||||
launch_simulation -simset sim_1 -mode behavioral
|
|
||||||
@ -1,197 +0,0 @@
|
|||||||
|
|
||||||
`timescale 1ns / 1ps
|
|
||||||
`include "ip_fan_v1_0_tb_include.svh"
|
|
||||||
|
|
||||||
import axi_vip_pkg::*;
|
|
||||||
import ip_fan_v1_0_bfm_1_master_0_0_pkg::*;
|
|
||||||
|
|
||||||
module ip_fan_v1_0_tb();
|
|
||||||
|
|
||||||
|
|
||||||
xil_axi_uint error_cnt = 0;
|
|
||||||
xil_axi_uint comparison_cnt = 0;
|
|
||||||
axi_transaction wr_transaction;
|
|
||||||
axi_transaction rd_transaction;
|
|
||||||
axi_monitor_transaction mst_monitor_transaction;
|
|
||||||
axi_monitor_transaction master_moniter_transaction_queue[$];
|
|
||||||
xil_axi_uint master_moniter_transaction_queue_size =0;
|
|
||||||
axi_monitor_transaction mst_scb_transaction;
|
|
||||||
axi_monitor_transaction passthrough_monitor_transaction;
|
|
||||||
axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
|
|
||||||
xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
|
|
||||||
axi_monitor_transaction passthrough_mst_scb_transaction;
|
|
||||||
axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
|
|
||||||
xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
|
|
||||||
axi_monitor_transaction passthrough_slv_scb_transaction;
|
|
||||||
axi_monitor_transaction slv_monitor_transaction;
|
|
||||||
axi_monitor_transaction slave_moniter_transaction_queue[$];
|
|
||||||
xil_axi_uint slave_moniter_transaction_queue_size =0;
|
|
||||||
axi_monitor_transaction slv_scb_transaction;
|
|
||||||
xil_axi_uint mst_agent_verbosity = 0;
|
|
||||||
xil_axi_uint slv_agent_verbosity = 0;
|
|
||||||
xil_axi_uint passthrough_agent_verbosity = 0;
|
|
||||||
bit clock;
|
|
||||||
bit reset;
|
|
||||||
integer result_slave;
|
|
||||||
bit [31:0] S00_AXI_test_data[3:0];
|
|
||||||
localparam LC_AXI_BURST_LENGTH = 8;
|
|
||||||
localparam LC_AXI_DATA_WIDTH = 32;
|
|
||||||
task automatic COMPARE_DATA;
|
|
||||||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected;
|
|
||||||
input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual;
|
|
||||||
begin
|
|
||||||
if (expected === 'hx || actual === 'hx) begin
|
|
||||||
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
|
|
||||||
result_slave = 0; $stop;
|
|
||||||
end
|
|
||||||
if (actual != expected) begin
|
|
||||||
$display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual);
|
|
||||||
result_slave = 0;
|
|
||||||
$stop;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
$display("TESTBENCH Passed! Data expected is equal to actual.",
|
|
||||||
" expected = 0x%h",expected, " actual = 0x%h",actual);
|
|
||||||
end
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
integer i;
|
|
||||||
integer j;
|
|
||||||
xil_axi_uint trans_cnt_before_switch = 48;
|
|
||||||
xil_axi_uint passthrough_cmd_switch_cnt = 0;
|
|
||||||
event passthrough_mastermode_start_event;
|
|
||||||
event passthrough_mastermode_end_event;
|
|
||||||
event passthrough_slavemode_end_event;
|
|
||||||
xil_axi_uint mtestID;
|
|
||||||
xil_axi_ulong mtestADDR;
|
|
||||||
xil_axi_len_t mtestBurstLength;
|
|
||||||
xil_axi_size_t mtestDataSize;
|
|
||||||
xil_axi_burst_t mtestBurstType;
|
|
||||||
xil_axi_lock_t mtestLOCK;
|
|
||||||
xil_axi_cache_t mtestCacheType = 0;
|
|
||||||
xil_axi_prot_t mtestProtectionType = 3'b000;
|
|
||||||
xil_axi_region_t mtestRegion = 4'b000;
|
|
||||||
xil_axi_qos_t mtestQOS = 4'b000;
|
|
||||||
xil_axi_data_beat dbeat;
|
|
||||||
xil_axi_data_beat [255:0] mtestWUSER;
|
|
||||||
xil_axi_data_beat mtestAWUSER = 'h0;
|
|
||||||
xil_axi_data_beat mtestARUSER = 0;
|
|
||||||
xil_axi_data_beat [255:0] mtestRUSER;
|
|
||||||
xil_axi_uint mtestBUSER = 0;
|
|
||||||
xil_axi_resp_t mtestBresp;
|
|
||||||
xil_axi_resp_t[255:0] mtestRresp;
|
|
||||||
bit [63:0] mtestWDataL;
|
|
||||||
bit [63:0] mtestRDataL;
|
|
||||||
axi_transaction pss_wr_transaction;
|
|
||||||
axi_transaction pss_rd_transaction;
|
|
||||||
axi_transaction reactive_transaction;
|
|
||||||
axi_transaction rd_payload_transaction;
|
|
||||||
axi_transaction wr_rand;
|
|
||||||
axi_transaction rd_rand;
|
|
||||||
axi_transaction wr_reactive;
|
|
||||||
axi_transaction rd_reactive;
|
|
||||||
axi_transaction wr_reactive2;
|
|
||||||
axi_transaction rd_reactive2;
|
|
||||||
axi_ready_gen bready_gen;
|
|
||||||
axi_ready_gen rready_gen;
|
|
||||||
axi_ready_gen awready_gen;
|
|
||||||
axi_ready_gen wready_gen;
|
|
||||||
axi_ready_gen arready_gen;
|
|
||||||
axi_ready_gen bready_gen2;
|
|
||||||
axi_ready_gen rready_gen2;
|
|
||||||
axi_ready_gen awready_gen2;
|
|
||||||
axi_ready_gen wready_gen2;
|
|
||||||
axi_ready_gen arready_gen2;
|
|
||||||
xil_axi_payload_byte data_mem[xil_axi_ulong];
|
|
||||||
ip_fan_v1_0_bfm_1_master_0_0_mst_t mst_agent_0;
|
|
||||||
|
|
||||||
`BD_WRAPPER DUT(
|
|
||||||
.ARESETN(reset),
|
|
||||||
.ACLK(clock)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms
|
|
||||||
mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
|
|
||||||
mst_agent_0.set_agent_tag("Master VIP");
|
|
||||||
mst_agent_0.set_verbosity(mst_agent_verbosity);
|
|
||||||
mst_agent_0.start_master();
|
|
||||||
$timeformat (-12, 1, " ps", 1);
|
|
||||||
end
|
|
||||||
initial begin
|
|
||||||
reset <= 1'b0;
|
|
||||||
#200ns;
|
|
||||||
reset <= 1'b1;
|
|
||||||
repeat (5) @(negedge clock);
|
|
||||||
end
|
|
||||||
always #5 clock <= ~clock;
|
|
||||||
initial begin
|
|
||||||
S_AXI_TEST ( );
|
|
||||||
|
|
||||||
#1ns;
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
task automatic S_AXI_TEST;
|
|
||||||
begin
|
|
||||||
#1;
|
|
||||||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts");
|
|
||||||
mtestID = 0;
|
|
||||||
mtestADDR = 64'h00000000;
|
|
||||||
mtestBurstLength = 0;
|
|
||||||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
|
|
||||||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
|
|
||||||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
|
|
||||||
mtestCacheType = 0;
|
|
||||||
mtestProtectionType = 0;
|
|
||||||
mtestRegion = 0;
|
|
||||||
mtestQOS = 0;
|
|
||||||
result_slave = 1;
|
|
||||||
mtestWDataL[31:0] = 32'h00000001;
|
|
||||||
for(int i = 0; i < 4;i++) begin
|
|
||||||
S00_AXI_test_data[i] <= mtestWDataL[31:0];
|
|
||||||
mst_agent_0.AXI4LITE_WRITE_BURST(
|
|
||||||
mtestADDR,
|
|
||||||
mtestProtectionType,
|
|
||||||
mtestWDataL,
|
|
||||||
mtestBresp
|
|
||||||
);
|
|
||||||
mtestWDataL[31:0] = mtestWDataL[31:0] + 1;
|
|
||||||
mtestADDR = mtestADDR + 64'h4;
|
|
||||||
end
|
|
||||||
$display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes");
|
|
||||||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method starts");
|
|
||||||
mtestID = 0;
|
|
||||||
mtestADDR = 64'h00000000;
|
|
||||||
mtestBurstLength = 0;
|
|
||||||
mtestDataSize = xil_axi_size_t'(xil_clog2(32/8));
|
|
||||||
mtestBurstType = XIL_AXI_BURST_TYPE_INCR;
|
|
||||||
mtestLOCK = XIL_AXI_ALOCK_NOLOCK;
|
|
||||||
mtestCacheType = 0;
|
|
||||||
mtestProtectionType = 0;
|
|
||||||
mtestRegion = 0;
|
|
||||||
mtestQOS = 0;
|
|
||||||
for(int i = 0; i < 4;i++) begin
|
|
||||||
mst_agent_0.AXI4LITE_READ_BURST(
|
|
||||||
mtestADDR,
|
|
||||||
mtestProtectionType,
|
|
||||||
mtestRDataL,
|
|
||||||
mtestRresp
|
|
||||||
);
|
|
||||||
mtestADDR = mtestADDR + 64'h4;
|
|
||||||
COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL);
|
|
||||||
end
|
|
||||||
$display("Sequential read transfers example similar to AXI BFM READ_BURST method completes");
|
|
||||||
$display("Sequential read transfers example similar to AXI VIP READ_BURST method completes");
|
|
||||||
$display("---------------------------------------------------------");
|
|
||||||
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
|
|
||||||
if ( result_slave ) begin
|
|
||||||
$display("PTGEN_TEST: PASSED!");
|
|
||||||
end else begin
|
|
||||||
$display("PTGEN_TEST: FAILED!");
|
|
||||||
end
|
|
||||||
$display("---------------------------------------------------------");
|
|
||||||
end
|
|
||||||
endtask
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,118 +0,0 @@
|
|||||||
|
|
||||||
proc create_ipi_design { offsetfile design_name } {
|
|
||||||
|
|
||||||
create_bd_design $design_name
|
|
||||||
open_bd_design $design_name
|
|
||||||
|
|
||||||
# Create and configure Clock/Reset
|
|
||||||
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
|
|
||||||
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
|
|
||||||
|
|
||||||
#Constraints will be provided manually while pin planning.
|
|
||||||
create_bd_port -dir I -type rst reset_rtl
|
|
||||||
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
|
|
||||||
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
|
|
||||||
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
|
|
||||||
set external_reset_port reset_rtl
|
|
||||||
create_bd_port -dir I -type clk clock_rtl
|
|
||||||
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
|
|
||||||
set external_clock_port clock_rtl
|
|
||||||
|
|
||||||
#Avoid IPI DRC, make clock port synchronous to reset
|
|
||||||
if { $external_clock_port ne "" && $external_reset_port ne "" } {
|
|
||||||
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
|
|
||||||
}
|
|
||||||
|
|
||||||
# Connect other sys_reset pins
|
|
||||||
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
|
|
||||||
|
|
||||||
# Create instance: ip_fan_0, and set properties
|
|
||||||
set ip_fan_0 [ create_bd_cell -type ip -vlnv user.org:user:ip_fan:1.0 ip_fan_0 ]
|
|
||||||
|
|
||||||
# Create instance: jtag_axi_0, and set properties
|
|
||||||
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
|
|
||||||
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
|
|
||||||
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
|
||||||
|
|
||||||
# Create instance: axi_peri_interconnect, and set properties
|
|
||||||
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
|
|
||||||
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
|
||||||
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
|
|
||||||
|
|
||||||
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
|
||||||
|
|
||||||
# Connect all clock & reset of ip_fan_0 slave interfaces..
|
|
||||||
connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins ip_fan_0/S00_AXI]
|
|
||||||
connect_bd_net [get_bd_pins ip_fan_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
|
|
||||||
connect_bd_net [get_bd_pins ip_fan_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
|
|
||||||
|
|
||||||
|
|
||||||
# Auto assign address
|
|
||||||
assign_bd_address
|
|
||||||
|
|
||||||
# Copy all address to ip_fan_v1_0_include.tcl file
|
|
||||||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
|
|
||||||
upvar 1 $offsetfile offset_file
|
|
||||||
set offset_file "${bd_path}/ip_fan_v1_0_include.tcl"
|
|
||||||
set fp [open $offset_file "w"]
|
|
||||||
puts $fp "# Configuration address parameters"
|
|
||||||
|
|
||||||
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_ip_fan_0_S00_AXI_* ]]
|
|
||||||
puts $fp "set s00_axi_addr ${offset}"
|
|
||||||
|
|
||||||
close $fp
|
|
||||||
}
|
|
||||||
|
|
||||||
# Set IP Repository and Update IP Catalogue
|
|
||||||
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:ip_fan:1.0]]]]
|
|
||||||
set hw_test_file ${ip_path}/example_designs/debug_hw_design/ip_fan_v1_0_hw_test.tcl
|
|
||||||
|
|
||||||
set repo_paths [get_property ip_repo_paths [current_fileset]]
|
|
||||||
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
|
|
||||||
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
|
|
||||||
update_ip_catalog
|
|
||||||
}
|
|
||||||
|
|
||||||
set design_name ""
|
|
||||||
set all_bd {}
|
|
||||||
set all_bd_files [get_files *.bd -quiet]
|
|
||||||
foreach file $all_bd_files {
|
|
||||||
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
|
|
||||||
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
|
|
||||||
lappend all_bd $bd_name
|
|
||||||
}
|
|
||||||
|
|
||||||
for { set i 1 } { 1 } { incr i } {
|
|
||||||
set design_name "ip_fan_v1_0_hw_${i}"
|
|
||||||
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
|
|
||||||
break
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
set intf_address_include_file ""
|
|
||||||
create_ipi_design intf_address_include_file ${design_name}
|
|
||||||
save_bd_design
|
|
||||||
validate_bd_design
|
|
||||||
|
|
||||||
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
|
|
||||||
import_files -force -norecurse $wrapper_file
|
|
||||||
|
|
||||||
puts "-------------------------------------------------------------------------------------------------"
|
|
||||||
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
|
|
||||||
puts " please perform following steps to test design in targeted board."
|
|
||||||
puts "1. Generate bitstream"
|
|
||||||
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
|
|
||||||
puts "3. Download generated bitstream"
|
|
||||||
puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
|
|
||||||
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
|
|
||||||
puts " : source -notrace ${hw_test_file}"
|
|
||||||
puts "-------------------------------------------------------------------------------------------------"
|
|
||||||
|
|
||||||
@ -1,45 +0,0 @@
|
|||||||
# Runtime Tcl commands to interact with - ip_fan_v1_0
|
|
||||||
|
|
||||||
# Sourcing design address info tcl
|
|
||||||
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
|
|
||||||
source ${bd_path}/ip_fan_v1_0_include.tcl
|
|
||||||
|
|
||||||
# jtag axi master interface hardware name, change as per your design.
|
|
||||||
set jtag_axi_master hw_axi_1
|
|
||||||
set ec 0
|
|
||||||
|
|
||||||
# hw test script
|
|
||||||
# Delete all previous axis transactions
|
|
||||||
if { [llength [get_hw_axi_txns -quiet]] } {
|
|
||||||
delete_hw_axi_txn [get_hw_axi_txns -quiet]
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
# Test all lite slaves.
|
|
||||||
set wdata_1 abcd1234
|
|
||||||
|
|
||||||
# Test: S00_AXI
|
|
||||||
# Create a write transaction at s00_axi_addr address
|
|
||||||
create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
|
|
||||||
# Create a read transaction at s00_axi_addr address
|
|
||||||
create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
|
|
||||||
# Initiate transactions
|
|
||||||
run_hw_axi r_s00_axi_addr
|
|
||||||
run_hw_axi w_s00_axi_addr
|
|
||||||
run_hw_axi r_s00_axi_addr
|
|
||||||
set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
|
|
||||||
# Compare read data
|
|
||||||
if { $rdata_tmp == $wdata_1 } {
|
|
||||||
puts "Data comparison test pass for - S00_AXI"
|
|
||||||
} else {
|
|
||||||
puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
|
|
||||||
inc ec
|
|
||||||
}
|
|
||||||
|
|
||||||
# Check error flag
|
|
||||||
if { $ec == 0 } {
|
|
||||||
puts "PTGEN_TEST: PASSED!"
|
|
||||||
} else {
|
|
||||||
puts "PTGEN_TEST: FAILED!"
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,82 +0,0 @@
|
|||||||
|
|
||||||
`timescale 1 ns / 1 ps
|
|
||||||
|
|
||||||
module ip_fan_v1_0 #
|
|
||||||
(
|
|
||||||
// Users to add parameters here
|
|
||||||
parameter FAN_PWM_FREQ = 10,
|
|
||||||
parameter SYS_CLK_FREQ = 200_000_000,
|
|
||||||
// User parameters ends
|
|
||||||
// Do not modify the parameters beyond this line
|
|
||||||
|
|
||||||
|
|
||||||
// Parameters of Axi Slave Bus Interface S00_AXI
|
|
||||||
parameter integer C_S00_AXI_DATA_WIDTH = 32,
|
|
||||||
parameter integer C_S00_AXI_ADDR_WIDTH = 4
|
|
||||||
)
|
|
||||||
(
|
|
||||||
// Users to add ports here
|
|
||||||
output wire fan,
|
|
||||||
// User ports ends
|
|
||||||
// Do not modify the ports beyond this line
|
|
||||||
|
|
||||||
|
|
||||||
// Ports of Axi Slave Bus Interface S00_AXI
|
|
||||||
input wire s00_axi_aclk,
|
|
||||||
input wire s00_axi_aresetn,
|
|
||||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
|
|
||||||
input wire [2 : 0] s00_axi_awprot,
|
|
||||||
input wire s00_axi_awvalid,
|
|
||||||
output wire s00_axi_awready,
|
|
||||||
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
|
|
||||||
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
|
|
||||||
input wire s00_axi_wvalid,
|
|
||||||
output wire s00_axi_wready,
|
|
||||||
output wire [1 : 0] s00_axi_bresp,
|
|
||||||
output wire s00_axi_bvalid,
|
|
||||||
input wire s00_axi_bready,
|
|
||||||
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
|
|
||||||
input wire [2 : 0] s00_axi_arprot,
|
|
||||||
input wire s00_axi_arvalid,
|
|
||||||
output wire s00_axi_arready,
|
|
||||||
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
|
|
||||||
output wire [1 : 0] s00_axi_rresp,
|
|
||||||
output wire s00_axi_rvalid,
|
|
||||||
input wire s00_axi_rready
|
|
||||||
);
|
|
||||||
// Instantiation of Axi Bus Interface S00_AXI
|
|
||||||
ip_fan_v1_0_S00_AXI # (
|
|
||||||
.FAN_PWM_FREQ(FAN_PWM_FREQ),
|
|
||||||
.SYS_CLK_FREQ(SYS_CLK_FREQ),
|
|
||||||
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
|
|
||||||
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
|
|
||||||
) ip_fan_v1_0_S00_AXI_inst (
|
|
||||||
.fan(fan),
|
|
||||||
.S_AXI_ACLK(s00_axi_aclk),
|
|
||||||
.S_AXI_ARESETN(s00_axi_aresetn),
|
|
||||||
.S_AXI_AWADDR(s00_axi_awaddr),
|
|
||||||
.S_AXI_AWPROT(s00_axi_awprot),
|
|
||||||
.S_AXI_AWVALID(s00_axi_awvalid),
|
|
||||||
.S_AXI_AWREADY(s00_axi_awready),
|
|
||||||
.S_AXI_WDATA(s00_axi_wdata),
|
|
||||||
.S_AXI_WSTRB(s00_axi_wstrb),
|
|
||||||
.S_AXI_WVALID(s00_axi_wvalid),
|
|
||||||
.S_AXI_WREADY(s00_axi_wready),
|
|
||||||
.S_AXI_BRESP(s00_axi_bresp),
|
|
||||||
.S_AXI_BVALID(s00_axi_bvalid),
|
|
||||||
.S_AXI_BREADY(s00_axi_bready),
|
|
||||||
.S_AXI_ARADDR(s00_axi_araddr),
|
|
||||||
.S_AXI_ARPROT(s00_axi_arprot),
|
|
||||||
.S_AXI_ARVALID(s00_axi_arvalid),
|
|
||||||
.S_AXI_ARREADY(s00_axi_arready),
|
|
||||||
.S_AXI_RDATA(s00_axi_rdata),
|
|
||||||
.S_AXI_RRESP(s00_axi_rresp),
|
|
||||||
.S_AXI_RVALID(s00_axi_rvalid),
|
|
||||||
.S_AXI_RREADY(s00_axi_rready)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Add user logic here
|
|
||||||
|
|
||||||
// User logic ends
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,457 +0,0 @@
|
|||||||
|
|
||||||
`timescale 1 ns / 1 ps
|
|
||||||
|
|
||||||
module ip_fan_v1_0_S00_AXI #
|
|
||||||
(
|
|
||||||
// Users to add parameters here
|
|
||||||
parameter FAN_PWM_FREQ = 200,
|
|
||||||
parameter SYS_CLK_FREQ = 20_000_000,
|
|
||||||
// User parameters ends
|
|
||||||
// Do not modify the parameters beyond this line
|
|
||||||
|
|
||||||
// Width of S_AXI data bus
|
|
||||||
parameter integer C_S_AXI_DATA_WIDTH = 32,
|
|
||||||
// Width of S_AXI address bus
|
|
||||||
parameter integer C_S_AXI_ADDR_WIDTH = 4
|
|
||||||
)
|
|
||||||
(
|
|
||||||
// Users to add ports here
|
|
||||||
|
|
||||||
output reg fan,
|
|
||||||
|
|
||||||
// User ports ends
|
|
||||||
// Do not modify the ports beyond this line
|
|
||||||
|
|
||||||
// Global Clock Signal
|
|
||||||
input wire S_AXI_ACLK,
|
|
||||||
// Global Reset Signal. This Signal is Active LOW
|
|
||||||
input wire S_AXI_ARESETN,
|
|
||||||
// Write address (issued by master, acceped by Slave)
|
|
||||||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
|
|
||||||
// Write channel Protection type. This signal indicates the
|
|
||||||
// privilege and security level of the transaction, and whether
|
|
||||||
// the transaction is a data access or an instruction access.
|
|
||||||
input wire [2 : 0] S_AXI_AWPROT,
|
|
||||||
// Write address valid. This signal indicates that the master signaling
|
|
||||||
// valid write address and control information.
|
|
||||||
input wire S_AXI_AWVALID,
|
|
||||||
// Write address ready. This signal indicates that the slave is ready
|
|
||||||
// to accept an address and associated control signals.
|
|
||||||
output wire S_AXI_AWREADY,
|
|
||||||
// Write data (issued by master, acceped by Slave)
|
|
||||||
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
|
|
||||||
// Write strobes. This signal indicates which byte lanes hold
|
|
||||||
// valid data. There is one write strobe bit for each eight
|
|
||||||
// bits of the write data bus.
|
|
||||||
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
|
|
||||||
// Write valid. This signal indicates that valid write
|
|
||||||
// data and strobes are available.
|
|
||||||
input wire S_AXI_WVALID,
|
|
||||||
// Write ready. This signal indicates that the slave
|
|
||||||
// can accept the write data.
|
|
||||||
output wire S_AXI_WREADY,
|
|
||||||
// Write response. This signal indicates the status
|
|
||||||
// of the write transaction.
|
|
||||||
output wire [1 : 0] S_AXI_BRESP,
|
|
||||||
// Write response valid. This signal indicates that the channel
|
|
||||||
// is signaling a valid write response.
|
|
||||||
output wire S_AXI_BVALID,
|
|
||||||
// Response ready. This signal indicates that the master
|
|
||||||
// can accept a write response.
|
|
||||||
input wire S_AXI_BREADY,
|
|
||||||
// Read address (issued by master, acceped by Slave)
|
|
||||||
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
|
|
||||||
// Protection type. This signal indicates the privilege
|
|
||||||
// and security level of the transaction, and whether the
|
|
||||||
// transaction is a data access or an instruction access.
|
|
||||||
input wire [2 : 0] S_AXI_ARPROT,
|
|
||||||
// Read address valid. This signal indicates that the channel
|
|
||||||
// is signaling valid read address and control information.
|
|
||||||
input wire S_AXI_ARVALID,
|
|
||||||
// Read address ready. This signal indicates that the slave is
|
|
||||||
// ready to accept an address and associated control signals.
|
|
||||||
output wire S_AXI_ARREADY,
|
|
||||||
// Read data (issued by slave)
|
|
||||||
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
|
|
||||||
// Read response. This signal indicates the status of the
|
|
||||||
// read transfer.
|
|
||||||
output wire [1 : 0] S_AXI_RRESP,
|
|
||||||
// Read valid. This signal indicates that the channel is
|
|
||||||
// signaling the required read data.
|
|
||||||
output wire S_AXI_RVALID,
|
|
||||||
// Read ready. This signal indicates that the master can
|
|
||||||
// accept the read data and response information.
|
|
||||||
input wire S_AXI_RREADY
|
|
||||||
);
|
|
||||||
|
|
||||||
// AXI4LITE signals
|
|
||||||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
|
|
||||||
reg axi_awready;
|
|
||||||
reg axi_wready;
|
|
||||||
reg [1 : 0] axi_bresp;
|
|
||||||
reg axi_bvalid;
|
|
||||||
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
|
|
||||||
reg axi_arready;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
|
|
||||||
reg [1 : 0] axi_rresp;
|
|
||||||
reg axi_rvalid;
|
|
||||||
|
|
||||||
// Example-specific design signals
|
|
||||||
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
|
||||||
// ADDR_LSB is used for addressing 32/64 bit registers/memories
|
|
||||||
// ADDR_LSB = 2 for 32 bits (n downto 2)
|
|
||||||
// ADDR_LSB = 3 for 64 bits (n downto 3)
|
|
||||||
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
|
|
||||||
localparam integer OPT_MEM_ADDR_BITS = 1;
|
|
||||||
//----------------------------------------------
|
|
||||||
//-- Signals for user logic register space example
|
|
||||||
//------------------------------------------------
|
|
||||||
//-- Number of Slave Registers 4
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
|
|
||||||
wire slv_reg_rden;
|
|
||||||
wire slv_reg_wren;
|
|
||||||
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
|
|
||||||
integer byte_index;
|
|
||||||
reg aw_en;
|
|
||||||
|
|
||||||
// I/O Connections assignments
|
|
||||||
|
|
||||||
assign S_AXI_AWREADY = axi_awready;
|
|
||||||
assign S_AXI_WREADY = axi_wready;
|
|
||||||
assign S_AXI_BRESP = axi_bresp;
|
|
||||||
assign S_AXI_BVALID = axi_bvalid;
|
|
||||||
assign S_AXI_ARREADY = axi_arready;
|
|
||||||
assign S_AXI_RDATA = axi_rdata;
|
|
||||||
assign S_AXI_RRESP = axi_rresp;
|
|
||||||
assign S_AXI_RVALID = axi_rvalid;
|
|
||||||
// Implement axi_awready generation
|
|
||||||
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
|
||||||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
|
||||||
// de-asserted when reset is low.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_awready <= 1'b0;
|
|
||||||
aw_en <= 1'b1;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
|
||||||
begin
|
|
||||||
// slave is ready to accept write address when
|
|
||||||
// there is a valid write address and write data
|
|
||||||
// on the write address and data bus. This design
|
|
||||||
// expects no outstanding transactions.
|
|
||||||
axi_awready <= 1'b1;
|
|
||||||
aw_en <= 1'b0;
|
|
||||||
end
|
|
||||||
else if (S_AXI_BREADY && axi_bvalid)
|
|
||||||
begin
|
|
||||||
aw_en <= 1'b1;
|
|
||||||
axi_awready <= 1'b0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
axi_awready <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement axi_awaddr latching
|
|
||||||
// This process is used to latch the address when both
|
|
||||||
// S_AXI_AWVALID and S_AXI_WVALID are valid.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_awaddr <= 0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
|
|
||||||
begin
|
|
||||||
// Write Address latching
|
|
||||||
axi_awaddr <= S_AXI_AWADDR;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement axi_wready generation
|
|
||||||
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
|
||||||
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
|
||||||
// de-asserted when reset is low.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_wready <= 1'b0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
|
|
||||||
begin
|
|
||||||
// slave is ready to accept write data when
|
|
||||||
// there is a valid write address and write data
|
|
||||||
// on the write address and data bus. This design
|
|
||||||
// expects no outstanding transactions.
|
|
||||||
axi_wready <= 1'b1;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
axi_wready <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement memory mapped register select and write logic generation
|
|
||||||
// The write data is accepted and written to memory mapped registers when
|
|
||||||
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
|
||||||
// select byte enables of slave registers while writing.
|
|
||||||
// These registers are cleared when reset (active low) is applied.
|
|
||||||
// Slave register write enable is asserted when valid address and data are available
|
|
||||||
// and the slave is ready to accept the write address and write data.
|
|
||||||
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
slv_reg0 <= 0;
|
|
||||||
slv_reg1 <= 0;
|
|
||||||
slv_reg2 <= 0;
|
|
||||||
slv_reg3 <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
if (slv_reg_wren) begin
|
|
||||||
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
|
|
||||||
2'h0:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 0
|
|
||||||
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
2'h1:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 1
|
|
||||||
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
2'h2:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 2
|
|
||||||
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
2'h3:
|
|
||||||
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
|
|
||||||
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
|
|
||||||
// Respective byte enables are asserted as per write strobes
|
|
||||||
// Slave register 3
|
|
||||||
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
|
|
||||||
end
|
|
||||||
default : begin
|
|
||||||
slv_reg0 <= slv_reg0;
|
|
||||||
slv_reg1 <= slv_reg1;
|
|
||||||
slv_reg2 <= slv_reg2;
|
|
||||||
slv_reg3 <= slv_reg3;
|
|
||||||
end
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement write response logic generation
|
|
||||||
// The write response and response valid signals are asserted by the slave
|
|
||||||
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
|
||||||
// This marks the acceptance of address and indicates the status of
|
|
||||||
// write transaction.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_bvalid <= 0;
|
|
||||||
axi_bresp <= 2'b0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
|
|
||||||
begin
|
|
||||||
// indicates a valid write response is available
|
|
||||||
axi_bvalid <= 1'b1;
|
|
||||||
axi_bresp <= 2'b0; // 'OKAY' response
|
|
||||||
end // work error responses in future
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (S_AXI_BREADY && axi_bvalid)
|
|
||||||
//check if bready is asserted while bvalid is high)
|
|
||||||
//(there is a possibility that bready is always asserted high)
|
|
||||||
begin
|
|
||||||
axi_bvalid <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement axi_arready generation
|
|
||||||
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
|
||||||
// S_AXI_ARVALID is asserted. axi_awready is
|
|
||||||
// de-asserted when reset (active low) is asserted.
|
|
||||||
// The read address is also latched when S_AXI_ARVALID is
|
|
||||||
// asserted. axi_araddr is reset to zero on reset assertion.
|
|
||||||
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_arready <= 1'b0;
|
|
||||||
axi_araddr <= 32'b0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (~axi_arready && S_AXI_ARVALID)
|
|
||||||
begin
|
|
||||||
// indicates that the slave has acceped the valid read address
|
|
||||||
axi_arready <= 1'b1;
|
|
||||||
// Read address latching
|
|
||||||
axi_araddr <= S_AXI_ARADDR;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
axi_arready <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement axi_arvalid generation
|
|
||||||
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
|
||||||
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
|
||||||
// data are available on the axi_rdata bus at this instance. The
|
|
||||||
// assertion of axi_rvalid marks the validity of read data on the
|
|
||||||
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
|
||||||
// is deasserted on reset (active low). axi_rresp and axi_rdata are
|
|
||||||
// cleared to zero on reset (active low).
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_rvalid <= 0;
|
|
||||||
axi_rresp <= 0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
|
|
||||||
begin
|
|
||||||
// Valid read data is available at the read data bus
|
|
||||||
axi_rvalid <= 1'b1;
|
|
||||||
axi_rresp <= 2'b0; // 'OKAY' response
|
|
||||||
end
|
|
||||||
else if (axi_rvalid && S_AXI_RREADY)
|
|
||||||
begin
|
|
||||||
// Read data is accepted by the master
|
|
||||||
axi_rvalid <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Implement memory mapped register select and read logic generation
|
|
||||||
// Slave register read enable is asserted when valid address is available
|
|
||||||
// and the slave is ready to accept the read address.
|
|
||||||
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
|
|
||||||
always @(*)
|
|
||||||
begin
|
|
||||||
// Address decoding for reading registers
|
|
||||||
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
|
|
||||||
2'h0 : reg_data_out <= slv_reg0;
|
|
||||||
2'h1 : reg_data_out <= slv_reg1;
|
|
||||||
2'h2 : reg_data_out <= slv_reg2;
|
|
||||||
2'h3 : reg_data_out <= slv_reg3;
|
|
||||||
default : reg_data_out <= 0;
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
|
|
||||||
// slv_reg0[0]:
|
|
||||||
// 1 - turn on pwm, the fan is controlled by pwm
|
|
||||||
// 0 - turn off the fan
|
|
||||||
|
|
||||||
// slv_reg1:
|
|
||||||
// 32bit register, an unsigned integer defining the dutycycle of pwm. dutycycle% = slv_reg1 / (2 ^ 32 - 1) * 100%
|
|
||||||
//
|
|
||||||
// Output register or memory read data
|
|
||||||
always @( posedge S_AXI_ACLK )
|
|
||||||
begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 )
|
|
||||||
begin
|
|
||||||
axi_rdata <= 0;
|
|
||||||
end
|
|
||||||
else
|
|
||||||
begin
|
|
||||||
// When there is a valid read address (S_AXI_ARVALID) with
|
|
||||||
// acceptance of read address by the slave (axi_arready),
|
|
||||||
// output the read dada
|
|
||||||
if (slv_reg_rden)
|
|
||||||
begin
|
|
||||||
axi_rdata <= reg_data_out; // register read data
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Add user logic here
|
|
||||||
reg S_AXI_BREADY_D0;
|
|
||||||
reg S_AXI_BREADY_D1;
|
|
||||||
wire S_AXI_BREADY_NEGEDGE = S_AXI_BREADY_D0 && !S_AXI_BREADY_D1;
|
|
||||||
parameter RELOAD_VALUE = SYS_CLK_FREQ / FAN_PWM_FREQ;
|
|
||||||
reg [31:0] counter;
|
|
||||||
|
|
||||||
always @(posedge S_AXI_ACLK) begin
|
|
||||||
if (S_AXI_ARESETN == 1'b0) begin
|
|
||||||
S_AXI_BREADY_D0 <= 0;
|
|
||||||
S_AXI_BREADY_D1 <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
S_AXI_BREADY_D0 <= S_AXI_BREADY;
|
|
||||||
S_AXI_BREADY_D1 <= S_AXI_BREADY_D0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge S_AXI_ACLK) begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 || S_AXI_BREADY_NEGEDGE == 1'b1) begin
|
|
||||||
fan <= 0;
|
|
||||||
end
|
|
||||||
else if (counter < slv_reg1) begin
|
|
||||||
fan <= 1'b1 & slv_reg0[0];
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
fan <= 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge S_AXI_ACLK) begin
|
|
||||||
if ( S_AXI_ARESETN == 1'b0 || S_AXI_BREADY_NEGEDGE == 1'b1) begin
|
|
||||||
counter <= 0;
|
|
||||||
end
|
|
||||||
else if (slv_reg0[0] == 1'b1)begin
|
|
||||||
if (counter >= RELOAD_VALUE) begin
|
|
||||||
counter <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
counter <= counter + 32'd1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
counter <= 0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
// User logic ends
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
Binary file not shown.
@ -1,81 +0,0 @@
|
|||||||
# Definitional proc to organize widgets for parameters.
|
|
||||||
proc init_gui { IPINST } {
|
|
||||||
ipgui::add_param $IPINST -name "Component_Name"
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.FAN_PWM_FREQ { PARAM_VALUE.FAN_PWM_FREQ } {
|
|
||||||
# Procedure called to update FAN_PWM_FREQ when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.FAN_PWM_FREQ { PARAM_VALUE.FAN_PWM_FREQ } {
|
|
||||||
# Procedure called to validate FAN_PWM_FREQ
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.SYS_CLK_FREQ { PARAM_VALUE.SYS_CLK_FREQ } {
|
|
||||||
# Procedure called to update SYS_CLK_FREQ when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.SYS_CLK_FREQ { PARAM_VALUE.SYS_CLK_FREQ } {
|
|
||||||
# Procedure called to validate SYS_CLK_FREQ
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
|
||||||
# Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
|
||||||
# Procedure called to validate C_S00_AXI_DATA_WIDTH
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
|
||||||
# Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
|
||||||
# Procedure called to validate C_S00_AXI_ADDR_WIDTH
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
|
||||||
# Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
|
|
||||||
# Procedure called to validate C_S00_AXI_BASEADDR
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
|
||||||
# Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
|
|
||||||
}
|
|
||||||
|
|
||||||
proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
|
|
||||||
# Procedure called to validate C_S00_AXI_HIGHADDR
|
|
||||||
return true
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.FAN_PWM_FREQ { MODELPARAM_VALUE.FAN_PWM_FREQ PARAM_VALUE.FAN_PWM_FREQ } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.FAN_PWM_FREQ}] ${MODELPARAM_VALUE.FAN_PWM_FREQ}
|
|
||||||
}
|
|
||||||
|
|
||||||
proc update_MODELPARAM_VALUE.SYS_CLK_FREQ { MODELPARAM_VALUE.SYS_CLK_FREQ PARAM_VALUE.SYS_CLK_FREQ } {
|
|
||||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
|
||||||
set_property value [get_property value ${PARAM_VALUE.SYS_CLK_FREQ}] ${MODELPARAM_VALUE.SYS_CLK_FREQ}
|
|
||||||
}
|
|
||||||
|
|
||||||
@ -1,568 +0,0 @@
|
|||||||
#*****************************************************************************************
|
|
||||||
# Vivado (TM) v2022.1 (64-bit)
|
|
||||||
#
|
|
||||||
# lower_machine.tcl: Tcl script for re-creating project 'lower_machine'
|
|
||||||
#
|
|
||||||
# Generated by Vivado on Fri Apr 28 09:33:21 PDT 2023
|
|
||||||
# IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
|
|
||||||
#
|
|
||||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
|
||||||
# when this script was generated. In order to re-create the project, please source this
|
|
||||||
# file in the Vivado Tcl Shell.
|
|
||||||
#
|
|
||||||
# * Note that the runs in the created project will be configured the same way as the
|
|
||||||
# original project, however they will not be launched automatically. To regenerate the
|
|
||||||
# run results please launch the synthesis/implementation runs as needed.
|
|
||||||
#
|
|
||||||
#*****************************************************************************************
|
|
||||||
# NOTE: In order to use this script for source control purposes, please make sure that the
|
|
||||||
# following files are added to the source control system:-
|
|
||||||
#
|
|
||||||
# 1. This project restoration tcl script (lower_machine.tcl) that was generated.
|
|
||||||
#
|
|
||||||
# 2. The following source(s) files that were local or imported into the original project.
|
|
||||||
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
|
|
||||||
#
|
|
||||||
# "$origin_dir/bd/system.tcl"
|
|
||||||
#
|
|
||||||
# 3. The following remote source files that were added to the original project:-
|
|
||||||
#
|
|
||||||
# "$origin_dir/cstr/lower_machine.xdc"
|
|
||||||
#
|
|
||||||
#*****************************************************************************************
|
|
||||||
|
|
||||||
# Check file required for this script exists
|
|
||||||
proc checkRequiredFiles { origin_dir} {
|
|
||||||
set status true
|
|
||||||
set files [list \
|
|
||||||
"[file normalize "$origin_dir/bd/system.tcl"]"\
|
|
||||||
]
|
|
||||||
foreach ifile $files {
|
|
||||||
if { ![file isfile $ifile] } {
|
|
||||||
puts " Could not find local file $ifile "
|
|
||||||
set status false
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
set files [list \
|
|
||||||
"[file normalize "$origin_dir/cstr/lower_machine.xdc"]"\
|
|
||||||
]
|
|
||||||
foreach ifile $files {
|
|
||||||
if { ![file isfile $ifile] } {
|
|
||||||
puts " Could not find remote file $ifile "
|
|
||||||
set status false
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
set paths [list \
|
|
||||||
"[file normalize "$origin_dir/../[file normalize "$origin_dir/ip_repo"]"]"\
|
|
||||||
]
|
|
||||||
foreach ipath $paths {
|
|
||||||
if { ![file isdirectory $ipath] } {
|
|
||||||
puts " Could not access $ipath "
|
|
||||||
set status false
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return $status
|
|
||||||
}
|
|
||||||
# Set the reference directory for source file relative paths (by default the value is script directory path)
|
|
||||||
set origin_dir [file dirname [info script]]
|
|
||||||
|
|
||||||
# Use origin directory path location variable, if specified in the tcl shell
|
|
||||||
if { [info exists ::origin_dir_loc] } {
|
|
||||||
set origin_dir $::origin_dir_loc
|
|
||||||
}
|
|
||||||
|
|
||||||
# Set the project name
|
|
||||||
set _xil_proj_name_ "lower_machine"
|
|
||||||
|
|
||||||
# Use project name variable, if specified in the tcl shell
|
|
||||||
if { [info exists ::user_project_name] } {
|
|
||||||
set _xil_proj_name_ $::user_project_name
|
|
||||||
}
|
|
||||||
|
|
||||||
variable script_file
|
|
||||||
set script_file "lower_machine.tcl"
|
|
||||||
|
|
||||||
# Help information for this script
|
|
||||||
proc print_help {} {
|
|
||||||
variable script_file
|
|
||||||
puts "\nDescription:"
|
|
||||||
puts "Recreate a Vivado project from this script. The created project will be"
|
|
||||||
puts "functionally equivalent to the original project for which this script was"
|
|
||||||
puts "generated. The script contains commands for creating a project, filesets,"
|
|
||||||
puts "runs, adding/importing sources and setting properties on various objects.\n"
|
|
||||||
puts "Syntax:"
|
|
||||||
puts "$script_file"
|
|
||||||
puts "$script_file -tclargs \[--origin_dir <path>\]"
|
|
||||||
puts "$script_file -tclargs \[--project_name <name>\]"
|
|
||||||
puts "$script_file -tclargs \[--help\]\n"
|
|
||||||
puts "Usage:"
|
|
||||||
puts "Name Description"
|
|
||||||
puts "-------------------------------------------------------------------------"
|
|
||||||
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
|
|
||||||
puts " origin_dir path value is \".\", otherwise, the value"
|
|
||||||
puts " that was set with the \"-paths_relative_to\" switch"
|
|
||||||
puts " when this script was generated.\n"
|
|
||||||
puts "\[--project_name <name>\] Create project with the specified name. Default"
|
|
||||||
puts " name is the name of the project from where this"
|
|
||||||
puts " script was generated.\n"
|
|
||||||
puts "\[--help\] Print help information for this script"
|
|
||||||
puts "-------------------------------------------------------------------------\n"
|
|
||||||
exit 0
|
|
||||||
}
|
|
||||||
|
|
||||||
if { $::argc > 0 } {
|
|
||||||
for {set i 0} {$i < $::argc} {incr i} {
|
|
||||||
set option [string trim [lindex $::argv $i]]
|
|
||||||
switch -regexp -- $option {
|
|
||||||
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
|
|
||||||
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
|
|
||||||
"--help" { print_help }
|
|
||||||
default {
|
|
||||||
if { [regexp {^-} $option] } {
|
|
||||||
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
|
|
||||||
return 1
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
# Set the directory path for the original project from where this script was exported
|
|
||||||
set orig_proj_dir "[file normalize "$origin_dir/lower_machine"]"
|
|
||||||
|
|
||||||
# Check for paths and files needed for project creation
|
|
||||||
set validate_required 0
|
|
||||||
if { $validate_required } {
|
|
||||||
if { [checkRequiredFiles $origin_dir] } {
|
|
||||||
puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
|
|
||||||
} else {
|
|
||||||
puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
|
|
||||||
return
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
# Create project
|
|
||||||
create_project ${_xil_proj_name_} $origin_dir/${_xil_proj_name_} -part xc7z010clg400-1
|
|
||||||
|
|
||||||
# Set the directory path for the new project
|
|
||||||
set proj_dir [get_property directory [current_project]]
|
|
||||||
|
|
||||||
# Set project properties
|
|
||||||
set obj [current_project]
|
|
||||||
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
|
|
||||||
set_property -name "enable_resource_estimation" -value "0" -objects $obj
|
|
||||||
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
|
|
||||||
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
|
|
||||||
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
|
|
||||||
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
|
|
||||||
set_property -name "part" -value "xc7z010clg400-1" -objects $obj
|
|
||||||
set_property -name "revised_directory_structure" -value "1" -objects $obj
|
|
||||||
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
|
|
||||||
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
|
|
||||||
set_property -name "simulator_language" -value "Mixed" -objects $obj
|
|
||||||
set_property -name "webtalk.activehdl_export_sim" -value "1" -objects $obj
|
|
||||||
set_property -name "webtalk.modelsim_export_sim" -value "1" -objects $obj
|
|
||||||
set_property -name "webtalk.questa_export_sim" -value "1" -objects $obj
|
|
||||||
set_property -name "webtalk.riviera_export_sim" -value "1" -objects $obj
|
|
||||||
set_property -name "webtalk.vcs_export_sim" -value "1" -objects $obj
|
|
||||||
set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
|
|
||||||
set_property -name "webtalk.xsim_export_sim" -value "1" -objects $obj
|
|
||||||
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
|
|
||||||
|
|
||||||
# Create 'sources_1' fileset (if not found)
|
|
||||||
if {[string equal [get_filesets -quiet sources_1] ""]} {
|
|
||||||
create_fileset -srcset sources_1
|
|
||||||
}
|
|
||||||
|
|
||||||
# Set IP repository paths
|
|
||||||
set obj [get_filesets sources_1]
|
|
||||||
if { $obj != {} } {
|
|
||||||
set_property "ip_repo_paths" "[file normalize "$origin_dir/ip_repo"]" $obj
|
|
||||||
|
|
||||||
# Rebuild user ip_repo's index before adding any source files
|
|
||||||
update_ip_catalog -rebuild
|
|
||||||
}
|
|
||||||
|
|
||||||
# Create block design
|
|
||||||
source $origin_dir/bd/system.tcl
|
|
||||||
|
|
||||||
# Generate the wrapper
|
|
||||||
make_wrapper -files [get_files system.bd] -top -import
|
|
||||||
|
|
||||||
|
|
||||||
# Set 'sources_1' fileset file properties for local files
|
|
||||||
set file "system/system.bd"
|
|
||||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
|
||||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
|
||||||
|
|
||||||
|
|
||||||
# Set 'sources_1' fileset properties
|
|
||||||
set obj [get_filesets sources_1]
|
|
||||||
set_property -name "top" -value "system_wrapper" -objects $obj
|
|
||||||
|
|
||||||
# Create 'constrs_1' fileset (if not found)
|
|
||||||
if {[string equal [get_filesets -quiet constrs_1] ""]} {
|
|
||||||
create_fileset -constrset constrs_1
|
|
||||||
}
|
|
||||||
|
|
||||||
# Set 'constrs_1' fileset object
|
|
||||||
set obj [get_filesets constrs_1]
|
|
||||||
|
|
||||||
# Add/Import constrs file and set constrs file properties
|
|
||||||
set file "[file normalize "$origin_dir/cstr/lower_machine.xdc"]"
|
|
||||||
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
|
||||||
set file "$origin_dir/cstr/lower_machine.xdc"
|
|
||||||
set file [file normalize $file]
|
|
||||||
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
|
||||||
set_property -name "file_type" -value "XDC" -objects $file_obj
|
|
||||||
|
|
||||||
# Set 'constrs_1' fileset properties
|
|
||||||
set obj [get_filesets constrs_1]
|
|
||||||
set_property -name "target_part" -value "xc7z010clg400-1" -objects $obj
|
|
||||||
|
|
||||||
# Create 'sim_1' fileset (if not found)
|
|
||||||
if {[string equal [get_filesets -quiet sim_1] ""]} {
|
|
||||||
create_fileset -simset sim_1
|
|
||||||
}
|
|
||||||
|
|
||||||
# Set 'sim_1' fileset object
|
|
||||||
set obj [get_filesets sim_1]
|
|
||||||
# Empty (no sources present)
|
|
||||||
|
|
||||||
# Set 'sim_1' fileset properties
|
|
||||||
set obj [get_filesets sim_1]
|
|
||||||
set_property -name "incremental" -value "0" -objects $obj
|
|
||||||
set_property -name "top" -value "system_wrapper" -objects $obj
|
|
||||||
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
|
|
||||||
|
|
||||||
# Set 'utils_1' fileset object
|
|
||||||
set obj [get_filesets utils_1]
|
|
||||||
# Empty (no sources present)
|
|
||||||
|
|
||||||
# Set 'utils_1' fileset properties
|
|
||||||
set obj [get_filesets utils_1]
|
|
||||||
|
|
||||||
set idrFlowPropertiesConstraints ""
|
|
||||||
catch {
|
|
||||||
set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
|
|
||||||
set_param runs.disableIDRFlowPropertyConstraints 1
|
|
||||||
}
|
|
||||||
|
|
||||||
# Create 'synth_1' run (if not found)
|
|
||||||
if {[string equal [get_runs -quiet synth_1] ""]} {
|
|
||||||
create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2022} -strategy "Flow_PerfOptimized_high" -report_strategy {No Reports} -constrset constrs_1
|
|
||||||
} else {
|
|
||||||
set_property strategy "Flow_PerfOptimized_high" [get_runs synth_1]
|
|
||||||
set_property flow "Vivado Synthesis 2022" [get_runs synth_1]
|
|
||||||
}
|
|
||||||
set obj [get_runs synth_1]
|
|
||||||
set_property set_report_strategy_name 1 $obj
|
|
||||||
set_property report_strategy {Vivado Synthesis Default Reports} $obj
|
|
||||||
set_property set_report_strategy_name 0 $obj
|
|
||||||
# Create 'synth_1_synth_report_utilization_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
|
|
||||||
create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
set obj [get_runs synth_1]
|
|
||||||
set_property -name "part" -value "xc7z010clg400-1" -objects $obj
|
|
||||||
set_property -name "strategy" -value "Flow_PerfOptimized_high" -objects $obj
|
|
||||||
set_property -name "steps.synth_design.args.directive" -value "PerformanceOptimized" -objects $obj
|
|
||||||
set_property -name "steps.synth_design.args.fsm_extraction" -value "one_hot" -objects $obj
|
|
||||||
set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "1" -objects $obj
|
|
||||||
set_property -name "steps.synth_design.args.resource_sharing" -value "off" -objects $obj
|
|
||||||
set_property -name "steps.synth_design.args.no_lc" -value "1" -objects $obj
|
|
||||||
set_property -name "steps.synth_design.args.shreg_min_size" -value "5" -objects $obj
|
|
||||||
|
|
||||||
# set the current synth run
|
|
||||||
current_run -synthesis [get_runs synth_1]
|
|
||||||
|
|
||||||
# Create 'impl_1' run (if not found)
|
|
||||||
if {[string equal [get_runs -quiet impl_1] ""]} {
|
|
||||||
create_run -name impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2022} -strategy "Performance_ExtraTimingOpt" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
|
|
||||||
} else {
|
|
||||||
set_property strategy "Performance_ExtraTimingOpt" [get_runs impl_1]
|
|
||||||
set_property flow "Vivado Implementation 2022" [get_runs impl_1]
|
|
||||||
}
|
|
||||||
set obj [get_runs impl_1]
|
|
||||||
set_property set_report_strategy_name 1 $obj
|
|
||||||
set_property report_strategy {Vivado Implementation Default Reports} $obj
|
|
||||||
set_property set_report_strategy_name 0 $obj
|
|
||||||
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "is_enabled" -value "0" -objects $obj
|
|
||||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
||||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_opt_report_drc_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "is_enabled" -value "0" -objects $obj
|
|
||||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
||||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "is_enabled" -value "0" -objects $obj
|
|
||||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
||||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_place_report_io_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_place_report_utilization_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_place_report_control_sets_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "options.verbose" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "is_enabled" -value "0" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "is_enabled" -value "0" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "is_enabled" -value "0" -objects $obj
|
|
||||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
||||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "is_enabled" -value "0" -objects $obj
|
|
||||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
||||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "is_enabled" -value "0" -objects $obj
|
|
||||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
||||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_route_report_drc_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_route_report_methodology_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_route_report_power_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_route_report_route_status_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
||||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "options.max_paths" -value "10" -objects $obj
|
|
||||||
set_property -name "options.report_unconstrained" -value "1" -objects $obj
|
|
||||||
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
|
|
||||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
|
|
||||||
create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
|
|
||||||
}
|
|
||||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
|
|
||||||
if { $obj != "" } {
|
|
||||||
set_property -name "options.warn_on_violation" -value "1" -objects $obj
|
|
||||||
|
|
||||||
}
|
|
||||||
set obj [get_runs impl_1]
|
|
||||||
set_property -name "part" -value "xc7z010clg400-1" -objects $obj
|
|
||||||
set_property -name "strategy" -value "Performance_ExtraTimingOpt" -objects $obj
|
|
||||||
set_property -name "steps.place_design.args.directive" -value "ExtraTimingOpt" -objects $obj
|
|
||||||
set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj
|
|
||||||
set_property -name "steps.route_design.args.directive" -value "NoTimingRelaxation" -objects $obj
|
|
||||||
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
|
|
||||||
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
|
|
||||||
|
|
||||||
# set the current impl run
|
|
||||||
current_run -implementation [get_runs impl_1]
|
|
||||||
catch {
|
|
||||||
if { $idrFlowPropertiesConstraints != {} } {
|
|
||||||
set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
puts "INFO: Project created:${_xil_proj_name_}"
|
|
||||||
# Create 'drc_1' gadget (if not found)
|
|
||||||
if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
|
|
||||||
create_dashboard_gadget -name {drc_1} -type drc
|
|
||||||
}
|
|
||||||
set obj [get_dashboard_gadgets [ list "drc_1" ] ]
|
|
||||||
set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
|
|
||||||
|
|
||||||
# Create 'methodology_1' gadget (if not found)
|
|
||||||
if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} {
|
|
||||||
create_dashboard_gadget -name {methodology_1} -type methodology
|
|
||||||
}
|
|
||||||
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
|
|
||||||
set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
|
|
||||||
|
|
||||||
# Create 'power_1' gadget (if not found)
|
|
||||||
if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} {
|
|
||||||
create_dashboard_gadget -name {power_1} -type power
|
|
||||||
}
|
|
||||||
set obj [get_dashboard_gadgets [ list "power_1" ] ]
|
|
||||||
set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
|
|
||||||
|
|
||||||
# Create 'timing_1' gadget (if not found)
|
|
||||||
if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} {
|
|
||||||
create_dashboard_gadget -name {timing_1} -type timing
|
|
||||||
}
|
|
||||||
set obj [get_dashboard_gadgets [ list "timing_1" ] ]
|
|
||||||
set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
|
|
||||||
|
|
||||||
# Create 'utilization_1' gadget (if not found)
|
|
||||||
if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} {
|
|
||||||
create_dashboard_gadget -name {utilization_1} -type utilization
|
|
||||||
}
|
|
||||||
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
|
|
||||||
set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
|
|
||||||
set_property -name "run.step" -value "synth_design" -objects $obj
|
|
||||||
set_property -name "run.type" -value "synthesis" -objects $obj
|
|
||||||
|
|
||||||
# Create 'utilization_2' gadget (if not found)
|
|
||||||
if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} {
|
|
||||||
create_dashboard_gadget -name {utilization_2} -type utilization
|
|
||||||
}
|
|
||||||
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
|
|
||||||
set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
|
|
||||||
|
|
||||||
move_dashboard_gadget -name {utilization_1} -row 0 -col 0
|
|
||||||
move_dashboard_gadget -name {power_1} -row 1 -col 0
|
|
||||||
move_dashboard_gadget -name {drc_1} -row 2 -col 0
|
|
||||||
move_dashboard_gadget -name {timing_1} -row 0 -col 1
|
|
||||||
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
|
|
||||||
move_dashboard_gadget -name {methodology_1} -row 2 -col 1
|
|
||||||
@ -1 +0,0 @@
|
|||||||
1.2
|
|
||||||
Binary file not shown.
Binary file not shown.
@ -1 +0,0 @@
|
|||||||
2.0
|
|
||||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -1 +0,0 @@
|
|||||||
Record=TopLevelDocument|FileName=Sheet.SchDoc|SheetNumber=1
|
|
||||||
108
script/.bashrc
108
script/.bashrc
@ -1,108 +0,0 @@
|
|||||||
|
|
||||||
# If not running interactively, don't do anything
|
|
||||||
case $- in
|
|
||||||
*i*) ;;
|
|
||||||
*) return;;
|
|
||||||
esac
|
|
||||||
|
|
||||||
# don't put duplicate lines or lines starting with space in the history.
|
|
||||||
# See bash(1) for more options
|
|
||||||
HISTCONTROL=ignoreboth
|
|
||||||
|
|
||||||
# append to the history file, don't overwrite it
|
|
||||||
shopt -s histappend
|
|
||||||
|
|
||||||
# for setting history length see HISTSIZE and HISTFILESIZE in bash(1)
|
|
||||||
HISTSIZE=1000
|
|
||||||
HISTFILESIZE=2000
|
|
||||||
|
|
||||||
# check the window size after each command and, if necessary,
|
|
||||||
# update the values of LINES and COLUMNS.
|
|
||||||
shopt -s checkwinsize
|
|
||||||
|
|
||||||
# If set, the pattern "**" used in a pathname expansion context will
|
|
||||||
# match all files and zero or more directories and subdirectories.
|
|
||||||
#shopt -s globstar
|
|
||||||
|
|
||||||
# make less more friendly for non-text input files, see lesspipe(1)
|
|
||||||
[ -x /usr/bin/lesspipe ] && eval "$(SHELL=/bin/sh lesspipe)"
|
|
||||||
|
|
||||||
# set a fancy prompt (non-color, unless we know we "want" color)
|
|
||||||
case "$TERM" in
|
|
||||||
xterm-color|*-256color) color_prompt=yes;;
|
|
||||||
esac
|
|
||||||
|
|
||||||
# uncomment for a colored prompt, if the terminal has the capability; turned
|
|
||||||
# off by default to not distract the user: the focus in a terminal window
|
|
||||||
# should be on the output of commands, not on the prompt
|
|
||||||
force_color_prompt=yes
|
|
||||||
|
|
||||||
if [ -n "$force_color_prompt" ]; then
|
|
||||||
if [ -x /usr/bin/tput ] && tput setaf 1 >&/dev/null; then
|
|
||||||
# We have color support; assume it's compliant with Ecma-48
|
|
||||||
# (ISO/IEC-6429). (Lack of such support is extremely rare, and such
|
|
||||||
# a case would tend to support setf rather than setaf.)
|
|
||||||
color_prompt=yes
|
|
||||||
else
|
|
||||||
color_prompt=
|
|
||||||
fi
|
|
||||||
fi
|
|
||||||
|
|
||||||
if [ "$color_prompt" = yes ]; then
|
|
||||||
PS1='\[\033[01;32m\]\u@\h\[\033[00m\]:\[\033[01;34m\]\w\[\033[00m\]\$ '
|
|
||||||
else
|
|
||||||
PS1='\u@\h:\w\$ '
|
|
||||||
fi
|
|
||||||
unset color_prompt force_color_prompt
|
|
||||||
|
|
||||||
# If this is an xterm set the title to user@host:dir
|
|
||||||
case "$TERM" in
|
|
||||||
xterm*|rxvt*)
|
|
||||||
PS1="\[\e]0;${debian_chroot:+($debian_chroot)}\u@\h: \w\a\]$PS1"
|
|
||||||
;;
|
|
||||||
*)
|
|
||||||
;;
|
|
||||||
esac
|
|
||||||
|
|
||||||
# enable color support of ls and also add handy aliases
|
|
||||||
|
|
||||||
alias ls='ls --color=auto'
|
|
||||||
#alias dir='dir --color=auto'
|
|
||||||
#alias vdir='vdir --color=auto'
|
|
||||||
|
|
||||||
alias grep='grep --color=auto'
|
|
||||||
alias fgrep='fgrep --color=auto'
|
|
||||||
alias egrep='egrep --color=auto'
|
|
||||||
|
|
||||||
|
|
||||||
# colored GCC warnings and errors
|
|
||||||
#export GCC_COLORS='error=01;31:warning=01;35:note=01;36:caret=01;32:locus=01:quote=01'
|
|
||||||
|
|
||||||
# some more ls aliases
|
|
||||||
alias ll='ls -alF'
|
|
||||||
alias la='ls -A'
|
|
||||||
alias l='ls -CF'
|
|
||||||
|
|
||||||
# Add an "alert" alias for long running commands. Use like so:
|
|
||||||
# sleep 10; alert
|
|
||||||
alias alert='notify-send --urgency=low -i "$([ $? = 0 ] && echo terminal || echo error)" "$(history|tail -n1|sed -e '\''s/^\s*[0-9]\+\s*//;s/[;&|]\s*alert$//'\'')"'
|
|
||||||
|
|
||||||
# Alias definitions.
|
|
||||||
# You may want to put all your additions into a separate file like
|
|
||||||
# ~/.bash_aliases, instead of adding them here directly.
|
|
||||||
# See /usr/share/doc/bash-doc/examples in the bash-doc package.
|
|
||||||
|
|
||||||
if [ -f ~/.bash_aliases ]; then
|
|
||||||
. ~/.bash_aliases
|
|
||||||
fi
|
|
||||||
|
|
||||||
# enable programmable completion features (you don't need to enable
|
|
||||||
# this, if it's already enabled in /etc/bash.bashrc and /etc/profile
|
|
||||||
# sources /etc/bash.bashrc).
|
|
||||||
if [ -f /usr/share/bash-completion/bash_completion ]; then
|
|
||||||
. /usr/share/bash-completion/bash_completion
|
|
||||||
elif [ -f /etc/bash_completion ]; then
|
|
||||||
. /etc/bash_completion
|
|
||||||
fi
|
|
||||||
|
|
||||||
|
|
||||||
@ -1,11 +0,0 @@
|
|||||||
# ~/.profile: executed by Bourne-compatible login shells.
|
|
||||||
|
|
||||||
if [ -f ~/.bashrc ]; then
|
|
||||||
. ~/.bashrc
|
|
||||||
fi
|
|
||||||
|
|
||||||
# path set by /etc/profile
|
|
||||||
# export PATH
|
|
||||||
|
|
||||||
# Might fail after "su - myuser" when /dev/tty* is not writable by "myuser".
|
|
||||||
mesg n 2>/dev/null
|
|
||||||
@ -1,3 +0,0 @@
|
|||||||
#!/bin/sh
|
|
||||||
|
|
||||||
modprobe encoder
|
|
||||||
@ -1,5 +0,0 @@
|
|||||||
#!/bin/sh
|
|
||||||
|
|
||||||
if [ -x /home/root/target ]; then
|
|
||||||
/home/root/target
|
|
||||||
fi
|
|
||||||
@ -1 +0,0 @@
|
|||||||
1.1
|
|
||||||
66
source/linux_app/.gitignore
vendored
66
source/linux_app/.gitignore
vendored
@ -1,66 +0,0 @@
|
|||||||
# Prerequisites
|
|
||||||
*.d
|
|
||||||
|
|
||||||
.vscode/*
|
|
||||||
!.vscode/settings.json
|
|
||||||
!.vscode/tasks.json
|
|
||||||
!.vscode/launch.json
|
|
||||||
!.vscode/extensions.json
|
|
||||||
!.vscode/c_cpp_properties.json
|
|
||||||
!.vscode/*.code-snippets
|
|
||||||
build/
|
|
||||||
|
|
||||||
# Local History for Visual Studio Code
|
|
||||||
.history/
|
|
||||||
|
|
||||||
# Built Visual Studio Code Extensions
|
|
||||||
*.vsix
|
|
||||||
# Object files
|
|
||||||
*.o
|
|
||||||
*.ko
|
|
||||||
*.obj
|
|
||||||
*.elf
|
|
||||||
|
|
||||||
# Linker output
|
|
||||||
*.ilk
|
|
||||||
*.map
|
|
||||||
*.exp
|
|
||||||
|
|
||||||
# Precompiled Headers
|
|
||||||
*.gch
|
|
||||||
*.pch
|
|
||||||
|
|
||||||
# Libraries
|
|
||||||
*.lib
|
|
||||||
*.a
|
|
||||||
*.la
|
|
||||||
*.lo
|
|
||||||
|
|
||||||
# Shared objects (inc. Windows DLLs)
|
|
||||||
*.dll
|
|
||||||
*.so
|
|
||||||
*.so.*
|
|
||||||
*.dylib
|
|
||||||
|
|
||||||
# Executables
|
|
||||||
*.exe
|
|
||||||
*.out
|
|
||||||
*.app
|
|
||||||
*.i*86
|
|
||||||
*.x86_64
|
|
||||||
*.hex
|
|
||||||
|
|
||||||
# Debug files
|
|
||||||
*.dSYM/
|
|
||||||
*.su
|
|
||||||
*.idb
|
|
||||||
*.pdb
|
|
||||||
|
|
||||||
# Kernel Module Compile Results
|
|
||||||
*.mod*
|
|
||||||
*.cmd
|
|
||||||
.tmp_versions/
|
|
||||||
modules.order
|
|
||||||
Module.symvers
|
|
||||||
Mkfile.old
|
|
||||||
dkms.conf
|
|
||||||
@ -1,85 +0,0 @@
|
|||||||
CROSS_COMPILE ?= /home/miaow/software/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/bin/arm-none-linux-gnueabihf-
|
|
||||||
TARGET := target
|
|
||||||
BUILD_DIR := build
|
|
||||||
|
|
||||||
ifeq ("$(origin V)", "command line")
|
|
||||||
KBUILD_VERBOSE = $(V)
|
|
||||||
endif
|
|
||||||
ifndef KBUILD_VERBOSE
|
|
||||||
KBUILD_VERBOSE = 0
|
|
||||||
endif
|
|
||||||
|
|
||||||
ifeq ($(KBUILD_VERBOSE),1)
|
|
||||||
quiet =
|
|
||||||
Q =
|
|
||||||
else
|
|
||||||
quiet=quiet_
|
|
||||||
Q = @
|
|
||||||
endif
|
|
||||||
|
|
||||||
ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4
|
|
||||||
ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
|
|
||||||
quiet=silent_
|
|
||||||
endif
|
|
||||||
else # make-3.8x
|
|
||||||
ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
|
|
||||||
quiet=silent_
|
|
||||||
endif
|
|
||||||
endif
|
|
||||||
|
|
||||||
|
|
||||||
SRC := $(wildcard *.c)
|
|
||||||
ASM_SRC := $(wildcard *.s)
|
|
||||||
OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.o)))
|
|
||||||
ASM_OBJ := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.o)))
|
|
||||||
DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(SRC:.c=.dis)))
|
|
||||||
ASM_DIS := $(addprefix $(BUILD_DIR)/, $(notdir $(ASM_SRC:.s=.dis)))
|
|
||||||
|
|
||||||
_TARGET := $(BUILD_DIR)/$(TARGET)
|
|
||||||
TARGET_DIS := $(BUILD_DIR)/$(TARGET).dis
|
|
||||||
|
|
||||||
LD = $(CROSS_COMPILE)ld
|
|
||||||
CC = $(CROSS_COMPILE)gcc
|
|
||||||
CPP = $(CC) -E
|
|
||||||
AR = $(CROSS_COMPILE)ar
|
|
||||||
LDR = $(CROSS_COMPILE)ldr
|
|
||||||
STRIP = $(CROSS_COMPILE)strip
|
|
||||||
OBJCOPY = $(CROSS_COMPILE)objcopy
|
|
||||||
OBJDUMP = $(CROSS_COMPILE)objdump
|
|
||||||
CFLAGS = -g -std=gnu99 -Wall -I.
|
|
||||||
LDFLAGS = -lpthread -lc -lm -lrt
|
|
||||||
|
|
||||||
.SECONDARY:
|
|
||||||
|
|
||||||
.PHONY:all
|
|
||||||
all: $(_TARGET) $(DIS) $(ASM_DIS) $(TARGET_DIS)
|
|
||||||
|
|
||||||
$(BUILD_DIR)/%.i:%.c %.h Makefile | $(BUILD_DIR)
|
|
||||||
$(Q)$(CC) -E $(CFLAGS) $< -o $@
|
|
||||||
$(BUILD_DIR)/%.s:$(BUILD_DIR)/%.i Makefile | $(BUILD_DIR)
|
|
||||||
$(Q)$(CC) -S $(CFLAGS) $< -o $@
|
|
||||||
$(BUILD_DIR)/%.o:$(BUILD_DIR)/%.s Makefile | $(BUILD_DIR)
|
|
||||||
$(Q)$(CC) -c $(CFLAGS) $< -o $@
|
|
||||||
$(BUILD_DIR)/%.o:%.s Makefile | $(BUILD_DIR)
|
|
||||||
$(Q)$(CC) -c $(CFLAGS) $< -o $@
|
|
||||||
$(BUILD_DIR)/%.dis:$(BUILD_DIR)/%.o Makefile | $(BUILD_DIR)
|
|
||||||
$(Q)$(OBJDUMP) -s -d $< > $@
|
|
||||||
$(TARGET_DIS):$(_TARGET) Makefile | $(BUILD_DIR)
|
|
||||||
$(Q)$(OBJDUMP) -s -d $< > $@
|
|
||||||
$(_TARGET):$(OBJ) $(ASM_OBJ) Makefile | $(BUILD_DIR)
|
|
||||||
$(Q)$(CC) $(OBJ) $(ASM_OBJ) $(LDFLAGS) -o $@
|
|
||||||
|
|
||||||
|
|
||||||
.PHONY:clean
|
|
||||||
clean:
|
|
||||||
$(Q)$(RM) $(BUILD_DIR)/* -f
|
|
||||||
|
|
||||||
.PHONY:install
|
|
||||||
install:$(TARGET)
|
|
||||||
$(Q)chmod 777 $(TARGET)
|
|
||||||
|
|
||||||
.PHONY:$(BUILD_DIR)
|
|
||||||
$(BUILD_DIR):
|
|
||||||
$(Q)if [ ! -d $(BUILD_DIR) ]; then mkdir -p $@; fi
|
|
||||||
|
|
||||||
|
|
||||||
@ -1,46 +0,0 @@
|
|||||||
/**
|
|
||||||
* @file common.h
|
|
||||||
* @brief Common macros.
|
|
||||||
* @author miaow (3703781@qq.com)
|
|
||||||
* @version 1.0
|
|
||||||
* @date 2022/06/12
|
|
||||||
* @mainpage github.com/NanjingForestryUniversity
|
|
||||||
*
|
|
||||||
* @copyright Copyright (c) 2022 miaow
|
|
||||||
*
|
|
||||||
* @par Changelog:
|
|
||||||
* <table>
|
|
||||||
* <tr><th>Date <th>Version <th>Author <th>Description
|
|
||||||
* <tr><td>2022/06/12 <td>1.0 <td>miaow <td>Write this file
|
|
||||||
* </table>
|
|
||||||
*/
|
|
||||||
#ifndef __COMMON_H
|
|
||||||
#define __COMMON_H
|
|
||||||
|
|
||||||
#include <stdio.h>
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#define ON_ERROR(res, message1, message2) \
|
|
||||||
if (res < 0) \
|
|
||||||
{ \
|
|
||||||
sprintf(perror_buffer, "error %d at %s:%d, %s, %s", res, __FILE__, __LINE__, message1, message2); \
|
|
||||||
perror(perror_buffer); \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define ON_ERROR_RET_VOID(res, message1, message2) \
|
|
||||||
ON_ERROR(res, message1, message2); \
|
|
||||||
if (res < 0) \
|
|
||||||
{ \
|
|
||||||
res = 0; \
|
|
||||||
return; \
|
|
||||||
}
|
|
||||||
|
|
||||||
#define ON_ERROR_RET(res, message1, message2, retval) \
|
|
||||||
ON_ERROR(res, message1, message2); \
|
|
||||||
if (res < 0) \
|
|
||||||
{ \
|
|
||||||
res = 0; \
|
|
||||||
return retval; \
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,52 +0,0 @@
|
|||||||
/**
|
|
||||||
* @file data_filter.c
|
|
||||||
* @brief Manage the hardware encoder unit
|
|
||||||
* @author miaow (3703781@qq.com)
|
|
||||||
* @version 1.0
|
|
||||||
* @date 2022/08/06
|
|
||||||
*
|
|
||||||
* @copyright Copyright (c) 2022 miaow
|
|
||||||
*
|
|
||||||
* @par Changelog:
|
|
||||||
* <table>
|
|
||||||
* <tr><th>Date <th>Version <th>Author <th>Description
|
|
||||||
* <tr><td>2022/08/06 <td>1.0 <td>Miaow <td>Write this module
|
|
||||||
* </table>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <string.h>
|
|
||||||
#include <data_filter.h>
|
|
||||||
|
|
||||||
void datafilter_init(datafilter_typedef *filter, int w_size)
|
|
||||||
{
|
|
||||||
filter->cache = (int *)malloc(sizeof(int) * (w_size + 1));
|
|
||||||
memset(filter->cache, 0, sizeof(int) * (w_size + 1));
|
|
||||||
|
|
||||||
filter->w_size = w_size;
|
|
||||||
filter->sum = 0;
|
|
||||||
filter->head = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int datafilter_calculate(datafilter_typedef *filter, int z)
|
|
||||||
{
|
|
||||||
filter->cache[filter->head] = z;
|
|
||||||
filter->head = (filter->head + 1) % (filter->w_size + 1);
|
|
||||||
filter->sum = filter->sum + z - filter->cache[filter->head];
|
|
||||||
if (filter->w_size != 0)
|
|
||||||
return filter->sum / filter->w_size;
|
|
||||||
else
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
void datafilter_deinit(datafilter_typedef *filter)
|
|
||||||
{
|
|
||||||
if (filter->cache != NULL)
|
|
||||||
{
|
|
||||||
free(filter->cache);
|
|
||||||
filter->cache = NULL;
|
|
||||||
}
|
|
||||||
filter->sum = 0;
|
|
||||||
filter->w_size = 0;
|
|
||||||
filter->head = 0;
|
|
||||||
}
|
|
||||||
@ -1,34 +0,0 @@
|
|||||||
/**
|
|
||||||
* @file data_filter.h
|
|
||||||
* @brief Manage the hardware encoder unit
|
|
||||||
* @author miaow (3703781@qq.com)
|
|
||||||
* @version 1.0
|
|
||||||
* @date 2022/08/06
|
|
||||||
*
|
|
||||||
* @copyright Copyright (c) 2022 miaow
|
|
||||||
*
|
|
||||||
* @par Changelog:
|
|
||||||
* <table>
|
|
||||||
* <tr><th>Date <th>Version <th>Author <th>Description
|
|
||||||
* <tr><td>2022/08/06 <td>1.0 <td>Miaow <td>Write this module
|
|
||||||
* </table>
|
|
||||||
*/
|
|
||||||
#ifndef __DATA_FILTER_H
|
|
||||||
#define __DATA_FILTER_H
|
|
||||||
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
int w_size;
|
|
||||||
int head;
|
|
||||||
int sum;
|
|
||||||
int *cache;
|
|
||||||
} datafilter_typedef;
|
|
||||||
|
|
||||||
void datafilter_init(datafilter_typedef *filter, int w_size);
|
|
||||||
|
|
||||||
int datafilter_calculate(datafilter_typedef *filter, int z);
|
|
||||||
|
|
||||||
void datafilter_deinit(datafilter_typedef *filter);
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,151 +0,0 @@
|
|||||||
/**
|
|
||||||
* @file encoder_dev.c
|
|
||||||
* @brief Manage the hardware encoder unit
|
|
||||||
* @author miaow, lyz (3703781@qq.com)
|
|
||||||
* @version 0.11
|
|
||||||
* @date 2022/04/26
|
|
||||||
* @mainpage github.com/NanjingForestryUniversity
|
|
||||||
*
|
|
||||||
* @copyright Copyright (c) 2023 miaow, lyz
|
|
||||||
*
|
|
||||||
* @par Changelog:
|
|
||||||
* <table>
|
|
||||||
* <tr><th>Date <th>Version <th>Author <th>Description
|
|
||||||
* <tr><td>2022/06/11 <td>0.9 <td>Miaow <td>Write this module
|
|
||||||
* <tr><td>2022/04/11 <td>0.10 <td>lyz <td>Add seprate dividers up to 4 cameras
|
|
||||||
* <tr><td>2023/04/26 <td>0.11 <td>Miaow <td>Add Clear mode
|
|
||||||
* </table>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <encoder_dev.h>
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <fcntl.h>
|
|
||||||
#include <unistd.h>
|
|
||||||
#include <sys/ioctl.h>
|
|
||||||
#include <sys/types.h>
|
|
||||||
#include <sys/stat.h>
|
|
||||||
|
|
||||||
#define ENCODER_CMD_FUNCTION_CLEAR 1
|
|
||||||
#define ENCODER_CMD_FUNCTION_VIRT_INPUT 2
|
|
||||||
|
|
||||||
static int encoder_dev_fd = -1;
|
|
||||||
static char perror_buffer[128];
|
|
||||||
|
|
||||||
static struct
|
|
||||||
{
|
|
||||||
uint32_t valve_divide_value;
|
|
||||||
uint32_t camera_a_divide_value;
|
|
||||||
uint32_t camera_b_divide_value;
|
|
||||||
uint32_t camera_c_divide_value;
|
|
||||||
uint32_t camera_d_divide_value;
|
|
||||||
} encoder_dev_divide_value_structure;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initialize the hardware encoder unit
|
|
||||||
* @note This function just open the file descriptor of the hardware encoder unit
|
|
||||||
* @return 0 - success, other - error
|
|
||||||
*/
|
|
||||||
int encoder_dev_init()
|
|
||||||
{
|
|
||||||
encoder_dev_fd = open(ENCODER_DEV_PATH, O_RDWR);
|
|
||||||
ON_ERROR_RET(encoder_dev_fd, "", "", -1);
|
|
||||||
encoder_dev_set_divide( 100, 100, 100, 100);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set the two divider in the hareware encoder unit.
|
|
||||||
* @param camera_a_divide the frequency division factor between the encoder signal and camera a triggle signal
|
|
||||||
* Set ENCODER_DEV_DIVIDE_NOT_TO_SET to skip changing the division facter
|
|
||||||
* @param camera_b_divide the frequency division factor between the encoder signal and camera b triggle signal
|
|
||||||
* Set ENCODER_DEV_DIVIDE_NOT_TO_SET to skip changing the division facter
|
|
||||||
* @param camera_c_divide the frequency division factor between the encoder signal and camera c triggle signal
|
|
||||||
* Set ENCODER_DEV_DIVIDE_NOT_TO_SET to skip changing the division facter
|
|
||||||
* @param camera_d_divide the frequency division factor between the encoder signal and camera d triggle signal
|
|
||||||
* Set ENCODER_DEV_DIVIDE_NOT_TO_SET to skip changing the division facter
|
|
||||||
* @return 0 - success, other - error
|
|
||||||
*/
|
|
||||||
int encoder_dev_set_divide(int camera_a_divide,
|
|
||||||
int camera_b_divide,
|
|
||||||
int camera_c_divide,
|
|
||||||
int camera_d_divide)
|
|
||||||
{
|
|
||||||
encoder_dev_divide_value_structure.valve_divide_value = 2;
|
|
||||||
if (camera_a_divide != ENCODER_DEV_DIVIDE_NOT_TO_SET)
|
|
||||||
encoder_dev_divide_value_structure.camera_a_divide_value = camera_a_divide;
|
|
||||||
if (camera_b_divide != ENCODER_DEV_DIVIDE_NOT_TO_SET)
|
|
||||||
encoder_dev_divide_value_structure.camera_b_divide_value = camera_b_divide;
|
|
||||||
if (camera_c_divide != ENCODER_DEV_DIVIDE_NOT_TO_SET)
|
|
||||||
encoder_dev_divide_value_structure.camera_c_divide_value = camera_c_divide;
|
|
||||||
if (camera_d_divide != ENCODER_DEV_DIVIDE_NOT_TO_SET)
|
|
||||||
encoder_dev_divide_value_structure.camera_d_divide_value = camera_d_divide;
|
|
||||||
|
|
||||||
ssize_t size = write(encoder_dev_fd, &encoder_dev_divide_value_structure, sizeof(encoder_dev_divide_value_structure));
|
|
||||||
int res = -(size != sizeof(encoder_dev_divide_value_structure));
|
|
||||||
ON_ERROR_RET(res, "size=", "", -1);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set the trig signal to internal or external.
|
|
||||||
* @param count the count of virtual trig cycles.
|
|
||||||
* @return 0 - success, other - error
|
|
||||||
*/
|
|
||||||
int encoder_dev_virtual_trig(int count)
|
|
||||||
{
|
|
||||||
int res = ioctl(encoder_dev_fd, _IOW('D', ENCODER_CMD_FUNCTION_VIRT_INPUT, int), count);
|
|
||||||
ON_ERROR_RET(res, "", "", -1);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set the trig signal to internal or external.
|
|
||||||
* @param mode ENCODER_TRIG_MODE_EXTERNEL for externally trig, or ENCODER_TRIG_MODE_INTERNEL for internally trig
|
|
||||||
* @return 0 - success, other - error
|
|
||||||
*/
|
|
||||||
int encoder_dev_set_trigmod(encoder_dev_trig_mode_enum mode)
|
|
||||||
{
|
|
||||||
int res = ioctl(encoder_dev_fd, _IOW('D', mode, int));
|
|
||||||
ON_ERROR_RET(res, "", "", -1);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set the clr signal to internal or both external and internal.
|
|
||||||
* @return 0 - success, other - error
|
|
||||||
*/
|
|
||||||
int encoder_dev_set_clrmod(encoder_dev_clear_mode_enum mode)
|
|
||||||
{
|
|
||||||
int res = ioctl(encoder_dev_fd, _IOW('D', mode, int));
|
|
||||||
ON_ERROR_RET(res, "", "", -1);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Claer the cache in hardware encoder unit.
|
|
||||||
* @note The frequency division counters continutly count pluses of external/internal signal.
|
|
||||||
* This functhion clears the counters.
|
|
||||||
* @return 0 - success, other - error
|
|
||||||
*/
|
|
||||||
int encoder_dev_flush()
|
|
||||||
{
|
|
||||||
int res = ioctl(encoder_dev_fd, _IOW('D', ENCODER_CMD_FUNCTION_CLEAR, 0));
|
|
||||||
ON_ERROR_RET(res, "", "", -1);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Deinitialize the hardware encoder unit.
|
|
||||||
* @note This function just close the file descriptor of the encoder unit.
|
|
||||||
* @return 0 - success, other - error
|
|
||||||
*/
|
|
||||||
int encoder_dev_deinit()
|
|
||||||
{
|
|
||||||
int res = close(encoder_dev_fd);
|
|
||||||
|
|
||||||
ON_ERROR_RET(res, "", "", -1);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
@ -1,51 +0,0 @@
|
|||||||
/**
|
|
||||||
* @file encoder_dev.h
|
|
||||||
* @brief Manage the hardware encoder unit
|
|
||||||
* @author miaow, lzy (3703781@qq.com)
|
|
||||||
* @version 0.11
|
|
||||||
* @date 2022/04/26
|
|
||||||
* @mainpage github.com/NanjingForestryUniversity
|
|
||||||
*
|
|
||||||
* @copyright Copyright (c) 2023 miaow, lyz
|
|
||||||
*
|
|
||||||
* @par Changelog:
|
|
||||||
* <table>
|
|
||||||
* <tr><th>Date <th>Version <th>Author <th>Description
|
|
||||||
* <tr><td>2022/06/11 <td>0.9 <td>Miaow <td>Write this module
|
|
||||||
* <tr><td>2022/04/11 <td>0.10 <td>lyz <td>Add seprate dividers up to 4 cameras
|
|
||||||
* <tr><td>2023/04/26 <td>0.11 <td>Miaow <td>Add Clear mode
|
|
||||||
* </table>
|
|
||||||
*/
|
|
||||||
#ifndef __ENCODER_DEV_H
|
|
||||||
#define __ENCODER_DEV_H
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
|
|
||||||
#define ENCODER_DEV_PATH "/dev/encoder"
|
|
||||||
|
|
||||||
#define ENCODER_DEV_DIVIDE_NOT_TO_SET 0
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
ENCODER_TRIG_MODE_EXTERNEL = 100,
|
|
||||||
ENCODER_TRIG_MODE_INTERNEL = 101
|
|
||||||
} encoder_dev_trig_mode_enum;
|
|
||||||
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
ENCODER_CLEAR_MODE_BOTH = 200,
|
|
||||||
ENCODER_CLEAR_MODE_INTERNAL = 201
|
|
||||||
} encoder_dev_clear_mode_enum;
|
|
||||||
|
|
||||||
int encoder_dev_set_divide(int camera_a_divide,
|
|
||||||
int camera_b_divide,
|
|
||||||
int camera_c_divide,
|
|
||||||
int camera_d_divide);
|
|
||||||
int encoder_dev_flush(void);
|
|
||||||
int encoder_dev_set_trigmod(encoder_dev_trig_mode_enum mode);
|
|
||||||
int encoder_dev_set_clrmod(encoder_dev_clear_mode_enum mode);
|
|
||||||
int encoder_dev_virtual_trig(int count);
|
|
||||||
int encoder_dev_init(void);
|
|
||||||
int encoder_dev_deinit(void);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,295 +0,0 @@
|
|||||||
/**
|
|
||||||
* @file host_computer.c
|
|
||||||
* @brief Commnunicate with host computer. Protocal is described in 下位机和上位机通信协议 V1.4
|
|
||||||
* @author miaow (3703781@qq.com)
|
|
||||||
* @version 1.2
|
|
||||||
* @date 2023/05/07
|
|
||||||
* @mainpage github.com/NanjingForestryUniversity
|
|
||||||
*
|
|
||||||
* @copyright Copyright (c) 2023 miaow
|
|
||||||
*
|
|
||||||
* @par Changelog:
|
|
||||||
* <table>
|
|
||||||
* <tr><th>Date <th>Version <th>Author <th>Description
|
|
||||||
* <tr><td>2022/01/16 <td>1.0 <td>miaow <td>Write this file
|
|
||||||
* <tr><td>2022/08/06 <td>1.1 <td>miaow <td>Add fifob
|
|
||||||
* <tr><td>2023/05/07 <td>1.2 <td>miaow <td>Port to b03 branch
|
|
||||||
* </table>
|
|
||||||
*/
|
|
||||||
#include <host_computer.h>
|
|
||||||
#include <sys/socket.h>
|
|
||||||
#include <netinet/in.h>
|
|
||||||
#include <arpa/inet.h>
|
|
||||||
#include <netinet/tcp.h>
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <pthread.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <stdio.h>
|
|
||||||
#include <string.h>
|
|
||||||
#include <unistd.h>
|
|
||||||
#include <fcntl.h>
|
|
||||||
#include <encoder_dev.h>
|
|
||||||
#include <data_filter.h>
|
|
||||||
#include <sys/time.h>
|
|
||||||
#include <time.h>
|
|
||||||
#include <signal.h>
|
|
||||||
|
|
||||||
static char perror_buffer[128];
|
|
||||||
/**
|
|
||||||
* @brief Queue handle structure
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
queue_uint64_msg_t *cmd_q; // A pointer to the queue for commands
|
|
||||||
int socket_fd; // The socket fd for receiving commands and data
|
|
||||||
int need_exit; // The flag variable to indicate whether to exit the loop_thread in this file
|
|
||||||
pthread_t loop_thread; // The main routine of this module, which parses commands and data from host, puts them into the queue
|
|
||||||
pthread_mutex_t loop_thread_mutex; // The mutex for loop_thread
|
|
||||||
pthread_mutex_t is_connected_mutex;
|
|
||||||
timer_t heartbeat_timer;
|
|
||||||
} hostcomputer_t;
|
|
||||||
|
|
||||||
static hostcomputer_t _global_structure;
|
|
||||||
void *loop_thread_func(void *param);
|
|
||||||
void heartbeat_timer_func(__sigval_t param);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Pre initialize host computer module
|
|
||||||
* @param data_q A pointer to the queue storing the valve data from host computer
|
|
||||||
* @param cmd_q A pointer#include <sys/time.h> to the queue storing the cmd from host computer
|
|
||||||
* @return 0 - success
|
|
||||||
*/
|
|
||||||
int hostcomputer_init(queue_uint64_msg_t *cmd_q)
|
|
||||||
{
|
|
||||||
struct sigevent evp;
|
|
||||||
struct itimerspec ts;
|
|
||||||
_global_structure.cmd_q = cmd_q;
|
|
||||||
|
|
||||||
pthread_mutex_init(&_global_structure.loop_thread_mutex, NULL);
|
|
||||||
pthread_mutex_init(&_global_structure.is_connected_mutex, NULL);
|
|
||||||
pthread_create(&_global_structure.loop_thread, NULL, loop_thread_func, NULL);
|
|
||||||
memset(&evp, 0, sizeof(evp));
|
|
||||||
evp.sigev_value.sival_ptr = &_global_structure.heartbeat_timer;
|
|
||||||
evp.sigev_notify = SIGEV_THREAD;
|
|
||||||
evp.sigev_notify_function = heartbeat_timer_func;
|
|
||||||
timer_create(CLOCK_REALTIME, &evp, &_global_structure.heartbeat_timer);
|
|
||||||
ts.it_interval.tv_sec = 3;
|
|
||||||
ts.it_interval.tv_nsec = 0;
|
|
||||||
ts.it_value.tv_sec = 3;
|
|
||||||
ts.it_value.tv_nsec = 0;
|
|
||||||
timer_settime(_global_structure.heartbeat_timer, TIMER_ABSTIME, &ts, NULL);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Receive `size` bytes from a socket. If no more bytes are available at the socket, this function return -1 when timeout reaches.
|
|
||||||
* @param fd The socket fd
|
|
||||||
* @param buf Received bytes
|
|
||||||
* @param size Number of bytes to receive
|
|
||||||
* @return These calls return the number of bytes received, or -1 if time out occurred
|
|
||||||
*/
|
|
||||||
static int recvn(int fd, char *buf, int size)
|
|
||||||
{
|
|
||||||
char *pt = buf;
|
|
||||||
int count = size;
|
|
||||||
while (count > 0)
|
|
||||||
{
|
|
||||||
int len = recv(fd, pt, count, 0);
|
|
||||||
// if (len == -1 && (errno == EAGAIN || errno == EWOULDBLOCK))
|
|
||||||
// {
|
|
||||||
// // printf("recv timeout\r\n");
|
|
||||||
// }
|
|
||||||
if (len == -1)
|
|
||||||
return -1;
|
|
||||||
else if (len == 0)
|
|
||||||
return size - count;
|
|
||||||
pt += len;
|
|
||||||
count -= len;
|
|
||||||
}
|
|
||||||
return size;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief To inspect the status of TCP connection
|
|
||||||
* @param sock_fd The socket
|
|
||||||
* @return 0 - Not connected, 1 - connected
|
|
||||||
*/
|
|
||||||
static int is_connected(int sock_fd)
|
|
||||||
{
|
|
||||||
struct tcp_info info;
|
|
||||||
int len = sizeof(info);
|
|
||||||
pthread_mutex_lock(&_global_structure.is_connected_mutex);
|
|
||||||
getsockopt(sock_fd, IPPROTO_TCP, TCP_INFO, &info, (socklen_t *)&len);
|
|
||||||
pthread_mutex_unlock(&_global_structure.is_connected_mutex);
|
|
||||||
return info.tcpi_state == TCP_ESTABLISHED;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function runs in child thread and handles communication with host computer
|
|
||||||
* @param param NULL
|
|
||||||
* @return NULL
|
|
||||||
*/
|
|
||||||
void *loop_thread_func(void *param)
|
|
||||||
{
|
|
||||||
// printf("loop thread in %s start\r\n", __FILE__);
|
|
||||||
int need_exit = 0;
|
|
||||||
char pre;
|
|
||||||
uint32_t n_bytes;
|
|
||||||
char type[2];
|
|
||||||
char data[20];
|
|
||||||
char check[2];
|
|
||||||
|
|
||||||
while (!need_exit)
|
|
||||||
{
|
|
||||||
pthread_mutex_lock(&_global_structure.loop_thread_mutex);
|
|
||||||
need_exit = _global_structure.need_exit;
|
|
||||||
pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
|
|
||||||
// reconnect if not connected
|
|
||||||
if (!is_connected(_global_structure.socket_fd))
|
|
||||||
{
|
|
||||||
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_STOP);
|
|
||||||
_global_structure.socket_fd = socket(AF_INET, SOCK_STREAM, 0);
|
|
||||||
struct timeval timeout = {.tv_sec = 10, .tv_usec = 0};
|
|
||||||
setsockopt(_global_structure.socket_fd, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout));
|
|
||||||
ON_ERROR_RET(_global_structure.socket_fd, "hostcomputer_init", "", NULL);
|
|
||||||
struct sockaddr_in serAddr;
|
|
||||||
serAddr.sin_family = AF_INET;
|
|
||||||
// serAddr.sin_addr.s_addr = inet_addr(HOST_COMPUTER_IP);
|
|
||||||
inet_pton(AF_INET, HOST_COMPUTER_IP, &serAddr.sin_addr);
|
|
||||||
serAddr.sin_port = htons(HOST_COMPUTER_PORT);
|
|
||||||
printf("Connecting host computer...");
|
|
||||||
fflush(stdout);
|
|
||||||
if (connect(_global_structure.socket_fd, (struct sockaddr *)&serAddr, sizeof(struct sockaddr_in)) == -1)
|
|
||||||
{
|
|
||||||
sleep(2);
|
|
||||||
close(_global_structure.socket_fd);
|
|
||||||
printf("FAILED\r\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
printf("OK\r\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
// =======================parse the protocol=========================================
|
|
||||||
if (recvn(_global_structure.socket_fd, (char *)&pre, 1) > 1)
|
|
||||||
{
|
|
||||||
// close(_global_structure.socket_fd);
|
|
||||||
printf("pre_len!=1\r\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (pre != 0xAA)
|
|
||||||
{
|
|
||||||
// close(_global_structure.socket_fd);
|
|
||||||
// printf("%X ", (int)pre);
|
|
||||||
// fflush(stdout);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (recvn(_global_structure.socket_fd, (char *)&n_bytes, 4) != 4)
|
|
||||||
{
|
|
||||||
// close(_global_structure.socket_fd);
|
|
||||||
printf("n_bytes_len!=4\r\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
n_bytes = ntohl(n_bytes);
|
|
||||||
if (n_bytes != 10 && n_bytes != 3)
|
|
||||||
{
|
|
||||||
// close(_global_structure.socket_fd);
|
|
||||||
printf("n_bytes is not 10 or 3\r\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (recvn(_global_structure.socket_fd, (char *)type, 2) != 2)
|
|
||||||
{
|
|
||||||
// close(_global_structure.socket_fd);
|
|
||||||
printf("type!=2\r\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (recvn(_global_structure.socket_fd, (char *)data, n_bytes - 2) != n_bytes - 2)
|
|
||||||
{
|
|
||||||
// close(_global_structure.socket_fd);
|
|
||||||
printf("data_len!=n_bytes-2\r\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
data[n_bytes - 2] = 0;
|
|
||||||
if (recvn(_global_structure.socket_fd, (char *)check, 2) != 2)
|
|
||||||
{
|
|
||||||
// close(_global_structure.socket_fd);
|
|
||||||
printf("check_len!=2\r\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (recvn(_global_structure.socket_fd, (char *)&pre, 1) != 1)
|
|
||||||
{
|
|
||||||
// close(_global_structure.socket_fd);
|
|
||||||
printf("end_len!=1\r\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (pre != 0xBB)
|
|
||||||
{
|
|
||||||
// close(_global_structure.socket_fd);
|
|
||||||
printf("end!=0xBB\r\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
// =======================parse the commands=========================================
|
|
||||||
// commands are reformed as an uint64_t, 0x--------xxxxxxxx, where `-` refers its paramter and `x` is HOSTCOMPUTER_CMD
|
|
||||||
if (type[0] == 's' && type[1] == 't')
|
|
||||||
{
|
|
||||||
// printf("Start put to cmd queue, param:%d\r\n", (int)atoll(data));
|
|
||||||
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_START);
|
|
||||||
}
|
|
||||||
else if (type[0] == 's' && type[1] == 'p')
|
|
||||||
{
|
|
||||||
// printf("Stop put to cmd queue, param:%d\r\n", (int)atoll(data));
|
|
||||||
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_STOP);
|
|
||||||
}
|
|
||||||
else if (type[0] == 'p' && type[1] == 'a')
|
|
||||||
{
|
|
||||||
// printf("Set camera triggle pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
|
|
||||||
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_A);
|
|
||||||
}
|
|
||||||
else if (type[0] == 'p' && type[1] == 'b')
|
|
||||||
{
|
|
||||||
// printf("Set camera triggle pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
|
|
||||||
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_B);
|
|
||||||
}
|
|
||||||
else if (type[0] == 'p' && type[1] == 'c')
|
|
||||||
{
|
|
||||||
// printf("Set camera triggle pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
|
|
||||||
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_C);
|
|
||||||
}
|
|
||||||
else if (type[0] == 'p' && type[1] == 'd')
|
|
||||||
{
|
|
||||||
// printf("Set camera triggle pulse count put to cmd queue, param:%d\r\n", (int)atoll(data));
|
|
||||||
queue_uint64_put(_global_structure.cmd_q, (atoll(data) << 32) | HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_D);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
printf("loop thread in %s exit\r\n", __FILE__);
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
void heartbeat_timer_func(__sigval_t param)
|
|
||||||
{
|
|
||||||
static uint8_t heartbeat_packet[] = {0xaa, 0x00, 0x00, 0x00, 0x03, 'h', 'b', 0xff, 0xff, 0xff, 0xbb};
|
|
||||||
if (is_connected(_global_structure.socket_fd))
|
|
||||||
write(_global_structure.socket_fd, heartbeat_packet, sizeof(heartbeat_packet));
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Deinitialize and release resources used by host computer module
|
|
||||||
* @return int
|
|
||||||
*/
|
|
||||||
int hostcomputer_deinit()
|
|
||||||
{
|
|
||||||
timer_delete(_global_structure.heartbeat_timer);
|
|
||||||
|
|
||||||
pthread_mutex_lock(&_global_structure.loop_thread_mutex);
|
|
||||||
_global_structure.need_exit = 1;
|
|
||||||
pthread_mutex_unlock(&_global_structure.loop_thread_mutex);
|
|
||||||
pthread_join(_global_structure.loop_thread, NULL);
|
|
||||||
pthread_mutex_destroy(&_global_structure.loop_thread_mutex);
|
|
||||||
|
|
||||||
close(_global_structure.socket_fd);
|
|
||||||
_global_structure.socket_fd = 0;
|
|
||||||
_global_structure.need_exit = 0;
|
|
||||||
_global_structure.cmd_q = NULL;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
@ -1,45 +0,0 @@
|
|||||||
/**
|
|
||||||
* @file host_computer.h
|
|
||||||
* @brief Commnunicate with host computer. Protocal is described in 下位机和上位机通信协议 V1.4
|
|
||||||
* @author miaow (3703781@qq.com)
|
|
||||||
* @version 1.2
|
|
||||||
* @date 2023/05/07
|
|
||||||
* @mainpage github.com/NanjingForestryUniversity
|
|
||||||
*
|
|
||||||
* @copyright Copyright (c) 2023 miaow
|
|
||||||
*
|
|
||||||
* @par Changelog:
|
|
||||||
* <table>
|
|
||||||
* <tr><th>Date <th>Version <th>Author <th>Description
|
|
||||||
* <tr><td>2022/01/16 <td>1.0 <td>miaow <td>Write this file
|
|
||||||
* <tr><td>2022/08/06 <td>1.1 <td>miaow <td>Add fifob
|
|
||||||
* <tr><td>2023/05/07 <td>1.2 <td>miaow <td>Port to b03 branch
|
|
||||||
* </table>
|
|
||||||
*/
|
|
||||||
#ifndef __HOST_COMPUTER_H
|
|
||||||
#define __HOST_COMPUTER_H
|
|
||||||
|
|
||||||
#include <queue_uint64.h>
|
|
||||||
#include <pthread.h>
|
|
||||||
#include <stdint.h>
|
|
||||||
|
|
||||||
#define HOST_COMPUTER_IP "192.168.2.125"
|
|
||||||
#define HOST_COMPUTER_PORT 13452
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief The commonds, ref 下位机和上位机通信协议V1.4
|
|
||||||
*/
|
|
||||||
enum HOSTCOMPUTER_CMD
|
|
||||||
{
|
|
||||||
HOSTCOMPUTER_CMD_START = 1,
|
|
||||||
HOSTCOMPUTER_CMD_STOP = 2,
|
|
||||||
HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_A = 3,
|
|
||||||
HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_B = 4,
|
|
||||||
HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_C = 5,
|
|
||||||
HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_D = 6,
|
|
||||||
};
|
|
||||||
|
|
||||||
int hostcomputer_init(queue_uint64_msg_t *cmd_q);
|
|
||||||
int hostcomputer_deinit(void);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,159 +0,0 @@
|
|||||||
/**
|
|
||||||
* @file main.c
|
|
||||||
* @brief Excute the commands from host_computer
|
|
||||||
* @author miaow (3703781@qq.com)
|
|
||||||
* @version 1.2
|
|
||||||
* @date 2023/05/27
|
|
||||||
* @mainpage github.com/NanjingForestryUniversity
|
|
||||||
*
|
|
||||||
* @copyright Copyright (c) 2023 miaow
|
|
||||||
*
|
|
||||||
* @par Changelog:
|
|
||||||
* <table>
|
|
||||||
* <tr><th>Date <th>Version <th>Author <th>Description
|
|
||||||
* <tr><td>2022/06/12 <td>1.0 <td>miaow <td>Write this file
|
|
||||||
* <tr><td>2023/05/07 <td>1.1 <td>miaow <td>Port to b03
|
|
||||||
* <tr><td>2023/05/27 <td>1.2 <td>miaow <td>Fix bug caused by the missing encoder_dev_set_clrmod()
|
|
||||||
* </table>
|
|
||||||
*/
|
|
||||||
#include <sys/socket.h>
|
|
||||||
#include <arpa/inet.h>
|
|
||||||
#include <math.h>
|
|
||||||
#include <queue_uint64.h>
|
|
||||||
#include <encoder_dev.h>
|
|
||||||
#include <host_computer.h>
|
|
||||||
#include <memory.h>
|
|
||||||
#include <stdio.h>
|
|
||||||
#include <unistd.h>
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Value of state machine
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
SLEEPING = 0,
|
|
||||||
RUNNING = 1,
|
|
||||||
} status_enum_t;
|
|
||||||
|
|
||||||
queue_uint64_msg_t cmd_queue = {0};
|
|
||||||
|
|
||||||
static status_enum_t status = SLEEPING;
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t a;
|
|
||||||
uint32_t b;
|
|
||||||
uint32_t c;
|
|
||||||
uint32_t d;
|
|
||||||
} camera_trigger_pulse_count_typedef;
|
|
||||||
|
|
||||||
camera_trigger_pulse_count_typedef camera_trigger_pulse_count = {
|
|
||||||
.a = 100,
|
|
||||||
.b = 100,
|
|
||||||
.c = 100,
|
|
||||||
.d = 100};
|
|
||||||
|
|
||||||
void process_cmd(uint64_t *cmd);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Read from the cmd_queue and excute the command every 100ms.
|
|
||||||
* @param argc not used
|
|
||||||
* @param argv not used
|
|
||||||
* @return int should not return.
|
|
||||||
*/
|
|
||||||
int main(int argc, char *argv[])
|
|
||||||
{
|
|
||||||
uint64_t cmd;
|
|
||||||
queue_uint64_init(&cmd_queue, 9999);
|
|
||||||
|
|
||||||
// Initialize drivers and clear all caches
|
|
||||||
encoder_dev_init();
|
|
||||||
encoder_dev_set_trigmod(ENCODER_TRIG_MODE_INTERNEL);
|
|
||||||
encoder_dev_set_divide(8, 8, 8, 8);
|
|
||||||
|
|
||||||
hostcomputer_init(&cmd_queue);
|
|
||||||
printf("\r\n>>>>>\r\nstatus==SLEEPING\r\n<<<<<\r\n\r\n");
|
|
||||||
|
|
||||||
// Read from the cmd_queue and excute the command every 100ms
|
|
||||||
while (1)
|
|
||||||
{
|
|
||||||
if (queue_uint64_get(&cmd_queue, &cmd) == 0)
|
|
||||||
process_cmd(&cmd);
|
|
||||||
usleep(1000);
|
|
||||||
}
|
|
||||||
|
|
||||||
// Never run here
|
|
||||||
hostcomputer_deinit();
|
|
||||||
encoder_dev_set_divide(100,100,100,100);
|
|
||||||
encoder_dev_virtual_trig(20);
|
|
||||||
|
|
||||||
encoder_dev_set_trigmod(ENCODER_TRIG_MODE_INTERNEL);
|
|
||||||
encoder_dev_deinit();
|
|
||||||
queue_uint64_deinit(&cmd_queue);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Excute the command and control the states
|
|
||||||
* @param cmd The command to be excuted
|
|
||||||
*/
|
|
||||||
void process_cmd(uint64_t *cmd)
|
|
||||||
{
|
|
||||||
int tmp_cmd = (int)*cmd;
|
|
||||||
int tmp_data = (int)(*cmd >> 32);
|
|
||||||
|
|
||||||
// Only in the SLEEPING state, it resbonds to START or TEST command.
|
|
||||||
if (status == SLEEPING)
|
|
||||||
{
|
|
||||||
if (tmp_cmd == HOSTCOMPUTER_CMD_START)
|
|
||||||
{
|
|
||||||
// Before running, clear the hardware fifo and hardware encoder. Then, the two dividers and delay value should be set.
|
|
||||||
// Also, the hareware encoder is expected to receiving pluse of encoder: the EXTERNAL mode
|
|
||||||
encoder_dev_flush();
|
|
||||||
|
|
||||||
encoder_dev_set_divide(camera_trigger_pulse_count.a,
|
|
||||||
camera_trigger_pulse_count.b,
|
|
||||||
camera_trigger_pulse_count.c,
|
|
||||||
camera_trigger_pulse_count.d);
|
|
||||||
|
|
||||||
encoder_dev_set_trigmod(ENCODER_TRIG_MODE_EXTERNEL);
|
|
||||||
encoder_dev_set_clrmod(ENCODER_CLEAR_MODE_BOTH);
|
|
||||||
printf("\r\n>>>>>\r\nstatus==RUNNING\r\ncamera_a=%d\r\ncamera_b=%d\r\ncamera_c=%d\r\ncamera_d=%d\r\n<<<<<\r\n\r\n",
|
|
||||||
camera_trigger_pulse_count.a,
|
|
||||||
camera_trigger_pulse_count.b,
|
|
||||||
camera_trigger_pulse_count.c,
|
|
||||||
camera_trigger_pulse_count.d);
|
|
||||||
status = RUNNING;
|
|
||||||
}
|
|
||||||
else if (tmp_cmd == HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_A)
|
|
||||||
{
|
|
||||||
camera_trigger_pulse_count.a = tmp_data;
|
|
||||||
}
|
|
||||||
else if (tmp_cmd == HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_B)
|
|
||||||
{
|
|
||||||
camera_trigger_pulse_count.b = tmp_data;
|
|
||||||
}
|
|
||||||
else if (tmp_cmd == HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_C)
|
|
||||||
{
|
|
||||||
camera_trigger_pulse_count.c = tmp_data;
|
|
||||||
}
|
|
||||||
else if (tmp_cmd == HOSTCOMPUTER_CMD_SETCAMERATRIGPULSECOUNT_D)
|
|
||||||
{
|
|
||||||
camera_trigger_pulse_count.d = tmp_data;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
// Only in RUNNING state, the lower machine responds to STOP command.
|
|
||||||
else if (status == RUNNING)
|
|
||||||
{
|
|
||||||
if (tmp_cmd == HOSTCOMPUTER_CMD_STOP)
|
|
||||||
{
|
|
||||||
// Hardware encoder is flushed for a fresh start.
|
|
||||||
encoder_dev_set_trigmod(ENCODER_TRIG_MODE_INTERNEL);
|
|
||||||
encoder_dev_set_divide(4, 4, 4, 4);
|
|
||||||
encoder_dev_virtual_trig(20);
|
|
||||||
encoder_dev_flush();
|
|
||||||
status = SLEEPING;
|
|
||||||
printf("\r\n>>>>>\r\nstatus==SLEEPING\r\n<<<<<\r\n\r\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user